LLVM  12.0.0git
RISCVInstrInfo.h
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1 //===-- RISCVInstrInfo.h - RISCV Instruction Information --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
14 #define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
15 
16 #include "RISCVRegisterInfo.h"
18 
19 #define GET_INSTRINFO_HEADER
20 #include "RISCVGenInstrInfo.inc"
21 
22 namespace llvm {
23 
24 class RISCVSubtarget;
25 
27 
28 public:
30 
31  unsigned isLoadFromStackSlot(const MachineInstr &MI,
32  int &FrameIndex) const override;
33  unsigned isStoreToStackSlot(const MachineInstr &MI,
34  int &FrameIndex) const override;
35 
37  const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
38  bool KillSrc) const override;
39 
42  bool IsKill, int FrameIndex,
43  const TargetRegisterClass *RC,
44  const TargetRegisterInfo *TRI) const override;
45 
48  int FrameIndex, const TargetRegisterClass *RC,
49  const TargetRegisterInfo *TRI) const override;
50 
51  // Materializes the given integer Val into DstReg.
53  const DebugLoc &DL, Register DstReg, uint64_t Val,
55 
56  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
57 
59  MachineBasicBlock *&FBB,
61  bool AllowModify) const override;
62 
65  const DebugLoc &dl,
66  int *BytesAdded = nullptr) const override;
67 
69  MachineBasicBlock &NewDestBB,
70  const DebugLoc &DL, int64_t BrOffset,
71  RegScavenger *RS = nullptr) const override;
72 
73  unsigned removeBranch(MachineBasicBlock &MBB,
74  int *BytesRemoved = nullptr) const override;
75 
76  bool
78 
79  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
80 
81  bool isBranchOffsetInRange(unsigned BranchOpc,
82  int64_t BrOffset) const override;
83 
84  bool isAsCheapAsAMove(const MachineInstr &MI) const override;
85 
86  bool verifyInstruction(const MachineInstr &MI,
87  StringRef &ErrInfo) const override;
88 
90  const MachineOperand *&BaseOp,
91  int64_t &Offset, unsigned &Width,
92  const TargetRegisterInfo *TRI) const;
93 
95  const MachineInstr &MIb) const override;
96 
97 
98  std::pair<unsigned, unsigned>
99  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
100 
103 
104  // Return true if the function can safely be outlined from.
105  virtual bool
107  bool OutlineFromLinkOnceODRs) const override;
108 
109  // Return true if MBB is safe to outline from, and return any target-specific
110  // information in Flags.
111  virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
112  unsigned &Flags) const override;
113 
114  // Calculate target-specific information for a set of outlining candidates.
116  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
117 
118  // Return if/how a given MachineInstr should be outlined.
119  virtual outliner::InstrType
121  unsigned Flags) const override;
122 
123  // Insert a custom frame for outlined functions.
124  virtual void
126  const outliner::OutlinedFunction &OF) const override;
127 
128  // Insert a call to an outlined function into a given basic block.
132  const outliner::Candidate &C) const override;
133 protected:
135 };
136 
137 namespace RISCV {
138 // Match with the definitions in RISCVInstrFormatsV.td
141  WidenV = 1,
142  WidenW = 2,
143  WidenCvt = 3,
144  Narrow = 4,
145  Iota = 5,
146  SlideUp = 6,
147  Vrgather = 7,
149 
151  ConstraintMask = 0b1111
152 };
153 } // end namespace RISCV
154 
155 } // end namespace llvm
156 #endif
uint64_t CallInst * C
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
This class represents lattice values for constants.
Definition: AllocatorList.h:23
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:67
virtual MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
An individual sequence of instructions to be replaced with a call to an outlined function.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
MachineBasicBlock & MBB
virtual void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isAsCheapAsAMove(const MachineInstr &MI) const override
outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:138
SmallVector< MachineOperand, 4 > Cond
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
InstrType
Represents how an instruction should be mapped by the outliner.
The information necessary to create an outlined function for some class of candidate.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const override
RISCVInstrInfo(RISCVSubtarget &STI)
virtual outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MBBI, unsigned Flags) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
MachineOperand class - Representation of each machine instruction operand.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
const RISCVSubtarget & STI
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Representation of each machine instruction.
Definition: MachineInstr.h:62
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
unsigned insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS=nullptr) const override
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
MachineBasicBlock MachineBasicBlock::iterator MBBI
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL