LLVM 19.0.0git
RISCVMatInt.cpp
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1//===- RISCVMatInt.cpp - Immediate materialisation -------------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "RISCVMatInt.h"
11#include "llvm/ADT/APInt.h"
14using namespace llvm;
15
17 if (!HasRVC)
18 return Res.size();
19
20 int Cost = 0;
21 for (auto Instr : Res) {
22 // Assume instructions that aren't listed aren't compressible.
23 bool Compressed = false;
24 switch (Instr.getOpcode()) {
25 case RISCV::SLLI:
26 case RISCV::SRLI:
27 Compressed = true;
28 break;
29 case RISCV::ADDI:
30 case RISCV::ADDIW:
31 case RISCV::LUI:
32 Compressed = isInt<6>(Instr.getImm());
33 break;
34 }
35 // Two RVC instructions take the same space as one RVI instruction, but
36 // can take longer to execute than the single RVI instruction. Thus, we
37 // consider that two RVC instruction are slightly more costly than one
38 // RVI instruction. For longer sequences of RVC instructions the space
39 // savings can be worth it, though. The costs below try to model that.
40 if (!Compressed)
41 Cost += 100; // Baseline cost of one RVI instruction: 100%.
42 else
43 Cost += 70; // 70% cost of baseline.
44 }
45 return Cost;
46}
47
48// Recursively generate a sequence for materializing an integer.
49static void generateInstSeqImpl(int64_t Val, const MCSubtargetInfo &STI,
51 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
52
53 // Use BSETI for a single bit that can't be expressed by a single LUI or ADDI.
54 if (STI.hasFeature(RISCV::FeatureStdExtZbs) && isPowerOf2_64(Val) &&
55 (!isInt<32>(Val) || Val == 0x800)) {
56 Res.emplace_back(RISCV::BSETI, Log2_64(Val));
57 return;
58 }
59
60 if (isInt<32>(Val)) {
61 // Depending on the active bits in the immediate Value v, the following
62 // instruction sequences are emitted:
63 //
64 // v == 0 : ADDI
65 // v[0,12) != 0 && v[12,32) == 0 : ADDI
66 // v[0,12) == 0 && v[12,32) != 0 : LUI
67 // v[0,32) != 0 : LUI+ADDI(W)
68 int64_t Hi20 = ((Val + 0x800) >> 12) & 0xFFFFF;
69 int64_t Lo12 = SignExtend64<12>(Val);
70
71 if (Hi20)
72 Res.emplace_back(RISCV::LUI, Hi20);
73
74 if (Lo12 || Hi20 == 0) {
75 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI;
76 Res.emplace_back(AddiOpc, Lo12);
77 }
78 return;
79 }
80
81 assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target");
82
83 // In the worst case, for a full 64-bit constant, a sequence of 8 instructions
84 // (i.e., LUI+ADDIW+SLLI+ADDI+SLLI+ADDI+SLLI+ADDI) has to be emitted. Note
85 // that the first two instructions (LUI+ADDIW) can contribute up to 32 bits
86 // while the following ADDI instructions contribute up to 12 bits each.
87 //
88 // On the first glance, implementing this seems to be possible by simply
89 // emitting the most significant 32 bits (LUI+ADDIW) followed by as many left
90 // shift (SLLI) and immediate additions (ADDI) as needed. However, due to the
91 // fact that ADDI performs a sign extended addition, doing it like that would
92 // only be possible when at most 11 bits of the ADDI instructions are used.
93 // Using all 12 bits of the ADDI instructions, like done by GAS, actually
94 // requires that the constant is processed starting with the least significant
95 // bit.
96 //
97 // In the following, constants are processed from LSB to MSB but instruction
98 // emission is performed from MSB to LSB by recursively calling
99 // generateInstSeq. In each recursion, first the lowest 12 bits are removed
100 // from the constant and the optimal shift amount, which can be greater than
101 // 12 bits if the constant is sparse, is determined. Then, the shifted
102 // remaining constant is processed recursively and gets emitted as soon as it
103 // fits into 32 bits. The emission of the shifts and additions is subsequently
104 // performed when the recursion returns.
105
106 int64_t Lo12 = SignExtend64<12>(Val);
107 Val = (uint64_t)Val - (uint64_t)Lo12;
108
109 int ShiftAmount = 0;
110 bool Unsigned = false;
111
112 // Val might now be valid for LUI without needing a shift.
113 if (!isInt<32>(Val)) {
114 ShiftAmount = llvm::countr_zero((uint64_t)Val);
115 Val >>= ShiftAmount;
116
117 // If the remaining bits don't fit in 12 bits, we might be able to reduce the
118 // shift amount in order to use LUI which will zero the lower 12 bits.
119 if (ShiftAmount > 12 && !isInt<12>(Val)) {
120 if (isInt<32>((uint64_t)Val << 12)) {
121 // Reduce the shift amount and add zeros to the LSBs so it will match LUI.
122 ShiftAmount -= 12;
123 Val = (uint64_t)Val << 12;
124 } else if (isUInt<32>((uint64_t)Val << 12) &&
125 STI.hasFeature(RISCV::FeatureStdExtZba)) {
126 // Reduce the shift amount and add zeros to the LSBs so it will match
127 // LUI, then shift left with SLLI.UW to clear the upper 32 set bits.
128 ShiftAmount -= 12;
129 Val = ((uint64_t)Val << 12) | (0xffffffffull << 32);
130 Unsigned = true;
131 }
132 }
133
134 // Try to use SLLI_UW for Val when it is uint32 but not int32.
135 if (isUInt<32>((uint64_t)Val) && !isInt<32>((uint64_t)Val) &&
136 STI.hasFeature(RISCV::FeatureStdExtZba)) {
137 // Use LUI+ADDI or LUI to compose, then clear the upper 32 bits with
138 // SLLI_UW.
139 Val = ((uint64_t)Val) | (0xffffffffull << 32);
140 Unsigned = true;
141 }
142 }
143
144 generateInstSeqImpl(Val, STI, Res);
145
146 // Skip shift if we were able to use LUI directly.
147 if (ShiftAmount) {
148 unsigned Opc = Unsigned ? RISCV::SLLI_UW : RISCV::SLLI;
149 Res.emplace_back(Opc, ShiftAmount);
150 }
151
152 if (Lo12)
153 Res.emplace_back(RISCV::ADDI, Lo12);
154}
155
156static unsigned extractRotateInfo(int64_t Val) {
157 // for case: 0b111..1..xxxxxx1..1..
158 unsigned LeadingOnes = llvm::countl_one((uint64_t)Val);
159 unsigned TrailingOnes = llvm::countr_one((uint64_t)Val);
160 if (TrailingOnes > 0 && TrailingOnes < 64 &&
161 (LeadingOnes + TrailingOnes) > (64 - 12))
162 return 64 - TrailingOnes;
163
164 // for case: 0bxxx1..1..1...xxx
165 unsigned UpperTrailingOnes = llvm::countr_one(Hi_32(Val));
166 unsigned LowerLeadingOnes = llvm::countl_one(Lo_32(Val));
167 if (UpperTrailingOnes < 32 &&
168 (UpperTrailingOnes + LowerLeadingOnes) > (64 - 12))
169 return 32 - UpperTrailingOnes;
170
171 return 0;
172}
173
174static void generateInstSeqLeadingZeros(int64_t Val, const MCSubtargetInfo &STI,
176 assert(Val > 0 && "Expected postive val");
177
178 unsigned LeadingZeros = llvm::countl_zero((uint64_t)Val);
179 uint64_t ShiftedVal = (uint64_t)Val << LeadingZeros;
180 // Fill in the bits that will be shifted out with 1s. An example where this
181 // helps is trailing one masks with 32 or more ones. This will generate
182 // ADDI -1 and an SRLI.
183 ShiftedVal |= maskTrailingOnes<uint64_t>(LeadingZeros);
184
186 generateInstSeqImpl(ShiftedVal, STI, TmpSeq);
187
188 // Keep the new sequence if it is an improvement or the original is empty.
189 if ((TmpSeq.size() + 1) < Res.size() ||
190 (Res.empty() && TmpSeq.size() < 8)) {
191 TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros);
192 Res = TmpSeq;
193 }
194
195 // Some cases can benefit from filling the lower bits with zeros instead.
196 ShiftedVal &= maskTrailingZeros<uint64_t>(LeadingZeros);
197 TmpSeq.clear();
198 generateInstSeqImpl(ShiftedVal, STI, TmpSeq);
199
200 // Keep the new sequence if it is an improvement or the original is empty.
201 if ((TmpSeq.size() + 1) < Res.size() ||
202 (Res.empty() && TmpSeq.size() < 8)) {
203 TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros);
204 Res = TmpSeq;
205 }
206
207 // If we have exactly 32 leading zeros and Zba, we can try using zext.w at
208 // the end of the sequence.
209 if (LeadingZeros == 32 && STI.hasFeature(RISCV::FeatureStdExtZba)) {
210 // Try replacing upper bits with 1.
211 uint64_t LeadingOnesVal = Val | maskLeadingOnes<uint64_t>(LeadingZeros);
212 TmpSeq.clear();
213 generateInstSeqImpl(LeadingOnesVal, STI, TmpSeq);
214
215 // Keep the new sequence if it is an improvement.
216 if ((TmpSeq.size() + 1) < Res.size() ||
217 (Res.empty() && TmpSeq.size() < 8)) {
218 TmpSeq.emplace_back(RISCV::ADD_UW, 0);
219 Res = TmpSeq;
220 }
221 }
222}
223
225InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI) {
227 generateInstSeqImpl(Val, STI, Res);
228
229 // If the low 12 bits are non-zero, the first expansion may end with an ADDI
230 // or ADDIW. If there are trailing zeros, try generating a sign extended
231 // constant with no trailing zeros and use a final SLLI to restore them.
232 if ((Val & 0xfff) != 0 && (Val & 1) == 0 && Res.size() >= 2) {
233 unsigned TrailingZeros = llvm::countr_zero((uint64_t)Val);
234 int64_t ShiftedVal = Val >> TrailingZeros;
235 // If we can use C.LI+C.SLLI instead of LUI+ADDI(W) prefer that since
236 // its more compressible. But only if LUI+ADDI(W) isn't fusable.
237 // NOTE: We don't check for C extension to minimize differences in generated
238 // code.
239 bool IsShiftedCompressible =
240 isInt<6>(ShiftedVal) && !STI.hasFeature(RISCV::TuneLUIADDIFusion);
242 generateInstSeqImpl(ShiftedVal, STI, TmpSeq);
243
244 // Keep the new sequence if it is an improvement.
245 if ((TmpSeq.size() + 1) < Res.size() || IsShiftedCompressible) {
246 TmpSeq.emplace_back(RISCV::SLLI, TrailingZeros);
247 Res = TmpSeq;
248 }
249 }
250
251 // If we have a 1 or 2 instruction sequence this is the best we can do. This
252 // will always be true for RV32 and will often be true for RV64.
253 if (Res.size() <= 2)
254 return Res;
255
256 assert(STI.hasFeature(RISCV::Feature64Bit) &&
257 "Expected RV32 to only need 2 instructions");
258
259 // If the lower 13 bits are something like 0x17ff, try to add 1 to change the
260 // lower 13 bits to 0x1800. We can restore this with an ADDI of -1 at the end
261 // of the sequence. Call generateInstSeqImpl on the new constant which may
262 // subtract 0xfffffffffffff800 to create another ADDI. This will leave a
263 // constant with more than 12 trailing zeros for the next recursive step.
264 if ((Val & 0xfff) != 0 && (Val & 0x1800) == 0x1000) {
265 int64_t Imm12 = -(0x800 - (Val & 0xfff));
266 int64_t AdjustedVal = Val - Imm12;
268 generateInstSeqImpl(AdjustedVal, STI, TmpSeq);
269
270 // Keep the new sequence if it is an improvement.
271 if ((TmpSeq.size() + 1) < Res.size()) {
272 TmpSeq.emplace_back(RISCV::ADDI, Imm12);
273 Res = TmpSeq;
274 }
275 }
276
277 // If the constant is positive we might be able to generate a shifted constant
278 // with no leading zeros and use a final SRLI to restore them.
279 if (Val > 0 && Res.size() > 2) {
280 generateInstSeqLeadingZeros(Val, STI, Res);
281 }
282
283 // If the constant is negative, trying inverting and using our trailing zero
284 // optimizations. Use an xori to invert the final value.
285 if (Val < 0 && Res.size() > 3) {
286 uint64_t InvertedVal = ~(uint64_t)Val;
288 generateInstSeqLeadingZeros(InvertedVal, STI, TmpSeq);
289
290 // Keep it if we found a sequence that is smaller after inverting.
291 if (!TmpSeq.empty() && (TmpSeq.size() + 1) < Res.size()) {
292 TmpSeq.emplace_back(RISCV::XORI, -1);
293 Res = TmpSeq;
294 }
295 }
296
297 // If the Low and High halves are the same, use pack. The pack instruction
298 // packs the XLEN/2-bit lower halves of rs1 and rs2 into rd, with rs1 in the
299 // lower half and rs2 in the upper half.
300 if (Res.size() > 2 && STI.hasFeature(RISCV::FeatureStdExtZbkb)) {
301 int64_t LoVal = SignExtend64<32>(Val);
302 int64_t HiVal = SignExtend64<32>(Val >> 32);
303 if (LoVal == HiVal) {
305 generateInstSeqImpl(LoVal, STI, TmpSeq);
306 if ((TmpSeq.size() + 1) < Res.size()) {
307 TmpSeq.emplace_back(RISCV::PACK, 0);
308 Res = TmpSeq;
309 }
310 }
311 }
312
313 // Perform optimization with BCLRI/BSETI in the Zbs extension.
314 if (Res.size() > 2 && STI.hasFeature(RISCV::FeatureStdExtZbs)) {
315 // 1. For values in range 0xffffffff 7fffffff ~ 0xffffffff 00000000,
316 // call generateInstSeqImpl with Val|0x80000000 (which is expected be
317 // an int32), then emit (BCLRI r, 31).
318 // 2. For values in range 0x80000000 ~ 0xffffffff, call generateInstSeqImpl
319 // with Val&~0x80000000 (which is expected to be an int32), then
320 // emit (BSETI r, 31).
321 int64_t NewVal;
322 unsigned Opc;
323 if (Val < 0) {
324 Opc = RISCV::BCLRI;
325 NewVal = Val | 0x80000000ll;
326 } else {
327 Opc = RISCV::BSETI;
328 NewVal = Val & ~0x80000000ll;
329 }
330 if (isInt<32>(NewVal)) {
332 generateInstSeqImpl(NewVal, STI, TmpSeq);
333 if ((TmpSeq.size() + 1) < Res.size()) {
334 TmpSeq.emplace_back(Opc, 31);
335 Res = TmpSeq;
336 }
337 }
338
339 // Try to use BCLRI for upper 32 bits if the original lower 32 bits are
340 // negative int32, or use BSETI for upper 32 bits if the original lower
341 // 32 bits are positive int32.
342 int32_t Lo = Lo_32(Val);
343 uint32_t Hi = Hi_32(Val);
344 Opc = 0;
346 generateInstSeqImpl(Lo, STI, TmpSeq);
347 // Check if it is profitable to use BCLRI/BSETI.
348 if (Lo > 0 && TmpSeq.size() + llvm::popcount(Hi) < Res.size()) {
349 Opc = RISCV::BSETI;
350 } else if (Lo < 0 && TmpSeq.size() + llvm::popcount(~Hi) < Res.size()) {
351 Opc = RISCV::BCLRI;
352 Hi = ~Hi;
353 }
354 // Search for each bit and build corresponding BCLRI/BSETI.
355 if (Opc > 0) {
356 while (Hi != 0) {
357 unsigned Bit = llvm::countr_zero(Hi);
358 TmpSeq.emplace_back(Opc, Bit + 32);
359 Hi &= (Hi - 1); // Clear lowest set bit.
360 }
361 if (TmpSeq.size() < Res.size())
362 Res = TmpSeq;
363 }
364 }
365
366 // Perform optimization with SH*ADD in the Zba extension.
367 if (Res.size() > 2 && STI.hasFeature(RISCV::FeatureStdExtZba)) {
368 int64_t Div = 0;
369 unsigned Opc = 0;
371 // Select the opcode and divisor.
372 if ((Val % 3) == 0 && isInt<32>(Val / 3)) {
373 Div = 3;
374 Opc = RISCV::SH1ADD;
375 } else if ((Val % 5) == 0 && isInt<32>(Val / 5)) {
376 Div = 5;
377 Opc = RISCV::SH2ADD;
378 } else if ((Val % 9) == 0 && isInt<32>(Val / 9)) {
379 Div = 9;
380 Opc = RISCV::SH3ADD;
381 }
382 // Build the new instruction sequence.
383 if (Div > 0) {
384 generateInstSeqImpl(Val / Div, STI, TmpSeq);
385 if ((TmpSeq.size() + 1) < Res.size()) {
386 TmpSeq.emplace_back(Opc, 0);
387 Res = TmpSeq;
388 }
389 } else {
390 // Try to use LUI+SH*ADD+ADDI.
391 int64_t Hi52 = ((uint64_t)Val + 0x800ull) & ~0xfffull;
392 int64_t Lo12 = SignExtend64<12>(Val);
393 Div = 0;
394 if (isInt<32>(Hi52 / 3) && (Hi52 % 3) == 0) {
395 Div = 3;
396 Opc = RISCV::SH1ADD;
397 } else if (isInt<32>(Hi52 / 5) && (Hi52 % 5) == 0) {
398 Div = 5;
399 Opc = RISCV::SH2ADD;
400 } else if (isInt<32>(Hi52 / 9) && (Hi52 % 9) == 0) {
401 Div = 9;
402 Opc = RISCV::SH3ADD;
403 }
404 // Build the new instruction sequence.
405 if (Div > 0) {
406 // For Val that has zero Lo12 (implies Val equals to Hi52) should has
407 // already been processed to LUI+SH*ADD by previous optimization.
408 assert(Lo12 != 0 &&
409 "unexpected instruction sequence for immediate materialisation");
410 assert(TmpSeq.empty() && "Expected empty TmpSeq");
411 generateInstSeqImpl(Hi52 / Div, STI, TmpSeq);
412 if ((TmpSeq.size() + 2) < Res.size()) {
413 TmpSeq.emplace_back(Opc, 0);
414 TmpSeq.emplace_back(RISCV::ADDI, Lo12);
415 Res = TmpSeq;
416 }
417 }
418 }
419 }
420
421 // Perform optimization with rori in the Zbb and th.srri in the XTheadBb
422 // extension.
423 if (Res.size() > 2 && (STI.hasFeature(RISCV::FeatureStdExtZbb) ||
424 STI.hasFeature(RISCV::FeatureVendorXTHeadBb))) {
425 if (unsigned Rotate = extractRotateInfo(Val)) {
427 uint64_t NegImm12 = llvm::rotl<uint64_t>(Val, Rotate);
428 assert(isInt<12>(NegImm12));
429 TmpSeq.emplace_back(RISCV::ADDI, NegImm12);
430 TmpSeq.emplace_back(STI.hasFeature(RISCV::FeatureStdExtZbb)
431 ? RISCV::RORI
432 : RISCV::TH_SRRI,
433 Rotate);
434 Res = TmpSeq;
435 }
436 }
437 return Res;
438}
439
440void generateMCInstSeq(int64_t Val, const MCSubtargetInfo &STI,
441 MCRegister DestReg, SmallVectorImpl<MCInst> &Insts) {
443
444 MCRegister SrcReg = RISCV::X0;
445 for (RISCVMatInt::Inst &Inst : Seq) {
446 switch (Inst.getOpndKind()) {
447 case RISCVMatInt::Imm:
449 .addReg(DestReg)
450 .addImm(Inst.getImm()));
451 break;
454 .addReg(DestReg)
455 .addReg(SrcReg)
456 .addReg(RISCV::X0));
457 break;
460 .addReg(DestReg)
461 .addReg(SrcReg)
462 .addReg(SrcReg));
463 break;
466 .addReg(DestReg)
467 .addReg(SrcReg)
468 .addImm(Inst.getImm()));
469 break;
470 }
471
472 // Only the first instruction has X0 as its source.
473 SrcReg = DestReg;
474 }
475}
476
478 unsigned &ShiftAmt, unsigned &AddOpc) {
479 int64_t LoVal = SignExtend64<32>(Val);
480 if (LoVal == 0)
481 return RISCVMatInt::InstSeq();
482
483 // Subtract the LoVal to emulate the effect of the final ADD.
484 uint64_t Tmp = (uint64_t)Val - (uint64_t)LoVal;
485 assert(Tmp != 0);
486
487 // Use trailing zero counts to figure how far we need to shift LoVal to line
488 // up with the remaining constant.
489 // TODO: This algorithm assumes all non-zero bits in the low 32 bits of the
490 // final constant come from LoVal.
491 unsigned TzLo = llvm::countr_zero((uint64_t)LoVal);
492 unsigned TzHi = llvm::countr_zero(Tmp);
493 assert(TzLo < 32 && TzHi >= 32);
494 ShiftAmt = TzHi - TzLo;
495 AddOpc = RISCV::ADD;
496
497 if (Tmp == ((uint64_t)LoVal << ShiftAmt))
498 return RISCVMatInt::generateInstSeq(LoVal, STI);
499
500 // If we have Zba, we can use (ADD_UW X, (SLLI X, 32)).
501 if (STI.hasFeature(RISCV::FeatureStdExtZba) && Lo_32(Val) == Hi_32(Val)) {
502 ShiftAmt = 32;
503 AddOpc = RISCV::ADD_UW;
504 return RISCVMatInt::generateInstSeq(LoVal, STI);
505 }
506
507 return RISCVMatInt::InstSeq();
508}
509
510int getIntMatCost(const APInt &Val, unsigned Size, const MCSubtargetInfo &STI,
511 bool CompressionCost) {
512 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
513 bool HasRVC = CompressionCost && (STI.hasFeature(RISCV::FeatureStdExtC) ||
514 STI.hasFeature(RISCV::FeatureStdExtZca));
515 int PlatRegSize = IsRV64 ? 64 : 32;
516
517 // Split the constant into platform register sized chunks, and calculate cost
518 // of each chunk.
519 int Cost = 0;
520 for (unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) {
521 APInt Chunk = Val.ashr(ShiftVal).sextOrTrunc(PlatRegSize);
522 InstSeq MatSeq = generateInstSeq(Chunk.getSExtValue(), STI);
523 Cost += getInstSeqCost(MatSeq, HasRVC);
524 }
525 return std::max(1, Cost);
526}
527
529 switch (Opc) {
530 default:
531 llvm_unreachable("Unexpected opcode!");
532 case RISCV::LUI:
533 return RISCVMatInt::Imm;
534 case RISCV::ADD_UW:
535 return RISCVMatInt::RegX0;
536 case RISCV::SH1ADD:
537 case RISCV::SH2ADD:
538 case RISCV::SH3ADD:
539 case RISCV::PACK:
540 return RISCVMatInt::RegReg;
541 case RISCV::ADDI:
542 case RISCV::ADDIW:
543 case RISCV::XORI:
544 case RISCV::SLLI:
545 case RISCV::SRLI:
546 case RISCV::SLLI_UW:
547 case RISCV::RORI:
548 case RISCV::BSETI:
549 case RISCV::BCLRI:
550 case RISCV::TH_SRRI:
551 return RISCVMatInt::RegImm;
552 }
553}
554
555} // namespace llvm::RISCVMatInt
This file implements a class to represent arbitrary precision integral constant values and operations...
uint64_t Size
bool HasRVC
Definition: ELF_riscv.cpp:502
static void generateInstSeqLeadingZeros(int64_t Val, const MCSubtargetInfo &STI, RISCVMatInt::InstSeq &Res)
static void generateInstSeqImpl(int64_t Val, const MCSubtargetInfo &STI, RISCVMatInt::InstSeq &Res)
Definition: RISCVMatInt.cpp:49
static unsigned extractRotateInfo(int64_t Val)
static int getInstSeqCost(RISCVMatInt::InstSeq &Res, bool HasRVC)
Definition: RISCVMatInt.cpp:16
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Class for arbitrary precision integers.
Definition: APInt.h:76
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
Definition: APInt.cpp:1010
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
Definition: APInt.h:805
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1513
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:37
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:43
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
int64_t getImm() const
Definition: RISCVMatInt.h:39
unsigned getOpcode() const
Definition: RISCVMatInt.h:38
OpndKind getOpndKind() const
bool empty() const
Definition: SmallVector.h:94
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:950
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI)
int getIntMatCost(const APInt &Val, unsigned Size, const MCSubtargetInfo &STI, bool CompressionCost)
SmallVector< Inst, 8 > InstSeq
Definition: RISCVMatInt.h:43
InstSeq generateTwoRegInstSeq(int64_t Val, const MCSubtargetInfo &STI, unsigned &ShiftAmt, unsigned &AddOpc)
void generateMCInstSeq(int64_t Val, const MCSubtargetInfo &STI, MCRegister DestReg, SmallVectorImpl< MCInst > &Insts)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
int popcount(T Value) noexcept
Count the number of set bits in a value.
Definition: bit.h:385
int countr_one(T Value)
Count the number of ones from the least significant bit to the first zero bit.
Definition: bit.h:307
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
Definition: MathExtras.h:269
unsigned Log2_64(uint64_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:319
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: bit.h:215
int countl_zero(T Val)
Count number of 0's from the most significant bit to the least stopping at the first 1.
Definition: bit.h:281
constexpr uint32_t Hi_32(uint64_t Value)
Return the high 32 bits of a 64 bit value.
Definition: MathExtras.h:136
int countl_one(T Value)
Count the number of ones from the most significant bit to the first zero bit.
Definition: bit.h:294
constexpr uint32_t Lo_32(uint64_t Value)
Return the low 32 bits of a 64 bit value.
Definition: MathExtras.h:141