LLVM  10.0.0svn
RegUsageInfoCollector.cpp
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1 //===-- RegUsageInfoCollector.cpp - Register Usage Information Collector --===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// This pass is required to take advantage of the interprocedural register
10 /// allocation infrastructure.
11 ///
12 /// This pass is simple MachineFunction pass which collects register usage
13 /// details by iterating through each physical registers and checking
14 /// MRI::isPhysRegUsed() then creates a RegMask based on this details.
15 /// The pass then stores this RegMask in PhysicalRegisterUsageInfo.cpp
16 ///
17 //===----------------------------------------------------------------------===//
18 
19 #include "llvm/ADT/Statistic.h"
25 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/Support/Debug.h"
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "ip-regalloc"
34 
35 STATISTIC(NumCSROpt,
36  "Number of functions optimized for callee saved registers");
37 
38 namespace {
39 
41 public:
45  }
46 
47  StringRef getPassName() const override {
48  return "Register Usage Information Collector Pass";
49  }
50 
51  void getAnalysisUsage(AnalysisUsage &AU) const override {
53  AU.setPreservesAll();
55  }
56 
57  bool runOnMachineFunction(MachineFunction &MF) override;
58 
59  // Call determineCalleeSaves and then also set the bits for subregs and
60  // fully saved superregs.
61  static void computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF);
62 
63  static char ID;
64 };
65 
66 } // end of anonymous namespace
67 
69 
70 INITIALIZE_PASS_BEGIN(RegUsageInfoCollector, "RegUsageInfoCollector",
71  "Register Usage Information Collector", false, false)
73 INITIALIZE_PASS_END(RegUsageInfoCollector, "RegUsageInfoCollector",
74  "Register Usage Information Collector", false, false)
75 
77  return new RegUsageInfoCollector();
78 }
79 
80 // TODO: Move to hook somwehere?
81 
82 // Return true if it is useful to track the used registers for IPRA / no CSR
83 // optimizations. This is not useful for entry points, and computing the
84 // register usage information is expensive.
85 static bool isCallableFunction(const MachineFunction &MF) {
86  switch (MF.getFunction().getCallingConv()) {
95  return false;
96  default:
97  return true;
98  }
99 }
100 
101 bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
104  const LLVMTargetMachine &TM = MF.getTarget();
105 
106  LLVM_DEBUG(dbgs() << " -------------------- " << getPassName()
107  << " -------------------- \nFunction Name : "
108  << MF.getName() << '\n');
109 
110  // Analyzing the register usage may be expensive on some targets.
111  if (!isCallableFunction(MF)) {
112  LLVM_DEBUG(dbgs() << "Not analyzing non-callable function\n");
113  return false;
114  }
115 
116  // If there are no callers, there's no point in computing more precise
117  // register usage here.
118  if (MF.getFunction().use_empty()) {
119  LLVM_DEBUG(dbgs() << "Not analyzing function with no callers\n");
120  return false;
121  }
122 
123  std::vector<uint32_t> RegMask;
124 
125  // Compute the size of the bit vector to represent all the registers.
126  // The bit vector is broken into 32-bit chunks, thus takes the ceil of
127  // the number of registers divided by 32 for the size.
128  unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
129  RegMask.resize(RegMaskSize, ~((uint32_t)0));
130 
131  const Function &F = MF.getFunction();
132 
133  PhysicalRegisterUsageInfo &PRUI = getAnalysis<PhysicalRegisterUsageInfo>();
134  PRUI.setTargetMachine(TM);
135 
136  LLVM_DEBUG(dbgs() << "Clobbered Registers: ");
137 
138  BitVector SavedRegs;
139  computeCalleeSavedRegs(SavedRegs, MF);
140 
141  const BitVector &UsedPhysRegsMask = MRI->getUsedPhysRegsMask();
142  auto SetRegAsDefined = [&RegMask] (unsigned Reg) {
143  RegMask[Reg / 32] &= ~(1u << Reg % 32);
144  };
145 
146  // Some targets can clobber registers "inside" a call, typically in
147  // linker-generated code.
148  for (const MCPhysReg Reg : TRI->getIntraCallClobberedRegs(&MF))
149  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
150  SetRegAsDefined(*AI);
151 
152  // Scan all the physical registers. When a register is defined in the current
153  // function set it and all the aliasing registers as defined in the regmask.
154  // FIXME: Rewrite to use regunits.
155  for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
156  // Don't count registers that are saved and restored.
157  if (SavedRegs.test(PReg))
158  continue;
159  // If a register is defined by an instruction mark it as defined together
160  // with all it's unsaved aliases.
161  if (!MRI->def_empty(PReg)) {
162  for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI)
163  if (!SavedRegs.test(*AI))
164  SetRegAsDefined(*AI);
165  continue;
166  }
167  // If a register is in the UsedPhysRegsMask set then mark it as defined.
168  // All clobbered aliases will also be in the set, so we can skip setting
169  // as defined all the aliases here.
170  if (UsedPhysRegsMask.test(PReg))
171  SetRegAsDefined(PReg);
172  }
173 
176  ++NumCSROpt;
177  LLVM_DEBUG(dbgs() << MF.getName()
178  << " function optimized for not having CSR.\n");
179  }
180 
181  LLVM_DEBUG(
182  for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
183  if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg))
184  dbgs() << printReg(PReg, TRI) << " ";
185  }
186 
187  dbgs() << " \n----------------------------------------\n";
188  );
189 
190  PRUI.storeUpdateRegUsageInfo(F, RegMask);
191 
192  return false;
193 }
194 
195 void RegUsageInfoCollector::
196 computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF) {
199 
200  // Target will return the set of registers that it saves/restores as needed.
201  SavedRegs.clear();
202  TFI.determineCalleeSaves(MF, SavedRegs);
203  if (SavedRegs.none())
204  return;
205 
206  // Insert subregs.
207  const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
208  for (unsigned i = 0; CSRegs[i]; ++i) {
209  MCPhysReg Reg = CSRegs[i];
210  if (SavedRegs.test(Reg)) {
211  // Save subregisters
212  for (MCSubRegIterator SR(Reg, &TRI); SR.isValid(); ++SR)
213  SavedRegs.set(*SR);
214  }
215  }
216 }
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
BitVector & set()
Definition: BitVector.h:397
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:199
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
A global registry used in conjunction with static constructors to make pluggable components (like tar...
Definition: Registry.h:44
unsigned Reg
bool test(unsigned Idx) const
Definition: BitVector.h:501
void initializeRegUsageInfoCollectorPass(PassRegistry &)
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
F(f)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
static bool isSafeForNoCSROpt(const Function &F)
Check if given function is safe for not having callee saved registers.
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:50
void clear()
clear - Removes all bits from the bitvector. Does not change capacity.
Definition: BitVector.h:366
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Calling convention used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (ve...
Definition: CallingConv.h:193
FunctionPass * createRegUsageInfoCollector()
This pass is executed POST-RA to collect which physical registers are preserved by given machine func...
virtual ArrayRef< MCPhysReg > getIntraCallClobberedRegs(const MachineFunction *MF) const
Return a list of all of the registers which are clobbered "inside" a call to the given function...
Calling convention used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:196
Calling convention used for AMDPAL vertex shader if tessellation is in use.
Definition: CallingConv.h:220
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
void storeUpdateRegUsageInfo(const Function &FP, ArrayRef< uint32_t > RegMask)
To store RegMask for given Function *.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
MCRegAliasIterator enumerates all registers aliasing Reg.
Represent the analysis usage information of a pass.
void setTargetMachine(const LLVMTargetMachine &TM)
Set TargetMachine which is used to print analysis.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCSubRegIterator enumerates all sub-registers of Reg.
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
INITIALIZE_PASS_BEGIN(RegUsageInfoCollector, "RegUsageInfoCollector", "Register Usage Information Collector", false, false) INITIALIZE_PASS_END(RegUsageInfoCollector
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
Information about stack frame layout on the target.
Calling convention used for Mesa/AMDPAL compute shaders.
Definition: CallingConv.h:202
Natural Loop Information
Definition: LoopInfo.cpp:1058
const BitVector & getUsedPhysRegsMask() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void setPreservesAll()
Set by analyses that do not transform their input at all.
RegUsageInfoCollector
Calling convention used for AMDPAL shader stage before geometry shader if geometry is in use...
Definition: CallingConv.h:225
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:201
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
virtual const TargetFrameLowering * getFrameLowering() const
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
This pass is required to take advantage of the interprocedural register allocation infrastructure...
static bool isCallableFunction(const MachineFunction &MF)
Calling convention used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:212
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
#define LLVM_DEBUG(X)
Definition: Debug.h:122
Register Usage Information Collector
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:205
bool use_empty() const
Definition: Value.h:342
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
virtual bool isProfitableForNoCSROpt(const Function &F) const
Check if the no-CSR optimisation is profitable for the given function.