LLVM  10.0.0svn
RetireStage.h
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1 //===---------------------- RetireStage.h -----------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// This file defines the retire stage of a default instruction pipeline.
11 /// The RetireStage represents the process logic that interacts with the
12 /// simulated RetireControlUnit hardware.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_MCA_RETIRE_STAGE_H
17 #define LLVM_MCA_RETIRE_STAGE_H
18 
22 #include "llvm/MCA/Stages/Stage.h"
23 
24 namespace llvm {
25 namespace mca {
26 
27 class RetireStage final : public Stage {
28  // Owner will go away when we move listeners/eventing to the stages.
29  RetireControlUnit &RCU;
30  RegisterFile &PRF;
31  LSUnitBase &LSU;
32 
33  RetireStage(const RetireStage &Other) = delete;
34  RetireStage &operator=(const RetireStage &Other) = delete;
35 
36 public:
38  : Stage(), RCU(R), PRF(F), LSU(LS) {}
39 
40  bool hasWorkToComplete() const override { return !RCU.isEmpty(); }
41  Error cycleStart() override;
42  Error execute(InstRef &IR) override;
43  void notifyInstructionRetired(const InstRef &IR) const;
44 };
45 
46 } // namespace mca
47 } // namespace llvm
48 
49 #endif // LLVM_MCA_RETIRE_STAGE_H
RetireStage(RetireControlUnit &R, RegisterFile &F, LSUnitBase &LS)
Definition: RetireStage.h:37
This class represents lattice values for constants.
Definition: AllocatorList.h:23
This file simulates the hardware responsible for retiring instructions.
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:953
void notifyInstructionRetired(const InstRef &IR) const
Definition: RetireStage.cpp:50
F(f)
An InstRef contains both a SourceMgr index and Instruction pair.
Definition: Instruction.h:562
A Load/Store unit class that models load/store queues and that implements a simple weak memory consis...
This class tracks which instructions are in-flight (i.e., dispatched but not retired) in the OoO back...
Abstract base interface for LS (load/store) units in llvm-mca.
Definition: LSUnit.h:167
bool hasWorkToComplete() const override
Returns true if some instructions are still executing this stage.
Definition: RetireStage.h:40
This file defines a register mapping file class.
This file defines a stage.
Manages hardware register files, and tracks register definitions for register renaming purposes...
Definition: RegisterFile.h:36
Error cycleStart() override
Called once at the start of each cycle.
Definition: RetireStage.cpp:25
Error execute(InstRef &IR) override
The primary action that this stage performs on instruction IR.
Definition: RetireStage.cpp:45
Lightweight error class with error context and mandatory checking.
Definition: Error.h:157
Statically lint checks LLVM IR
Definition: Lint.cpp:192