LLVM  9.0.0svn
SIDefines.h
Go to the documentation of this file.
1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 //===----------------------------------------------------------------------===//
9 
10 #include "llvm/MC/MCInstrDesc.h"
11 
12 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
13 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
14 
15 namespace llvm {
16 
17 namespace SIInstrFlags {
18 // This needs to be kept in sync with the field bits in InstSI.
19 enum : uint64_t {
20  // Low bits - basic encoding information.
21  SALU = 1 << 0,
22  VALU = 1 << 1,
23 
24  // SALU instruction formats.
25  SOP1 = 1 << 2,
26  SOP2 = 1 << 3,
27  SOPC = 1 << 4,
28  SOPK = 1 << 5,
29  SOPP = 1 << 6,
30 
31  // VALU instruction formats.
32  VOP1 = 1 << 7,
33  VOP2 = 1 << 8,
34  VOPC = 1 << 9,
35 
36  // TODO: Should this be spilt into VOP3 a and b?
37  VOP3 = 1 << 10,
38  VOP3P = 1 << 12,
39 
40  VINTRP = 1 << 13,
41  SDWA = 1 << 14,
42  DPP = 1 << 15,
43 
44  // Memory instruction formats.
45  MUBUF = 1 << 16,
46  MTBUF = 1 << 17,
47  SMRD = 1 << 18,
48  MIMG = 1 << 19,
49  EXP = 1 << 20,
50  FLAT = 1 << 21,
51  DS = 1 << 22,
52 
53  // Pseudo instruction formats.
54  VGPRSpill = 1 << 23,
55  SGPRSpill = 1 << 24,
56 
57  // High bits - other information.
58  VM_CNT = UINT64_C(1) << 32,
59  EXP_CNT = UINT64_C(1) << 33,
60  LGKM_CNT = UINT64_C(1) << 34,
61 
62  WQM = UINT64_C(1) << 35,
63  DisableWQM = UINT64_C(1) << 36,
64  Gather4 = UINT64_C(1) << 37,
65  SOPK_ZEXT = UINT64_C(1) << 38,
66  SCALAR_STORE = UINT64_C(1) << 39,
67  FIXED_SIZE = UINT64_C(1) << 40,
68  VOPAsmPrefer32Bit = UINT64_C(1) << 41,
69  VOP3_OPSEL = UINT64_C(1) << 42,
70  maybeAtomic = UINT64_C(1) << 43,
71  renamedInGFX9 = UINT64_C(1) << 44,
72 
73  // Is a clamp on FP type.
74  FPClamp = UINT64_C(1) << 45,
75 
76  // Is an integer clamp
77  IntClamp = UINT64_C(1) << 46,
78 
79  // Clamps lo component of register.
80  ClampLo = UINT64_C(1) << 47,
81 
82  // Clamps hi component of register.
83  // ClampLo and ClampHi set for packed clamp.
84  ClampHi = UINT64_C(1) << 48,
85 
86  // Is a packed VOP3P instruction.
87  IsPacked = UINT64_C(1) << 49,
88 
89  // Is a D16 buffer instruction.
90  D16Buf = UINT64_C(1) << 50,
91 
92  // Uses floating point double precision rounding mode
93  FPDPRounding = UINT64_C(1) << 51
94 };
95 
96 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
97 // The result is true if any of these tests are true.
98 enum ClassFlags : unsigned {
99  S_NAN = 1 << 0, // Signaling NaN
100  Q_NAN = 1 << 1, // Quiet NaN
101  N_INFINITY = 1 << 2, // Negative infinity
102  N_NORMAL = 1 << 3, // Negative normal
103  N_SUBNORMAL = 1 << 4, // Negative subnormal
104  N_ZERO = 1 << 5, // Negative zero
105  P_ZERO = 1 << 6, // Positive zero
106  P_SUBNORMAL = 1 << 7, // Positive subnormal
107  P_NORMAL = 1 << 8, // Positive normal
108  P_INFINITY = 1 << 9 // Positive infinity
109 };
110 }
111 
112 namespace AMDGPU {
113  enum OperandType : unsigned {
114  /// Operands with register or 32-bit immediate
121 
122  /// Operands with register or inline constant
131 
134 
137 
140 
141  // Operand for source modifiers for VOP instructions
143 
144  // Operand for SDWA instructions
146 
147  /// Operand with 32-bit immediate that uses the constant bus.
150  };
151 }
152 
153 namespace SIStackID {
154 enum StackTypes : uint8_t {
155  SCRATCH = 0,
157 };
158 }
159 
160 // Input operand modifiers bit-masks
161 // NEG and SEXT share same bit-mask because they can't be set simultaneously.
162 namespace SISrcMods {
163  enum : unsigned {
164  NEG = 1 << 0, // Floating-point negate modifier
165  ABS = 1 << 1, // Floating-point absolute modifier
166  SEXT = 1 << 0, // Integer sign-extend modifier
167  NEG_HI = ABS, // Floating-point negate high packed component modifier.
168  OP_SEL_0 = 1 << 2,
169  OP_SEL_1 = 1 << 3,
170  DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
171  };
172 }
173 
174 namespace SIOutMods {
175  enum : unsigned {
176  NONE = 0,
177  MUL2 = 1,
178  MUL4 = 2,
179  DIV2 = 3
180  };
181 }
182 
183 namespace AMDGPU {
184 namespace VGPRIndexMode {
185 
186 enum Id : unsigned { // id of symbolic names
187  ID_SRC0 = 0,
191 
194 };
195 
196 enum EncBits : unsigned {
197  OFF = 0,
203 };
204 
205 } // namespace VGPRIndexMode
206 } // namespace AMDGPU
207 
208 namespace AMDGPUAsmVariants {
209  enum : unsigned {
210  DEFAULT = 0,
211  VOP3 = 1,
212  SDWA = 2,
213  SDWA9 = 3,
214  DPP = 4
215  };
216 }
217 
218 namespace AMDGPU {
219 namespace EncValues { // Encoding values of enum9/8/7 operands
220 
221 enum : unsigned {
222  SGPR_MIN = 0,
223  SGPR_MAX = 101,
224  TTMP_VI_MIN = 112,
225  TTMP_VI_MAX = 123,
234  VGPR_MIN = 256,
235  VGPR_MAX = 511
236 };
237 
238 } // namespace EncValues
239 } // namespace AMDGPU
240 
241 namespace AMDGPU {
242 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
243 
244 enum Id { // Message ID, width(4) [3:0].
249  ID_SYSMSG = 15,
250  ID_GAPS_LAST_, // Indicate that sequence has gaps.
254  ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
255 };
256 
257 enum Op { // Both GS and SYS operation IDs.
260  // width(2) [5:4]
268  OP_GS_MASK_ = (((1 << OP_GS_WIDTH_) - 1) << OP_SHIFT_),
269  // width(3) [6:4]
278 };
279 
280 enum StreamId : unsigned { // Stream ID, (2) [9:8].
287 };
288 
289 } // namespace SendMsg
290 
291 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
292 
293 enum Id { // HwRegCode, (6) [5:0]
295  ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined.
296  ID_MODE = 1,
299  ID_HW_ID = 4,
308  ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
309 };
310 
311 enum Offset : unsigned { // Offset, (5) [10:6]
316 
319 };
320 
321 enum WidthMinusOne : unsigned { // WidthMinusOne, (5) [15:11]
326 
329 };
330 
331 } // namespace Hwreg
332 
333 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
334 
335 enum Id : unsigned { // id of symbolic names
341 };
342 
343 enum EncBits : unsigned {
344 
345  // swizzle mode encodings
346 
347  QUAD_PERM_ENC = 0x8000,
349 
352 
353  // QUAD_PERM encodings
354 
355  LANE_MASK = 0x3,
358  LANE_NUM = 4,
359 
360  // BITMASK_PERM encodings
361 
362  BITMASK_MASK = 0x1F,
365 
369 };
370 
371 } // namespace Swizzle
372 
373 namespace SDWA {
374 
375 enum SdwaSel : unsigned {
376  BYTE_0 = 0,
377  BYTE_1 = 1,
378  BYTE_2 = 2,
379  BYTE_3 = 3,
380  WORD_0 = 4,
381  WORD_1 = 5,
382  DWORD = 6,
383 };
384 
385 enum DstUnused : unsigned {
389 };
390 
391 enum SDWA9EncValues : unsigned {
392  SRC_SGPR_MASK = 0x100,
396 
403 };
404 
405 } // namespace SDWA
406 
407 namespace DPP {
408 
409 enum DppCtrl : unsigned {
412  DPP_UNUSED1 = 0x100,
413  ROW_SHL0 = 0x100,
414  ROW_SHL_FIRST = 0x101,
415  ROW_SHL_LAST = 0x10F,
416  DPP_UNUSED2 = 0x110,
417  ROW_SHR0 = 0x110,
418  ROW_SHR_FIRST = 0x111,
419  ROW_SHR_LAST = 0x11F,
420  DPP_UNUSED3 = 0x120,
421  ROW_ROR0 = 0x120,
422  ROW_ROR_FIRST = 0x121,
423  ROW_ROR_LAST = 0x12F,
424  WAVE_SHL1 = 0x130,
427  WAVE_ROL1 = 0x134,
430  WAVE_SHR1 = 0x138,
433  WAVE_ROR1 = 0x13C,
436  ROW_MIRROR = 0x140,
438  BCAST15 = 0x142,
439  BCAST31 = 0x143,
441 };
442 
443 } // namespace DPP
444 } // namespace AMDGPU
445 
446 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
447 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
448 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
449 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
450 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
451 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
452 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
453 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
454 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
455 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
456 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
457 
458 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
459 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
460 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
461 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE
462 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
463 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
464 #define C_00B84C_USER_SGPR 0xFFFFFFC1
465 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
466 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
467 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
468 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
469 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
470 #define C_00B84C_TGID_X_EN 0xFFFFFF7F
471 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
472 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
473 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF
474 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
475 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
476 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF
477 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
478 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
479 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
480 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
481 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
482 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
483 /* CIK */
484 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
485 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
486 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
487 /* */
488 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
489 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
490 #define C_00B84C_LDS_SIZE 0xFF007FFF
491 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
492 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
493 #define C_00B84C_EXCP_EN
494 
495 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
496 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
497 
498 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
499 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
500 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
501 #define C_00B848_VGPRS 0xFFFFFFC0
502 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
503 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
504 #define C_00B848_SGPRS 0xFFFFFC3F
505 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
506 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
507 #define C_00B848_PRIORITY 0xFFFFF3FF
508 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
509 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
510 #define C_00B848_FLOAT_MODE 0xFFF00FFF
511 #define S_00B848_PRIV(x) (((x) & 0x1) << 20)
512 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
513 #define C_00B848_PRIV 0xFFEFFFFF
514 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
515 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
516 #define C_00B848_DX10_CLAMP 0xFFDFFFFF
517 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
518 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
519 #define C_00B848_DEBUG_MODE 0xFFBFFFFF
520 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
521 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
522 #define C_00B848_IEEE_MODE 0xFF7FFFFF
523 
524 
525 // Helpers for setting FLOAT_MODE
526 #define FP_ROUND_ROUND_TO_NEAREST 0
527 #define FP_ROUND_ROUND_TO_INF 1
528 #define FP_ROUND_ROUND_TO_NEGINF 2
529 #define FP_ROUND_ROUND_TO_ZERO 3
530 
531 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
532 // precision.
533 #define FP_ROUND_MODE_SP(x) ((x) & 0x3)
534 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
535 
536 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
537 #define FP_DENORM_FLUSH_OUT 1
538 #define FP_DENORM_FLUSH_IN 2
539 #define FP_DENORM_FLUSH_NONE 3
540 
541 
542 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
543 // precision.
544 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
545 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
546 
547 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
548 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
549 
550 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
551 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12)
552 
553 #define R_SPILLED_SGPRS 0x4
554 #define R_SPILLED_VGPRS 0x8
555 } // End namespace llvm
556 
557 #endif
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Operand with 32-bit immediate that uses the constant bus.
Definition: SIDefines.h:148
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned >> Src, R600InstrInfo::BankSwizzle Swz)
Operands with register or 32-bit immediate.
Definition: SIDefines.h:115
Operands with register or inline constant.
Definition: SIDefines.h:123