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SIISelLowering.cpp
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1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Custom DAG lowering for SI
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #if defined(_MSC_VER) || defined(__MINGW32__)
15 // Provide M_PI.
16 #define _USE_MATH_DEFINES
17 #endif
18 
19 #include "SIISelLowering.h"
20 #include "AMDGPU.h"
21 #include "AMDGPUSubtarget.h"
22 #include "AMDGPUTargetMachine.h"
23 #include "SIDefines.h"
24 #include "SIInstrInfo.h"
25 #include "SIMachineFunctionInfo.h"
26 #include "SIRegisterInfo.h"
28 #include "Utils/AMDGPUBaseInfo.h"
29 #include "llvm/ADT/APFloat.h"
30 #include "llvm/ADT/APInt.h"
31 #include "llvm/ADT/ArrayRef.h"
32 #include "llvm/ADT/BitVector.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/StringRef.h"
36 #include "llvm/ADT/StringSwitch.h"
37 #include "llvm/ADT/Twine.h"
38 #include "llvm/CodeGen/Analysis.h"
56 #include "llvm/IR/Constants.h"
57 #include "llvm/IR/DataLayout.h"
58 #include "llvm/IR/DebugLoc.h"
59 #include "llvm/IR/DerivedTypes.h"
60 #include "llvm/IR/DiagnosticInfo.h"
61 #include "llvm/IR/Function.h"
62 #include "llvm/IR/GlobalValue.h"
63 #include "llvm/IR/InstrTypes.h"
64 #include "llvm/IR/Instruction.h"
65 #include "llvm/IR/Instructions.h"
66 #include "llvm/IR/IntrinsicInst.h"
67 #include "llvm/IR/Type.h"
68 #include "llvm/Support/Casting.h"
69 #include "llvm/Support/CodeGen.h"
71 #include "llvm/Support/Compiler.h"
73 #include "llvm/Support/KnownBits.h"
77 #include <cassert>
78 #include <cmath>
79 #include <cstdint>
80 #include <iterator>
81 #include <tuple>
82 #include <utility>
83 #include <vector>
84 
85 using namespace llvm;
86 
87 #define DEBUG_TYPE "si-lower"
88 
89 STATISTIC(NumTailCalls, "Number of tail calls");
90 
92  "amdgpu-vgpr-index-mode",
93  cl::desc("Use GPR indexing mode instead of movrel for vector indexing"),
94  cl::init(false));
95 
97  "amdgpu-disable-loop-alignment",
98  cl::desc("Do not align and prefetch loops"),
99  cl::init(false));
100 
101 static unsigned findFirstFreeSGPR(CCState &CCInfo) {
102  unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
103  for (unsigned Reg = 0; Reg < NumSGPRs; ++Reg) {
104  if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) {
105  return AMDGPU::SGPR0 + Reg;
106  }
107  }
108  llvm_unreachable("Cannot allocate sgpr");
109 }
110 
112  const GCNSubtarget &STI)
113  : AMDGPUTargetLowering(TM, STI),
114  Subtarget(&STI) {
115  addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
116  addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
117 
118  addRegisterClass(MVT::i32, &AMDGPU::SReg_32_XM0RegClass);
119  addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
120 
121  addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
122  addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
123  addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
124 
125  addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass);
126  addRegisterClass(MVT::v3f32, &AMDGPU::VReg_96RegClass);
127 
128  addRegisterClass(MVT::v2i64, &AMDGPU::SReg_128RegClass);
129  addRegisterClass(MVT::v2f64, &AMDGPU::SReg_128RegClass);
130 
131  addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
132  addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
133 
134  addRegisterClass(MVT::v5i32, &AMDGPU::SGPR_160RegClass);
135  addRegisterClass(MVT::v5f32, &AMDGPU::VReg_160RegClass);
136 
137  addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
138  addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
139 
140  addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass);
141  addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
142 
143  if (Subtarget->has16BitInsts()) {
144  addRegisterClass(MVT::i16, &AMDGPU::SReg_32_XM0RegClass);
145  addRegisterClass(MVT::f16, &AMDGPU::SReg_32_XM0RegClass);
146 
147  // Unless there are also VOP3P operations, not operations are really legal.
148  addRegisterClass(MVT::v2i16, &AMDGPU::SReg_32_XM0RegClass);
149  addRegisterClass(MVT::v2f16, &AMDGPU::SReg_32_XM0RegClass);
150  addRegisterClass(MVT::v4i16, &AMDGPU::SReg_64RegClass);
151  addRegisterClass(MVT::v4f16, &AMDGPU::SReg_64RegClass);
152  }
153 
154  if (Subtarget->hasMAIInsts()) {
155  addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
156  addRegisterClass(MVT::v32f32, &AMDGPU::VReg_1024RegClass);
157  }
158 
160 
161  // We need to custom lower vector stores from local memory
170 
179 
191 
194 
199 
205 
210 
213 
222 
229 
232 
235 
239 
240 #if 0
243 #endif
244 
245  // We only support LOAD/STORE and vector manipulation ops for vectors
246  // with > 4 elements.
250  for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
251  switch (Op) {
252  case ISD::LOAD:
253  case ISD::STORE:
254  case ISD::BUILD_VECTOR:
255  case ISD::BITCAST:
261  break;
262  case ISD::CONCAT_VECTORS:
264  break;
265  default:
267  break;
268  }
269  }
270  }
271 
273 
274  // TODO: For dynamic 64-bit vector inserts/extracts, should emit a pseudo that
275  // is expanded to avoid having two separate loops in case the index is a VGPR.
276 
277  // Most operations are naturally 32-bit vector operations. We only support
278  // load and store of i64 vectors, so promote v2i64 vector operations to v4i32.
279  for (MVT Vec64 : { MVT::v2i64, MVT::v2f64 }) {
282 
285 
288 
291  }
292 
297 
300 
301  // Avoid stack access for these.
302  // TODO: Generalize to more vector types.
307 
313 
317 
322 
323  // Deal with vec3 vector operations when widened to vec4.
328 
329  // Deal with vec5 vector operations when widened to vec8.
334 
335  // BUFFER/FLAT_ATOMIC_CMP_SWAP on GCN GPUs needs input marshalling,
336  // and output demarshalling
339 
340  // We can't return success/failure, only the old value,
341  // let LLVM add the comparison
344 
345  if (Subtarget->hasFlatAddressSpace()) {
348  }
349 
352 
353  // On SI this is s_memtime and s_memrealtime on VI.
357 
358  if (Subtarget->has16BitInsts()) {
362  }
363 
364  // v_mad_f32 does not support denormals according to some sources.
365  if (!Subtarget->hasFP32Denormals())
367 
368  if (!Subtarget->hasBFI()) {
369  // fcopysign can be done in a single instruction with BFI.
372  }
373 
374  if (!Subtarget->hasBCNT(32))
376 
377  if (!Subtarget->hasBCNT(64))
379 
380  if (Subtarget->hasFFBH())
382 
383  if (Subtarget->hasFFBL())
385 
386  // We only really have 32-bit BFE instructions (and 16-bit on VI).
387  //
388  // On SI+ there are 64-bit BFEs, but they are scalar only and there isn't any
389  // effort to match them now. We want this to be false for i64 cases when the
390  // extraction isn't restricted to the upper or lower half. Ideally we would
391  // have some pass reduce 64-bit extracts to 32-bit if possible. Extracts that
392  // span the midpoint are probably relatively rare, so don't worry about them
393  // for now.
394  if (Subtarget->hasBFE())
395  setHasExtractBitsInsn(true);
396 
401 
402 
403  // These are really only legal for ieee_mode functions. We should be avoiding
404  // them for functions that don't have ieee_mode enabled, so just say they are
405  // legal.
410 
411 
412  if (Subtarget->haveRoundOpsF64()) {
416  } else {
421  }
422 
424 
429 
430  if (Subtarget->has16BitInsts()) {
432 
435 
438 
441 
444 
449 
452 
458 
460 
462 
464 
466 
471 
476 
477  // F16 - Constant Actions.
479 
480  // F16 - Load/Store Actions.
485 
486  // F16 - VOP1 Actions.
495 
496  // F16 - VOP2 Actions.
499 
501 
502  // F16 - VOP3 Actions.
504  if (!Subtarget->hasFP16Denormals() && STI.hasMadF16())
506 
507  for (MVT VT : {MVT::v2i16, MVT::v2f16, MVT::v4i16, MVT::v4f16}) {
508  for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
509  switch (Op) {
510  case ISD::LOAD:
511  case ISD::STORE:
512  case ISD::BUILD_VECTOR:
513  case ISD::BITCAST:
519  break;
520  case ISD::CONCAT_VECTORS:
522  break;
523  default:
525  break;
526  }
527  }
528  }
529 
530  // XXX - Do these do anything? Vector constants turn into build_vector.
533 
536 
541 
546 
553 
558 
563 
568 
572 
573  if (!Subtarget->hasVOP3PInsts()) {
576  }
577 
579  // This isn't really legal, but this avoids the legalizer unrolling it (and
580  // allows matching fneg (fabs x) patterns)
582 
587 
590 
593  }
594 
595  if (Subtarget->hasVOP3PInsts()) {
606 
610 
613 
615 
618 
621 
628 
633 
637 
640 
644 
648  }
649 
652 
653  if (Subtarget->has16BitInsts()) {
658  } else {
659  // Legalization hack.
662 
665  }
666 
669  }
670 
678 
688 
697 
725 
726  // All memory operations. Some folding on the pointer operand is done to help
727  // matching the constant offsets in the addressing modes.
746 
748 }
749 
751  return Subtarget;
752 }
753 
754 //===----------------------------------------------------------------------===//
755 // TargetLowering queries
756 //===----------------------------------------------------------------------===//
757 
758 // v_mad_mix* support a conversion from f16 to f32.
759 //
760 // There is only one special case when denormals are enabled we don't currently,
761 // where this is OK to use.
763  EVT DestVT, EVT SrcVT) const {
764  return ((Opcode == ISD::FMAD && Subtarget->hasMadMixInsts()) ||
765  (Opcode == ISD::FMA && Subtarget->hasFmaMixInsts())) &&
766  DestVT.getScalarType() == MVT::f32 && !Subtarget->hasFP32Denormals() &&
767  SrcVT.getScalarType() == MVT::f16;
768 }
769 
771  // SI has some legal vector types, but no legal vector operations. Say no
772  // shuffles are legal in order to prefer scalarizing some vector operations.
773  return false;
774 }
775 
777  CallingConv::ID CC,
778  EVT VT) const {
779  if (CC == CallingConv::AMDGPU_KERNEL)
780  return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
781 
782  if (VT.isVector()) {
783  EVT ScalarVT = VT.getScalarType();
784  unsigned Size = ScalarVT.getSizeInBits();
785  if (Size == 32)
786  return ScalarVT.getSimpleVT();
787 
788  if (Size > 32)
789  return MVT::i32;
790 
791  if (Size == 16 && Subtarget->has16BitInsts())
792  return VT.isInteger() ? MVT::v2i16 : MVT::v2f16;
793  } else if (VT.getSizeInBits() > 32)
794  return MVT::i32;
795 
796  return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
797 }
798 
800  CallingConv::ID CC,
801  EVT VT) const {
802  if (CC == CallingConv::AMDGPU_KERNEL)
803  return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
804 
805  if (VT.isVector()) {
806  unsigned NumElts = VT.getVectorNumElements();
807  EVT ScalarVT = VT.getScalarType();
808  unsigned Size = ScalarVT.getSizeInBits();
809 
810  if (Size == 32)
811  return NumElts;
812 
813  if (Size > 32)
814  return NumElts * ((Size + 31) / 32);
815 
816  if (Size == 16 && Subtarget->has16BitInsts())
817  return (NumElts + 1) / 2;
818  } else if (VT.getSizeInBits() > 32)
819  return (VT.getSizeInBits() + 31) / 32;
820 
821  return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
822 }
823 
826  EVT VT, EVT &IntermediateVT,
827  unsigned &NumIntermediates, MVT &RegisterVT) const {
828  if (CC != CallingConv::AMDGPU_KERNEL && VT.isVector()) {
829  unsigned NumElts = VT.getVectorNumElements();
830  EVT ScalarVT = VT.getScalarType();
831  unsigned Size = ScalarVT.getSizeInBits();
832  if (Size == 32) {
833  RegisterVT = ScalarVT.getSimpleVT();
834  IntermediateVT = RegisterVT;
835  NumIntermediates = NumElts;
836  return NumIntermediates;
837  }
838 
839  if (Size > 32) {
840  RegisterVT = MVT::i32;
841  IntermediateVT = RegisterVT;
842  NumIntermediates = NumElts * ((Size + 31) / 32);
843  return NumIntermediates;
844  }
845 
846  // FIXME: We should fix the ABI to be the same on targets without 16-bit
847  // support, but unless we can properly handle 3-vectors, it will be still be
848  // inconsistent.
849  if (Size == 16 && Subtarget->has16BitInsts()) {
850  RegisterVT = VT.isInteger() ? MVT::v2i16 : MVT::v2f16;
851  IntermediateVT = RegisterVT;
852  NumIntermediates = (NumElts + 1) / 2;
853  return NumIntermediates;
854  }
855  }
856 
858  Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
859 }
860 
862  // Only limited forms of aggregate type currently expected.
863  assert(Ty->isStructTy() && "Expected struct type");
864 
865 
866  Type *ElementType = nullptr;
867  unsigned NumElts;
868  if (Ty->getContainedType(0)->isVectorTy()) {
869  VectorType *VecComponent = cast<VectorType>(Ty->getContainedType(0));
870  ElementType = VecComponent->getElementType();
871  NumElts = VecComponent->getNumElements();
872  } else {
873  ElementType = Ty->getContainedType(0);
874  NumElts = 1;
875  }
876 
877  assert((Ty->getContainedType(1) && Ty->getContainedType(1)->isIntegerTy(32)) && "Expected int32 type");
878 
879  // Calculate the size of the memVT type from the aggregate
880  unsigned Pow2Elts = 0;
881  unsigned ElementSize;
882  switch (ElementType->getTypeID()) {
883  default:
884  llvm_unreachable("Unknown type!");
885  case Type::IntegerTyID:
886  ElementSize = cast<IntegerType>(ElementType)->getBitWidth();
887  break;
888  case Type::HalfTyID:
889  ElementSize = 16;
890  break;
891  case Type::FloatTyID:
892  ElementSize = 32;
893  break;
894  }
895  unsigned AdditionalElts = ElementSize == 16 ? 2 : 1;
896  Pow2Elts = 1 << Log2_32_Ceil(NumElts + AdditionalElts);
897 
898  return MVT::getVectorVT(MVT::getVT(ElementType, false),
899  Pow2Elts);
900 }
901 
903  const CallInst &CI,
904  MachineFunction &MF,
905  unsigned IntrID) const {
906  if (const AMDGPU::RsrcIntrinsic *RsrcIntr =
907  AMDGPU::lookupRsrcIntrinsic(IntrID)) {
909  (Intrinsic::ID)IntrID);
910  if (Attr.hasFnAttribute(Attribute::ReadNone))
911  return false;
912 
914 
915  if (RsrcIntr->IsImage) {
916  Info.ptrVal = MFI->getImagePSV(
918  CI.getArgOperand(RsrcIntr->RsrcArg));
919  Info.align.reset();
920  } else {
921  Info.ptrVal = MFI->getBufferPSV(
923  CI.getArgOperand(RsrcIntr->RsrcArg));
924  }
925 
927  if (Attr.hasFnAttribute(Attribute::ReadOnly)) {
929  Info.memVT = MVT::getVT(CI.getType(), true);
930  if (Info.memVT == MVT::Other) {
931  // Some intrinsics return an aggregate type - special case to work out
932  // the correct memVT
933  Info.memVT = memVTFromAggregate(CI.getType());
934  }
936  } else if (Attr.hasFnAttribute(Attribute::WriteOnly)) {
937  Info.opc = ISD::INTRINSIC_VOID;
938  Info.memVT = MVT::getVT(CI.getArgOperand(0)->getType());
940  } else {
941  // Atomic
943  Info.memVT = MVT::getVT(CI.getType());
947 
948  // XXX - Should this be volatile without known ordering?
950  }
951  return true;
952  }
953 
954  switch (IntrID) {
955  case Intrinsic::amdgcn_atomic_inc:
956  case Intrinsic::amdgcn_atomic_dec:
957  case Intrinsic::amdgcn_ds_ordered_add:
958  case Intrinsic::amdgcn_ds_ordered_swap:
959  case Intrinsic::amdgcn_ds_fadd:
960  case Intrinsic::amdgcn_ds_fmin:
961  case Intrinsic::amdgcn_ds_fmax: {
963  Info.memVT = MVT::getVT(CI.getType());
964  Info.ptrVal = CI.getOperand(0);
965  Info.align.reset();
967 
968  const ConstantInt *Vol = cast<ConstantInt>(CI.getOperand(4));
969  if (!Vol->isZero())
971 
972  return true;
973  }
974  case Intrinsic::amdgcn_buffer_atomic_fadd: {
976 
977  Info.opc = ISD::INTRINSIC_VOID;
978  Info.memVT = MVT::getVT(CI.getOperand(0)->getType());
979  Info.ptrVal = MFI->getBufferPSV(
981  CI.getArgOperand(1));
982  Info.align.reset();
984 
985  const ConstantInt *Vol = dyn_cast<ConstantInt>(CI.getOperand(4));
986  if (!Vol || !Vol->isZero())
988 
989  return true;
990  }
991  case Intrinsic::amdgcn_global_atomic_fadd: {
992  Info.opc = ISD::INTRINSIC_VOID;
993  Info.memVT = MVT::getVT(CI.getOperand(0)->getType()
995  Info.ptrVal = CI.getOperand(0);
996  Info.align.reset();
998 
999  return true;
1000  }
1001  case Intrinsic::amdgcn_ds_append:
1002  case Intrinsic::amdgcn_ds_consume: {
1003  Info.opc = ISD::INTRINSIC_W_CHAIN;
1004  Info.memVT = MVT::getVT(CI.getType());
1005  Info.ptrVal = CI.getOperand(0);
1006  Info.align.reset();
1008 
1009  const ConstantInt *Vol = cast<ConstantInt>(CI.getOperand(1));
1010  if (!Vol->isZero())
1012 
1013  return true;
1014  }
1015  case Intrinsic::amdgcn_ds_gws_init:
1016  case Intrinsic::amdgcn_ds_gws_barrier:
1017  case Intrinsic::amdgcn_ds_gws_sema_v:
1018  case Intrinsic::amdgcn_ds_gws_sema_br:
1019  case Intrinsic::amdgcn_ds_gws_sema_p:
1020  case Intrinsic::amdgcn_ds_gws_sema_release_all: {
1021  Info.opc = ISD::INTRINSIC_VOID;
1022 
1024  Info.ptrVal =
1026 
1027  // This is an abstract access, but we need to specify a type and size.
1028  Info.memVT = MVT::i32;
1029  Info.size = 4;
1030  Info.align = Align(4);
1031 
1033  if (IntrID == Intrinsic::amdgcn_ds_gws_barrier)
1035  return true;
1036  }
1037  default:
1038  return false;
1039  }
1040 }
1041 
1044  Type *&AccessTy) const {
1045  switch (II->getIntrinsicID()) {
1046  case Intrinsic::amdgcn_atomic_inc:
1047  case Intrinsic::amdgcn_atomic_dec:
1048  case Intrinsic::amdgcn_ds_ordered_add:
1049  case Intrinsic::amdgcn_ds_ordered_swap:
1050  case Intrinsic::amdgcn_ds_fadd:
1051  case Intrinsic::amdgcn_ds_fmin:
1052  case Intrinsic::amdgcn_ds_fmax: {
1053  Value *Ptr = II->getArgOperand(0);
1054  AccessTy = II->getType();
1055  Ops.push_back(Ptr);
1056  return true;
1057  }
1058  default:
1059  return false;
1060  }
1061 }
1062 
1063 bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {
1064  if (!Subtarget->hasFlatInstOffsets()) {
1065  // Flat instructions do not have offsets, and only have the register
1066  // address.
1067  return AM.BaseOffs == 0 && AM.Scale == 0;
1068  }
1069 
1070  // GFX9 added a 13-bit signed offset. When using regular flat instructions,
1071  // the sign bit is ignored and is treated as a 12-bit unsigned offset.
1072 
1073  // GFX10 shrinked signed offset to 12 bits. When using regular flat
1074  // instructions, the sign bit is also ignored and is treated as 11-bit
1075  // unsigned offset.
1076 
1077  if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10)
1078  return isUInt<11>(AM.BaseOffs) && AM.Scale == 0;
1079 
1080  // Just r + i
1081  return isUInt<12>(AM.BaseOffs) && AM.Scale == 0;
1082 }
1083 
1085  if (Subtarget->hasFlatGlobalInsts())
1086  return isInt<13>(AM.BaseOffs) && AM.Scale == 0;
1087 
1088  if (!Subtarget->hasAddr64() || Subtarget->useFlatForGlobal()) {
1089  // Assume the we will use FLAT for all global memory accesses
1090  // on VI.
1091  // FIXME: This assumption is currently wrong. On VI we still use
1092  // MUBUF instructions for the r + i addressing mode. As currently
1093  // implemented, the MUBUF instructions only work on buffer < 4GB.
1094  // It may be possible to support > 4GB buffers with MUBUF instructions,
1095  // by setting the stride value in the resource descriptor which would
1096  // increase the size limit to (stride * 4GB). However, this is risky,
1097  // because it has never been validated.
1098  return isLegalFlatAddressingMode(AM);
1099  }
1100 
1101  return isLegalMUBUFAddressingMode(AM);
1102 }
1103 
1104 bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {
1105  // MUBUF / MTBUF instructions have a 12-bit unsigned byte offset, and
1106  // additionally can do r + r + i with addr64. 32-bit has more addressing
1107  // mode options. Depending on the resource constant, it can also do
1108  // (i64 r0) + (i32 r1) * (i14 i).
1109  //
1110  // Private arrays end up using a scratch buffer most of the time, so also
1111  // assume those use MUBUF instructions. Scratch loads / stores are currently
1112  // implemented as mubuf instructions with offen bit set, so slightly
1113  // different than the normal addr64.
1114  if (!isUInt<12>(AM.BaseOffs))
1115  return false;
1116 
1117  // FIXME: Since we can split immediate into soffset and immediate offset,
1118  // would it make sense to allow any immediate?
1119 
1120  switch (AM.Scale) {
1121  case 0: // r + i or just i, depending on HasBaseReg.
1122  return true;
1123  case 1:
1124  return true; // We have r + r or r + i.
1125  case 2:
1126  if (AM.HasBaseReg) {
1127  // Reject 2 * r + r.
1128  return false;
1129  }
1130 
1131  // Allow 2 * r as r + r
1132  // Or 2 * r + i is allowed as r + r + i.
1133  return true;
1134  default: // Don't allow n * r
1135  return false;
1136  }
1137 }
1138 
1140  const AddrMode &AM, Type *Ty,
1141  unsigned AS, Instruction *I) const {
1142  // No global is ever allowed as a base.
1143  if (AM.BaseGV)
1144  return false;
1145 
1146  if (AS == AMDGPUAS::GLOBAL_ADDRESS)
1147  return isLegalGlobalAddressingMode(AM);
1148 
1149  if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
1152  // If the offset isn't a multiple of 4, it probably isn't going to be
1153  // correctly aligned.
1154  // FIXME: Can we get the real alignment here?
1155  if (AM.BaseOffs % 4 != 0)
1156  return isLegalMUBUFAddressingMode(AM);
1157 
1158  // There are no SMRD extloads, so if we have to do a small type access we
1159  // will use a MUBUF load.
1160  // FIXME?: We also need to do this if unaligned, but we don't know the
1161  // alignment here.
1162  if (Ty->isSized() && DL.getTypeStoreSize(Ty) < 4)
1163  return isLegalGlobalAddressingMode(AM);
1164 
1165  if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) {
1166  // SMRD instructions have an 8-bit, dword offset on SI.
1167  if (!isUInt<8>(AM.BaseOffs / 4))
1168  return false;
1169  } else if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS) {
1170  // On CI+, this can also be a 32-bit literal constant offset. If it fits
1171  // in 8-bits, it can use a smaller encoding.
1172  if (!isUInt<32>(AM.BaseOffs / 4))
1173  return false;
1174  } else if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
1175  // On VI, these use the SMEM format and the offset is 20-bit in bytes.
1176  if (!isUInt<20>(AM.BaseOffs))
1177  return false;
1178  } else
1179  llvm_unreachable("unhandled generation");
1180 
1181  if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
1182  return true;
1183 
1184  if (AM.Scale == 1 && AM.HasBaseReg)
1185  return true;
1186 
1187  return false;
1188 
1189  } else if (AS == AMDGPUAS::PRIVATE_ADDRESS) {
1190  return isLegalMUBUFAddressingMode(AM);
1191  } else if (AS == AMDGPUAS::LOCAL_ADDRESS ||
1192  AS == AMDGPUAS::REGION_ADDRESS) {
1193  // Basic, single offset DS instructions allow a 16-bit unsigned immediate
1194  // field.
1195  // XXX - If doing a 4-byte aligned 8-byte type access, we effectively have
1196  // an 8-bit dword offset but we don't know the alignment here.
1197  if (!isUInt<16>(AM.BaseOffs))
1198  return false;
1199 
1200  if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
1201  return true;
1202 
1203  if (AM.Scale == 1 && AM.HasBaseReg)
1204  return true;
1205 
1206  return false;
1207  } else if (AS == AMDGPUAS::FLAT_ADDRESS ||
1209  // For an unknown address space, this usually means that this is for some
1210  // reason being used for pure arithmetic, and not based on some addressing
1211  // computation. We don't have instructions that compute pointers with any
1212  // addressing modes, so treat them as having no offset like flat
1213  // instructions.
1214  return isLegalFlatAddressingMode(AM);
1215  } else {
1216  llvm_unreachable("unhandled address space");
1217  }
1218 }
1219 
1220 bool SITargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT,
1221  const SelectionDAG &DAG) const {
1222  if (AS == AMDGPUAS::GLOBAL_ADDRESS || AS == AMDGPUAS::FLAT_ADDRESS) {
1223  return (MemVT.getSizeInBits() <= 4 * 32);
1224  } else if (AS == AMDGPUAS::PRIVATE_ADDRESS) {
1225  unsigned MaxPrivateBits = 8 * getSubtarget()->getMaxPrivateElementSize();
1226  return (MemVT.getSizeInBits() <= MaxPrivateBits);
1227  } else if (AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS) {
1228  return (MemVT.getSizeInBits() <= 2 * 32);
1229  }
1230  return true;
1231 }
1232 
1234  unsigned Size, unsigned AddrSpace, unsigned Align,
1235  MachineMemOperand::Flags Flags, bool *IsFast) const {
1236  if (IsFast)
1237  *IsFast = false;
1238 
1239  if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
1240  AddrSpace == AMDGPUAS::REGION_ADDRESS) {
1241  // ds_read/write_b64 require 8-byte alignment, but we can do a 4 byte
1242  // aligned, 8 byte access in a single operation using ds_read2/write2_b32
1243  // with adjacent offsets.
1244  bool AlignedBy4 = (Align % 4 == 0);
1245  if (IsFast)
1246  *IsFast = AlignedBy4;
1247 
1248  return AlignedBy4;
1249  }
1250 
1251  // FIXME: We have to be conservative here and assume that flat operations
1252  // will access scratch. If we had access to the IR function, then we
1253  // could determine if any private memory was used in the function.
1254  if (!Subtarget->hasUnalignedScratchAccess() &&
1255  (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
1256  AddrSpace == AMDGPUAS::FLAT_ADDRESS)) {
1257  bool AlignedBy4 = Align >= 4;
1258  if (IsFast)
1259  *IsFast = AlignedBy4;
1260 
1261  return AlignedBy4;
1262  }
1263 
1264  if (Subtarget->hasUnalignedBufferAccess()) {
1265  // If we have an uniform constant load, it still requires using a slow
1266  // buffer instruction if unaligned.
1267  if (IsFast) {
1268  *IsFast = (AddrSpace == AMDGPUAS::CONSTANT_ADDRESS ||
1269  AddrSpace == AMDGPUAS::CONSTANT_ADDRESS_32BIT) ?
1270  (Align % 4 == 0) : true;
1271  }
1272 
1273  return true;
1274  }
1275 
1276  // Smaller than dword value must be aligned.
1277  if (Size < 32)
1278  return false;
1279 
1280  // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
1281  // byte-address are ignored, thus forcing Dword alignment.
1282  // This applies to private, global, and constant memory.
1283  if (IsFast)
1284  *IsFast = true;
1285 
1286  return Size >= 32 && Align >= 4;
1287 }
1288 
1290  EVT VT, unsigned AddrSpace, unsigned Align, MachineMemOperand::Flags Flags,
1291  bool *IsFast) const {
1292  if (IsFast)
1293  *IsFast = false;
1294 
1295  // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
1296  // which isn't a simple VT.
1297  // Until MVT is extended to handle this, simply check for the size and
1298  // rely on the condition below: allow accesses if the size is a multiple of 4.
1299  if (VT == MVT::Other || (VT != MVT::Other && VT.getSizeInBits() > 1024 &&
1300  VT.getStoreSize() > 16)) {
1301  return false;
1302  }
1303 
1304  return allowsMisalignedMemoryAccessesImpl(VT.getSizeInBits(), AddrSpace,
1305  Align, Flags, IsFast);
1306 }
1307 
1309  uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset,
1310  bool ZeroMemset, bool MemcpyStrSrc,
1311  const AttributeList &FuncAttributes) const {
1312  // FIXME: Should account for address space here.
1313 
1314  // The default fallback uses the private pointer size as a guess for a type to
1315  // use. Make sure we switch these to 64-bit accesses.
1316 
1317  if (Size >= 16 && DstAlign >= 4) // XXX: Should only do for global
1318  return MVT::v4i32;
1319 
1320  if (Size >= 8 && DstAlign >= 4)
1321  return MVT::v2i32;
1322 
1323  // Use the default.
1324  return MVT::Other;
1325 }
1326 
1327 static bool isFlatGlobalAddrSpace(unsigned AS) {
1328  return AS == AMDGPUAS::GLOBAL_ADDRESS ||
1329  AS == AMDGPUAS::FLAT_ADDRESS ||
1332 }
1333 
1335  unsigned DestAS) const {
1336  return isFlatGlobalAddrSpace(SrcAS) && isFlatGlobalAddrSpace(DestAS);
1337 }
1338 
1340  const MemSDNode *MemNode = cast<MemSDNode>(N);
1341  const Value *Ptr = MemNode->getMemOperand()->getValue();
1342  const Instruction *I = dyn_cast_or_null<Instruction>(Ptr);
1343  return I && I->getMetadata("amdgpu.noclobber");
1344 }
1345 
1347  unsigned DestAS) const {
1348  // Flat -> private/local is a simple truncate.
1349  // Flat -> global is no-op
1350  if (SrcAS == AMDGPUAS::FLAT_ADDRESS)
1351  return true;
1352 
1353  return isNoopAddrSpaceCast(SrcAS, DestAS);
1354 }
1355 
1357  const MemSDNode *MemNode = cast<MemSDNode>(N);
1358 
1359  return AMDGPUInstrInfo::isUniformMMO(MemNode->getMemOperand());
1360 }
1361 
1364  int NumElts = VT.getVectorNumElements();
1365  if (NumElts != 1 && VT.getScalarType().bitsLE(MVT::i16))
1368 }
1369 
1371  Type *Ty) const {
1372  // FIXME: Could be smarter if called for vector constants.
1373  return true;
1374 }
1375 
1377  if (Subtarget->has16BitInsts() && VT == MVT::i16) {
1378  switch (Op) {
1379  case ISD::LOAD:
1380  case ISD::STORE:
1381 
1382  // These operations are done with 32-bit instructions anyway.
1383  case ISD::AND:
1384  case ISD::OR:
1385  case ISD::XOR:
1386  case ISD::SELECT:
1387  // TODO: Extensions?
1388  return true;
1389  default:
1390  return false;
1391  }
1392  }
1393 
1394  // SimplifySetCC uses this function to determine whether or not it should
1395  // create setcc with i1 operands. We don't have instructions for i1 setcc.
1396  if (VT == MVT::i1 && Op == ISD::SETCC)
1397  return false;
1398 
1399  return TargetLowering::isTypeDesirableForOp(Op, VT);
1400 }
1401 
1402 SDValue SITargetLowering::lowerKernArgParameterPtr(SelectionDAG &DAG,
1403  const SDLoc &SL,
1404  SDValue Chain,
1405  uint64_t Offset) const {
1406  const DataLayout &DL = DAG.getDataLayout();
1407  MachineFunction &MF = DAG.getMachineFunction();
1409 
1410  const ArgDescriptor *InputPtrReg;
1411  const TargetRegisterClass *RC;
1412 
1413  std::tie(InputPtrReg, RC)
1415 
1418  SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
1419  MRI.getLiveInVirtReg(InputPtrReg->getRegister()), PtrVT);
1420 
1421  return DAG.getObjectPtrOffset(SL, BasePtr, Offset);
1422 }
1423 
1424 SDValue SITargetLowering::getImplicitArgPtr(SelectionDAG &DAG,
1425  const SDLoc &SL) const {
1426  uint64_t Offset = getImplicitParameterOffset(DAG.getMachineFunction(),
1427  FIRST_IMPLICIT);
1428  return lowerKernArgParameterPtr(DAG, SL, DAG.getEntryNode(), Offset);
1429 }
1430 
1431 SDValue SITargetLowering::convertArgType(SelectionDAG &DAG, EVT VT, EVT MemVT,
1432  const SDLoc &SL, SDValue Val,
1433  bool Signed,
1434  const ISD::InputArg *Arg) const {
1435  // First, if it is a widened vector, narrow it.
1436  if (VT.isVector() &&
1437  VT.getVectorNumElements() != MemVT.getVectorNumElements()) {
1438  EVT NarrowedVT =
1440  VT.getVectorNumElements());
1441  Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, NarrowedVT, Val,
1442  DAG.getConstant(0, SL, MVT::i32));
1443  }
1444 
1445  // Then convert the vector elements or scalar value.
1446  if (Arg && (Arg->Flags.isSExt() || Arg->Flags.isZExt()) &&
1447  VT.bitsLT(MemVT)) {
1448  unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext;
1449  Val = DAG.getNode(Opc, SL, MemVT, Val, DAG.getValueType(VT));
1450  }
1451 
1452  if (MemVT.isFloatingPoint())
1453  Val = getFPExtOrFPTrunc(DAG, Val, SL, VT);
1454  else if (Signed)
1455  Val = DAG.getSExtOrTrunc(Val, SL, VT);
1456  else
1457  Val = DAG.getZExtOrTrunc(Val, SL, VT);
1458 
1459  return Val;
1460 }
1461 
1462 SDValue SITargetLowering::lowerKernargMemParameter(
1463  SelectionDAG &DAG, EVT VT, EVT MemVT,
1464  const SDLoc &SL, SDValue Chain,
1465  uint64_t Offset, unsigned Align, bool Signed,
1466  const ISD::InputArg *Arg) const {
1467  Type *Ty = MemVT.getTypeForEVT(*DAG.getContext());
1469  MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
1470 
1471  // Try to avoid using an extload by loading earlier than the argument address,
1472  // and extracting the relevant bits. The load should hopefully be merged with
1473  // the previous argument.
1474  if (MemVT.getStoreSize() < 4 && Align < 4) {
1475  // TODO: Handle align < 4 and size >= 4 (can happen with packed structs).
1476  int64_t AlignDownOffset = alignDown(Offset, 4);
1477  int64_t OffsetDiff = Offset - AlignDownOffset;
1478 
1479  EVT IntVT = MemVT.changeTypeToInteger();
1480 
1481  // TODO: If we passed in the base kernel offset we could have a better
1482  // alignment than 4, but we don't really need it.
1483  SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, AlignDownOffset);
1484  SDValue Load = DAG.getLoad(MVT::i32, SL, Chain, Ptr, PtrInfo, 4,
1487 
1488  SDValue ShiftAmt = DAG.getConstant(OffsetDiff * 8, SL, MVT::i32);
1489  SDValue Extract = DAG.getNode(ISD::SRL, SL, MVT::i32, Load, ShiftAmt);
1490 
1491  SDValue ArgVal = DAG.getNode(ISD::TRUNCATE, SL, IntVT, Extract);
1492  ArgVal = DAG.getNode(ISD::BITCAST, SL, MemVT, ArgVal);
1493  ArgVal = convertArgType(DAG, VT, MemVT, SL, ArgVal, Signed, Arg);
1494 
1495 
1496  return DAG.getMergeValues({ ArgVal, Load.getValue(1) }, SL);
1497  }
1498 
1499  SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, Offset);
1500  SDValue Load = DAG.getLoad(MemVT, SL, Chain, Ptr, PtrInfo, Align,
1503 
1504  SDValue Val = convertArgType(DAG, VT, MemVT, SL, Load, Signed, Arg);
1505  return DAG.getMergeValues({ Val, Load.getValue(1) }, SL);
1506 }
1507 
1508 SDValue SITargetLowering::lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
1509  const SDLoc &SL, SDValue Chain,
1510  const ISD::InputArg &Arg) const {
1511  MachineFunction &MF = DAG.getMachineFunction();
1512  MachineFrameInfo &MFI = MF.getFrameInfo();
1513 
1514  if (Arg.Flags.isByVal()) {
1515  unsigned Size = Arg.Flags.getByValSize();
1516  int FrameIdx = MFI.CreateFixedObject(Size, VA.getLocMemOffset(), false);
1517  return DAG.getFrameIndex(FrameIdx, MVT::i32);
1518  }
1519 
1520  unsigned ArgOffset = VA.getLocMemOffset();
1521  unsigned ArgSize = VA.getValVT().getStoreSize();
1522 
1523  int FI = MFI.CreateFixedObject(ArgSize, ArgOffset, true);
1524 
1525  // Create load nodes to retrieve arguments from the stack.
1526  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1527  SDValue ArgValue;
1528 
1529  // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
1531  MVT MemVT = VA.getValVT();
1532 
1533  switch (VA.getLocInfo()) {
1534  default:
1535  break;
1536  case CCValAssign::BCvt:
1537  MemVT = VA.getLocVT();
1538  break;
1539  case CCValAssign::SExt:
1540  ExtType = ISD::SEXTLOAD;
1541  break;
1542  case CCValAssign::ZExt:
1543  ExtType = ISD::ZEXTLOAD;
1544  break;
1545  case CCValAssign::AExt:
1546  ExtType = ISD::EXTLOAD;
1547  break;
1548  }
1549 
1550  ArgValue = DAG.getExtLoad(
1551  ExtType, SL, VA.getLocVT(), Chain, FIN,
1553  MemVT);
1554  return ArgValue;
1555 }
1556 
1557 SDValue SITargetLowering::getPreloadedValue(SelectionDAG &DAG,
1558  const SIMachineFunctionInfo &MFI,
1559  EVT VT,
1561  const ArgDescriptor *Reg;
1562  const TargetRegisterClass *RC;
1563 
1564  std::tie(Reg, RC) = MFI.getPreloadedValue(PVID);
1565  return CreateLiveInRegister(DAG, RC, Reg->getRegister(), VT);
1566 }
1567 
1569  CallingConv::ID CallConv,
1571  BitVector &Skipped,
1572  FunctionType *FType,
1574  for (unsigned I = 0, E = Ins.size(), PSInputNum = 0; I != E; ++I) {
1575  const ISD::InputArg *Arg = &Ins[I];
1576 
1577  assert((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) &&
1578  "vector type argument should have been split");
1579 
1580  // First check if it's a PS input addr.
1581  if (CallConv == CallingConv::AMDGPU_PS &&
1582  !Arg->Flags.isInReg() && PSInputNum <= 15) {
1583  bool SkipArg = !Arg->Used && !Info->isPSInputAllocated(PSInputNum);
1584 
1585  // Inconveniently only the first part of the split is marked as isSplit,
1586  // so skip to the end. We only want to increment PSInputNum once for the
1587  // entire split argument.
1588  if (Arg->Flags.isSplit()) {
1589  while (!Arg->Flags.isSplitEnd()) {
1590  assert((!Arg->VT.isVector() ||
1591  Arg->VT.getScalarSizeInBits() == 16) &&
1592  "unexpected vector split in ps argument type");
1593  if (!SkipArg)
1594  Splits.push_back(*Arg);
1595  Arg = &Ins[++I];
1596  }
1597  }
1598 
1599  if (SkipArg) {
1600  // We can safely skip PS inputs.
1601  Skipped.set(Arg->getOrigArgIndex());
1602  ++PSInputNum;
1603  continue;
1604  }
1605 
1606  Info->markPSInputAllocated(PSInputNum);
1607  if (Arg->Used)
1608  Info->markPSInputEnabled(PSInputNum);
1609 
1610  ++PSInputNum;
1611  }
1612 
1613  Splits.push_back(*Arg);
1614  }
1615 }
1616 
1617 // Allocate special inputs passed in VGPRs.
1619  MachineFunction &MF,
1620  const SIRegisterInfo &TRI,
1621  SIMachineFunctionInfo &Info) const {
1622  const LLT S32 = LLT::scalar(32);
1624 
1625  if (Info.hasWorkItemIDX()) {
1626  Register Reg = AMDGPU::VGPR0;
1627  MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1628 
1629  CCInfo.AllocateReg(Reg);
1631  }
1632 
1633  if (Info.hasWorkItemIDY()) {
1634  Register Reg = AMDGPU::VGPR1;
1635  MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1636 
1637  CCInfo.AllocateReg(Reg);
1639  }
1640 
1641  if (Info.hasWorkItemIDZ()) {
1642  Register Reg = AMDGPU::VGPR2;
1643  MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1644 
1645  CCInfo.AllocateReg(Reg);
1647  }
1648 }
1649 
1650 // Try to allocate a VGPR at the end of the argument list, or if no argument
1651 // VGPRs are left allocating a stack slot.
1652 // If \p Mask is is given it indicates bitfield position in the register.
1653 // If \p Arg is given use it with new ]p Mask instead of allocating new.
1654 static ArgDescriptor allocateVGPR32Input(CCState &CCInfo, unsigned Mask = ~0u,
1655  ArgDescriptor Arg = ArgDescriptor()) {
1656  if (Arg.isSet())
1657  return ArgDescriptor::createArg(Arg, Mask);
1658 
1659  ArrayRef<MCPhysReg> ArgVGPRs
1660  = makeArrayRef(AMDGPU::VGPR_32RegClass.begin(), 32);
1661  unsigned RegIdx = CCInfo.getFirstUnallocated(ArgVGPRs);
1662  if (RegIdx == ArgVGPRs.size()) {
1663  // Spill to stack required.
1664  int64_t Offset = CCInfo.AllocateStack(4, 4);
1665 
1666  return ArgDescriptor::createStack(Offset, Mask);
1667  }
1668 
1669  unsigned Reg = ArgVGPRs[RegIdx];
1670  Reg = CCInfo.AllocateReg(Reg);
1671  assert(Reg != AMDGPU::NoRegister);
1672 
1673  MachineFunction &MF = CCInfo.getMachineFunction();
1674  Register LiveInVReg = MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
1675  MF.getRegInfo().setType(LiveInVReg, LLT::scalar(32));
1676  return ArgDescriptor::createRegister(Reg, Mask);
1677 }
1678 
1680  const TargetRegisterClass *RC,
1681  unsigned NumArgRegs) {
1682  ArrayRef<MCPhysReg> ArgSGPRs = makeArrayRef(RC->begin(), 32);
1683  unsigned RegIdx = CCInfo.getFirstUnallocated(ArgSGPRs);
1684  if (RegIdx == ArgSGPRs.size())
1685  report_fatal_error("ran out of SGPRs for arguments");
1686 
1687  unsigned Reg = ArgSGPRs[RegIdx];
1688  Reg = CCInfo.AllocateReg(Reg);
1689  assert(Reg != AMDGPU::NoRegister);
1690 
1691  MachineFunction &MF = CCInfo.getMachineFunction();
1692  MF.addLiveIn(Reg, RC);
1693  return ArgDescriptor::createRegister(Reg);
1694 }
1695 
1697  return allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_32RegClass, 32);
1698 }
1699 
1701  return allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_64RegClass, 16);
1702 }
1703 
1705  MachineFunction &MF,
1706  const SIRegisterInfo &TRI,
1707  SIMachineFunctionInfo &Info) const {
1708  const unsigned Mask = 0x3ff;
1710 
1711  if (Info.hasWorkItemIDX()) {
1712  Arg = allocateVGPR32Input(CCInfo, Mask);
1713  Info.setWorkItemIDX(Arg);
1714  }
1715 
1716  if (Info.hasWorkItemIDY()) {
1717  Arg = allocateVGPR32Input(CCInfo, Mask << 10, Arg);
1718  Info.setWorkItemIDY(Arg);
1719  }
1720 
1721  if (Info.hasWorkItemIDZ())
1722  Info.setWorkItemIDZ(allocateVGPR32Input(CCInfo, Mask << 20, Arg));
1723 }
1724 
1726  CCState &CCInfo,
1727  MachineFunction &MF,
1728  const SIRegisterInfo &TRI,
1729  SIMachineFunctionInfo &Info) const {
1730  auto &ArgInfo = Info.getArgInfo();
1731 
1732  // TODO: Unify handling with private memory pointers.
1733 
1734  if (Info.hasDispatchPtr())
1735  ArgInfo.DispatchPtr = allocateSGPR64Input(CCInfo);
1736 
1737  if (Info.hasQueuePtr())
1738  ArgInfo.QueuePtr = allocateSGPR64Input(CCInfo);
1739 
1740  if (Info.hasKernargSegmentPtr())
1741  ArgInfo.KernargSegmentPtr = allocateSGPR64Input(CCInfo);
1742 
1743  if (Info.hasDispatchID())
1744  ArgInfo.DispatchID = allocateSGPR64Input(CCInfo);
1745 
1746  // flat_scratch_init is not applicable for non-kernel functions.
1747 
1748  if (Info.hasWorkGroupIDX())
1749  ArgInfo.WorkGroupIDX = allocateSGPR32Input(CCInfo);
1750 
1751  if (Info.hasWorkGroupIDY())
1752  ArgInfo.WorkGroupIDY = allocateSGPR32Input(CCInfo);
1753 
1754  if (Info.hasWorkGroupIDZ())
1755  ArgInfo.WorkGroupIDZ = allocateSGPR32Input(CCInfo);
1756 
1757  if (Info.hasImplicitArgPtr())
1758  ArgInfo.ImplicitArgPtr = allocateSGPR64Input(CCInfo);
1759 }
1760 
1761 // Allocate special inputs passed in user SGPRs.
1763  MachineFunction &MF,
1764  const SIRegisterInfo &TRI,
1765  SIMachineFunctionInfo &Info) const {
1766  if (Info.hasImplicitBufferPtr()) {
1767  unsigned ImplicitBufferPtrReg = Info.addImplicitBufferPtr(TRI);
1768  MF.addLiveIn(ImplicitBufferPtrReg, &AMDGPU::SGPR_64RegClass);
1769  CCInfo.AllocateReg(ImplicitBufferPtrReg);
1770  }
1771 
1772  // FIXME: How should these inputs interact with inreg / custom SGPR inputs?
1773  if (Info.hasPrivateSegmentBuffer()) {
1774  unsigned PrivateSegmentBufferReg = Info.addPrivateSegmentBuffer(TRI);
1775  MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SGPR_128RegClass);
1776  CCInfo.AllocateReg(PrivateSegmentBufferReg);
1777  }
1778 
1779  if (Info.hasDispatchPtr()) {
1780  unsigned DispatchPtrReg = Info.addDispatchPtr(TRI);
1781  MF.addLiveIn(DispatchPtrReg, &AMDGPU::SGPR_64RegClass);
1782  CCInfo.AllocateReg(DispatchPtrReg);
1783  }
1784 
1785  if (Info.hasQueuePtr()) {
1786  unsigned QueuePtrReg = Info.addQueuePtr(TRI);
1787  MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass);
1788  CCInfo.AllocateReg(QueuePtrReg);
1789  }
1790 
1791  if (Info.hasKernargSegmentPtr()) {
1793  Register InputPtrReg = Info.addKernargSegmentPtr(TRI);
1794  CCInfo.AllocateReg(InputPtrReg);
1795 
1796  Register VReg = MF.addLiveIn(InputPtrReg, &AMDGPU::SGPR_64RegClass);
1798  }
1799 
1800  if (Info.hasDispatchID()) {
1801  unsigned DispatchIDReg = Info.addDispatchID(TRI);
1802  MF.addLiveIn(DispatchIDReg, &AMDGPU::SGPR_64RegClass);
1803  CCInfo.AllocateReg(DispatchIDReg);
1804  }
1805 
1806  if (Info.hasFlatScratchInit()) {
1807  unsigned FlatScratchInitReg = Info.addFlatScratchInit(TRI);
1808  MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass);
1809  CCInfo.AllocateReg(FlatScratchInitReg);
1810  }
1811 
1812  // TODO: Add GridWorkGroupCount user SGPRs when used. For now with HSA we read
1813  // these from the dispatch pointer.
1814 }
1815 
1816 // Allocate special input registers that are initialized per-wave.
1818  MachineFunction &MF,
1820  CallingConv::ID CallConv,
1821  bool IsShader) const {
1822  if (Info.hasWorkGroupIDX()) {
1823  unsigned Reg = Info.addWorkGroupIDX();
1824  MF.addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass);
1825  CCInfo.AllocateReg(Reg);
1826  }
1827 
1828  if (Info.hasWorkGroupIDY()) {
1829  unsigned Reg = Info.addWorkGroupIDY();
1830  MF.addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass);
1831  CCInfo.AllocateReg(Reg);
1832  }
1833 
1834  if (Info.hasWorkGroupIDZ()) {
1835  unsigned Reg = Info.addWorkGroupIDZ();
1836  MF.addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass);
1837  CCInfo.AllocateReg(Reg);
1838  }
1839 
1840  if (Info.hasWorkGroupInfo()) {
1841  unsigned Reg = Info.addWorkGroupInfo();
1842  MF.addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass);
1843  CCInfo.AllocateReg(Reg);
1844  }
1845 
1846  if (Info.hasPrivateSegmentWaveByteOffset()) {
1847  // Scratch wave offset passed in system SGPR.
1848  unsigned PrivateSegmentWaveByteOffsetReg;
1849 
1850  if (IsShader) {
1851  PrivateSegmentWaveByteOffsetReg =
1853 
1854  // This is true if the scratch wave byte offset doesn't have a fixed
1855  // location.
1856  if (PrivateSegmentWaveByteOffsetReg == AMDGPU::NoRegister) {
1857  PrivateSegmentWaveByteOffsetReg = findFirstFreeSGPR(CCInfo);
1858  Info.setPrivateSegmentWaveByteOffset(PrivateSegmentWaveByteOffsetReg);
1859  }
1860  } else
1861  PrivateSegmentWaveByteOffsetReg = Info.addPrivateSegmentWaveByteOffset();
1862 
1863  MF.addLiveIn(PrivateSegmentWaveByteOffsetReg, &AMDGPU::SGPR_32RegClass);
1864  CCInfo.AllocateReg(PrivateSegmentWaveByteOffsetReg);
1865  }
1866 }
1867 
1869  MachineFunction &MF,
1870  const SIRegisterInfo &TRI,
1872  // Now that we've figured out where the scratch register inputs are, see if
1873  // should reserve the arguments and use them directly.
1874  MachineFrameInfo &MFI = MF.getFrameInfo();
1875  bool HasStackObjects = MFI.hasStackObjects();
1876  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1877 
1878  // Record that we know we have non-spill stack objects so we don't need to
1879  // check all stack objects later.
1880  if (HasStackObjects)
1881  Info.setHasNonSpillStackObjects(true);
1882 
1883  // Everything live out of a block is spilled with fast regalloc, so it's
1884  // almost certain that spilling will be required.
1885  if (TM.getOptLevel() == CodeGenOpt::None)
1886  HasStackObjects = true;
1887 
1888  // For now assume stack access is needed in any callee functions, so we need
1889  // the scratch registers to pass in.
1890  bool RequiresStackAccess = HasStackObjects || MFI.hasCalls();
1891 
1892  if (RequiresStackAccess && ST.isAmdHsaOrMesa(MF.getFunction())) {
1893  // If we have stack objects, we unquestionably need the private buffer
1894  // resource. For the Code Object V2 ABI, this will be the first 4 user
1895  // SGPR inputs. We can reserve those and use them directly.
1896 
1897  Register PrivateSegmentBufferReg =
1899  Info.setScratchRSrcReg(PrivateSegmentBufferReg);
1900  } else {
1901  unsigned ReservedBufferReg = TRI.reservedPrivateSegmentBufferReg(MF);
1902  // We tentatively reserve the last registers (skipping the last registers
1903  // which may contain VCC, FLAT_SCR, and XNACK). After register allocation,
1904  // we'll replace these with the ones immediately after those which were
1905  // really allocated. In the prologue copies will be inserted from the
1906  // argument to these reserved registers.
1907 
1908  // Without HSA, relocations are used for the scratch pointer and the
1909  // buffer resource setup is always inserted in the prologue. Scratch wave
1910  // offset is still in an input SGPR.
1911  Info.setScratchRSrcReg(ReservedBufferReg);
1912  }
1913 
1914  // hasFP should be accurate for kernels even before the frame is finalized.
1915  if (ST.getFrameLowering()->hasFP(MF)) {
1917 
1918  // Try to use s32 as the SP, but move it if it would interfere with input
1919  // arguments. This won't work with calls though.
1920  //
1921  // FIXME: Move SP to avoid any possible inputs, or find a way to spill input
1922  // registers.
1923  if (!MRI.isLiveIn(AMDGPU::SGPR32)) {
1924  Info.setStackPtrOffsetReg(AMDGPU::SGPR32);
1925  } else {
1927 
1928  if (MFI.hasCalls())
1929  report_fatal_error("call in graphics shader with too many input SGPRs");
1930 
1931  for (unsigned Reg : AMDGPU::SGPR_32RegClass) {
1932  if (!MRI.isLiveIn(Reg)) {
1933  Info.setStackPtrOffsetReg(Reg);
1934  break;
1935  }
1936  }
1937 
1938  if (Info.getStackPtrOffsetReg() == AMDGPU::SP_REG)
1939  report_fatal_error("failed to find register for SP");
1940  }
1941 
1942  if (MFI.hasCalls()) {
1943  Info.setScratchWaveOffsetReg(AMDGPU::SGPR33);
1944  Info.setFrameOffsetReg(AMDGPU::SGPR33);
1945  } else {
1946  unsigned ReservedOffsetReg =
1948  Info.setScratchWaveOffsetReg(ReservedOffsetReg);
1949  Info.setFrameOffsetReg(ReservedOffsetReg);
1950  }
1951  } else if (RequiresStackAccess) {
1952  assert(!MFI.hasCalls());
1953  // We know there are accesses and they will be done relative to SP, so just
1954  // pin it to the input.
1955  //
1956  // FIXME: Should not do this if inline asm is reading/writing these
1957  // registers.
1958  Register PreloadedSP = Info.getPreloadedReg(
1960 
1961  Info.setStackPtrOffsetReg(PreloadedSP);
1962  Info.setScratchWaveOffsetReg(PreloadedSP);
1963  Info.setFrameOffsetReg(PreloadedSP);
1964  } else {
1965  assert(!MFI.hasCalls());
1966 
1967  // There may not be stack access at all. There may still be spills, or
1968  // access of a constant pointer (in which cases an extra copy will be
1969  // emitted in the prolog).
1970  unsigned ReservedOffsetReg
1972  Info.setStackPtrOffsetReg(ReservedOffsetReg);
1973  Info.setScratchWaveOffsetReg(ReservedOffsetReg);
1974  Info.setFrameOffsetReg(ReservedOffsetReg);
1975  }
1976 }
1977 
1980  return !Info->isEntryFunction();
1981 }
1982 
1984 
1985 }
1986 
1989  const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
1991 
1992  const MCPhysReg *IStart = TRI->getCalleeSavedRegsViaCopy(Entry->getParent());
1993  if (!IStart)
1994  return;
1995 
1996  const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1997  MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();
1998  MachineBasicBlock::iterator MBBI = Entry->begin();
1999  for (const MCPhysReg *I = IStart; *I; ++I) {
2000  const TargetRegisterClass *RC = nullptr;
2001  if (AMDGPU::SReg_64RegClass.contains(*I))
2002  RC = &AMDGPU::SGPR_64RegClass;
2003  else if (AMDGPU::SReg_32RegClass.contains(*I))
2004  RC = &AMDGPU::SGPR_32RegClass;
2005  else
2006  llvm_unreachable("Unexpected register class in CSRsViaCopy!");
2007 
2008  Register NewVR = MRI->createVirtualRegister(RC);
2009  // Create copy from CSR to a virtual register.
2010  Entry->addLiveIn(*I);
2011  BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
2012  .addReg(*I);
2013 
2014  // Insert the copy-back instructions right before the terminator.
2015  for (auto *Exit : Exits)
2016  BuildMI(*Exit, Exit->getFirstTerminator(), DebugLoc(),
2017  TII->get(TargetOpcode::COPY), *I)
2018  .addReg(NewVR);
2019  }
2020 }
2021 
2023  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2024  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
2025  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
2027 
2028  MachineFunction &MF = DAG.getMachineFunction();
2029  const Function &Fn = MF.getFunction();
2030  FunctionType *FType = MF.getFunction().getFunctionType();
2032 
2033  if (Subtarget->isAmdHsaOS() && AMDGPU::isShader(CallConv)) {
2034  DiagnosticInfoUnsupported NoGraphicsHSA(
2035  Fn, "unsupported non-compute shaders with HSA", DL.getDebugLoc());
2036  DAG.getContext()->diagnose(NoGraphicsHSA);
2037  return DAG.getEntryNode();
2038  }
2039 
2042  BitVector Skipped(Ins.size());
2043  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2044  *DAG.getContext());
2045 
2046  bool IsShader = AMDGPU::isShader(CallConv);
2047  bool IsKernel = AMDGPU::isKernel(CallConv);
2048  bool IsEntryFunc = AMDGPU::isEntryFunctionCC(CallConv);
2049 
2050  if (IsShader) {
2051  processShaderInputArgs(Splits, CallConv, Ins, Skipped, FType, Info);
2052 
2053  // At least one interpolation mode must be enabled or else the GPU will
2054  // hang.
2055  //
2056  // Check PSInputAddr instead of PSInputEnable. The idea is that if the user
2057  // set PSInputAddr, the user wants to enable some bits after the compilation
2058  // based on run-time states. Since we can't know what the final PSInputEna
2059  // will look like, so we shouldn't do anything here and the user should take
2060  // responsibility for the correct programming.
2061  //
2062  // Otherwise, the following restrictions apply:
2063  // - At least one of PERSP_* (0xF) or LINEAR_* (0x70) must be enabled.
2064  // - If POS_W_FLOAT (11) is enabled, at least one of PERSP_* must be
2065  // enabled too.
2066  if (CallConv == CallingConv::AMDGPU_PS) {
2067  if ((Info->getPSInputAddr() & 0x7F) == 0 ||
2068  ((Info->getPSInputAddr() & 0xF) == 0 &&
2069  Info->isPSInputAllocated(11))) {
2070  CCInfo.AllocateReg(AMDGPU::VGPR0);
2071  CCInfo.AllocateReg(AMDGPU::VGPR1);
2072  Info->markPSInputAllocated(0);
2073  Info->markPSInputEnabled(0);
2074  }
2075  if (Subtarget->isAmdPalOS()) {
2076  // For isAmdPalOS, the user does not enable some bits after compilation
2077  // based on run-time states; the register values being generated here are
2078  // the final ones set in hardware. Therefore we need to apply the
2079  // workaround to PSInputAddr and PSInputEnable together. (The case where
2080  // a bit is set in PSInputAddr but not PSInputEnable is where the
2081  // frontend set up an input arg for a particular interpolation mode, but
2082  // nothing uses that input arg. Really we should have an earlier pass
2083  // that removes such an arg.)
2084  unsigned PsInputBits = Info->getPSInputAddr() & Info->getPSInputEnable();
2085  if ((PsInputBits & 0x7F) == 0 ||
2086  ((PsInputBits & 0xF) == 0 &&
2087  (PsInputBits >> 11 & 1)))
2088  Info->markPSInputEnabled(
2090  }
2091  }
2092 
2093  assert(!Info->hasDispatchPtr() &&
2094  !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() &&
2095  !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&
2096  !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() &&
2097  !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() &&
2098  !Info->hasWorkItemIDZ());
2099  } else if (IsKernel) {
2100  assert(Info->hasWorkGroupIDX() && Info->hasWorkItemIDX());
2101  } else {
2102  Splits.append(Ins.begin(), Ins.end());
2103  }
2104 
2105  if (IsEntryFunc) {
2106  allocateSpecialEntryInputVGPRs(CCInfo, MF, *TRI, *Info);
2107  allocateHSAUserSGPRs(CCInfo, MF, *TRI, *Info);
2108  }
2109 
2110  if (IsKernel) {
2111  analyzeFormalArgumentsCompute(CCInfo, Ins);
2112  } else {
2113  CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, isVarArg);
2114  CCInfo.AnalyzeFormalArguments(Splits, AssignFn);
2115  }
2116 
2117  SmallVector<SDValue, 16> Chains;
2118 
2119  // FIXME: This is the minimum kernel argument alignment. We should improve
2120  // this to the maximum alignment of the arguments.
2121  //
2122  // FIXME: Alignment of explicit arguments totally broken with non-0 explicit
2123  // kern arg offset.
2124  const unsigned KernelArgBaseAlign = 16;
2125 
2126  for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
2127  const ISD::InputArg &Arg = Ins[i];
2128  if (Arg.isOrigArg() && Skipped[Arg.getOrigArgIndex()]) {
2129  InVals.push_back(DAG.getUNDEF(Arg.VT));
2130  continue;
2131  }
2132 
2133  CCValAssign &VA = ArgLocs[ArgIdx++];
2134  MVT VT = VA.getLocVT();
2135 
2136  if (IsEntryFunc && VA.isMemLoc()) {
2137  VT = Ins[i].VT;
2138  EVT MemVT = VA.getLocVT();
2139 
2140  const uint64_t Offset = VA.getLocMemOffset();
2141  unsigned Align = MinAlign(KernelArgBaseAlign, Offset);
2142 
2143  SDValue Arg = lowerKernargMemParameter(
2144  DAG, VT, MemVT, DL, Chain, Offset, Align, Ins[i].Flags.isSExt(), &Ins[i]);
2145  Chains.push_back(Arg.getValue(1));
2146 
2147  auto *ParamTy =
2148  dyn_cast<PointerType>(FType->getParamType(Ins[i].getOrigArgIndex()));
2149  if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
2150  ParamTy && (ParamTy->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
2151  ParamTy->getAddressSpace() == AMDGPUAS::REGION_ADDRESS)) {
2152  // On SI local pointers are just offsets into LDS, so they are always
2153  // less than 16-bits. On CI and newer they could potentially be
2154  // real pointers, so we can't guarantee their size.
2155  Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
2156  DAG.getValueType(MVT::i16));
2157  }
2158 
2159  InVals.push_back(Arg);
2160  continue;
2161  } else if (!IsEntryFunc && VA.isMemLoc()) {
2162  SDValue Val = lowerStackParameter(DAG, VA, DL, Chain, Arg);
2163  InVals.push_back(Val);
2164  if (!Arg.Flags.isByVal())
2165  Chains.push_back(Val.getValue(1));
2166  continue;
2167  }
2168 
2169  assert(VA.isRegLoc() && "Parameter must be in a register!");
2170 
2171  Register Reg = VA.getLocReg();
2172  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2173  EVT ValVT = VA.getValVT();
2174 
2175  Reg = MF.addLiveIn(Reg, RC);
2176  SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
2177 
2178  if (Arg.Flags.isSRet()) {
2179  // The return object should be reasonably addressable.
2180 
2181  // FIXME: This helps when the return is a real sret. If it is a
2182  // automatically inserted sret (i.e. CanLowerReturn returns false), an
2183  // extra copy is inserted in SelectionDAGBuilder which obscures this.
2184  unsigned NumBits
2186  Val = DAG.getNode(ISD::AssertZext, DL, VT, Val,
2187  DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), NumBits)));
2188  }
2189 
2190  // If this is an 8 or 16-bit value, it is really passed promoted
2191  // to 32 bits. Insert an assert[sz]ext to capture this, then
2192  // truncate to the right size.
2193  switch (VA.getLocInfo()) {
2194  case CCValAssign::Full:
2195  break;
2196  case CCValAssign::BCvt:
2197  Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
2198  break;
2199  case CCValAssign::SExt:
2200  Val = DAG.getNode(ISD::AssertSext, DL, VT, Val,
2201  DAG.getValueType(ValVT));
2202  Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2203  break;
2204  case CCValAssign::ZExt:
2205  Val = DAG.getNode(ISD::AssertZext, DL, VT, Val,
2206  DAG.getValueType(ValVT));
2207  Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2208  break;
2209  case CCValAssign::AExt:
2210  Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2211  break;
2212  default:
2213  llvm_unreachable("Unknown loc info!");
2214  }
2215 
2216  InVals.push_back(Val);
2217  }
2218 
2219  if (!IsEntryFunc) {
2220  // Special inputs come after user arguments.
2221  allocateSpecialInputVGPRs(CCInfo, MF, *TRI, *Info);
2222  }
2223 
2224  // Start adding system SGPRs.
2225  if (IsEntryFunc) {
2226  allocateSystemSGPRs(CCInfo, MF, *Info, CallConv, IsShader);
2227  } else {
2228  CCInfo.AllocateReg(Info->getScratchRSrcReg());
2229  CCInfo.AllocateReg(Info->getScratchWaveOffsetReg());
2230  CCInfo.AllocateReg(Info->getFrameOffsetReg());
2231  allocateSpecialInputSGPRs(CCInfo, MF, *TRI, *Info);
2232  }
2233 
2234  auto &ArgUsageInfo =
2236  ArgUsageInfo.setFuncArgInfo(Fn, Info->getArgInfo());
2237 
2238  unsigned StackArgSize = CCInfo.getNextStackOffset();
2239  Info->setBytesInStackArgArea(StackArgSize);
2240 
2241  return Chains.empty() ? Chain :
2242  DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
2243 }
2244 
2245 // TODO: If return values can't fit in registers, we should return as many as
2246 // possible in registers before passing on stack.
2248  CallingConv::ID CallConv,
2249  MachineFunction &MF, bool IsVarArg,
2250  const SmallVectorImpl<ISD::OutputArg> &Outs,
2251  LLVMContext &Context) const {
2252  // Replacing returns with sret/stack usage doesn't make sense for shaders.
2253  // FIXME: Also sort of a workaround for custom vector splitting in LowerReturn
2254  // for shaders. Vector types should be explicitly handled by CC.
2255  if (AMDGPU::isEntryFunctionCC(CallConv))
2256  return true;
2257 
2259  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
2260  return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg));
2261 }
2262 
2263 SDValue
2265  bool isVarArg,
2266  const SmallVectorImpl<ISD::OutputArg> &Outs,
2267  const SmallVectorImpl<SDValue> &OutVals,
2268  const SDLoc &DL, SelectionDAG &DAG) const {
2269  MachineFunction &MF = DAG.getMachineFunction();
2271 
2272  if (AMDGPU::isKernel(CallConv)) {
2273  return AMDGPUTargetLowering::LowerReturn(Chain, CallConv, isVarArg, Outs,
2274  OutVals, DL, DAG);
2275  }
2276 
2277  bool IsShader = AMDGPU::isShader(CallConv);
2278 
2279  Info->setIfReturnsVoid(Outs.empty());
2280  bool IsWaveEnd = Info->returnsVoid() && IsShader;
2281 
2282  // CCValAssign - represent the assignment of the return value to a location.
2285 
2286  // CCState - Info about the registers and stack slots.
2287  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2288  *DAG.getContext());
2289 
2290  // Analyze outgoing return values.
2291  CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2292 
2293  SDValue Flag;
2294  SmallVector<SDValue, 48> RetOps;
2295  RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2296 
2297  // Add return address for callable functions.
2298  if (!Info->isEntryFunction()) {
2300  SDValue ReturnAddrReg = CreateLiveInRegister(
2301  DAG, &AMDGPU::SReg_64RegClass, TRI->getReturnAddressReg(MF), MVT::i64);
2302 
2303  SDValue ReturnAddrVirtualReg = DAG.getRegister(
2304  MF.getRegInfo().createVirtualRegister(&AMDGPU::CCR_SGPR_64RegClass),
2305  MVT::i64);
2306  Chain =
2307  DAG.getCopyToReg(Chain, DL, ReturnAddrVirtualReg, ReturnAddrReg, Flag);
2308  Flag = Chain.getValue(1);
2309  RetOps.push_back(ReturnAddrVirtualReg);
2310  }
2311 
2312  // Copy the result values into the output registers.
2313  for (unsigned I = 0, RealRVLocIdx = 0, E = RVLocs.size(); I != E;
2314  ++I, ++RealRVLocIdx) {
2315  CCValAssign &VA = RVLocs[I];
2316  assert(VA.isRegLoc() && "Can only return in registers!");
2317  // TODO: Partially return in registers if return values don't fit.
2318  SDValue Arg = OutVals[RealRVLocIdx];
2319 
2320  // Copied from other backends.
2321  switch (VA.getLocInfo()) {
2322  case CCValAssign::Full:
2323  break;
2324  case CCValAssign::BCvt:
2325  Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2326  break;
2327  case CCValAssign::SExt:
2328  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2329  break;
2330  case CCValAssign::ZExt:
2331  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2332  break;
2333  case CCValAssign::AExt:
2334  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2335  break;
2336  default:
2337  llvm_unreachable("Unknown loc info!");
2338  }
2339 
2340  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2341  Flag = Chain.getValue(1);
2342  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2343  }
2344 
2345  // FIXME: Does sret work properly?
2346  if (!Info->isEntryFunction()) {
2347  const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
2348  const MCPhysReg *I =
2350  if (I) {
2351  for (; *I; ++I) {
2352  if (AMDGPU::SReg_64RegClass.contains(*I))
2353  RetOps.push_back(DAG.getRegister(*I, MVT::i64));
2354  else if (AMDGPU::SReg_32RegClass.contains(*I))
2355  RetOps.push_back(DAG.getRegister(*I, MVT::i32));
2356  else
2357  llvm_unreachable("Unexpected register class in CSRsViaCopy!");
2358  }
2359  }
2360  }
2361 
2362  // Update chain and glue.
2363  RetOps[0] = Chain;
2364  if (Flag.getNode())
2365  RetOps.push_back(Flag);
2366 
2367  unsigned Opc = AMDGPUISD::ENDPGM;
2368  if (!IsWaveEnd)
2370  return DAG.getNode(Opc, DL, MVT::Other, RetOps);
2371 }
2372 
2374  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
2375  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
2376  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool IsThisReturn,
2377  SDValue ThisVal) const {
2378  CCAssignFn *RetCC = CCAssignFnForReturn(CallConv, IsVarArg);
2379 
2380  // Assign locations to each value returned by this call.
2382  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2383  *DAG.getContext());
2384  CCInfo.AnalyzeCallResult(Ins, RetCC);
2385 
2386  // Copy all of the result registers out of their specified physreg.
2387  for (unsigned i = 0; i != RVLocs.size(); ++i) {
2388  CCValAssign VA = RVLocs[i];
2389  SDValue Val;
2390 
2391  if (VA.isRegLoc()) {
2392  Val = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2393  Chain = Val.getValue(1);
2394  InFlag = Val.getValue(2);
2395  } else if (VA.isMemLoc()) {
2396  report_fatal_error("TODO: return values in memory");
2397  } else
2398  llvm_unreachable("unknown argument location type");
2399 
2400  switch (VA.getLocInfo()) {
2401  case CCValAssign::Full:
2402  break;
2403  case CCValAssign::BCvt:
2404  Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2405  break;
2406  case CCValAssign::ZExt:
2407  Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
2408  DAG.getValueType(VA.getValVT()));
2409  Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2410  break;
2411  case CCValAssign::SExt:
2412  Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
2413  DAG.getValueType(VA.getValVT()));
2414  Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2415  break;
2416  case CCValAssign::AExt:
2417  Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2418  break;
2419  default:
2420  llvm_unreachable("Unknown loc info!");
2421  }
2422 
2423  InVals.push_back(Val);
2424  }
2425 
2426  return Chain;
2427 }
2428 
2429 // Add code to pass special inputs required depending on used features separate
2430 // from the explicit user arguments present in the IR.
2432  CallLoweringInfo &CLI,
2433  CCState &CCInfo,
2434  const SIMachineFunctionInfo &Info,
2435  SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
2436  SmallVectorImpl<SDValue> &MemOpChains,
2437  SDValue Chain) const {
2438  // If we don't have a call site, this was a call inserted by
2439  // legalization. These can never use special inputs.
2440  if (!CLI.CS)
2441  return;
2442 
2443  const Function *CalleeFunc = CLI.CS.getCalledFunction();
2444  assert(CalleeFunc);
2445 
2446  SelectionDAG &DAG = CLI.DAG;
2447  const SDLoc &DL = CLI.DL;
2448 
2449  const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
2450 
2451  auto &ArgUsageInfo =
2453  const AMDGPUFunctionArgInfo &CalleeArgInfo
2454  = ArgUsageInfo.lookupFuncArgInfo(*CalleeFunc);
2455 
2456  const AMDGPUFunctionArgInfo &CallerArgInfo = Info.getArgInfo();
2457 
2458  // TODO: Unify with private memory register handling. This is complicated by
2459  // the fact that at least in kernels, the input argument is not necessarily
2460  // in the same location as the input.
2470  };
2471 
2472  for (auto InputID : InputRegs) {
2473  const ArgDescriptor *OutgoingArg;
2474  const TargetRegisterClass *ArgRC;
2475 
2476  std::tie(OutgoingArg, ArgRC) = CalleeArgInfo.getPreloadedValue(InputID);
2477  if (!OutgoingArg)
2478  continue;
2479 
2480  const ArgDescriptor *IncomingArg;
2481  const TargetRegisterClass *IncomingArgRC;
2482  std::tie(IncomingArg, IncomingArgRC)
2483  = CallerArgInfo.getPreloadedValue(InputID);
2484  assert(IncomingArgRC == ArgRC);
2485 
2486  // All special arguments are ints for now.
2487  EVT ArgVT = TRI->getSpillSize(*ArgRC) == 8 ? MVT::i64 : MVT::i32;
2488  SDValue InputReg;
2489 
2490  if (IncomingArg) {
2491  InputReg = loadInputValue(DAG, ArgRC, ArgVT, DL, *IncomingArg);
2492  } else {
2493  // The implicit arg ptr is special because it doesn't have a corresponding
2494  // input for kernels, and is computed from the kernarg segment pointer.
2495  assert(InputID == AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR);
2496  InputReg = getImplicitArgPtr(DAG, DL);
2497  }
2498 
2499  if (OutgoingArg->isRegister()) {
2500  RegsToPass.emplace_back(OutgoingArg->getRegister(), InputReg);
2501  } else {
2502  unsigned SpecialArgOffset = CCInfo.AllocateStack(ArgVT.getStoreSize(), 4);
2503  SDValue ArgStore = storeStackInputValue(DAG, DL, Chain, InputReg,
2504  SpecialArgOffset);
2505  MemOpChains.push_back(ArgStore);
2506  }
2507  }
2508 
2509  // Pack workitem IDs into a single register or pass it as is if already
2510  // packed.
2511  const ArgDescriptor *OutgoingArg;
2512  const TargetRegisterClass *ArgRC;
2513 
2514  std::tie(OutgoingArg, ArgRC) =
2515  CalleeArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_X);
2516  if (!OutgoingArg)
2517  std::tie(OutgoingArg, ArgRC) =
2518  CalleeArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Y);
2519  if (!OutgoingArg)
2520  std::tie(OutgoingArg, ArgRC) =
2521  CalleeArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Z);
2522  if (!OutgoingArg)
2523  return;
2524 
2525  const ArgDescriptor *IncomingArgX
2527  const ArgDescriptor *IncomingArgY
2529  const ArgDescriptor *IncomingArgZ
2531 
2532  SDValue InputReg;
2533  SDLoc SL;
2534 
2535  // If incoming ids are not packed we need to pack them.
2536  if (IncomingArgX && !IncomingArgX->isMasked() && CalleeArgInfo.WorkItemIDX)
2537  InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgX);
2538 
2539  if (IncomingArgY && !IncomingArgY->isMasked() && CalleeArgInfo.WorkItemIDY) {
2540  SDValue Y = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgY);
2541  Y = DAG.getNode(ISD::SHL, SL, MVT::i32, Y,
2542  DAG.getShiftAmountConstant(10, MVT::i32, SL));
2543  InputReg = InputReg.getNode() ?
2544  DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Y) : Y;
2545  }
2546 
2547  if (IncomingArgZ && !IncomingArgZ->isMasked() && CalleeArgInfo.WorkItemIDZ) {
2548  SDValue Z = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgZ);
2549  Z = DAG.getNode(ISD::SHL, SL, MVT::i32, Z,
2550  DAG.getShiftAmountConstant(20, MVT::i32, SL));
2551  InputReg = InputReg.getNode() ?
2552  DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Z) : Z;
2553  }
2554 
2555  if (!InputReg.getNode()) {
2556  // Workitem ids are already packed, any of present incoming arguments
2557  // will carry all required fields.
2559  IncomingArgX ? *IncomingArgX :
2560  IncomingArgY ? *IncomingArgY :
2561  *IncomingArgZ, ~0u);
2562  InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, IncomingArg);
2563  }
2564 
2565  if (OutgoingArg->isRegister()) {
2566  RegsToPass.emplace_back(OutgoingArg->getRegister(), InputReg);
2567  } else {
2568  unsigned SpecialArgOffset = CCInfo.AllocateStack(4, 4);
2569  SDValue ArgStore = storeStackInputValue(DAG, DL, Chain, InputReg,
2570  SpecialArgOffset);
2571  MemOpChains.push_back(ArgStore);
2572  }
2573 }
2574 
2576  return CC == CallingConv::Fast;
2577 }
2578 
2579 /// Return true if we might ever do TCO for calls with this calling convention.
2581  switch (CC) {
2582  case CallingConv::C:
2583  return true;
2584  default:
2585  return canGuaranteeTCO(CC);
2586  }
2587 }
2588 
2590  SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg,
2591  const SmallVectorImpl<ISD::OutputArg> &Outs,
2592  const SmallVectorImpl<SDValue> &OutVals,
2593  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2594  if (!mayTailCallThisCC(CalleeCC))
2595  return false;
2596 
2597  MachineFunction &MF = DAG.getMachineFunction();
2598  const Function &CallerF = MF.getFunction();
2599  CallingConv::ID CallerCC = CallerF.getCallingConv();
2601  const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2602 
2603  // Kernels aren't callable, and don't have a live in return address so it
2604  // doesn't make sense to do a tail call with entry functions.
2605  if (!CallerPreserved)
2606  return false;
2607 
2608  bool CCMatch = CallerCC == CalleeCC;
2609 
2611  if (canGuaranteeTCO(CalleeCC) && CCMatch)
2612  return true;
2613  return false;
2614  }
2615 
2616  // TODO: Can we handle var args?
2617  if (IsVarArg)
2618  return false;
2619 
2620  for (const Argument &Arg : CallerF.args()) {
2621  if (Arg.hasByValAttr())
2622  return false;
2623  }
2624 
2625  LLVMContext &Ctx = *DAG.getContext();
2626 
2627  // Check that the call results are passed in the same way.
2628  if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, Ctx, Ins,
2629  CCAssignFnForCall(CalleeCC, IsVarArg),
2630  CCAssignFnForCall(CallerCC, IsVarArg)))
2631  return false;
2632 
2633  // The callee has to preserve all registers the caller needs to preserve.
2634  if (!CCMatch) {
2635  const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2636  if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2637  return false;
2638  }
2639 
2640  // Nothing more to check if the callee is taking no arguments.
2641  if (Outs.empty())
2642  return true;
2643 
2645  CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, Ctx);
2646 
2647  CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, IsVarArg));
2648 
2649  const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
2650  // If the stack arguments for this call do not fit into our own save area then
2651  // the call cannot be made tail.
2652  // TODO: Is this really necessary?
2653  if (CCInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea())
2654  return false;
2655 
2656  const MachineRegisterInfo &MRI = MF.getRegInfo();
2657  return parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals);
2658 }
2659 
2661  if (!CI->isTailCall())
2662  return false;
2663 
2664  const Function *ParentFn = CI->getParent()->getParent();
2665  if (AMDGPU::isEntryFunctionCC(ParentFn->getCallingConv()))
2666  return false;
2667 
2668  auto Attr = ParentFn->getFnAttribute("disable-tail-calls");
2669  return (Attr.getValueAsString() != "true");
2670 }
2671 
2672 // The wave scratch offset register is used as the global base pointer.
2674  SmallVectorImpl<SDValue> &InVals) const {
2675  SelectionDAG &DAG = CLI.DAG;
2676  const SDLoc &DL = CLI.DL;
2678  SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2680  SDValue Chain = CLI.Chain;
2681  SDValue Callee = CLI.Callee;
2682  bool &IsTailCall = CLI.IsTailCall;
2683  CallingConv::ID CallConv = CLI.CallConv;
2684  bool IsVarArg = CLI.IsVarArg;
2685  bool IsSibCall = false;
2686  bool IsThisReturn = false;
2687  MachineFunction &MF = DAG.getMachineFunction();
2688 
2689  if (IsVarArg) {
2690  return lowerUnhandledCall(CLI, InVals,
2691  "unsupported call to variadic function ");
2692  }
2693 
2694  if (!CLI.CS.getInstruction())
2695  report_fatal_error("unsupported libcall legalization");
2696 
2697  if (!CLI.CS.getCalledFunction()) {
2698  return lowerUnhandledCall(CLI, InVals,
2699  "unsupported indirect call to function ");
2700  }
2701 
2702  if (IsTailCall && MF.getTarget().Options.GuaranteedTailCallOpt) {
2703  return lowerUnhandledCall(CLI, InVals,
2704  "unsupported required tail call to function ");
2705  }
2706 
2708  // Note the issue is with the CC of the calling function, not of the call
2709  // itself.
2710  return lowerUnhandledCall(CLI, InVals,
2711  "unsupported call from graphics shader of function ");
2712  }
2713 
2714  if (IsTailCall) {
2715  IsTailCall = isEligibleForTailCallOptimization(
2716  Callee, CallConv, IsVarArg, Outs, OutVals, Ins, DAG);
2717  if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall()) {
2718  report_fatal_error("failed to perform tail call elimination on a call "
2719  "site marked musttail");
2720  }
2721 
2722  bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2723 
2724  // A sibling call is one where we're under the usual C ABI and not planning
2725  // to change that but can still do a tail call:
2726  if (!TailCallOpt && IsTailCall)
2727  IsSibCall = true;
2728 
2729  if (IsTailCall)
2730  ++NumTailCalls;
2731  }
2732 
2734 
2735  // Analyze operands of the call, assigning locations to each operand.
2737  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
2738  CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, IsVarArg);
2739 
2740  CCInfo.AnalyzeCallOperands(Outs, AssignFn);
2741 
2742  // Get a count of how many bytes are to be pushed on the stack.
2743  unsigned NumBytes = CCInfo.getNextStackOffset();
2744 
2745  if (IsSibCall) {
2746  // Since we're not changing the ABI to make this a tail call, the memory
2747  // operands are already available in the caller's incoming argument space.
2748  NumBytes = 0;
2749  }
2750 
2751  // FPDiff is the byte offset of the call's argument area from the callee's.
2752  // Stores to callee stack arguments will be placed in FixedStackSlots offset
2753  // by this amount for a tail call. In a sibling call it must be 0 because the
2754  // caller will deallocate the entire stack and the callee still expects its
2755  // arguments to begin at SP+0. Completely unused for non-tail calls.
2756  int32_t FPDiff = 0;
2757  MachineFrameInfo &MFI = MF.getFrameInfo();
2759 
2760  // Adjust the stack pointer for the new arguments...
2761  // These operations are automatically eliminated by the prolog/epilog pass
2762  if (!IsSibCall) {
2763  Chain = DAG.getCALLSEQ_START(Chain, 0, 0, DL);
2764 
2765  SmallVector<SDValue, 4> CopyFromChains;
2766 
2767  // In the HSA case, this should be an identity copy.
2768  SDValue ScratchRSrcReg
2769  = DAG.getCopyFromReg(Chain, DL, Info->getScratchRSrcReg(), MVT::v4i32);
2770  RegsToPass.emplace_back(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, ScratchRSrcReg);
2771  CopyFromChains.push_back(ScratchRSrcReg.getValue(1));
2772  Chain = DAG.getTokenFactor(DL, CopyFromChains);
2773  }
2774 
2775  SmallVector<SDValue, 8> MemOpChains;
2776  MVT PtrVT = MVT::i32;
2777 
2778  // Walk the register/memloc assignments, inserting copies/loads.
2779  for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2780  ++i, ++realArgIdx) {
2781  CCValAssign &VA = ArgLocs[i];
2782  SDValue Arg = OutVals[realArgIdx];
2783 
2784  // Promote the value if needed.
2785  switch (VA.getLocInfo()) {
2786  case CCValAssign::Full:
2787  break;
2788  case CCValAssign::BCvt:
2789  Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2790  break;
2791  case CCValAssign::ZExt:
2792  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2793  break;
2794  case CCValAssign::SExt:
2795  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2796  break;
2797  case CCValAssign::AExt:
2798  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2799  break;
2800  case CCValAssign::FPExt:
2801  Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2802  break;
2803  default:
2804  llvm_unreachable("Unknown loc info!");
2805  }
2806 
2807  if (VA.isRegLoc()) {
2808  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2809  } else {
2810  assert(VA.isMemLoc());
2811 
2812  SDValue DstAddr;
2813  MachinePointerInfo DstInfo;
2814 
2815  unsigned LocMemOffset = VA.getLocMemOffset();
2816  int32_t Offset = LocMemOffset;
2817 
2818  SDValue PtrOff = DAG.getConstant(Offset, DL, PtrVT);
2819  unsigned Align = 0;
2820 
2821  if (IsTailCall) {
2822  ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2823  unsigned OpSize = Flags.isByVal() ?
2824  Flags.getByValSize() : VA.getValVT().getStoreSize();
2825 
2826  // FIXME: We can have better than the minimum byval required alignment.
2827  Align = Flags.isByVal() ? Flags.getByValAlign() :
2828  MinAlign(Subtarget->getStackAlignment(), Offset);
2829 
2830  Offset = Offset + FPDiff;
2831  int FI = MFI.CreateFixedObject(OpSize, Offset, true);
2832 
2833  DstAddr = DAG.getFrameIndex(FI, PtrVT);
2834  DstInfo = MachinePointerInfo::getFixedStack(MF, FI);
2835 
2836  // Make sure any stack arguments overlapping with where we're storing
2837  // are loaded before this eventual operation. Otherwise they'll be
2838  // clobbered.
2839 
2840  // FIXME: Why is this really necessary? This seems to just result in a
2841  // lot of code to copy the stack and write them back to the same
2842  // locations, which are supposed to be immutable?
2843  Chain = addTokenForArgument(Chain, DAG, MFI, FI);
2844  } else {
2845  DstAddr = PtrOff;
2846  DstInfo = MachinePointerInfo::getStack(MF, LocMemOffset);
2847  Align = MinAlign(Subtarget->getStackAlignment(), LocMemOffset);
2848  }
2849 
2850  if (Outs[i].Flags.isByVal()) {
2851  SDValue SizeNode =
2852  DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i32);
2853  SDValue Cpy = DAG.getMemcpy(
2854  Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2855  /*isVol = */ false, /*AlwaysInline = */ true,
2856  /*isTailCall = */ false, DstInfo,
2859 
2860  MemOpChains.push_back(Cpy);
2861  } else {
2862  SDValue Store = DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, Align);
2863  MemOpChains.push_back(Store);
2864  }
2865  }
2866  }
2867 
2868  // Copy special input registers after user input arguments.
2869  passSpecialInputs(CLI, CCInfo, *Info, RegsToPass, MemOpChains, Chain);
2870 
2871  if (!MemOpChains.empty())
2872  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2873 
2874  // Build a sequence of copy-to-reg nodes chained together with token chain
2875  // and flag operands which copy the outgoing args into the appropriate regs.
2876  SDValue InFlag;
2877  for (auto &RegToPass : RegsToPass) {
2878  Chain = DAG.getCopyToReg(Chain, DL, RegToPass.first,
2879  RegToPass.second, InFlag);
2880  InFlag = Chain.getValue(1);
2881  }
2882 
2883 
2884  SDValue PhysReturnAddrReg;
2885  if (IsTailCall) {
2886  // Since the return is being combined with the call, we need to pass on the
2887  // return address.
2888 
2890  SDValue ReturnAddrReg = CreateLiveInRegister(
2891  DAG, &AMDGPU::SReg_64RegClass, TRI->getReturnAddressReg(MF), MVT::i64);
2892 
2893  PhysReturnAddrReg = DAG.getRegister(TRI->getReturnAddressReg(MF),
2894  MVT::i64);
2895  Chain = DAG.getCopyToReg(Chain, DL, PhysReturnAddrReg, ReturnAddrReg, InFlag);
2896  InFlag = Chain.getValue(1);
2897  }
2898 
2899  // We don't usually want to end the call-sequence here because we would tidy
2900  // the frame up *after* the call, however in the ABI-changing tail-call case
2901  // we've carefully laid out the parameters so that when sp is reset they'll be
2902  // in the correct location.
2903  if (IsTailCall && !IsSibCall) {
2904  Chain = DAG.getCALLSEQ_END(Chain,
2905  DAG.getTargetConstant(NumBytes, DL, MVT::i32),
2906  DAG.getTargetConstant(0, DL, MVT::i32),
2907  InFlag, DL);
2908  InFlag = Chain.getValue(1);
2909  }
2910 
2911  std::vector<SDValue> Ops;
2912  Ops.push_back(Chain);
2913  Ops.push_back(Callee);
2914  // Add a redundant copy of the callee global which will not be legalized, as
2915  // we need direct access to the callee later.
2916  GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Callee);
2917  const GlobalValue *GV = GSD->getGlobal();
2918  Ops.push_back(DAG.getTargetGlobalAddress(GV, DL, MVT::i64));
2919 
2920  if (IsTailCall) {
2921  // Each tail call may have to adjust the stack by a different amount, so
2922  // this information must travel along with the operation for eventual
2923  // consumption by emitEpilogue.
2924  Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32));
2925 
2926  Ops.push_back(PhysReturnAddrReg);
2927  }
2928 
2929  // Add argument registers to the end of the list so that they are known live
2930  // into the call.
2931  for (auto &RegToPass : RegsToPass) {
2932  Ops.push_back(DAG.getRegister(RegToPass.first,
2933  RegToPass.second.getValueType()));
2934  }
2935 
2936  // Add a register mask operand representing the call-preserved registers.
2937 
2938  auto *TRI = static_cast<const SIRegisterInfo*>(Subtarget->getRegisterInfo());
2939  const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
2940  assert(Mask && "Missing call preserved mask for calling convention");
2941  Ops.push_back(DAG.getRegisterMask(Mask));
2942 
2943  if (InFlag.getNode())
2944  Ops.push_back(InFlag);
2945 
2946  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2947 
2948  // If we're doing a tall call, use a TC_RETURN here rather than an
2949  // actual call instruction.
2950  if (IsTailCall) {
2951  MFI.setHasTailCall();
2952  return DAG.getNode(AMDGPUISD::TC_RETURN, DL, NodeTys, Ops);
2953  }
2954 
2955  // Returns a chain and a flag for retval copy to use.
2956  SDValue Call = DAG.getNode(AMDGPUISD::CALL, DL, NodeTys, Ops);
2957  Chain = Call.getValue(0);
2958  InFlag = Call.getValue(1);
2959 
2960  uint64_t CalleePopBytes = NumBytes;
2961  Chain = DAG.getCALLSEQ_END(Chain, DAG.getTargetConstant(0, DL, MVT::i32),
2962  DAG.getTargetConstant(CalleePopBytes, DL, MVT::i32),
2963  InFlag, DL);
2964  if (!Ins.empty())
2965  InFlag = Chain.getValue(1);
2966 
2967  // Handle result values, copying them out of physregs into vregs that we
2968  // return.
2969  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2970  InVals, IsThisReturn,
2971  IsThisReturn ? OutVals[0] : SDValue());
2972 }
2973 
2974 unsigned SITargetLowering::getRegisterByName(const char* RegName, EVT VT,
2975  SelectionDAG &DAG) const {
2976  unsigned Reg = StringSwitch<unsigned>(RegName)
2977  .Case("m0", AMDGPU::M0)
2978  .Case("exec", AMDGPU::EXEC)
2979  .Case("exec_lo", AMDGPU::EXEC_LO)
2980  .Case("exec_hi", AMDGPU::EXEC_HI)
2981  .Case("flat_scratch", AMDGPU::FLAT_SCR)
2982  .Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)
2983  .Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI)
2984  .Default(AMDGPU::NoRegister);
2985 
2986  if (Reg == AMDGPU::NoRegister) {
2987  report_fatal_error(Twine("invalid register name \""
2988  + StringRef(RegName) + "\"."));
2989 
2990  }
2991 
2992  if (!Subtarget->hasFlatScrRegister() &&
2993  Subtarget->getRegisterInfo()->regsOverlap(Reg, AMDGPU::FLAT_SCR)) {
2994  report_fatal_error(Twine("invalid register \""
2995  + StringRef(RegName) + "\" for subtarget."));
2996  }
2997 
2998  switch (Reg) {
2999  case AMDGPU::M0:
3000  case AMDGPU::EXEC_LO:
3001  case AMDGPU::EXEC_HI:
3002  case AMDGPU::FLAT_SCR_LO:
3003  case AMDGPU::FLAT_SCR_HI:
3004  if (VT.getSizeInBits() == 32)
3005  return Reg;
3006  break;
3007  case AMDGPU::EXEC:
3008  case AMDGPU::FLAT_SCR:
3009  if (VT.getSizeInBits() == 64)
3010  return Reg;
3011  break;
3012  default:
3013  llvm_unreachable("missing register type checking");
3014  }
3015 
3016  report_fatal_error(Twine("invalid type for register \""
3017  + StringRef(RegName) + "\"."));
3018 }
3019 
3020 // If kill is not the last instruction, split the block so kill is always a
3021 // proper terminator.
3023  MachineBasicBlock *BB) const {
3024  const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3025 
3026  MachineBasicBlock::iterator SplitPoint(&MI);
3027  ++SplitPoint;
3028 
3029  if (SplitPoint == BB->end()) {
3030  // Don't bother with a new block.
3032  return BB;
3033  }
3034 
3035  MachineFunction *MF = BB->getParent();
3036  MachineBasicBlock *SplitBB
3038 
3039  MF->insert(++MachineFunction::iterator(BB), SplitBB);
3040  SplitBB->splice(SplitBB->begin(), BB, SplitPoint, BB->end());
3041 
3042  SplitBB->transferSuccessorsAndUpdatePHIs(BB);
3043  BB->addSuccessor(SplitBB);
3044 
3046  return SplitBB;
3047 }
3048 
3049 // Split block \p MBB at \p MI, as to insert a loop. If \p InstInLoop is true,
3050 // \p MI will be the only instruction in the loop body block. Otherwise, it will
3051 // be the first instruction in the remainder block.
3052 //
3053 /// \returns { LoopBody, Remainder }
3054 static std::pair<MachineBasicBlock *, MachineBasicBlock *>
3056  MachineFunction *MF = MBB.getParent();
3058 
3059  // To insert the loop we need to split the block. Move everything after this
3060  // point to a new block, and insert a new empty block between the two.
3062  MachineBasicBlock *RemainderBB = MF->CreateMachineBasicBlock();
3063  MachineFunction::iterator MBBI(MBB);
3064  ++MBBI;
3065 
3066  MF->insert(MBBI, LoopBB);
3067  MF->insert(MBBI, RemainderBB);
3068 
3069  LoopBB->addSuccessor(LoopBB);
3070  LoopBB->addSuccessor(RemainderBB);
3071 
3072  // Move the rest of the block into a new block.
3073  RemainderBB->transferSuccessorsAndUpdatePHIs(&MBB);
3074 
3075  if (InstInLoop) {
3076  auto Next = std::next(I);
3077 
3078  // Move instruction to loop body.
3079  LoopBB->splice(LoopBB->begin(), &MBB, I, Next);
3080 
3081  // Move the rest of the block.
3082  RemainderBB->splice(RemainderBB->begin(), &MBB, Next, MBB.end());
3083  } else {
3084  RemainderBB->splice(RemainderBB->begin(), &MBB, I, MBB.end());
3085  }
3086 
3087  MBB.addSuccessor(LoopBB);
3088 
3089  return std::make_pair(LoopBB, RemainderBB);
3090 }
3091 
3092 /// Insert \p MI into a BUNDLE with an S_WAITCNT 0 immediately following it.
3094  MachineBasicBlock *MBB = MI.getParent();
3095  const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3096  auto I = MI.getIterator();
3097  auto E = std::next(I);
3098 
3099  BuildMI(*MBB, E, MI.getDebugLoc(), TII->get(AMDGPU::S_WAITCNT))
3100  .addImm(0);
3101 
3102  MIBundleBuilder Bundler(*MBB, I, E);
3103  finalizeBundle(*MBB, Bundler.begin());
3104 }
3105 
3108  MachineBasicBlock *BB) const {
3109  const DebugLoc &DL = MI.getDebugLoc();
3110 
3112 
3113  MachineBasicBlock *LoopBB;
3114  MachineBasicBlock *RemainderBB;
3115  const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3116 
3117  // Apparently kill flags are only valid if the def is in the same block?
3118  if (MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0))
3119  Src->setIsKill(false);
3120 
3121  std::tie(LoopBB, RemainderBB) = splitBlockForLoop(MI, *BB, true);
3122 
3123  MachineBasicBlock::iterator I = LoopBB->end();
3124 
3125  const unsigned EncodedReg = AMDGPU::Hwreg::encodeHwreg(
3127 
3128  // Clear TRAP_STS.MEM_VIOL
3129  BuildMI(*LoopBB, LoopBB->begin(), DL, TII->get(AMDGPU::S_SETREG_IMM32_B32))
3130  .addImm(0)
3131  .addImm(EncodedReg);
3132 
3134 
3135  Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3136 
3137  // Load and check TRAP_STS.MEM_VIOL
3138  BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_GETREG_B32), Reg)
3139  .addImm(EncodedReg);
3140 
3141  // FIXME: Do we need to use an isel pseudo that may clobber scc?
3142  BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_CMP_LG_U32))
3143  .addReg(Reg, RegState::Kill)
3144  .addImm(0);
3145  BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
3146  .addMBB(LoopBB);
3147 
3148  return RemainderBB;
3149 }
3150 
3151 // Do a v_movrels_b32 or v_movreld_b32 for each unique value of \p IdxReg in the
3152 // wavefront. If the value is uniform and just happens to be in a VGPR, this
3153 // will only do one iteration. In the worst case, this will loop 64 times.
3154 //
3155 // TODO: Just use v_readlane_b32 if we know the VGPR has a uniform value.
3157  const SIInstrInfo *TII,
3159  MachineBasicBlock &OrigBB,
3160  MachineBasicBlock &LoopBB,
3161  const DebugLoc &DL,
3162  const MachineOperand &IdxReg,
3163  unsigned InitReg,
3164  unsigned ResultReg,
3165  unsigned PhiReg,
3166  unsigned InitSaveExecReg,
3167  int Offset,
3168  bool UseGPRIdxMode,
3169  bool IsIndirectSrc) {
3170  MachineFunction *MF = OrigBB.getParent();
3171  const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3172  const SIRegisterInfo *TRI = ST.getRegisterInfo();
3173  MachineBasicBlock::iterator I = LoopBB.begin();
3174 
3175  const TargetRegisterClass *BoolRC = TRI->getBoolRC();
3176  Register PhiExec = MRI.createVirtualRegister(BoolRC);
3177  Register NewExec = MRI.createVirtualRegister(BoolRC);
3178  Register CurrentIdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3179  Register CondReg = MRI.createVirtualRegister(BoolRC);
3180 
3181  BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiReg)
3182  .addReg(InitReg)
3183  .addMBB(&OrigBB)
3184  .addReg(ResultReg)
3185  .addMBB(&LoopBB);
3186 
3187  BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiExec)
3188  .addReg(InitSaveExecReg)
3189  .addMBB(&OrigBB)
3190  .addReg(NewExec)
3191  .addMBB(&LoopBB);
3192 
3193  // Read the next variant <- also loop target.
3194  BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), CurrentIdxReg)
3195  .addReg(IdxReg.getReg(), getUndefRegState(IdxReg.isUndef()));
3196 
3197  // Compare the just read M0 value to all possible Idx values.
3198  BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e64), CondReg)
3199  .addReg(CurrentIdxReg)
3200  .addReg(IdxReg.getReg(), 0, IdxReg.getSubReg());
3201 
3202  // Update EXEC, save the original EXEC value to VCC.
3203  BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_AND_SAVEEXEC_B32
3204  : AMDGPU::S_AND_SAVEEXEC_B64),
3205  NewExec)
3206  .addReg(CondReg, RegState::Kill);
3207 
3208  MRI.setSimpleHint(NewExec, CondReg);
3209 
3210  if (UseGPRIdxMode) {
3211  unsigned IdxReg;
3212  if (Offset == 0) {
3213  IdxReg = CurrentIdxReg;
3214  } else {
3215  IdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3216  BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), IdxReg)
3217  .addReg(CurrentIdxReg, RegState::Kill)
3218  .addImm(Offset);
3219  }
3220  unsigned IdxMode = IsIndirectSrc ?
3222  MachineInstr *SetOn =
3223  BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
3224  .addReg(IdxReg, RegState::Kill)
3225  .addImm(IdxMode);
3226  SetOn->getOperand(3).setIsUndef();
3227  } else {
3228  // Move index from VCC into M0
3229  if (Offset == 0) {
3230  BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3231  .addReg(CurrentIdxReg, RegState::Kill);
3232  } else {
3233  BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
3234  .addReg(CurrentIdxReg, RegState::Kill)
3235  .addImm(Offset);
3236  }
3237  }
3238 
3239  // Update EXEC, switch all done bits to 0 and all todo bits to 1.
3240  unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3241  MachineInstr *InsertPt =
3242  BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_XOR_B32_term
3243  : AMDGPU::S_XOR_B64_term), Exec)
3244  .addReg(Exec)
3245  .addReg(NewExec);
3246 
3247  // XXX - s_xor_b64 sets scc to 1 if the result is nonzero, so can we use
3248  // s_cbranch_scc0?
3249 
3250  // Loop back to V_READFIRSTLANE_B32 if there are still variants to cover.
3251  BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
3252  .addMBB(&LoopBB);
3253 
3254  return InsertPt->getIterator();
3255 }
3256 
3257 // This has slightly sub-optimal regalloc when the source vector is killed by
3258 // the read. The register allocator does not understand that the kill is
3259 // per-workitem, so is kept alive for the whole loop so we end up not re-using a
3260 // subregister from it, using 1 more VGPR than necessary. This was saved when
3261 // this was expanded after register allocation.
3263  MachineBasicBlock &MBB,
3264  MachineInstr &MI,
3265  unsigned InitResultReg,
3266  unsigned PhiReg,
3267  int Offset,
3268  bool UseGPRIdxMode,
3269  bool IsIndirectSrc) {
3270  MachineFunction *MF = MBB.getParent();
3271  const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3272  const SIRegisterInfo *TRI = ST.getRegisterInfo();
3274  const DebugLoc &DL = MI.getDebugLoc();
3276 
3277  const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
3278  Register DstReg = MI.getOperand(0).getReg();
3279  Register SaveExec = MRI.createVirtualRegister(BoolXExecRC);
3280  Register TmpExec = MRI.createVirtualRegister(BoolXExecRC);
3281  unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3282  unsigned MovExecOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
3283 
3284  BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), TmpExec);
3285 
3286  // Save the EXEC mask
3287  BuildMI(MBB, I, DL, TII->get(MovExecOpc), SaveExec)
3288  .addReg(Exec);
3289 
3290  MachineBasicBlock *LoopBB;
3291  MachineBasicBlock *RemainderBB;
3292  std::tie(LoopBB, RemainderBB) = splitBlockForLoop(MI, MBB, false);
3293 
3294  const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3295 
3296  auto InsPt = emitLoadM0FromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, *Idx,
3297  InitResultReg, DstReg, PhiReg, TmpExec,
3298  Offset, UseGPRIdxMode, IsIndirectSrc);
3299 
3300  MachineBasicBlock::iterator First = RemainderBB->begin();
3301  BuildMI(*RemainderBB, First, DL, TII->get(MovExecOpc), Exec)
3302  .addReg(SaveExec);
3303 
3304  return InsPt;
3305 }
3306 
3307 // Returns subreg index, offset
3308 static std::pair<unsigned, int>
3310  const TargetRegisterClass *SuperRC,
3311  unsigned VecReg,
3312  int Offset) {
3313  int NumElts = TRI.getRegSizeInBits(*SuperRC) / 32;
3314 
3315  // Skip out of bounds offsets, or else we would end up using an undefined
3316  // register.
3317  if (Offset >= NumElts || Offset < 0)
3318  return std::make_pair(AMDGPU::sub0, Offset);
3319 
3320  return std::make_pair(AMDGPU::sub0 + Offset, 0);
3321 }
3322 
3323 // Return true if the index is an SGPR and was set.
3326  MachineInstr &MI,
3327  int Offset,
3328  bool UseGPRIdxMode,
3329  bool IsIndirectSrc) {
3330  MachineBasicBlock *MBB = MI.getParent();
3331  const DebugLoc &DL = MI.getDebugLoc();
3333 
3334  const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3335  const TargetRegisterClass *IdxRC = MRI.getRegClass(Idx->getReg());
3336 
3337  assert(Idx->getReg() != AMDGPU::NoRegister);
3338 
3339  if (!TII->getRegisterInfo().isSGPRClass(IdxRC))
3340  return false;
3341 
3342  if (UseGPRIdxMode) {
3343  unsigned IdxMode = IsIndirectSrc ?
3345  if (Offset == 0) {
3346  MachineInstr *SetOn =
3347  BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
3348  .add(*Idx)
3349  .addImm(IdxMode);
3350 
3351  SetOn->getOperand(3).setIsUndef();
3352  } else {
3353  Register Tmp = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3354  BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), Tmp)
3355  .add(*Idx)
3356  .addImm(Offset);
3357  MachineInstr *SetOn =
3358  BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
3359  .addReg(Tmp, RegState::Kill)
3360  .addImm(IdxMode);
3361 
3362  SetOn->getOperand(3).setIsUndef();
3363  }
3364 
3365  return true;
3366  }
3367 
3368  if (Offset == 0) {
3369  BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3370  .add(*Idx);
3371  } else {
3372  BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
3373  .add(*Idx)
3374  .addImm(Offset);
3375  }
3376 
3377  return true;
3378 }
3379 
3380 // Control flow needs to be inserted if indexing with a VGPR.
3382  MachineBasicBlock &MBB,
3383  const GCNSubtarget &ST) {
3384  const SIInstrInfo *TII = ST.getInstrInfo();
3385  const SIRegisterInfo &TRI = TII->getRegisterInfo();
3386  MachineFunction *MF = MBB.getParent();
3388 
3389  Register Dst = MI.getOperand(0).getReg();
3390  Register SrcReg = TII->getNamedOperand(MI, AMDGPU::OpName::src)->getReg();
3391  int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
3392 
3393  const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg);
3394 
3395  unsigned SubReg;
3396  std::tie(SubReg, Offset)
3397  = computeIndirectRegAndOffset(TRI, VecRC, SrcReg, Offset);
3398 
3399  bool UseGPRIdxMode = ST.useVGPRIndexMode(EnableVGPRIndexMode);
3400 
3401  if (setM0ToIndexFromSGPR(TII, MRI, MI, Offset, UseGPRIdxMode, true)) {
3403  const DebugLoc &DL = MI.getDebugLoc();
3404 
3405  if (UseGPRIdxMode) {
3406  // TODO: Look at the uses to avoid the copy. This may require rescheduling
3407  // to avoid interfering with other uses, so probably requires a new
3408  // optimization pass.
3409  BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
3410  .addReg(SrcReg, RegState::Undef, SubReg)
3411  .addReg(SrcReg, RegState::Implicit)
3412  .addReg(AMDGPU::M0, RegState::Implicit);
3413  BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3414  } else {
3415  BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
3416  .addReg(SrcReg, RegState::Undef, SubReg)
3417  .addReg(SrcReg, RegState::Implicit);
3418  }
3419 
3420  MI.eraseFromParent();
3421 
3422  return &MBB;
3423  }
3424 
3425  const DebugLoc &DL = MI.getDebugLoc();
3427 
3428  Register PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3429  Register InitReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3430 
3431  BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), InitReg);
3432 
3433  auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg,
3434  Offset, UseGPRIdxMode, true);
3435  MachineBasicBlock *LoopBB = InsPt->getParent();
3436 
3437  if (UseGPRIdxMode) {
3438  BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
3439  .addReg(SrcReg, RegState::Undef, SubReg)
3440  .addReg(SrcReg, RegState::Implicit)
3441  .addReg(AMDGPU::M0, RegState::Implicit);
3442  BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3443  } else {
3444  BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
3445  .addReg(SrcReg, RegState::Undef, SubReg)
3446  .addReg(SrcReg, RegState::Implicit);
3447  }
3448 
3449  MI.eraseFromParent();
3450 
3451  return LoopBB;
3452 }
3453 
3454 static unsigned getMOVRELDPseudo(const SIRegisterInfo &TRI,
3455  const TargetRegisterClass *VecRC) {
3456  switch (TRI.getRegSizeInBits(*VecRC)) {
3457  case 32: // 4 bytes
3458  return AMDGPU::V_MOVRELD_B32_V1;
3459  case 64: // 8 bytes
3460  return AMDGPU::V_MOVRELD_B32_V2;
3461  case 128: // 16 bytes
3462  return AMDGPU::V_MOVRELD_B32_V4;
3463  case 256: // 32 bytes
3464  return AMDGPU::V_MOVRELD_B32_V8;
3465  case 512: // 64 bytes
3466  return AMDGPU::V_MOVRELD_B32_V16;
3467  default:
3468  llvm_unreachable("unsupported size for MOVRELD pseudos");
3469  }
3470 }
3471 
3473  MachineBasicBlock &MBB,
3474  const GCNSubtarget &ST) {
3475  const SIInstrInfo *TII = ST.getInstrInfo();
3476  const SIRegisterInfo &TRI = TII->getRegisterInfo();
3477  MachineFunction *MF = MBB.getParent();
3479 
3480  Register Dst = MI.getOperand(0).getReg();
3481  const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src);
3482  const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3483  const MachineOperand *Val = TII->getNamedOperand(MI, AMDGPU::OpName::val);
3484  int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
3485  const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg());
3486 
3487  // This can be an immediate, but will be folded later.
3488  assert(Val->getReg());
3489 
3490  unsigned SubReg;
3491  std::tie(SubReg, Offset) = computeIndirectRegAndOffset(TRI, VecRC,
3492  SrcVec->getReg(),
3493  Offset);
3494  bool UseGPRIdxMode = ST.useVGPRIndexMode(EnableVGPRIndexMode);
3495 
3496  if (Idx->getReg() == AMDGPU::NoRegister) {
3498  const DebugLoc &DL = MI.getDebugLoc();
3499 
3500  assert(Offset == 0);
3501 
3502  BuildMI(MBB, I, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dst)
3503  .add(*SrcVec)
3504  .add(*Val)
3505  .addImm(SubReg);
3506 
3507  MI.eraseFromParent();
3508  return &MBB;
3509  }
3510 
3511  if (setM0ToIndexFromSGPR(TII, MRI, MI, Offset, UseGPRIdxMode, false)) {
3513  const DebugLoc &DL = MI.getDebugLoc();
3514 
3515  if (UseGPRIdxMode) {
3516  BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_indirect))
3517  .addReg(SrcVec->getReg(), RegState::Undef, SubReg) // vdst
3518  .add(*Val)
3519  .addReg(Dst, RegState::ImplicitDefine)
3520  .addReg(SrcVec->getReg(), RegState::Implicit)
3521  .addReg(AMDGPU::M0, RegState::Implicit);
3522 
3523  BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3524  } else {
3525  const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(TRI, VecRC));
3526 
3527  BuildMI(MBB, I, DL, MovRelDesc)
3528  .addReg(Dst, RegState::Define)
3529  .addReg(SrcVec->getReg())
3530  .add(*Val)
3531  .addImm(SubReg - AMDGPU::sub0);
3532  }
3533 
3534  MI.eraseFromParent();
3535  return &MBB;
3536  }
3537 
3538  if (Val->isReg())
3539  MRI.clearKillFlags(Val->getReg());
3540 
3541  const DebugLoc &DL = MI.getDebugLoc();
3542 
3543  Register PhiReg = MRI.createVirtualRegister(VecRC);
3544 
3545  auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg,
3546  Offset, UseGPRIdxMode, false);
3547  MachineBasicBlock *LoopBB = InsPt->getParent();
3548 
3549  if (UseGPRIdxMode) {
3550  BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOV_B32_indirect))
3551  .addReg(PhiReg, RegState::Undef, SubReg) // vdst
3552  .add(*Val) // src0
3554  .addReg(PhiReg, RegState::Implicit)
3555  .addReg(AMDGPU::M0, RegState::Implicit);
3556  BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3557  } else {
3558  const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(TRI, VecRC));
3559 
3560  BuildMI(*LoopBB, InsPt, DL, MovRelDesc)
3561  .addReg(Dst, RegState::Define)
3562  .addReg(PhiReg)
3563  .add(*Val)
3564  .addImm(SubReg - AMDGPU::sub0);
3565  }
3566 
3567  MI.eraseFromParent();
3568 
3569  return LoopBB;
3570 }
3571 
3573  MachineInstr &MI, MachineBasicBlock *BB) const {
3574 
3575  const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3576  MachineFunction *MF = BB->getParent();
3578 
3579  if (TII->isMIMG(MI)) {
3580  if (MI.memoperands_empty() && MI.mayLoadOrStore()) {
3581  report_fatal_error("missing mem operand from MIMG instruction");
3582  }
3583  // Add a memoperand for mimg instructions so that they aren't assumed to
3584  // be ordered memory instuctions.
3585 
3586  return BB;
3587  }
3588 
3589  switch (MI.getOpcode()) {
3590  case AMDGPU::S_ADD_U64_PSEUDO:
3591  case AMDGPU::S_SUB_U64_PSEUDO: {
3593  const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3594  const SIRegisterInfo *TRI = ST.getRegisterInfo();
3595  const TargetRegisterClass *BoolRC = TRI->getBoolRC();
3596  const DebugLoc &DL = MI.getDebugLoc();
3597 
3598  MachineOperand &Dest = MI.getOperand(0);
3599  MachineOperand &Src0 = MI.getOperand(1);
3600  MachineOperand &Src1 = MI.getOperand(2);
3601 
3602  Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3603  Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3604 
3605  MachineOperand Src0Sub0 = TII->buildExtractSubRegOrImm(MI, MRI,
3606  Src0, BoolRC, AMDGPU::sub0,
3607  &AMDGPU::SReg_32_XM0RegClass);
3608  MachineOperand Src0Sub1 = TII->buildExtractSubRegOrImm(MI, MRI,
3609  Src0, BoolRC, AMDGPU::sub1,
3610  &AMDGPU::SReg_32_XM0RegClass);
3611 
3612  MachineOperand Src1Sub0 = TII->buildExtractSubRegOrImm(MI, MRI,
3613  Src1, BoolRC, AMDGPU::sub0,
3614  &AMDGPU::SReg_32_XM0RegClass);
3615  MachineOperand Src1Sub1 = TII->buildExtractSubRegOrImm(MI, MRI,
3616  Src1, BoolRC, AMDGPU::sub1,
3617  &AMDGPU::SReg_32_XM0RegClass);
3618 
3619  bool IsAdd = (MI.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO);
3620 
3621  unsigned LoOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
3622  unsigned HiOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
3623  BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0)
3624  .add(Src0Sub0)
3625  .add(Src1Sub0);
3626  BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1)
3627  .add(Src0Sub1)
3628  .add(Src1Sub1);
3629  BuildMI(*BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest.getReg())
3630  .addReg(DestSub0)
3631  .addImm(AMDGPU::sub0)
3632  .addReg(DestSub1)
3633  .addImm(AMDGPU::sub1);
3634  MI.eraseFromParent();
3635  return BB;
3636  }
3637  case AMDGPU::SI_INIT_M0: {
3638  BuildMI(*BB, MI.getIterator(), MI.getDebugLoc(),
3639  TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3640  .add(MI.getOperand(0));
3641  MI.eraseFromParent();
3642  return BB;
3643  }
3644  case AMDGPU::SI_INIT_EXEC:
3645  // This should be before all vector instructions.
3646  BuildMI(*BB, &*BB->begin(), MI.getDebugLoc(), TII->get(AMDGPU::S_MOV_B64),
3647  AMDGPU::EXEC)
3648  .addImm(MI.getOperand(0).getImm());
3649  MI.eraseFromParent();
3650  return BB;
3651 
3652  case AMDGPU::SI_INIT_EXEC_LO:
3653  // This should be before all vector instructions.
3654  BuildMI(*BB, &*BB->begin(), MI.getDebugLoc(), TII->get(AMDGPU::S_MOV_B32),
3655  AMDGPU::EXEC_LO)
3656  .addImm(MI.getOperand(0).getImm());
3657  MI.eraseFromParent();
3658  return BB;
3659 
3660  case AMDGPU::SI_INIT_EXEC_FROM_INPUT: {
3661  // Extract the thread count from an SGPR input and set EXEC accordingly.
3662  // Since BFM can't shift by 64, handle that case with CMP + CMOV.
3663  //
3664  // S_BFE_U32 count, input, {shift, 7}
3665  // S_BFM_B64 exec, count, 0
3666  // S_CMP_EQ_U32 count, 64
3667  // S_CMOV_B64 exec, -1
3668  MachineInstr *FirstMI = &*BB->begin();
3670  Register InputReg = MI.getOperand(0).getReg();
3671  Register CountReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3672  bool Found = false;
3673 
3674  // Move the COPY of the input reg to the beginning, so that we can use it.
3675  for (auto I = BB->begin(); I != &MI; I++) {
3676  if (I->getOpcode() != TargetOpcode::COPY ||
3677  I->getOperand(0).getReg() != InputReg)
3678  continue;
3679 
3680  if (I == FirstMI) {
3681  FirstMI = &*++BB->begin();
3682  } else {
3683  I->removeFromParent();
3684  BB->insert(FirstMI, &*I);
3685  }
3686  Found = true;
3687  break;
3688  }
3689  assert(Found);
3690  (void)Found;
3691 
3692  // This should be before all vector instructions.
3693  unsigned Mask = (getSubtarget()->getWavefrontSize() << 1) - 1;
3694  bool isWave32 = getSubtarget()->isWave32();
3695  unsigned Exec = isWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3696  BuildMI(*BB, FirstMI, DebugLoc(), TII->get(AMDGPU::S_BFE_U32), CountReg)
3697  .addReg(InputReg)
3698  .addImm((MI.getOperand(1).getImm() & Mask) | 0x70000);
3699  BuildMI(*BB, FirstMI, DebugLoc(),
3700  TII->get(isWave32 ? AMDGPU::S_BFM_B32 : AMDGPU::S_BFM_B64),
3701  Exec)
3702  .addReg(CountReg)
3703  .addImm(0);
3704  BuildMI(*BB, FirstMI, DebugLoc(), TII->get(AMDGPU::S_CMP_EQ_U32))
3705  .addReg(CountReg, RegState::Kill)
3707  BuildMI(*BB, FirstMI, DebugLoc(),
3708  TII->get(isWave32 ? AMDGPU::S_CMOV_B32 : AMDGPU::S_CMOV_B64),
3709  Exec)
3710  .addImm(-1);
3711  MI.eraseFromParent();
3712  return BB;
3713  }
3714 
3715  case AMDGPU::GET_GROUPSTATICSIZE: {
3716  assert(getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA ||
3717  getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL);
3718  DebugLoc DL = MI.getDebugLoc();
3719  BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_MOV_B32))
3720  .add(MI.getOperand(0))
3721  .addImm(MFI->getLDSSize());
3722  MI.eraseFromParent();
3723  return BB;
3724  }
3725  case AMDGPU::SI_INDIRECT_SRC_V1:
3726  case AMDGPU::SI_INDIRECT_SRC_V2:
3727  case AMDGPU::SI_INDIRECT_SRC_V4:
3728  case AMDGPU::SI_INDIRECT_SRC_V8:
3729  case AMDGPU::SI_INDIRECT_SRC_V16:
3730  return emitIndirectSrc(MI, *BB, *getSubtarget());
3731  case AMDGPU::SI_INDIRECT_DST_V1:
3732  case AMDGPU::SI_INDIRECT_DST_V2:
3733  case AMDGPU::SI_INDIRECT_DST_V4:
3734  case AMDGPU::SI_INDIRECT_DST_V8:
3735  case AMDGPU::SI_INDIRECT_DST_V16:
3736  return emitIndirectDst(MI, *BB, *getSubtarget());
3737  case AMDGPU::SI_KILL_F32_COND_IMM_PSEUDO:
3738  case AMDGPU::SI_KILL_I1_PSEUDO:
3739  return splitKillBlock(MI, BB);
3740  case AMDGPU::V_CNDMASK_B64_PSEUDO: {
3742  const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3743  const SIRegisterInfo *TRI = ST.getRegisterInfo();
3744 
3745  Register Dst = MI.getOperand(0).getReg();
3746  Register Src0 = MI.getOperand(1).getReg();
3747  Register Src1 = MI.getOperand(2).getReg();
3748  const DebugLoc &DL = MI.getDebugLoc();
3749  Register SrcCond = MI.getOperand(3).getReg();
3750 
3751  Register DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3752  Register DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3753  const auto *CondRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
3754  Register SrcCondCopy = MRI.createVirtualRegister(CondRC);
3755 
3756  BuildMI(*BB, MI, DL, TII->get(AMDGPU::COPY), SrcCondCopy)
3757  .addReg(SrcCond);
3758  BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
3759  .addImm(0)
3760  .addReg(Src0, 0, AMDGPU::sub0)
3761  .addImm(0)
3762  .addReg(Src1, 0, AMDGPU::sub0)
3763  .addReg(SrcCondCopy);
3764  BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
3765  .addImm(0)
3766  .addReg(Src0, 0, AMDGPU::sub1)
3767  .addImm(0)
3768  .addReg(Src1, 0, AMDGPU::sub1)
3769  .addReg(SrcCondCopy);
3770 
3771  BuildMI(*BB, MI, DL, TII->get(AMDGPU::REG_SEQUENCE), Dst)
3772  .addReg(DstLo)
3773  .addImm(AMDGPU::sub0)
3774  .addReg(DstHi)
3775  .addImm(AMDGPU::sub1);
3776  MI.eraseFromParent();
3777  return BB;
3778  }
3779  case AMDGPU::SI_BR_UNDEF: {
3780  const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3781  const DebugLoc &DL = MI.getDebugLoc();
3782  MachineInstr *Br = BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
3783  .add(MI.getOperand(0));
3784  Br->getOperand(1).setIsUndef(true); // read undef SCC
3785  MI.eraseFromParent();
3786  return BB;
3787  }
3788  case AMDGPU::ADJCALLSTACKUP:
3789  case AMDGPU::ADJCALLSTACKDOWN: {
3791  MachineInstrBuilder MIB(*MF, &MI);
3792 
3793  // Add an implicit use of the frame offset reg to prevent the restore copy
3794  // inserted after the call from being reorderd after stack operations in the
3795  // the caller's frame.
3796  MIB.addReg(Info->getStackPtrOffsetReg(), RegState::ImplicitDefine)
3797  .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit)
3798  .addReg(Info->getFrameOffsetReg(), RegState::Implicit);
3799  return BB;
3800  }
3801  case AMDGPU::SI_CALL_ISEL: {
3802  const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3803  const DebugLoc &DL = MI.getDebugLoc();
3804 
3805  unsigned ReturnAddrReg = TII->getRegisterInfo().getReturnAddressReg(*MF);
3806 
3807  MachineInstrBuilder MIB;
3808  MIB = BuildMI(*BB, MI, DL, TII->get(AMDGPU::SI_CALL), ReturnAddrReg);
3809 
3810  for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I)
3811  MIB.add(MI.getOperand(I));
3812 
3813  MIB.cloneMemRefs(MI);
3814  MI.eraseFromParent();
3815  return BB;
3816  }
3817  case AMDGPU::V_ADD_I32_e32:
3818  case AMDGPU::V_SUB_I32_e32:
3819  case AMDGPU::V_SUBREV_I32_e32: {
3820  // TODO: Define distinct V_*_I32_Pseudo instructions instead.
3821  const DebugLoc &DL = MI.getDebugLoc();
3822  unsigned Opc = MI.getOpcode();
3823 
3824  bool NeedClampOperand = false;
3825  if (TII->pseudoToMCOpcode(Opc) == -1) {
3826  Opc = AMDGPU::getVOPe64(Opc);
3827  NeedClampOperand = true;
3828  }
3829 
3830  auto I = BuildMI(*BB, MI, DL, TII->get(Opc), MI.getOperand(0).getReg());
3831  if (TII->isVOP3(*I)) {
3832  const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3833  const SIRegisterInfo *TRI = ST.getRegisterInfo();
3834  I.addReg(TRI->getVCC(), RegState::Define);
3835  }
3836  I.add(MI.getOperand(1))
3837  .add(MI.getOperand(2));
3838  if (NeedClampOperand)
3839  I.addImm(0); // clamp bit for e64 encoding
3840 
3841  TII->legalizeOperands(*I);
3842 
3843  MI.eraseFromParent();
3844  return BB;
3845  }
3846  case AMDGPU::DS_GWS_INIT:
3847  case AMDGPU::DS_GWS_SEMA_V:
3848  case AMDGPU::DS_GWS_SEMA_BR:
3849  case AMDGPU::DS_GWS_SEMA_P:
3850  case AMDGPU::DS_GWS_SEMA_RELEASE_ALL:
3851  case AMDGPU::DS_GWS_BARRIER:
3852  // A s_waitcnt 0 is required to be the instruction immediately following.
3853  if (getSubtarget()->hasGWSAutoReplay()) {
3855  return BB;
3856  }
3857 
3858  return emitGWSMemViolTestLoop(MI, BB);
3859  default:
3861  }
3862 }
3863 
3865  return isTypeLegal(VT.getScalarType());
3866 }
3867 
3869  // This currently forces unfolding various combinations of fsub into fma with
3870  // free fneg'd operands. As long as we have fast FMA (controlled by
3871  // isFMAFasterThanFMulAndFAdd), we should perform these.
3872 
3873  // When fma is quarter rate, for f64 where add / sub are at best half rate,
3874  // most of these combines appear to be cycle neutral but save on instruction
3875  // count / code size.
3876  return true;
3877 }
3878 
3880  EVT VT) const {
3881  if (!VT.isVector()) {
3882  return MVT::i1;
3883  }
3884  return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
3885 }
3886 
3888  // TODO: Should i16 be used always if legal? For now it would force VALU
3889  // shifts.
3890  return (VT == MVT::i16) ? MVT::i16 : MVT::i32;
3891 }
3892 
3893 // Answering this is somewhat tricky and depends on the specific device which
3894 // have different rates for fma or all f64 operations.
3895 //
3896 // v_fma_f64 and v_mul_f64 always take the same number of cycles as each other
3897 // regardless of which device (although the number of cycles differs between
3898 // devices), so it is always profitable for f64.
3899 //
3900 // v_fma_f32 takes 4 or 16 cycles depending on the device, so it is profitable
3901 // only on full rate devices. Normally, we should prefer selecting v_mad_f32
3902 // which we can always do even without fused FP ops since it returns the same
3903 // result as the separate operations and since it is always full
3904 // rate. Therefore, we lie and report that it is not faster for f32. v_mad_f32
3905 // however does not support denormals, so we do report fma as faster if we have
3906 // a fast fma device and require denormals.
3907 //
3909  VT = VT.getScalarType();
3910 
3911  switch (VT.getSimpleVT().SimpleTy) {
3912  case MVT::f32: {
3913  // This is as fast on some subtargets. However, we always have full rate f32
3914  // mad available which returns the same result as the separate operations
3915  // which we should prefer over fma. We can't use this if we want to support
3916  // denormals, so only report this in these cases.
3917  if (Subtarget->hasFP32Denormals())
3918  return Subtarget->hasFastFMAF32() || Subtarget->hasDLInsts();
3919 
3920  // If the subtarget has v_fmac_f32, that's just as good as v_mac_f32.
3921  return Subtarget->hasFastFMAF32() && Subtarget->hasDLInsts();
3922  }
3923  case MVT::f64:
3924  return true;
3925  case MVT::f16:
3926  return Subtarget->has16BitInsts() && Subtarget->hasFP16Denormals();
3927  default:
3928  break;
3929  }
3930 
3931  return false;
3932 }
3933 
3934 //===----------------------------------------------------------------------===//
3935 // Custom DAG Lowering Operations
3936 //===----------------------------------------------------------------------===//
3937 
3938 // Work around LegalizeDAG doing the wrong thing and fully scalarizing if the
3939 // wider vector type is legal.
3941  SelectionDAG &DAG) const {
3942  unsigned Opc = Op.getOpcode();
3943  EVT VT = Op.getValueType();
3944  assert(VT == MVT::v4f16);
3945 
3946  SDValue Lo, Hi;
3947  std::tie(Lo, Hi) = DAG.SplitVectorOperand(Op.getNode(), 0);
3948 
3949  SDLoc SL(Op);
3950  SDValue OpLo = DAG.getNode(Opc, SL, Lo.getValueType(), Lo,
3951  Op->getFlags());
3952  SDValue OpHi = DAG.getNode(Opc, SL, Hi.getValueType(), Hi,
3953  Op->getFlags());
3954 
3955  return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
3956 }
3957 
3958 // Work around LegalizeDAG doing the wrong thing and fully scalarizing if the
3959 // wider vector type is legal.
3961  SelectionDAG &DAG) const {
3962  unsigned Opc = Op.getOpcode();
3963  EVT VT = Op.getValueType();
3964  assert(VT == MVT::v4i16 || VT == MVT::v4f16);
3965 
3966  SDValue Lo0, Hi0;
3967  std::tie(Lo0, Hi0) = DAG.SplitVectorOperand(Op.getNode(), 0);
3968  SDValue Lo1, Hi1;
3969  std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1);
3970 
3971  SDLoc SL(Op);
3972 
3973  SDValue OpLo = DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1,
3974  Op->getFlags());
3975  SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1,
3976  Op->getFlags());
3977 
3978  return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
3979 }
3980 
3982  SelectionDAG &DAG) const {
3983  unsigned Opc = Op.getOpcode();
3984  EVT VT = Op.getValueType();
3985  assert(VT == MVT::v4i16 || VT == MVT::v4f16);
3986 
3987  SDValue Lo0, Hi0;
3988  std::tie(Lo0, Hi0) = DAG.SplitVectorOperand(Op.getNode(), 0);
3989  SDValue Lo1, Hi1;
3990  std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1);
3991  SDValue Lo2, Hi2;
3992  std::tie(Lo2, Hi2) = DAG.SplitVectorOperand(Op.getNode(), 2);
3993 
3994  SDLoc SL(Op);
3995 
3996  SDValue OpLo = DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1, Lo2,
3997  Op->getFlags());
3998  SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1, Hi2,
3999  Op->getFlags());
4000 
4001  return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
4002 }
4003 
4004 
4006  switch (Op.getOpcode()) {
4007  default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
4008  case ISD::BRCOND: return LowerBRCOND(Op, DAG);
4009  case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4010  case ISD::LOAD: {
4011  SDValue Result = LowerLOAD(Op, DAG);
4012  assert((!Result.getNode() ||
4013  Result.getNode()->getNumValues() == 2) &&
4014  "Load should return a value and a chain");
4015  return Result;
4016  }
4017 
4018  case ISD::FSIN:
4019  case ISD::FCOS:
4020  return LowerTrig(Op, DAG);
4021  case ISD::SELECT: return LowerSELECT(Op, DAG);
4022  case ISD::FDIV: return LowerFDIV(Op, DAG);
4023  case ISD::ATOMIC_CMP_SWAP: return LowerATOMIC_CMP_SWAP(Op, DAG);
4024  case ISD::STORE: return LowerSTORE(Op, DAG);
4025  case ISD::GlobalAddress: {
4026  MachineFunction &MF = DAG.getMachineFunction();
4028  return LowerGlobalAddress(MFI, Op, DAG);
4029  }
4030  case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4031  case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
4032  case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
4033  case ISD::ADDRSPACECAST: return lowerADDRSPACECAST(Op, DAG);
4034  case ISD::INSERT_SUBVECTOR:
4035  return lowerINSERT_SUBVECTOR(Op, DAG);
4037  return lowerINSERT_VECTOR_ELT(Op, DAG);
4039  return lowerEXTRACT_VECTOR_ELT(Op, DAG);
4040  case ISD::VECTOR_SHUFFLE:
4041  return lowerVECTOR_SHUFFLE(Op, DAG);
4042  case ISD::BUILD_VECTOR:
4043  return lowerBUILD_VECTOR(Op, DAG);
4044  case ISD::FP_ROUND:
4045  return lowerFP_ROUND(Op, DAG);
4046  case ISD::TRAP:
4047  return lowerTRAP(Op, DAG);
4048  case ISD::DEBUGTRAP:
4049  return lowerDEBUGTRAP(Op, DAG);
4050  case ISD::FABS:
4051  case ISD::FNEG:
4052  case ISD::FCANONICALIZE:
4053  return splitUnaryVectorOp(Op, DAG);
4054  case ISD::FMINNUM:
4055  case ISD::FMAXNUM:
4056  return lowerFMINNUM_FMAXNUM(Op, DAG);
4057  case ISD::FMA:
4058  return splitTernaryVectorOp(Op, DAG);
4059  case ISD::SHL:
4060  case ISD::SRA:
4061  case ISD::SRL:
4062  case ISD::ADD:
4063  case ISD::SUB:
4064  case ISD::MUL:
4065  case ISD::SMIN:
4066  case ISD::SMAX:
4067  case ISD::UMIN:
4068  case ISD::UMAX:
4069  case ISD::FADD:
4070  case ISD::FMUL:
4071  case ISD::FMINNUM_IEEE:
4072  case ISD::FMAXNUM_IEEE:
4073  return splitBinaryVectorOp(Op, DAG);
4074  }
4075  return SDValue();
4076 }
4077 
4079  const SDLoc &DL,
4080  SelectionDAG &DAG, bool Unpacked) {
4081  if (!LoadVT.isVector())
4082  return Result;
4083 
4084  if (Unpacked) { // From v2i32/v4i32 back to v2f16/v4f16.
4085  // Truncate to v2i16/v4i16.
4086  EVT IntLoadVT = LoadVT.changeTypeToInteger();
4087 
4088  // Workaround legalizer not scalarizing truncate after vector op
4089  // legalization byt not creating intermediate vector trunc.
4091  DAG.ExtractVectorElements(Result, Elts);
4092  for (SDValue &Elt : Elts)
4093  Elt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Elt);
4094 
4095  Result = DAG.getBuildVector(IntLoadVT, DL, Elts);
4096 
4097  // Bitcast to original type (v2f16/v4f16).
4098  return DAG.getNode(ISD::BITCAST, DL, LoadVT, Result);
4099  }
4100 
4101  // Cast back to the original packed type.
4102  return DAG.getNode(ISD::BITCAST, DL, LoadVT, Result);
4103 }
4104 
4105 SDValue SITargetLowering::adjustLoadValueType(unsigned Opcode,
4106  MemSDNode *M,
4107  SelectionDAG &DAG,
4108  ArrayRef<SDValue> Ops,
4109  bool IsIntrinsic) const {
4110  SDLoc DL(M);
4111 
4112  bool Unpacked = Subtarget->hasUnpackedD16VMem();
4113  EVT LoadVT = M->getValueType(0);
4114 
4115  EVT EquivLoadVT = LoadVT;
4116  if (Unpacked && LoadVT.isVector()) {
4117  EquivLoadVT = LoadVT.isVector() ?
4119  LoadVT.getVectorNumElements()) : LoadVT;
4120  }
4121 
4122  // Change from v4f16/v2f16 to EquivLoadVT.
4123  SDVTList VTList = DAG.getVTList(EquivLoadVT, MVT::Other);
4124 
4125  SDValue Load
4126  = DAG.getMemIntrinsicNode(
4127  IsIntrinsic ? (unsigned)ISD::INTRINSIC_W_CHAIN : Opcode, DL,
4128  VTList, Ops, M->getMemoryVT(),
4129  M->getMemOperand());
4130  if (!Unpacked) // Just adjusted the opcode.
4131  return Load;
4132 
4133  SDValue Adjusted = adjustLoadValueTypeImpl(Load, LoadVT, DL, DAG, Unpacked);
4134 
4135  return DAG.getMergeValues({ Adjusted, Load.getValue(1) }, DL);
4136 }
4137 
4138 SDValue SITargetLowering::lowerIntrinsicLoad(MemSDNode *M, bool IsFormat,
4139  SelectionDAG &DAG,
4140  ArrayRef<SDValue> Ops) const {
4141  SDLoc DL(M);
4142  EVT LoadVT = M->getValueType(0);
4143  EVT EltType = LoadVT.getScalarType();
4144  EVT IntVT = LoadVT.changeTypeToInteger();
4145 
4146  bool IsD16 = IsFormat && (EltType.getSizeInBits() == 16);
4147 
4148  unsigned Opc =
4150 
4151  if (IsD16) {
4152  return adjustLoadValueType(AMDGPUISD::BUFFER_LOAD_FORMAT_D16, M, DAG, Ops);
4153  }
4154 
4155  // Handle BUFFER_LOAD_BYTE/UBYTE/SHORT/USHORT overloaded intrinsics
4156  if (!IsD16 && !LoadVT.isVector() && EltType.getSizeInBits() < 32)
4157  return handleByteShortBufferLoads(DAG, LoadVT, DL, Ops, M);
4158 
4159  if (isTypeLegal(LoadVT)) {
4160  return getMemIntrinsicNode(Opc, DL, M->getVTList(), Ops, IntVT,
4161  M->getMemOperand(), DAG);
4162  }
4163 
4164  EVT CastVT = getEquivalentMemType(*DAG.getContext(), LoadVT);
4165  SDVTList VTList = DAG.getVTList(CastVT, MVT::Other);
4166  SDValue MemNode = getMemIntrinsicNode(Opc, DL, VTList, Ops, CastVT,
4167  M->getMemOperand(), DAG);
4168  return DAG.getMergeValues(
4169  {DAG.getNode(ISD::BITCAST, DL, LoadVT, MemNode), MemNode.getValue(1)},
4170  DL);
4171 }
4172 
4174  SDNode *N, SelectionDAG &DAG) {
4175  EVT VT = N->getValueType(0);
4176  const auto *CD = cast<ConstantSDNode>(N->getOperand(3));
4177  int CondCode = CD->getSExtValue();
4178  if (CondCode < ICmpInst::Predicate::FIRST_ICMP_PREDICATE ||
4179  CondCode > ICmpInst::Predicate::LAST_ICMP_PREDICATE)
4180  return DAG.getUNDEF(VT);
4181 
4182  ICmpInst::Predicate IcInput = static_cast<ICmpInst::Predicate>(CondCode);
4183 
4184  SDValue LHS = N->getOperand(1);
4185  SDValue RHS = N->getOperand(2);
4186 
4187  SDLoc DL(N);
4188 
4189  EVT CmpVT = LHS.getValueType();
4190  if (CmpVT == MVT::i16 && !TLI.isTypeLegal(MVT::i16)) {
4191  unsigned PromoteOp = ICmpInst::isSigned(IcInput) ?
4193  LHS = DAG.getNode(PromoteOp, DL, MVT::i32, LHS);
4194  RHS = DAG.getNode(PromoteOp, DL, MVT::i32, RHS);
4195  }
4196 
4197  ISD::CondCode CCOpcode = getICmpCondCode(IcInput);
4198 
4199  unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize();
4201 
4202  SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS,
4203  DAG.getCondCode(CCOpcode));
4204  if (VT.bitsEq(CCVT))
4205  return SetCC;
4206  return DAG.getZExtOrTrunc(SetCC, DL, VT);
4207 }
4208 
4210  SDNode *N, SelectionDAG &DAG) {
4211  EVT VT = N->getValueType(0);
4212  const auto *CD = cast<ConstantSDNode>(N->getOperand(3));
4213 
4214  int CondCode = CD->getSExtValue();
4215  if (CondCode < FCmpInst::Predicate::FIRST_FCMP_PREDICATE ||
4216  CondCode > FCmpInst::Predicate::LAST_FCMP_PREDICATE) {
4217  return DAG.getUNDEF(VT);
4218  }
4219 
4220  SDValue Src0 = N->getOperand(1);
4221  SDValue Src1 = N->getOperand(2);
4222  EVT CmpVT = Src0.getValueType();
4223  SDLoc SL(N);
4224 
4225  if (CmpVT == MVT::f16 && !TLI.isTypeLegal(CmpVT)) {
4226  Src0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
4227  Src1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1);
4228  }
4229 
4230  FCmpInst::Predicate IcInput = static_cast<FCmpInst::Predicate>(CondCode);
4231  ISD::CondCode CCOpcode = getFCmpCondCode(IcInput);
4232  unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize();
4234  SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0,
4235  Src1, DAG.getCondCode(CCOpcode));
4236  if (VT.bitsEq(CCVT))
4237  return SetCC;
4238  return DAG.getZExtOrTrunc(SetCC, SL, VT);
4239 }
4240 
4243  SelectionDAG &DAG) const {
4244  switch (N->getOpcode()) {
4245  case ISD::INSERT_VECTOR_ELT: {
4246  if (SDValue Res = lowerINSERT_VECTOR_ELT(SDValue(N, 0), DAG))
4247  Results.push_back(Res);
4248  return;
4249  }
4250  case ISD::EXTRACT_VECTOR_ELT: {
4251  if (SDValue Res = lowerEXTRACT_VECTOR_ELT(SDValue(N, 0), DAG))
4252  Results.push_back(Res);
4253  return;
4254  }
4255  case ISD::INTRINSIC_WO_CHAIN: {
4256  unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4257  switch (IID) {
4258  case Intrinsic::amdgcn_cvt_pkrtz: {
4259  SDValue Src0 = N->getOperand(1);
4260  SDValue Src1 = N->getOperand(2);
4261  SDLoc SL(N);
4263  Src0, Src1);
4264  Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Cvt));
4265  return;
4266  }
4267  case Intrinsic::amdgcn_cvt_pknorm_i16:
4268  case Intrinsic::amdgcn_cvt_pknorm_u16:
4269  case Intrinsic::amdgcn_cvt_pk_i16:
4270  case Intrinsic::amdgcn_cvt_pk_u16: {
4271  SDValue Src0 = N->getOperand(1);
4272  SDValue Src1 = N->getOperand(2);
4273  SDLoc SL(N);
4274  unsigned Opcode;
4275 
4276  if (IID == Intrinsic::amdgcn_cvt_pknorm_i16)
4278  else if (IID == Intrinsic::amdgcn_cvt_pknorm_u16)
4280  else if (IID == Intrinsic::amdgcn_cvt_pk_i16)
4281  Opcode = AMDGPUISD::CVT_PK_I16_I32;
4282  else
4283  Opcode = AMDGPUISD::CVT_PK_U16_U32;
4284 
4285  EVT VT = N->getValueType(0);
4286  if (isTypeLegal(VT))
4287  Results.push_back(DAG.getNode(Opcode, SL, VT, Src0, Src1));
4288  else {
4289  SDValue Cvt = DAG.getNode(Opcode, SL, MVT::i32, Src0, Src1);
4290  Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, Cvt));
4291  }
4292  return;
4293  }
4294  }
4295  break;
4296  }
4297  case ISD::INTRINSIC_W_CHAIN: {
4298  if (SDValue Res = LowerINTRINSIC_W_CHAIN(SDValue(N, 0), DAG)) {
4299  if (Res.getOpcode() == ISD::MERGE_VALUES) {
4300  // FIXME: Hacky
4301  Results.push_back(Res.getOperand(0));
4302  Results.push_back(Res.getOperand(1));
4303  } else {
4304  Results.push_back(Res);
4305  Results.push_back(Res.getValue(1));
4306  }
4307  return;
4308  }
4309 
4310  break;
4311  }
4312  case ISD::SELECT: {
4313  SDLoc SL(N);
4314  EVT VT = N->getValueType(0);
4315  EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
4316  SDValue LHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(1));
4317  SDValue RHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(2));
4318 
4319  EVT SelectVT = NewVT;
4320  if (NewVT.bitsLT(MVT::i32)) {
4321  LHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, LHS);
4322  RHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, RHS);
4323  SelectVT = MVT::i32;
4324  }
4325 
4326  SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, SelectVT,
4327  N->getOperand(0), LHS, RHS);
4328 
4329  if (NewVT != SelectVT)
4330  NewSelect = DAG.getNode(ISD::TRUNCATE, SL, NewVT, NewSelect);
4331  Results.push_back(DAG.getNode(ISD::BITCAST, SL, VT, NewSelect));
4332  return;
4333  }
4334  case ISD::FNEG: {
4335  if (N->getValueType(0) != MVT::v2f16)
4336  break;
4337 
4338  SDLoc SL(N);
4339  SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, N->getOperand(0));
4340 
4341  SDValue Op = DAG.getNode(ISD::XOR, SL, MVT::i32,
4342  BC,
4343  DAG.getConstant(0x80008000, SL, MVT::i32));
4344  Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Op));
4345  return;
4346  }
4347  case ISD::FABS: {
4348  if (N->getValueType(0) != MVT::v2f16)
4349  break;
4350 
4351  SDLoc SL(N);
4352  SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, N->getOperand(0));
4353 
4354  SDValue Op = DAG.getNode(ISD::AND, SL, MVT::i32,
4355  BC,
4356  DAG.getConstant(0x7fff7fff, SL, MVT::i32));
4357  Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Op));
4358  return;
4359  }
4360  default:
4361  break;
4362  }
4363 }
4364 
4365 /// Helper function for LowerBRCOND
4366 static SDNode *findUser(SDValue Value, unsigned Opcode) {
4367 
4368  SDNode *Parent = Value.getNode();
4369  for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
4370  I != E; ++I) {
4371 
4372  if (I.getUse().get() != Value)
4373  continue;
4374 
4375  if (I->getOpcode() == Opcode)
4376  return *I;
4377  }
4378  return nullptr;
4379 }
4380 
4381 unsigned SITargetLowering::isCFIntrinsic(const SDNode *Intr) const {
4382  if (Intr->getOpcode() ==