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1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// SI DAG Lowering interface definition
11 //
12 //===----------------------------------------------------------------------===//
17 #include "AMDGPUISelLowering.h"
19 #include "SIInstrInfo.h"
21 namespace llvm {
23 class SITargetLowering final : public AMDGPUTargetLowering {
24 private:
25  const GCNSubtarget *Subtarget;
27 public:
29  CallingConv::ID CC,
30  EVT VT) const override;
32  CallingConv::ID CC,
33  EVT VT) const override;
36  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
37  unsigned &NumIntermediates, MVT &RegisterVT) const override;
39 private:
40  SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
41  SDValue Chain, uint64_t Offset) const;
42  SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
43  SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
44  const SDLoc &SL, SDValue Chain,
45  uint64_t Offset, unsigned Align, bool Signed,
46  const ISD::InputArg *Arg = nullptr) const;
48  SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
49  const SDLoc &SL, SDValue Chain,
50  const ISD::InputArg &Arg) const;
51  SDValue getPreloadedValue(SelectionDAG &DAG,
52  const SIMachineFunctionInfo &MFI,
53  EVT VT,
56  SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
57  SelectionDAG &DAG) const override;
58  SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
59  MVT VT, unsigned Offset) const;
60  SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr,
61  SelectionDAG &DAG) const;
62  SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset,
63  SDValue GLC, SDValue DLC, SelectionDAG &DAG) const;
65  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
66  SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
67  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
69  // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset
70  // (the offset that is included in bounds checking and swizzling, to be split
71  // between the instruction's voffset and immoffset fields) and soffset (the
72  // offset that is excluded from bounds checking and swizzling, to go in the
73  // instruction's soffset field). This function takes the first kind of
74  // offset and figures out how to split it between voffset and immoffset.
75  std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset,
76  SelectionDAG &DAG) const;
78  SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const;
79  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
80  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
81  SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
82  SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
83  SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
84  SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
85  SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
86  SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
87  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const;
88  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
89  SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
90  SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
91  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
92  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
93  SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M,
95  bool IsIntrinsic = false) const;
97  // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to
98  // dwordx4 if on SI.
99  SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
100  ArrayRef<SDValue> Ops, EVT MemVT,
101  MachineMemOperand *MMO, SelectionDAG &DAG) const;
103  SDValue handleD16VData(SDValue VData, SelectionDAG &DAG) const;
105  /// Converts \p Op, which must be of floating point type, to the
106  /// floating point type \p VT, by either extending or truncating it.
107  SDValue getFPExtOrFPTrunc(SelectionDAG &DAG,
108  SDValue Op,
109  const SDLoc &DL,
110  EVT VT) const;
112  SDValue convertArgType(
113  SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
114  bool Signed, const ISD::InputArg *Arg = nullptr) const;
116  /// Custom lowering for ISD::FP_ROUND for MVT::f16.
117  SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
118  SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const;
120  SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
121  SelectionDAG &DAG) const;
123  SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
124  SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
125  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
126  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
127  SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
128  SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
129  SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
130  SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const;
132  SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
134  SDValue performUCharToFloatCombine(SDNode *N,
135  DAGCombinerInfo &DCI) const;
136  SDValue performSHLPtrCombine(SDNode *N,
137  unsigned AS,
138  EVT MemVT,
139  DAGCombinerInfo &DCI) const;
141  SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
143  SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
144  unsigned Opc, SDValue LHS,
145  const ConstantSDNode *CRHS) const;
147  SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
148  SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
149  SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
150  SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
151  SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
152  SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
153  SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT,
154  const APFloat &C) const;
155  SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
157  SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
158  SDValue Op0, SDValue Op1) const;
159  SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
160  SDValue Op0, SDValue Op1, bool Signed) const;
161  SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
162  SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
163  SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
164  SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
165  SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
167  SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const;
168  unsigned getFusedOpcode(const SelectionDAG &DAG,
169  const SDNode *N0, const SDNode *N1) const;
170  SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
171  SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const;
172  SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
173  SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
174  SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
175  SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const;
176  SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
177  SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
178  SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
179  SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
181  bool isLegalFlatAddressingMode(const AddrMode &AM) const;
182  bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
184  unsigned isCFIntrinsic(const SDNode *Intr) const;
186  /// \returns True if fixup needs to be emitted for given global value \p GV,
187  /// false otherwise.
188  bool shouldEmitFixup(const GlobalValue *GV) const;
190  /// \returns True if GOT relocation needs to be emitted for given global value
191  /// \p GV, false otherwise.
192  bool shouldEmitGOTReloc(const GlobalValue *GV) const;
194  /// \returns True if PC-relative relocation needs to be emitted for given
195  /// global value \p GV, false otherwise.
196  bool shouldEmitPCReloc(const GlobalValue *GV) const;
198  // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the
199  // three offsets (voffset, soffset and instoffset) into the SDValue[3] array
200  // pointed to by Offsets.
201  void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG,
202  SDValue *Offsets, unsigned Align = 4) const;
204  // Handle 8 bit and 16 bit buffer loads
205  SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
206  ArrayRef<SDValue> Ops, MemSDNode *M) const;
208  // Handle 8 bit and 16 bit buffer stores
209  SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType,
210  SDLoc DL, SDValue Ops[],
211  MemSDNode *M) const;
213 public:
214  SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI);
216  const GCNSubtarget *getSubtarget() const;
218  bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const override;
220  bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
222  bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
223  MachineFunction &MF,
224  unsigned IntrinsicID) const override;
226  bool getAddrModeArguments(IntrinsicInst * /*I*/,
227  SmallVectorImpl<Value*> &/*Ops*/,
228  Type *&/*AccessTy*/) const override;
230  bool isLegalGlobalAddressingMode(const AddrMode &AM) const;
231  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
232  unsigned AS,
233  Instruction *I = nullptr) const override;
235  bool canMergeStoresTo(unsigned AS, EVT MemVT,
236  const SelectionDAG &DAG) const override;
239  EVT VT, unsigned AS, unsigned Align,
241  bool *IsFast = nullptr) const override;
243  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
244  unsigned SrcAlign, bool IsMemset,
245  bool ZeroMemset,
246  bool MemcpyStrSrc,
247  const AttributeList &FuncAttributes) const override;
249  bool isMemOpUniform(const SDNode *N) const;
250  bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
251  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
252  bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
255  getPreferredVectorAction(MVT VT) const override;
258  Type *Ty) const override;
260  bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
262  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
264  bool supportSplitCSR(MachineFunction *MF) const override;
265  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
267  MachineBasicBlock *Entry,
268  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
271  bool isVarArg,
273  const SDLoc &DL, SelectionDAG &DAG,
274  SmallVectorImpl<SDValue> &InVals) const override;
276  bool CanLowerReturn(CallingConv::ID CallConv,
277  MachineFunction &MF, bool isVarArg,
279  LLVMContext &Context) const override;
281  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
283  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
284  SelectionDAG &DAG) const override;
286  void passSpecialInputs(
287  CallLoweringInfo &CLI,
288  CCState &CCInfo,
290  SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
291  SmallVectorImpl<SDValue> &MemOpChains,
292  SDValue Chain) const;
294  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
295  CallingConv::ID CallConv, bool isVarArg,
297  const SDLoc &DL, SelectionDAG &DAG,
298  SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
299  SDValue ThisVal) const;
301  bool mayBeEmittedAsTailCall(const CallInst *) const override;
304  SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
306  const SmallVectorImpl<SDValue> &OutVals,
307  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
310  SmallVectorImpl<SDValue> &InVals) const override;
312  unsigned getRegisterByName(const char* RegName, EVT VT,
313  SelectionDAG &DAG) const override;
316  MachineBasicBlock *BB) const;
319  MachineBasicBlock *BB) const;
323  MachineBasicBlock *BB) const override;
325  bool hasBitPreservingFPLogic(EVT VT) const override;
326  bool enableAggressiveFMAFusion(EVT VT) const override;
327  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
328  EVT VT) const override;
329  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
330  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
333  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
336  SelectionDAG &DAG) const override;
338  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
339  SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
341  SDNode *Node) const override;
346  SDValue Ptr) const;
347  MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
348  uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
349  std::pair<unsigned, const TargetRegisterClass *>
351  StringRef Constraint, MVT VT) const override;
352  ConstraintType getConstraintType(StringRef Constraint) const override;
353  SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
354  SDValue V) const;
356  void finalizeLowering(MachineFunction &MF) const override;
359  KnownBits &Known,
360  const APInt &DemandedElts,
361  const SelectionDAG &DAG,
362  unsigned Depth = 0) const override;
364  bool isSDNodeSourceOfDivergence(const SDNode *N,
365  FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override;
367  bool isCanonicalized(SelectionDAG &DAG, SDValue Op,
368  unsigned MaxDepth = 5) const;
369  bool denormalsEnabledForType(EVT VT) const;
372  const SelectionDAG &DAG,
373  bool SNaN = false,
374  unsigned Depth = 0) const override;
377  unsigned getPrefLoopAlignment(MachineLoop *ML) const override;
378 };
380 } // End namespace llvm
382 #endif
uint64_t CallInst * C
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
bool isLegalGlobalAddressingMode(const AddrMode &AM) const
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
LLVMContext & Context
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &MF, unsigned IntrinsicID) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
InputArg - This struct carries flags and type information about a single incoming (formal) argument o...
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, SDValue V) const
bool canMergeStoresTo(unsigned AS, EVT MemVT, const SelectionDAG &DAG) const override
Returns if it&#39;s reasonable to merge stores to MemVT size.
This class represents a function call, abstracting a target machine&#39;s calling convention.
const GCNSubtarget * getSubtarget() const
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1100
Function Alias Analysis Results
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
SDNode * legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const
Legalize target independent instructions (e.g.
unsigned const TargetRegisterInfo * TRI
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:693
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
MachineSDNode * wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr) const
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
A description of a memory reference used in the backend.
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset...
bool isMemOpUniform(const SDNode *N) const
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
unsigned Intr
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always beneficiates from combining into FMA for a given value type...
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
bool getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value *> &, Type *&) const override
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock *> &Exits) const override
Insert explicit copies in entry and exit blocks.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const
bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const
MachineBasicBlock * splitKillBlock(MachineInstr &MI, MachineBasicBlock *BB) const
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override
Fold the instructions after selecting them.
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
bool isEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const override
If SNaN is false,.
bool mayBeEmittedAsTailCall(const CallInst *) const override
Return true if the target may be able emit the call instruction as a tail call.
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Extended Value Type.
Definition: ValueTypes.h:33
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
const unsigned MaxDepth
MachineBasicBlock * emitGWSMemViolTestLoop(MachineInstr &MI, MachineBasicBlock *BB) const
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
MachineSDNode * buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, uint32_t RsrcDword1, uint64_t RsrcDword2And3) const
Return a resource descriptor with the &#39;Add TID&#39; bit enabled The TID (Thread ID) is multiplied by the ...
CCState - This class holds information needed while lowering arguments and return values...
bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const override
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
Interface definition of the TargetLowering class that is common to all AMD GPUs.
CCValAssign - Represent assignment of one arg/retval to a location.
bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
An SDNode that represents everything that will be needed to construct a MachineInstr.
This is an abstract virtual class for memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
Class for arbitrary precision integers.
Definition: APInt.h:69
amdgpu Simplify well known AMD library false FunctionCallee Callee
void finalizeLowering(MachineFunction &MF) const override
Execute target specific actions to finalize target lowering.
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
Assign the register class depending on the number of bits set in the writemask.
Flags values. These may be or&#39;d together.
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
Representation of each machine instruction.
Definition: MachineInstr.h:64
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Interface definition for SIInstrInfo.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *IsFast=nullptr) const override
Determine if the target supports unaligned memory accesses.
bool isCanonicalized(SelectionDAG &DAG, SDValue Op, unsigned MaxDepth=5) const
#define I(x, y, z)
Definition: MD5.cpp:58
bool isShuffleMaskLegal(ArrayRef< int >, EVT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
uint32_t Size
Definition: Profile.cpp:46
SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
bool denormalsEnabledForType(EVT VT) const
unsigned getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
void computeKnownBitsForFrameIndex(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits of FrameIndex FIOp are known to be 0.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool isTypeDesirableForOp(unsigned Op, EVT VT) const override
Return true if the target has native support for the specified value type and it is &#39;desirable&#39; to us...
void passSpecialInputs(CallLoweringInfo &CLI, CCState &CCInfo, const SIMachineFunctionInfo &Info, SmallVectorImpl< std::pair< unsigned, SDValue >> &RegsToPass, SmallVectorImpl< SDValue > &MemOpChains, SDValue Chain) const
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, bool isThisReturn, SDValue ThisVal) const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself...
void initializeSplitCSR(MachineBasicBlock *Entry) const override
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:43
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
This class is used to represent ISD::LOAD nodes.