LLVM  10.0.0svn
SIMachineFunctionInfo.cpp
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1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
11 #include "AMDGPUSubtarget.h"
12 #include "SIRegisterInfo.h"
14 #include "Utils/AMDGPUBaseInfo.h"
15 #include "llvm/ADT/Optional.h"
20 #include "llvm/IR/CallingConv.h"
21 #include "llvm/IR/Function.h"
22 #include <cassert>
23 #include <vector>
24 
25 #define MAX_LANES 64
26 
27 using namespace llvm;
28 
31  Mode(MF.getFunction()),
32  PrivateSegmentBuffer(false),
33  DispatchPtr(false),
34  QueuePtr(false),
35  KernargSegmentPtr(false),
36  DispatchID(false),
37  FlatScratchInit(false),
38  WorkGroupIDX(false),
39  WorkGroupIDY(false),
40  WorkGroupIDZ(false),
41  WorkGroupInfo(false),
42  PrivateSegmentWaveByteOffset(false),
43  WorkItemIDX(false),
44  WorkItemIDY(false),
45  WorkItemIDZ(false),
46  ImplicitBufferPtr(false),
47  ImplicitArgPtr(false),
48  GITPtrHigh(0xffffffff),
49  HighBitsOf32BitAddress(0),
50  GDSSize(0) {
52  const Function &F = MF.getFunction();
53  FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
54  WavesPerEU = ST.getWavesPerEU(F);
55 
56  Occupancy = getMaxWavesPerEU();
57  limitOccupancy(MF);
58  CallingConv::ID CC = F.getCallingConv();
59 
61  if (!F.arg_empty())
62  KernargSegmentPtr = true;
63  WorkGroupIDX = true;
64  WorkItemIDX = true;
65  } else if (CC == CallingConv::AMDGPU_PS) {
66  PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
67  }
68 
69  if (!isEntryFunction()) {
70  // Non-entry functions have no special inputs for now, other registers
71  // required for scratch access.
72  ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
73  ScratchWaveOffsetReg = AMDGPU::SGPR33;
74 
75  // TODO: Pick a high register, and shift down, similar to a kernel.
76  FrameOffsetReg = AMDGPU::SGPR34;
77  StackPtrOffsetReg = AMDGPU::SGPR32;
78 
79  ArgInfo.PrivateSegmentBuffer =
80  ArgDescriptor::createRegister(ScratchRSrcReg);
82  ArgDescriptor::createRegister(ScratchWaveOffsetReg);
83 
84  if (F.hasFnAttribute("amdgpu-implicitarg-ptr"))
85  ImplicitArgPtr = true;
86  } else {
87  if (F.hasFnAttribute("amdgpu-implicitarg-ptr")) {
88  KernargSegmentPtr = true;
91  }
92  }
93 
94  if (F.hasFnAttribute("amdgpu-work-group-id-x"))
95  WorkGroupIDX = true;
96 
97  if (F.hasFnAttribute("amdgpu-work-group-id-y"))
98  WorkGroupIDY = true;
99 
100  if (F.hasFnAttribute("amdgpu-work-group-id-z"))
101  WorkGroupIDZ = true;
102 
103  if (F.hasFnAttribute("amdgpu-work-item-id-x"))
104  WorkItemIDX = true;
105 
106  if (F.hasFnAttribute("amdgpu-work-item-id-y"))
107  WorkItemIDY = true;
108 
109  if (F.hasFnAttribute("amdgpu-work-item-id-z"))
110  WorkItemIDZ = true;
111 
112  const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
113  bool HasStackObjects = FrameInfo.hasStackObjects();
114 
115  if (isEntryFunction()) {
116  // X, XY, and XYZ are the only supported combinations, so make sure Y is
117  // enabled if Z is.
118  if (WorkItemIDZ)
119  WorkItemIDY = true;
120 
121  PrivateSegmentWaveByteOffset = true;
122 
123  // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
124  if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
127  ArgDescriptor::createRegister(AMDGPU::SGPR5);
128  }
129 
130  bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
131  if (isAmdHsaOrMesa) {
132  PrivateSegmentBuffer = true;
133 
134  if (F.hasFnAttribute("amdgpu-dispatch-ptr"))
135  DispatchPtr = true;
136 
137  if (F.hasFnAttribute("amdgpu-queue-ptr"))
138  QueuePtr = true;
139 
140  if (F.hasFnAttribute("amdgpu-dispatch-id"))
141  DispatchID = true;
142  } else if (ST.isMesaGfxShader(F)) {
143  ImplicitBufferPtr = true;
144  }
145 
146  if (F.hasFnAttribute("amdgpu-kernarg-segment-ptr"))
147  KernargSegmentPtr = true;
148 
149  if (ST.hasFlatAddressSpace() && isEntryFunction() && isAmdHsaOrMesa) {
150  auto hasNonSpillStackObjects = [&]() {
151  // Avoid expensive checking if there's no stack objects.
152  if (!HasStackObjects)
153  return false;
154  for (auto OI = FrameInfo.getObjectIndexBegin(),
155  OE = FrameInfo.getObjectIndexEnd(); OI != OE; ++OI)
156  if (!FrameInfo.isSpillSlotObjectIndex(OI))
157  return true;
158  // All stack objects are spill slots.
159  return false;
160  };
161  // TODO: This could be refined a lot. The attribute is a poor way of
162  // detecting calls that may require it before argument lowering.
163  if (hasNonSpillStackObjects() || F.hasFnAttribute("amdgpu-flat-scratch"))
164  FlatScratchInit = true;
165  }
166 
167  Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
168  StringRef S = A.getValueAsString();
169  if (!S.empty())
170  S.consumeInteger(0, GITPtrHigh);
171 
172  A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
173  S = A.getValueAsString();
174  if (!S.empty())
175  S.consumeInteger(0, HighBitsOf32BitAddress);
176 
177  S = F.getFnAttribute("amdgpu-gds-size").getValueAsString();
178  if (!S.empty())
179  S.consumeInteger(0, GDSSize);
180 }
181 
184  const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
186  MF.getFunction()));
187 }
188 
190  const SIRegisterInfo &TRI) {
191  ArgInfo.PrivateSegmentBuffer =
192  ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
193  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_128RegClass));
194  NumUserSGPRs += 4;
195  return ArgInfo.PrivateSegmentBuffer.getRegister();
196 }
197 
199  ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
200  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
201  NumUserSGPRs += 2;
202  return ArgInfo.DispatchPtr.getRegister();
203 }
204 
206  ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
207  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
208  NumUserSGPRs += 2;
209  return ArgInfo.QueuePtr.getRegister();
210 }
211 
213  ArgInfo.KernargSegmentPtr
214  = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
215  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
216  NumUserSGPRs += 2;
217  return ArgInfo.KernargSegmentPtr.getRegister();
218 }
219 
221  ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
222  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
223  NumUserSGPRs += 2;
224  return ArgInfo.DispatchID.getRegister();
225 }
226 
228  ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
229  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
230  NumUserSGPRs += 2;
231  return ArgInfo.FlatScratchInit.getRegister();
232 }
233 
235  ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
236  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
237  NumUserSGPRs += 2;
238  return ArgInfo.ImplicitBufferPtr.getRegister();
239 }
240 
241 static bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) {
242  for (unsigned I = 0; CSRegs[I]; ++I) {
243  if (CSRegs[I] == Reg)
244  return true;
245  }
246 
247  return false;
248 }
249 
250 /// \p returns true if \p NumLanes slots are available in VGPRs already used for
251 /// SGPR spilling.
252 //
253 // FIXME: This only works after processFunctionBeforeFrameFinalized
255  unsigned NumNeed) const {
256  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
257  unsigned WaveSize = ST.getWavefrontSize();
258  return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size();
259 }
260 
261 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
263  int FI) {
264  std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
265 
266  // This has already been allocated.
267  if (!SpillLanes.empty())
268  return true;
269 
270  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
271  const SIRegisterInfo *TRI = ST.getRegisterInfo();
272  MachineFrameInfo &FrameInfo = MF.getFrameInfo();
274  unsigned WaveSize = ST.getWavefrontSize();
275 
276  unsigned Size = FrameInfo.getObjectSize(FI);
277  assert(Size >= 4 && Size <= 64 && "invalid sgpr spill size");
278  assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
279 
280  int NumLanes = Size / 4;
281 
282  const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
283 
284  // Make sure to handle the case where a wide SGPR spill may span between two
285  // VGPRs.
286  for (int I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
287  unsigned LaneVGPR;
288  unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
289 
290  if (VGPRIndex == 0) {
291  LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
292  if (LaneVGPR == AMDGPU::NoRegister) {
293  // We have no VGPRs left for spilling SGPRs. Reset because we will not
294  // partially spill the SGPR to VGPRs.
295  SGPRToVGPRSpills.erase(FI);
296  NumVGPRSpillLanes -= I;
297  return false;
298  }
299 
300  Optional<int> CSRSpillFI;
301  if ((FrameInfo.hasCalls() || !isEntryFunction()) && CSRegs &&
302  isCalleeSavedReg(CSRegs, LaneVGPR)) {
303  CSRSpillFI = FrameInfo.CreateSpillStackObject(4, 4);
304  }
305 
306  SpillVGPRs.push_back(SGPRSpillVGPRCSR(LaneVGPR, CSRSpillFI));
307 
308  // Add this register as live-in to all blocks to avoid machine verifer
309  // complaining about use of an undefined physical register.
310  for (MachineBasicBlock &BB : MF)
311  BB.addLiveIn(LaneVGPR);
312  } else {
313  LaneVGPR = SpillVGPRs.back().VGPR;
314  }
315 
316  SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex));
317  }
318 
319  return true;
320 }
321 
322 /// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
323 /// Either AGPR is spilled to VGPR to vice versa.
324 /// Returns true if a \p FI can be eliminated completely.
326  int FI,
327  bool isAGPRtoVGPR) {
329  MachineFrameInfo &FrameInfo = MF.getFrameInfo();
330  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
331 
332  assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
333 
334  auto &Spill = VGPRToAGPRSpills[FI];
335 
336  // This has already been allocated.
337  if (!Spill.Lanes.empty())
338  return Spill.FullyAllocated;
339 
340  unsigned Size = FrameInfo.getObjectSize(FI);
341  unsigned NumLanes = Size / 4;
342  Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
343 
344  const TargetRegisterClass &RC =
345  isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
346  auto Regs = RC.getRegisters();
347 
348  auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
349  const SIRegisterInfo *TRI = ST.getRegisterInfo();
350  Spill.FullyAllocated = true;
351 
352  // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
353  // once.
354  BitVector OtherUsedRegs;
355  OtherUsedRegs.resize(TRI->getNumRegs());
356 
357  const uint32_t *CSRMask =
359  if (CSRMask)
360  OtherUsedRegs.setBitsInMask(CSRMask);
361 
362  // TODO: Should include register tuples, but doesn't matter with current
363  // usage.
364  for (MCPhysReg Reg : SpillAGPR)
365  OtherUsedRegs.set(Reg);
366  for (MCPhysReg Reg : SpillVGPR)
367  OtherUsedRegs.set(Reg);
368 
370  for (unsigned I = 0; I < NumLanes; ++I) {
371  NextSpillReg = std::find_if(
372  NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
373  return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
374  !OtherUsedRegs[Reg];
375  });
376 
377  if (NextSpillReg == Regs.end()) { // Registers exhausted
378  Spill.FullyAllocated = false;
379  break;
380  }
381 
382  OtherUsedRegs.set(*NextSpillReg);
383  SpillRegs.push_back(*NextSpillReg);
384  Spill.Lanes[I] = *NextSpillReg++;
385  }
386 
387  return Spill.FullyAllocated;
388 }
389 
391  // The FP spill hasn't been inserted yet, so keep it around.
392  for (auto &R : SGPRToVGPRSpills) {
393  if (R.first != FramePointerSaveIndex)
394  MFI.RemoveStackObject(R.first);
395  }
396 
397  // All other SPGRs must be allocated on the default stack, so reset the stack
398  // ID.
399  for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd(); i != e;
400  ++i)
401  if (i != FramePointerSaveIndex)
403 
404  for (auto &R : VGPRToAGPRSpills) {
405  if (R.second.FullyAllocated)
406  MFI.RemoveStackObject(R.first);
407  }
408 }
409 
410 MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
411  assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
412  return AMDGPU::SGPR0 + NumUserSGPRs;
413 }
414 
415 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
416  return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
417 }
418 
420  const TargetRegisterInfo &TRI) {
421  yaml::StringValue Dest;
422  {
423  raw_string_ostream OS(Dest.Value);
424  OS << printReg(Reg, &TRI);
425  }
426  return Dest;
427 }
428 
431  const TargetRegisterInfo &TRI) {
433 
434  auto convertArg = [&](Optional<yaml::SIArgument> &A,
435  const ArgDescriptor &Arg) {
436  if (!Arg)
437  return false;
438 
439  // Create a register or stack argument.
441  if (Arg.isRegister()) {
443  OS << printReg(Arg.getRegister(), &TRI);
444  } else
445  SA.StackOffset = Arg.getStackOffset();
446  // Check and update the optional mask.
447  if (Arg.isMasked())
448  SA.Mask = Arg.getMask();
449 
450  A = SA;
451  return true;
452  };
453 
454  bool Any = false;
455  Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
456  Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
457  Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
458  Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
459  Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
460  Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
461  Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
462  Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
463  Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
464  Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
465  Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
466  Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
468  Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
469  Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
470  Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
471  Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
472  Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
473 
474  if (Any)
475  return AI;
476 
477  return None;
478 }
479 
481  const llvm::SIMachineFunctionInfo& MFI,
482  const TargetRegisterInfo &TRI)
485  LDSSize(MFI.getLDSSize()),
488  MemoryBound(MFI.isMemoryBound()),
490  ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
491  ScratchWaveOffsetReg(regToString(MFI.getScratchWaveOffsetReg(), TRI)),
492  FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
493  StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
494  ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)),
495  Mode(MFI.getMode()) {}
496 
499 }
500 
502  const yaml::SIMachineFunctionInfo &YamlMFI) {
505  LDSSize = YamlMFI.LDSSize;
508  MemoryBound = YamlMFI.MemoryBound;
509  WaveLimiter = YamlMFI.WaveLimiter;
510  return false;
511 }
unsigned addImplicitBufferPtr(const SIRegisterInfo &TRI)
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:371
Optional< SIArgument > PrivateSegmentWaveByteOffset
BitVector & set()
Definition: BitVector.h:397
Definition: Any.h:26
Interface definition for SIRegisterInfo.
Calling convention used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:207
Register getRegister() const
bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR)
Reserve AGPRs or VGPRs to support spilling for FrameIndex FI.
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
AMDGPU specific subclass of TargetSubtarget.
SI Whole Quad Mode
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn&#39;t been...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned getOccupancyWithLocalMemSize(uint32_t Bytes, const Function &) const
Inverse of getMaxLocalMemWithWaveCount.
bool hasStackObjects() const
Return true if there are any stack objects in this function.
Optional< SIArgument > KernargSegmentPtr
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
unsigned addKernargSegmentPtr(const SIRegisterInfo &TRI)
unsigned Reg
Optional< SIArgument > PrivateSegmentSize
static SIArgument createArgument(bool IsReg)
unsigned const TargetRegisterInfo * TRI
F(f)
void removeDeadFrameIndices(MachineFrameInfo &MFI)
SIMachineFunctionInfo(const MachineFunction &MF)
Optional< SIArgument > WorkItemIDY
Calling convention used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:191
AMDGPU::SIModeRegisterDefaults getMode() const
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:136
bool isMesaGfxShader(const Function &F) const
static ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
unsigned addDispatchID(const SIRegisterInfo &TRI)
Optional< SIArgument > DispatchPtr
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
static yaml::StringValue regToString(unsigned Reg, const TargetRegisterInfo &TRI)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Optional< SIArgument > ImplicitArgPtr
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
bool haveFreeLanesForSGPRSpill(const MachineFunction &MF, unsigned NumLane) const
returns true if NumLanes slots are available in VGPRs already used for SGPR spilling.
Optional< SIArgument > FlatScratchInit
bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI)
void limitOccupancy(const MachineFunction &MF)
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type consumeInteger(unsigned Radix, T &Result)
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:512
int getObjectIndexBegin() const
Return the minimum frame object index.
int getObjectIndexEnd() const
Return one past the maximum frame object index.
static Function * getFunction(Constant *C)
Definition: Evaluator.cpp:258
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI)
Reserve a slice of a VGPR to support spilling for FrameIndex FI.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Optional< SIArgument > WorkItemIDX
std::pair< unsigned, unsigned > getWavesPerEU(const Function &F) const
iterator_range< SmallVectorImpl< MCPhysReg >::const_iterator > getRegisters() const
unsigned const MachineRegisterInfo * MRI
Optional< SIArgument > QueuePtr
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void RemoveStackObject(int ObjectIdx)
Remove or mark dead a statically sized stack object.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Optional< SIArgument > DispatchID
unsigned addQueuePtr(const SIRegisterInfo &TRI)
Generation getGeneration() const
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
auto find_if(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range))
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1220
AMDGPUFunctionArgInfo & getArgInfo()
void setStackID(int ObjectIdx, uint8_t ID)
Optional< SIArgument > WorkGroupIDZ
int CreateSpillStackObject(uint64_t Size, unsigned Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void push_back(bool Val)
Definition: BitVector.h:506
unsigned addDispatchPtr(const SIRegisterInfo &TRI)
bool hasFlatAddressSpace() const
unsigned getWavefrontSize() const
unsigned LDSSize
Number of bytes in the LDS that are being used.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:194
unsigned getScratchRSrcReg() const
Returns the physical register reserved for use as the resource descriptor for scratch accesses...
Optional< unsigned > Mask
Optional< SIArgument > PrivateSegmentBuffer
unsigned getAlignmentForImplicitArgPtr() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
Optional< SIArgument > WorkItemIDZ
Optional< SIArgument > WorkGroupIDY
A wrapper around std::string which contains a source range that&#39;s being set during parsing...
unsigned addPrivateSegmentBuffer(const SIRegisterInfo &TRI)
unsigned addFlatScratchInit(const SIRegisterInfo &TRI)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
unsigned getInitialPSInputAddr(const Function &F)
Provides AMDGPU specific target descriptions.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
void mappingImpl(yaml::IO &YamlIO) override
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Optional< SIArgument > ImplicitBufferPtr
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:223
#define I(x, y, z)
Definition: MD5.cpp:58
bool isAmdHsaOrMesa(const Function &F) const
uint32_t Size
Definition: Profile.cpp:46
static bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg)
Optional< SIArgument > WorkGroupInfo
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static Optional< yaml::SIArgumentInfo > convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo, const TargetRegisterInfo &TRI)
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:482
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
bool hasMAIInsts() const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
std::pair< unsigned, unsigned > getFlatWorkGroupSizes(const Function &F) const
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:200
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add &#39;1&#39; bits from Mask to this vector.
Definition: BitVector.h:775
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
Optional< SIArgument > WorkGroupIDX
bool hasCalls() const
Return true if the current function has any function calls.
const SIRegisterInfo * getRegisterInfo() const override