SIRegisterInfo.cpp File Reference

SI implementation of the TargetRegisterInfo class. More...

#include "AMDGPU.h"
#include "AMDGPURegisterBankInfo.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUInstPrinter.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIMachineFunctionInfo.h"
#include "SIRegisterInfo.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveRegUnits.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "AMDGPUGenRegisterInfo.inc"

Go to the source code of this file.

Classes
struct	llvm::SGPRSpillBuilder
struct	llvm::SGPRSpillBuilder::PerVGPRData

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.

Macros
#define	GET_REGINFO_TARGET_DESC

Functions
static unsigned	getNumSubRegsForSpillOp (unsigned Op)
static int	getOffsetMUBUFStore (unsigned Opc)
static int	getOffsetMUBUFLoad (unsigned Opc)
static int	getOffenMUBUFStore (unsigned Opc)
static int	getOffenMUBUFLoad (unsigned Opc)
static MachineInstrBuilder	spillVGPRtoAGPR (const GCNSubtarget &ST, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, int Index, unsigned Lane, unsigned ValueReg, bool IsKill)
static bool	buildMUBUFOffsetLoadStore (const GCNSubtarget &ST, MachineFrameInfo &MFI, MachineBasicBlock::iterator MI, int Index, int64_t Offset)
static unsigned	getFlatScratchSpillOpcode (const SIInstrInfo *TII, unsigned LoadStoreOp, unsigned EltSize)
static const TargetRegisterClass *	getAnyVGPRClassForBitWidth (unsigned BitWidth)
static const TargetRegisterClass *	getAlignedVGPRClassForBitWidth (unsigned BitWidth)
static const TargetRegisterClass *	getAnyAGPRClassForBitWidth (unsigned BitWidth)
static const TargetRegisterClass *	getAlignedAGPRClassForBitWidth (unsigned BitWidth)
static const TargetRegisterClass *	getAnyVectorSuperClassForBitWidth (unsigned BitWidth)
static const TargetRegisterClass *	getAlignedVectorSuperClassForBitWidth (unsigned BitWidth)

Variables
static cl::opt< bool >	EnableSpillSGPRToVGPR ("amdgpu-spill-sgpr-to-vgpr", cl::desc("Enable spilling SGPRs to VGPRs"), cl::ReallyHidden, cl::init(true))
static const std::array< unsigned, 17 >	SubRegFromChannelTableWidthMap

Detailed Description

SI implementation of the TargetRegisterInfo class.

Definition in file SIRegisterInfo.cpp.

Macro Definition Documentation

GET_REGINFO_TARGET_DESC

#define GET_REGINFO_TARGET_DESC

Definition at line 29 of file SIRegisterInfo.cpp.

Function Documentation

buildMUBUFOffsetLoadStore()

static bool buildMUBUFOffsetLoadStore ( const GCNSubtarget &  ST, MachineFrameInfo &  MFI, MachineBasicBlock::iterator  MI, int  Index, int64_t  Offset  )

static

Definition at line 1255 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), DL, llvm::MachineInstrBuilder::getInstr(), getOffsetMUBUFLoad(), getOffsetMUBUFStore(), MBB, MI, llvm::Offset, spillVGPRtoAGPR(), and TII.

Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().

getAlignedAGPRClassForBitWidth()

static const TargetRegisterClass * getAlignedAGPRClassForBitWidth ( unsigned  BitWidth )

static

Definition at line 2716 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by llvm::SIRegisterInfo::getAGPRClassForBitWidth(), and llvm::SIRegisterInfo::getProperlyAlignedRC().

getAlignedVectorSuperClassForBitWidth()

static const TargetRegisterClass * getAlignedVectorSuperClassForBitWidth ( unsigned  BitWidth )

static

Definition at line 2790 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by llvm::SIRegisterInfo::getProperlyAlignedRC(), and llvm::SIRegisterInfo::getVectorSuperClassForBitWidth().

getAlignedVGPRClassForBitWidth()

static const TargetRegisterClass * getAlignedVGPRClassForBitWidth ( unsigned  BitWidth )

static

Definition at line 2640 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by llvm::SIRegisterInfo::getProperlyAlignedRC(), and llvm::SIRegisterInfo::getVGPRClassForBitWidth().

getAnyAGPRClassForBitWidth()

static const TargetRegisterClass * getAnyAGPRClassForBitWidth ( unsigned  BitWidth )

static

Definition at line 2684 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by llvm::SIRegisterInfo::getAGPRClassForBitWidth().

getAnyVectorSuperClassForBitWidth()

static const TargetRegisterClass * getAnyVectorSuperClassForBitWidth ( unsigned  BitWidth )

static

Definition at line 2758 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by llvm::SIRegisterInfo::getVectorSuperClassForBitWidth().

getAnyVGPRClassForBitWidth()

static const TargetRegisterClass * getAnyVGPRClassForBitWidth ( unsigned  BitWidth )

static

Definition at line 2608 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by llvm::SIRegisterInfo::getVGPRClassForBitWidth().

getFlatScratchSpillOpcode()

static unsigned getFlatScratchSpillOpcode ( const SIInstrInfo *  TII, unsigned  LoadStoreOp, unsigned  EltSize  )

static

Definition at line 1292 of file SIRegisterInfo.cpp.

References llvm::AMDGPU::getFlatScratchInstSTfromSS(), llvm::AMDGPU::getFlatScratchInstSVfromSS(), llvm::AMDGPU::hasNamedOperand(), llvm_unreachable, and TII.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore().

getNumSubRegsForSpillOp()

static unsigned getNumSubRegsForSpillOp ( unsigned  Op )

static

Definition at line 959 of file SIRegisterInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().

getOffenMUBUFLoad()

static int getOffenMUBUFLoad ( unsigned  Opc )

static

Definition at line 1177 of file SIRegisterInfo.cpp.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore().

getOffenMUBUFStore()

static int getOffenMUBUFStore ( unsigned  Opc )

static

Definition at line 1154 of file SIRegisterInfo.cpp.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore().

getOffsetMUBUFLoad()

static int getOffsetMUBUFLoad ( unsigned  Opc )

static

Definition at line 1119 of file SIRegisterInfo.cpp.

Referenced by buildMUBUFOffsetLoadStore().

getOffsetMUBUFStore()

static int getOffsetMUBUFStore ( unsigned  Opc )

static

Definition at line 1096 of file SIRegisterInfo.cpp.

Referenced by buildMUBUFOffsetLoadStore().

spillVGPRtoAGPR()

static MachineInstrBuilder spillVGPRtoAGPR ( const GCNSubtarget &  ST, MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MI, int  Index, unsigned  Lane, unsigned  ValueReg, bool  IsKill  )

static

Definition at line 1212 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::MachineFunction::getInfo(), llvm::getKillRegState(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::SIMachineFunctionInfo::getVGPRToAGPRSpill(), MBB, MI, MRI, llvm::MachineInstr::ReloadReuse, llvm::MachineInstr::setAsmPrinterFlag(), TII, and TRI.

Referenced by buildMUBUFOffsetLoadStore(), and llvm::SIRegisterInfo::buildSpillLoadStore().

Variable Documentation

EnableSpillSGPRToVGPR

cl::opt< bool > EnableSpillSGPRToVGPR("amdgpu-spill-sgpr-to-vgpr", cl::desc("Enable spilling SGPRs to VGPRs"), cl::ReallyHidden, cl::init(true)) ( "amdgpu-spill-sgpr-to-vgpr"  , cl::desc("Enable spilling SGPRs to VGPRs")  , cl::ReallyHidden  , cl::init(true)    )

static

SubRegFromChannelTableWidthMap

const std::array<unsigned, 17> SubRegFromChannelTableWidthMap

static

Initial value:

= {
    0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 9}

Definition at line 45 of file SIRegisterInfo.cpp.

Referenced by llvm::SIRegisterInfo::getSubRegFromChannel(), and llvm::SIRegisterInfo::SIRegisterInfo().