LLVM  10.0.0svn
Functions | Variables
SIRegisterInfo.cpp File Reference

SI implementation of the TargetRegisterInfo class. More...

#include "SIRegisterInfo.h"
#include "AMDGPURegisterBankInfo.h"
#include "AMDGPUSubtarget.h"
#include "SIInstrInfo.h"
#include "SIMachineFunctionInfo.h"
#include "MCTargetDesc/AMDGPUInstPrinter.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/LLVMContext.h"
Include dependency graph for SIRegisterInfo.cpp:

Go to the source code of this file.

Functions

static bool hasPressureSet (const int *PSets, unsigned PSetID)
 
static unsigned findPrivateSegmentWaveByteOffsetRegIndex (unsigned RegCount)
 
static unsigned getNumSubRegsForSpillOp (unsigned Op)
 
static int getOffsetMUBUFStore (unsigned Opc)
 
static int getOffsetMUBUFLoad (unsigned Opc)
 
static MachineInstrBuilder spillVGPRtoAGPR (MachineBasicBlock::iterator MI, int Index, unsigned Lane, unsigned ValueReg, bool IsKill)
 
static bool buildMUBUFOffsetLoadStore (const SIInstrInfo *TII, MachineFrameInfo &MFI, MachineBasicBlock::iterator MI, int Index, int64_t Offset)
 
static std::pair< unsigned, unsignedgetSpillEltSize (unsigned SuperRegSize, bool Store)
 

Variables

static cl::opt< boolEnableSpillSGPRToSMEM ("amdgpu-spill-sgpr-to-smem", cl::desc("Use scalar stores to spill SGPRs if supported by subtarget"), cl::init(false))
 
static cl::opt< boolEnableSpillSGPRToVGPR ("amdgpu-spill-sgpr-to-vgpr", cl::desc("Enable spilling VGPRs to SGPRs"), cl::ReallyHidden, cl::init(true))
 

Detailed Description

SI implementation of the TargetRegisterInfo class.

Definition in file SIRegisterInfo.cpp.

Function Documentation

◆ buildMUBUFOffsetLoadStore()

static bool buildMUBUFOffsetLoadStore ( const SIInstrInfo TII,
MachineFrameInfo MFI,
MachineBasicBlock::iterator  MI,
int  Index,
int64_t  Offset 
)
static

◆ findPrivateSegmentWaveByteOffsetRegIndex()

static unsigned findPrivateSegmentWaveByteOffsetRegIndex ( unsigned  RegCount)
static

Definition at line 129 of file SIRegisterInfo.cpp.

References Reg.

Referenced by llvm::SIRegisterInfo::reservedPrivateSegmentWaveByteOffsetReg().

◆ getNumSubRegsForSpillOp()

static unsigned getNumSubRegsForSpillOp ( unsigned  Op)
static

Definition at line 450 of file SIRegisterInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().

◆ getOffsetMUBUFLoad()

static int getOffsetMUBUFLoad ( unsigned  Opc)
static

Definition at line 528 of file SIRegisterInfo.cpp.

Referenced by buildMUBUFOffsetLoadStore().

◆ getOffsetMUBUFStore()

static int getOffsetMUBUFStore ( unsigned  Opc)
static

Definition at line 507 of file SIRegisterInfo.cpp.

Referenced by buildMUBUFOffsetLoadStore().

◆ getSpillEltSize()

static std::pair<unsigned, unsigned> getSpillEltSize ( unsigned  SuperRegSize,
bool  Store 
)
static

◆ hasPressureSet()

static bool hasPressureSet ( const int *  PSets,
unsigned  PSetID 
)
static

◆ spillVGPRtoAGPR()

static MachineInstrBuilder spillVGPRtoAGPR ( MachineBasicBlock::iterator  MI,
int  Index,
unsigned  Lane,
unsigned  ValueReg,
bool  IsKill 
)
static

Variable Documentation

◆ EnableSpillSGPRToSMEM

cl::opt<bool> EnableSpillSGPRToSMEM("amdgpu-spill-sgpr-to-smem", cl::desc("Use scalar stores to spill SGPRs if supported by subtarget"), cl::init(false))
static

Referenced by hasPressureSet().

◆ EnableSpillSGPRToVGPR

cl::opt<bool> EnableSpillSGPRToVGPR("amdgpu-spill-sgpr-to-vgpr", cl::desc("Enable spilling VGPRs to SGPRs"), cl::ReallyHidden, cl::init(true))
static

Referenced by hasPressureSet().