LLVM  10.0.0svn
ScheduleDAGVLIW.cpp
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1 //===- ScheduleDAGVLIW.cpp - SelectionDAG list scheduler for VLIW -*- C++ -*-=//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements a top-down list scheduler, using standard algorithms.
10 // The basic approach uses a priority queue of available nodes to schedule.
11 // One at a time, nodes are taken from the priority queue (thus in priority
12 // order), checked for legality to schedule, and emitted if legal.
13 //
14 // Nodes may not be legal to schedule either due to structural hazards (e.g.
15 // pipeline or resource constraints) or because an input to the instruction has
16 // not completed execution.
17 //
18 //===----------------------------------------------------------------------===//
19 
20 #include "ScheduleDAGSDNodes.h"
21 #include "llvm/ADT/Statistic.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/Support/Debug.h"
34 #include <climits>
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "pre-RA-sched"
38 
39 STATISTIC(NumNoops , "Number of noops inserted");
40 STATISTIC(NumStalls, "Number of pipeline stalls");
41 
42 static RegisterScheduler
43  VLIWScheduler("vliw-td", "VLIW scheduler",
45 
46 namespace {
47 //===----------------------------------------------------------------------===//
48 /// ScheduleDAGVLIW - The actual DFA list scheduler implementation. This
49 /// supports / top-down scheduling.
50 ///
51 class ScheduleDAGVLIW : public ScheduleDAGSDNodes {
52 private:
53  /// AvailableQueue - The priority queue to use for the available SUnits.
54  ///
55  SchedulingPriorityQueue *AvailableQueue;
56 
57  /// PendingQueue - This contains all of the instructions whose operands have
58  /// been issued, but their results are not ready yet (due to the latency of
59  /// the operation). Once the operands become available, the instruction is
60  /// added to the AvailableQueue.
61  std::vector<SUnit*> PendingQueue;
62 
63  /// HazardRec - The hazard recognizer to use.
64  ScheduleHazardRecognizer *HazardRec;
65 
66  /// AA - AliasAnalysis for making memory reference queries.
67  AliasAnalysis *AA;
68 
69 public:
70  ScheduleDAGVLIW(MachineFunction &mf,
72  SchedulingPriorityQueue *availqueue)
73  : ScheduleDAGSDNodes(mf), AvailableQueue(availqueue), AA(aa) {
74  const TargetSubtargetInfo &STI = mf.getSubtarget();
75  HazardRec = STI.getInstrInfo()->CreateTargetHazardRecognizer(&STI, this);
76  }
77 
78  ~ScheduleDAGVLIW() override {
79  delete HazardRec;
80  delete AvailableQueue;
81  }
82 
83  void Schedule() override;
84 
85 private:
86  void releaseSucc(SUnit *SU, const SDep &D);
87  void releaseSuccessors(SUnit *SU);
88  void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
89  void listScheduleTopDown();
90 };
91 } // end anonymous namespace
92 
93 /// Schedule - Schedule the DAG using list scheduling.
94 void ScheduleDAGVLIW::Schedule() {
95  LLVM_DEBUG(dbgs() << "********** List Scheduling " << printMBBReference(*BB)
96  << " '" << BB->getName() << "' **********\n");
97 
98  // Build the scheduling graph.
99  BuildSchedGraph(AA);
100 
101  AvailableQueue->initNodes(SUnits);
102 
103  listScheduleTopDown();
104 
105  AvailableQueue->releaseState();
106 }
107 
108 //===----------------------------------------------------------------------===//
109 // Top-Down Scheduling
110 //===----------------------------------------------------------------------===//
111 
112 /// releaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
113 /// the PendingQueue if the count reaches zero. Also update its cycle bound.
114 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) {
115  SUnit *SuccSU = D.getSUnit();
116 
117 #ifndef NDEBUG
118  if (SuccSU->NumPredsLeft == 0) {
119  dbgs() << "*** Scheduling failed! ***\n";
120  dumpNode(*SuccSU);
121  dbgs() << " has been released too many times!\n";
122  llvm_unreachable(nullptr);
123  }
124 #endif
125  assert(!D.isWeak() && "unexpected artificial DAG edge");
126 
127  --SuccSU->NumPredsLeft;
128 
129  SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency());
130 
131  // If all the node's predecessors are scheduled, this node is ready
132  // to be scheduled. Ignore the special ExitSU node.
133  if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) {
134  PendingQueue.push_back(SuccSU);
135  }
136 }
137 
138 void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) {
139  // Top down: release successors.
140  for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
141  I != E; ++I) {
142  assert(!I->isAssignedRegDep() &&
143  "The list-td scheduler doesn't yet support physreg dependencies!");
144 
145  releaseSucc(SU, *I);
146  }
147 }
148 
149 /// scheduleNodeTopDown - Add the node to the schedule. Decrement the pending
150 /// count of its successors. If a successor pending count is zero, add it to
151 /// the Available queue.
152 void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
153  LLVM_DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: ");
154  LLVM_DEBUG(dumpNode(*SU));
155 
156  Sequence.push_back(SU);
157  assert(CurCycle >= SU->getDepth() && "Node scheduled above its depth!");
158  SU->setDepthToAtLeast(CurCycle);
159 
160  releaseSuccessors(SU);
161  SU->isScheduled = true;
162  AvailableQueue->scheduledNode(SU);
163 }
164 
165 /// listScheduleTopDown - The main loop of list scheduling for top-down
166 /// schedulers.
167 void ScheduleDAGVLIW::listScheduleTopDown() {
168  unsigned CurCycle = 0;
169 
170  // Release any successors of the special Entry node.
171  releaseSuccessors(&EntrySU);
172 
173  // All leaves to AvailableQueue.
174  for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
175  // It is available if it has no predecessors.
176  if (SUnits[i].Preds.empty()) {
177  AvailableQueue->push(&SUnits[i]);
178  SUnits[i].isAvailable = true;
179  }
180  }
181 
182  // While AvailableQueue is not empty, grab the node with the highest
183  // priority. If it is not ready put it back. Schedule the node.
184  std::vector<SUnit*> NotReady;
185  Sequence.reserve(SUnits.size());
186  while (!AvailableQueue->empty() || !PendingQueue.empty()) {
187  // Check to see if any of the pending instructions are ready to issue. If
188  // so, add them to the available queue.
189  for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
190  if (PendingQueue[i]->getDepth() == CurCycle) {
191  AvailableQueue->push(PendingQueue[i]);
192  PendingQueue[i]->isAvailable = true;
193  PendingQueue[i] = PendingQueue.back();
194  PendingQueue.pop_back();
195  --i; --e;
196  }
197  else {
198  assert(PendingQueue[i]->getDepth() > CurCycle && "Negative latency?");
199  }
200  }
201 
202  // If there are no instructions available, don't try to issue anything, and
203  // don't advance the hazard recognizer.
204  if (AvailableQueue->empty()) {
205  // Reset DFA state.
206  AvailableQueue->scheduledNode(nullptr);
207  ++CurCycle;
208  continue;
209  }
210 
211  SUnit *FoundSUnit = nullptr;
212 
213  bool HasNoopHazards = false;
214  while (!AvailableQueue->empty()) {
215  SUnit *CurSUnit = AvailableQueue->pop();
216 
218  HazardRec->getHazardType(CurSUnit, 0/*no stalls*/);
220  FoundSUnit = CurSUnit;
221  break;
222  }
223 
224  // Remember if this is a noop hazard.
225  HasNoopHazards |= HT == ScheduleHazardRecognizer::NoopHazard;
226 
227  NotReady.push_back(CurSUnit);
228  }
229 
230  // Add the nodes that aren't ready back onto the available list.
231  if (!NotReady.empty()) {
232  AvailableQueue->push_all(NotReady);
233  NotReady.clear();
234  }
235 
236  // If we found a node to schedule, do it now.
237  if (FoundSUnit) {
238  scheduleNodeTopDown(FoundSUnit, CurCycle);
239  HazardRec->EmitInstruction(FoundSUnit);
240 
241  // If this is a pseudo-op node, we don't want to increment the current
242  // cycle.
243  if (FoundSUnit->Latency) // Don't increment CurCycle for pseudo-ops!
244  ++CurCycle;
245  } else if (!HasNoopHazards) {
246  // Otherwise, we have a pipeline stall, but no other problem, just advance
247  // the current cycle and try again.
248  LLVM_DEBUG(dbgs() << "*** Advancing cycle, no work to do\n");
249  HazardRec->AdvanceCycle();
250  ++NumStalls;
251  ++CurCycle;
252  } else {
253  // Otherwise, we have no instructions to issue and we have instructions
254  // that will fault if we don't do this right. This is the case for
255  // processors without pipeline interlocks and other cases.
256  LLVM_DEBUG(dbgs() << "*** Emitting noop\n");
257  HazardRec->EmitNoop();
258  Sequence.push_back(nullptr); // NULL here means noop
259  ++NumNoops;
260  ++CurCycle;
261  }
262  }
263 
264 #ifndef NDEBUG
265  VerifyScheduledSequence(/*isBottomUp=*/false);
266 #endif
267 }
268 
269 //===----------------------------------------------------------------------===//
270 // Public Constructor Functions
271 //===----------------------------------------------------------------------===//
272 
273 /// createVLIWDAGScheduler - This creates a top-down list scheduler.
276  return new ScheduleDAGVLIW(*IS->MF, IS->AA, new ResourcePriorityQueue(IS));
277 }
virtual void initNodes(std::vector< SUnit > &SUnits)=0
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned getDepth() const
Returns the depth of this node, which is the length of the maximum path up to any node which has no p...
Definition: ScheduleDAG.h:398
virtual void push(SUnit *U)=0
STATISTIC(NumFunctions, "Total number of functions")
SmallVectorImpl< SDep >::iterator succ_iterator
Definition: ScheduleDAG.h:260
virtual void AdvanceCycle()
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot...
MachineFunction * MF
bool isScheduled
True once scheduled.
Definition: ScheduleDAG.h:284
This interface is used to plug different priorities computation algorithms into the list scheduler...
Definition: ScheduleDAG.h:496
unsigned getLatency() const
Returns the latency value for this edge, which roughly means the minimum number of cycles that must e...
Definition: ScheduleDAG.h:142
virtual void releaseState()=0
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
void push_all(const std::vector< SUnit *> &Nodes)
Definition: ScheduleDAG.h:527
unsigned NumPredsLeft
of preds not scheduled.
Definition: ScheduleDAG.h:268
virtual const TargetInstrInfo * getInstrInfo() const
SUnit * getSUnit() const
Definition: ScheduleDAG.h:480
void setDepthToAtLeast(unsigned NewDepth)
If NewDepth is greater than this node&#39;s depth value, sets it to be the new depth value.
Scheduling dependency.
Definition: ScheduleDAG.h:49
ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
ScheduleDAGSDNodes * createVLIWDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createVLIWDAGScheduler - Scheduler for VLIW targets.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
unsigned short Latency
Node latency.
Definition: ScheduleDAG.h:273
virtual bool empty() const =0
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
constexpr double e
Definition: MathExtras.h:57
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
virtual void EmitNoop()
EmitNoop - This callback is invoked when a noop was added to the instruction stream.
virtual void EmitInstruction(SUnit *)
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
static unsigned getDepth(const SmallVectorImpl< const MachineBasicBlock *> &Stack, const MachineBasicBlock *MBB)
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
virtual void scheduledNode(SUnit *)
As each node is scheduled, this method is invoked.
Definition: ScheduleDAG.h:542
TargetSubtargetInfo - Generic base class for all target subtargets.
static RegisterScheduler VLIWScheduler("vliw-td", "VLIW scheduler", createVLIWDAGScheduler)
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
#define I(x, y, z)
Definition: MD5.cpp:58
Sequence
A sequence of states that a pointer may go through in which an objc_retain and objc_release are actua...
Definition: PtrState.h:40
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SmallVector< SDep, 4 > Succs
All sunit successors.
Definition: ScheduleDAG.h:257
bool isWeak() const
Tests if this a weak dependence.
Definition: ScheduleDAG.h:194
#define LLVM_DEBUG(X)
Definition: Debug.h:122
virtual SUnit * pop()=0
virtual HazardType getHazardType(SUnit *m, int Stalls=0)
getHazardType - Return the hazard type of emitting this node.
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242