LLVM  9.0.0svn
SelectionDAGBuilder.cpp
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1 //===- SelectionDAGBuilder.cpp - Selection-DAG building -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements routines for translating from LLVM IR into SelectionDAG IR.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "SelectionDAGBuilder.h"
14 #include "SDNodeDbgValue.h"
15 #include "llvm/ADT/APFloat.h"
16 #include "llvm/ADT/APInt.h"
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/None.h"
21 #include "llvm/ADT/Optional.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/SmallPtrSet.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/ADT/Twine.h"
33 #include "llvm/Analysis/Loads.h"
38 #include "llvm/CodeGen/Analysis.h"
56 #include "llvm/CodeGen/StackMaps.h"
65 #include "llvm/IR/Argument.h"
66 #include "llvm/IR/Attributes.h"
67 #include "llvm/IR/BasicBlock.h"
68 #include "llvm/IR/CFG.h"
69 #include "llvm/IR/CallSite.h"
70 #include "llvm/IR/CallingConv.h"
71 #include "llvm/IR/Constant.h"
72 #include "llvm/IR/ConstantRange.h"
73 #include "llvm/IR/Constants.h"
74 #include "llvm/IR/DataLayout.h"
76 #include "llvm/IR/DebugLoc.h"
77 #include "llvm/IR/DerivedTypes.h"
78 #include "llvm/IR/Function.h"
80 #include "llvm/IR/InlineAsm.h"
81 #include "llvm/IR/InstrTypes.h"
82 #include "llvm/IR/Instruction.h"
83 #include "llvm/IR/Instructions.h"
84 #include "llvm/IR/IntrinsicInst.h"
85 #include "llvm/IR/Intrinsics.h"
86 #include "llvm/IR/LLVMContext.h"
87 #include "llvm/IR/Metadata.h"
88 #include "llvm/IR/Module.h"
89 #include "llvm/IR/Operator.h"
90 #include "llvm/IR/PatternMatch.h"
91 #include "llvm/IR/Statepoint.h"
92 #include "llvm/IR/Type.h"
93 #include "llvm/IR/User.h"
94 #include "llvm/IR/Value.h"
95 #include "llvm/MC/MCContext.h"
96 #include "llvm/MC/MCSymbol.h"
99 #include "llvm/Support/Casting.h"
100 #include "llvm/Support/CodeGen.h"
102 #include "llvm/Support/Compiler.h"
103 #include "llvm/Support/Debug.h"
106 #include "llvm/Support/MathExtras.h"
112 #include <algorithm>
113 #include <cassert>
114 #include <cstddef>
115 #include <cstdint>
116 #include <cstring>
117 #include <iterator>
118 #include <limits>
119 #include <numeric>
120 #include <tuple>
121 #include <utility>
122 #include <vector>
123 
124 using namespace llvm;
125 using namespace PatternMatch;
126 
127 #define DEBUG_TYPE "isel"
128 
129 /// LimitFloatPrecision - Generate low-precision inline sequences for
130 /// some float libcalls (6, 8 or 12 bits).
131 static unsigned LimitFloatPrecision;
132 
134  LimitFPPrecision("limit-float-precision",
135  cl::desc("Generate low-precision inline sequences "
136  "for some float libcalls"),
137  cl::location(LimitFloatPrecision), cl::Hidden,
138  cl::init(0));
139 
141  "switch-peel-threshold", cl::Hidden, cl::init(66),
142  cl::desc("Set the case probability threshold for peeling the case from a "
143  "switch statement. A value greater than 100 will void this "
144  "optimization"));
145 
146 // Limit the width of DAG chains. This is important in general to prevent
147 // DAG-based analysis from blowing up. For example, alias analysis and
148 // load clustering may not complete in reasonable time. It is difficult to
149 // recognize and avoid this situation within each individual analysis, and
150 // future analyses are likely to have the same behavior. Limiting DAG width is
151 // the safe approach and will be especially important with global DAGs.
152 //
153 // MaxParallelChains default is arbitrarily high to avoid affecting
154 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
155 // sequence over this should have been converted to llvm.memcpy by the
156 // frontend. It is easy to induce this behavior with .ll code such as:
157 // %buffer = alloca [4096 x i8]
158 // %data = load [4096 x i8]* %argPtr
159 // store [4096 x i8] %data, [4096 x i8]* %buffer
160 static const unsigned MaxParallelChains = 64;
161 
162 // Return the calling convention if the Value passed requires ABI mangling as it
163 // is a parameter to a function or a return value from a function which is not
164 // an intrinsic.
166  if (auto *R = dyn_cast<ReturnInst>(V))
167  return R->getParent()->getParent()->getCallingConv();
168 
169  if (auto *CI = dyn_cast<CallInst>(V)) {
170  const bool IsInlineAsm = CI->isInlineAsm();
171  const bool IsIndirectFunctionCall =
172  !IsInlineAsm && !CI->getCalledFunction();
173 
174  // It is possible that the call instruction is an inline asm statement or an
175  // indirect function call in which case the return value of
176  // getCalledFunction() would be nullptr.
177  const bool IsInstrinsicCall =
178  !IsInlineAsm && !IsIndirectFunctionCall &&
179  CI->getCalledFunction()->getIntrinsicID() != Intrinsic::not_intrinsic;
180 
181  if (!IsInlineAsm && !IsInstrinsicCall)
182  return CI->getCallingConv();
183  }
184 
185  return None;
186 }
187 
188 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
189  const SDValue *Parts, unsigned NumParts,
190  MVT PartVT, EVT ValueVT, const Value *V,
192 
193 /// getCopyFromParts - Create a value that contains the specified legal parts
194 /// combined into the value they represent. If the parts combine to a type
195 /// larger than ValueVT then AssertOp can be used to specify whether the extra
196 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
197 /// (ISD::AssertSext).
199  const SDValue *Parts, unsigned NumParts,
200  MVT PartVT, EVT ValueVT, const Value *V,
201  Optional<CallingConv::ID> CC = None,
202  Optional<ISD::NodeType> AssertOp = None) {
203  if (ValueVT.isVector())
204  return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V,
205  CC);
206 
207  assert(NumParts > 0 && "No parts to assemble!");
208  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
209  SDValue Val = Parts[0];
210 
211  if (NumParts > 1) {
212  // Assemble the value from multiple parts.
213  if (ValueVT.isInteger()) {
214  unsigned PartBits = PartVT.getSizeInBits();
215  unsigned ValueBits = ValueVT.getSizeInBits();
216 
217  // Assemble the power of 2 part.
218  unsigned RoundParts = NumParts & (NumParts - 1) ?
219  1 << Log2_32(NumParts) : NumParts;
220  unsigned RoundBits = PartBits * RoundParts;
221  EVT RoundVT = RoundBits == ValueBits ?
222  ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
223  SDValue Lo, Hi;
224 
225  EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
226 
227  if (RoundParts > 2) {
228  Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
229  PartVT, HalfVT, V);
230  Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
231  RoundParts / 2, PartVT, HalfVT, V);
232  } else {
233  Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
234  Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
235  }
236 
237  if (DAG.getDataLayout().isBigEndian())
238  std::swap(Lo, Hi);
239 
240  Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
241 
242  if (RoundParts < NumParts) {
243  // Assemble the trailing non-power-of-2 part.
244  unsigned OddParts = NumParts - RoundParts;
245  EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
246  Hi = getCopyFromParts(DAG, DL, Parts + RoundParts, OddParts, PartVT,
247  OddVT, V, CC);
248 
249  // Combine the round and odd parts.
250  Lo = Val;
251  if (DAG.getDataLayout().isBigEndian())
252  std::swap(Lo, Hi);
253  EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
254  Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
255  Hi =
256  DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
257  DAG.getConstant(Lo.getValueSizeInBits(), DL,
258  TLI.getPointerTy(DAG.getDataLayout())));
259  Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
260  Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
261  }
262  } else if (PartVT.isFloatingPoint()) {
263  // FP split into multiple FP parts (for ppcf128)
264  assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
265  "Unexpected split");
266  SDValue Lo, Hi;
267  Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
268  Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
269  if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
270  std::swap(Lo, Hi);
271  Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
272  } else {
273  // FP split into integer parts (soft fp)
274  assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
275  !PartVT.isVector() && "Unexpected split");
276  EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
277  Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V, CC);
278  }
279  }
280 
281  // There is now one part, held in Val. Correct it to match ValueVT.
282  // PartEVT is the type of the register class that holds the value.
283  // ValueVT is the type of the inline asm operation.
284  EVT PartEVT = Val.getValueType();
285 
286  if (PartEVT == ValueVT)
287  return Val;
288 
289  if (PartEVT.isInteger() && ValueVT.isFloatingPoint() &&
290  ValueVT.bitsLT(PartEVT)) {
291  // For an FP value in an integer part, we need to truncate to the right
292  // width first.
293  PartEVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
294  Val = DAG.getNode(ISD::TRUNCATE, DL, PartEVT, Val);
295  }
296 
297  // Handle types that have the same size.
298  if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
299  return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
300 
301  // Handle types with different sizes.
302  if (PartEVT.isInteger() && ValueVT.isInteger()) {
303  if (ValueVT.bitsLT(PartEVT)) {
304  // For a truncate, see if we have any information to
305  // indicate whether the truncated bits will always be
306  // zero or sign-extension.
307  if (AssertOp.hasValue())
308  Val = DAG.getNode(*AssertOp, DL, PartEVT, Val,
309  DAG.getValueType(ValueVT));
310  return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
311  }
312  return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
313  }
314 
315  if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
316  // FP_ROUND's are always exact here.
317  if (ValueVT.bitsLT(Val.getValueType()))
318  return DAG.getNode(
319  ISD::FP_ROUND, DL, ValueVT, Val,
320  DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
321 
322  return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
323  }
324 
325  llvm_unreachable("Unknown mismatch!");
326 }
327 
329  const Twine &ErrMsg) {
330  const Instruction *I = dyn_cast_or_null<Instruction>(V);
331  if (!V)
332  return Ctx.emitError(ErrMsg);
333 
334  const char *AsmError = ", possible invalid constraint for vector type";
335  if (const CallInst *CI = dyn_cast<CallInst>(I))
336  if (isa<InlineAsm>(CI->getCalledValue()))
337  return Ctx.emitError(I, ErrMsg + AsmError);
338 
339  return Ctx.emitError(I, ErrMsg);
340 }
341 
342 /// getCopyFromPartsVector - Create a value that contains the specified legal
343 /// parts combined into the value they represent. If the parts combine to a
344 /// type larger than ValueVT then AssertOp can be used to specify whether the
345 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
346 /// ValueVT (ISD::AssertSext).
348  const SDValue *Parts, unsigned NumParts,
349  MVT PartVT, EVT ValueVT, const Value *V,
350  Optional<CallingConv::ID> CallConv) {
351  assert(ValueVT.isVector() && "Not a vector value");
352  assert(NumParts > 0 && "No parts to assemble!");
353  const bool IsABIRegCopy = CallConv.hasValue();
354 
355  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
356  SDValue Val = Parts[0];
357 
358  // Handle a multi-element vector.
359  if (NumParts > 1) {
360  EVT IntermediateVT;
361  MVT RegisterVT;
362  unsigned NumIntermediates;
363  unsigned NumRegs;
364 
365  if (IsABIRegCopy) {
367  *DAG.getContext(), CallConv.getValue(), ValueVT, IntermediateVT,
368  NumIntermediates, RegisterVT);
369  } else {
370  NumRegs =
371  TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
372  NumIntermediates, RegisterVT);
373  }
374 
375  assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
376  NumParts = NumRegs; // Silence a compiler warning.
377  assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
378  assert(RegisterVT.getSizeInBits() ==
379  Parts[0].getSimpleValueType().getSizeInBits() &&
380  "Part type sizes don't match!");
381 
382  // Assemble the parts into intermediate operands.
383  SmallVector<SDValue, 8> Ops(NumIntermediates);
384  if (NumIntermediates == NumParts) {
385  // If the register was not expanded, truncate or copy the value,
386  // as appropriate.
387  for (unsigned i = 0; i != NumParts; ++i)
388  Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
389  PartVT, IntermediateVT, V);
390  } else if (NumParts > 0) {
391  // If the intermediate type was expanded, build the intermediate
392  // operands from the parts.
393  assert(NumParts % NumIntermediates == 0 &&
394  "Must expand into a divisible number of parts!");
395  unsigned Factor = NumParts / NumIntermediates;
396  for (unsigned i = 0; i != NumIntermediates; ++i)
397  Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
398  PartVT, IntermediateVT, V);
399  }
400 
401  // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
402  // intermediate operands.
403  EVT BuiltVectorTy =
404  EVT::getVectorVT(*DAG.getContext(), IntermediateVT.getScalarType(),
405  (IntermediateVT.isVector()
406  ? IntermediateVT.getVectorNumElements() * NumParts
407  : NumIntermediates));
408  Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
410  DL, BuiltVectorTy, Ops);
411  }
412 
413  // There is now one part, held in Val. Correct it to match ValueVT.
414  EVT PartEVT = Val.getValueType();
415 
416  if (PartEVT == ValueVT)
417  return Val;
418 
419  if (PartEVT.isVector()) {
420  // If the element type of the source/dest vectors are the same, but the
421  // parts vector has more elements than the value vector, then we have a
422  // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
423  // elements we want.
424  if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
425  assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
426  "Cannot narrow, it would be a lossy transformation");
427  return DAG.getNode(
428  ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
429  DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
430  }
431 
432  // Vector/Vector bitcast.
433  if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
434  return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
435 
436  assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
437  "Cannot handle this kind of promotion");
438  // Promoted vector extract
439  return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
440 
441  }
442 
443  // Trivial bitcast if the types are the same size and the destination
444  // vector type is legal.
445  if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
446  TLI.isTypeLegal(ValueVT))
447  return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
448 
449  if (ValueVT.getVectorNumElements() != 1) {
450  // Certain ABIs require that vectors are passed as integers. For vectors
451  // are the same size, this is an obvious bitcast.
452  if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) {
453  return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
454  } else if (ValueVT.getSizeInBits() < PartEVT.getSizeInBits()) {
455  // Bitcast Val back the original type and extract the corresponding
456  // vector we want.
457  unsigned Elts = PartEVT.getSizeInBits() / ValueVT.getScalarSizeInBits();
458  EVT WiderVecType = EVT::getVectorVT(*DAG.getContext(),
459  ValueVT.getVectorElementType(), Elts);
460  Val = DAG.getBitcast(WiderVecType, Val);
461  return DAG.getNode(
462  ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
463  DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
464  }
465 
467  *DAG.getContext(), V, "non-trivial scalar-to-vector conversion");
468  return DAG.getUNDEF(ValueVT);
469  }
470 
471  // Handle cases such as i8 -> <1 x i1>
472  EVT ValueSVT = ValueVT.getVectorElementType();
473  if (ValueVT.getVectorNumElements() == 1 && ValueSVT != PartEVT)
474  Val = ValueVT.isFloatingPoint() ? DAG.getFPExtendOrRound(Val, DL, ValueSVT)
475  : DAG.getAnyExtOrTrunc(Val, DL, ValueSVT);
476 
477  return DAG.getBuildVector(ValueVT, DL, Val);
478 }
479 
480 static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &dl,
481  SDValue Val, SDValue *Parts, unsigned NumParts,
482  MVT PartVT, const Value *V,
483  Optional<CallingConv::ID> CallConv);
484 
485 /// getCopyToParts - Create a series of nodes that contain the specified value
486 /// split into legal parts. If the parts contain more bits than Val, then, for
487 /// integers, ExtendKind can be used to specify how to generate the extra bits.
488 static void getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
489  SDValue *Parts, unsigned NumParts, MVT PartVT,
490  const Value *V,
491  Optional<CallingConv::ID> CallConv = None,
492  ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
493  EVT ValueVT = Val.getValueType();
494 
495  // Handle the vector case separately.
496  if (ValueVT.isVector())
497  return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V,
498  CallConv);
499 
500  unsigned PartBits = PartVT.getSizeInBits();
501  unsigned OrigNumParts = NumParts;
502  assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
503  "Copying to an illegal type!");
504 
505  if (NumParts == 0)
506  return;
507 
508  assert(!ValueVT.isVector() && "Vector case handled elsewhere");
509  EVT PartEVT = PartVT;
510  if (PartEVT == ValueVT) {
511  assert(NumParts == 1 && "No-op copy with multiple parts!");
512  Parts[0] = Val;
513  return;
514  }
515 
516  if (NumParts * PartBits > ValueVT.getSizeInBits()) {
517  // If the parts cover more bits than the value has, promote the value.
518  if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
519  assert(NumParts == 1 && "Do not know what to promote to!");
520  Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
521  } else {
522  if (ValueVT.isFloatingPoint()) {
523  // FP values need to be bitcast, then extended if they are being put
524  // into a larger container.
525  ValueVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
526  Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
527  }
528  assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
529  ValueVT.isInteger() &&
530  "Unknown mismatch!");
531  ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
532  Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
533  if (PartVT == MVT::x86mmx)
534  Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
535  }
536  } else if (PartBits == ValueVT.getSizeInBits()) {
537  // Different types of the same size.
538  assert(NumParts == 1 && PartEVT != ValueVT);
539  Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
540  } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
541  // If the parts cover less bits than value has, truncate the value.
542  assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
543  ValueVT.isInteger() &&
544  "Unknown mismatch!");
545  ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
546  Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
547  if (PartVT == MVT::x86mmx)
548  Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
549  }
550 
551  // The value may have changed - recompute ValueVT.
552  ValueVT = Val.getValueType();
553  assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
554  "Failed to tile the value with PartVT!");
555 
556  if (NumParts == 1) {
557  if (PartEVT != ValueVT) {
559  "scalar-to-vector conversion failed");
560  Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
561  }
562 
563  Parts[0] = Val;
564  return;
565  }
566 
567  // Expand the value into multiple parts.
568  if (NumParts & (NumParts - 1)) {
569  // The number of parts is not a power of 2. Split off and copy the tail.
570  assert(PartVT.isInteger() && ValueVT.isInteger() &&
571  "Do not know what to expand to!");
572  unsigned RoundParts = 1 << Log2_32(NumParts);
573  unsigned RoundBits = RoundParts * PartBits;
574  unsigned OddParts = NumParts - RoundParts;
575  SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
576  DAG.getShiftAmountConstant(RoundBits, ValueVT, DL, /*LegalTypes*/false));
577 
578  getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V,
579  CallConv);
580 
581  if (DAG.getDataLayout().isBigEndian())
582  // The odd parts were reversed by getCopyToParts - unreverse them.
583  std::reverse(Parts + RoundParts, Parts + NumParts);
584 
585  NumParts = RoundParts;
586  ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
587  Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
588  }
589 
590  // The number of parts is a power of 2. Repeatedly bisect the value using
591  // EXTRACT_ELEMENT.
592  Parts[0] = DAG.getNode(ISD::BITCAST, DL,
594  ValueVT.getSizeInBits()),
595  Val);
596 
597  for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
598  for (unsigned i = 0; i < NumParts; i += StepSize) {
599  unsigned ThisBits = StepSize * PartBits / 2;
600  EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
601  SDValue &Part0 = Parts[i];
602  SDValue &Part1 = Parts[i+StepSize/2];
603 
604  Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
605  ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
606  Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
607  ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
608 
609  if (ThisBits == PartBits && ThisVT != PartVT) {
610  Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
611  Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
612  }
613  }
614  }
615 
616  if (DAG.getDataLayout().isBigEndian())
617  std::reverse(Parts, Parts + OrigNumParts);
618 }
619 
621  SDValue Val, const SDLoc &DL, EVT PartVT) {
622  if (!PartVT.isVector())
623  return SDValue();
624 
625  EVT ValueVT = Val.getValueType();
626  unsigned PartNumElts = PartVT.getVectorNumElements();
627  unsigned ValueNumElts = ValueVT.getVectorNumElements();
628  if (PartNumElts > ValueNumElts &&
629  PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
630  EVT ElementVT = PartVT.getVectorElementType();
631  // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
632  // undef elements.
634  DAG.ExtractVectorElements(Val, Ops);
635  SDValue EltUndef = DAG.getUNDEF(ElementVT);
636  for (unsigned i = ValueNumElts, e = PartNumElts; i != e; ++i)
637  Ops.push_back(EltUndef);
638 
639  // FIXME: Use CONCAT for 2x -> 4x.
640  return DAG.getBuildVector(PartVT, DL, Ops);
641  }
642 
643  return SDValue();
644 }
645 
646 /// getCopyToPartsVector - Create a series of nodes that contain the specified
647 /// value split into legal parts.
648 static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &DL,
649  SDValue Val, SDValue *Parts, unsigned NumParts,
650  MVT PartVT, const Value *V,
651  Optional<CallingConv::ID> CallConv) {
652  EVT ValueVT = Val.getValueType();
653  assert(ValueVT.isVector() && "Not a vector");
654  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
655  const bool IsABIRegCopy = CallConv.hasValue();
656 
657  if (NumParts == 1) {
658  EVT PartEVT = PartVT;
659  if (PartEVT == ValueVT) {
660  // Nothing to do.
661  } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
662  // Bitconvert vector->vector case.
663  Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
664  } else if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, PartVT)) {
665  Val = Widened;
666  } else if (PartVT.isVector() &&
667  PartEVT.getVectorElementType().bitsGE(
668  ValueVT.getVectorElementType()) &&
669  PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
670 
671  // Promoted vector extract
672  Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
673  } else {
674  if (ValueVT.getVectorNumElements() == 1) {
675  Val = DAG.getNode(
676  ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
677  DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
678  } else {
679  assert(PartVT.getSizeInBits() > ValueVT.getSizeInBits() &&
680  "lossy conversion of vector to scalar type");
681  EVT IntermediateType =
682  EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
683  Val = DAG.getBitcast(IntermediateType, Val);
684  Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
685  }
686  }
687 
688  assert(Val.getValueType() == PartVT && "Unexpected vector part value type");
689  Parts[0] = Val;
690  return;
691  }
692 
693  // Handle a multi-element vector.
694  EVT IntermediateVT;
695  MVT RegisterVT;
696  unsigned NumIntermediates;
697  unsigned NumRegs;
698  if (IsABIRegCopy) {
699  NumRegs = TLI.getVectorTypeBreakdownForCallingConv(
700  *DAG.getContext(), CallConv.getValue(), ValueVT, IntermediateVT,
701  NumIntermediates, RegisterVT);
702  } else {
703  NumRegs =
704  TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
705  NumIntermediates, RegisterVT);
706  }
707 
708  assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
709  NumParts = NumRegs; // Silence a compiler warning.
710  assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
711 
712  unsigned IntermediateNumElts = IntermediateVT.isVector() ?
713  IntermediateVT.getVectorNumElements() : 1;
714 
715  // Convert the vector to the appropiate type if necessary.
716  unsigned DestVectorNoElts = NumIntermediates * IntermediateNumElts;
717 
718  EVT BuiltVectorTy = EVT::getVectorVT(
719  *DAG.getContext(), IntermediateVT.getScalarType(), DestVectorNoElts);
720  MVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
721  if (ValueVT != BuiltVectorTy) {
722  if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, BuiltVectorTy))
723  Val = Widened;
724 
725  Val = DAG.getNode(ISD::BITCAST, DL, BuiltVectorTy, Val);
726  }
727 
728  // Split the vector into intermediate operands.
729  SmallVector<SDValue, 8> Ops(NumIntermediates);
730  for (unsigned i = 0; i != NumIntermediates; ++i) {
731  if (IntermediateVT.isVector()) {
732  Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
733  DAG.getConstant(i * IntermediateNumElts, DL, IdxVT));
734  } else {
735  Ops[i] = DAG.getNode(
736  ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
737  DAG.getConstant(i, DL, IdxVT));
738  }
739  }
740 
741  // Split the intermediate operands into legal parts.
742  if (NumParts == NumIntermediates) {
743  // If the register was not expanded, promote or copy the value,
744  // as appropriate.
745  for (unsigned i = 0; i != NumParts; ++i)
746  getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V, CallConv);
747  } else if (NumParts > 0) {
748  // If the intermediate type was expanded, split each the value into
749  // legal parts.
750  assert(NumIntermediates != 0 && "division by zero");
751  assert(NumParts % NumIntermediates == 0 &&
752  "Must expand into a divisible number of parts!");
753  unsigned Factor = NumParts / NumIntermediates;
754  for (unsigned i = 0; i != NumIntermediates; ++i)
755  getCopyToParts(DAG, DL, Ops[i], &Parts[i * Factor], Factor, PartVT, V,
756  CallConv);
757  }
758 }
759 
761  EVT valuevt, Optional<CallingConv::ID> CC)
762  : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs),
763  RegCount(1, regs.size()), CallConv(CC) {}
764 
766  const DataLayout &DL, unsigned Reg, Type *Ty,
768  ComputeValueVTs(TLI, DL, Ty, ValueVTs);
769 
770  CallConv = CC;
771 
772  for (EVT ValueVT : ValueVTs) {
773  unsigned NumRegs =
774  isABIMangled()
775  ? TLI.getNumRegistersForCallingConv(Context, CC.getValue(), ValueVT)
776  : TLI.getNumRegisters(Context, ValueVT);
777  MVT RegisterVT =
778  isABIMangled()
779  ? TLI.getRegisterTypeForCallingConv(Context, CC.getValue(), ValueVT)
780  : TLI.getRegisterType(Context, ValueVT);
781  for (unsigned i = 0; i != NumRegs; ++i)
782  Regs.push_back(Reg + i);
783  RegVTs.push_back(RegisterVT);
784  RegCount.push_back(NumRegs);
785  Reg += NumRegs;
786  }
787 }
788 
790  FunctionLoweringInfo &FuncInfo,
791  const SDLoc &dl, SDValue &Chain,
792  SDValue *Flag, const Value *V) const {
793  // A Value with type {} or [0 x %t] needs no registers.
794  if (ValueVTs.empty())
795  return SDValue();
796 
797  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
798 
799  // Assemble the legal parts into the final values.
800  SmallVector<SDValue, 4> Values(ValueVTs.size());
802  for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
803  // Copy the legal parts from the registers.
804  EVT ValueVT = ValueVTs[Value];
805  unsigned NumRegs = RegCount[Value];
806  MVT RegisterVT = isABIMangled() ? TLI.getRegisterTypeForCallingConv(
807  *DAG.getContext(),
808  CallConv.getValue(), RegVTs[Value])
809  : RegVTs[Value];
810 
811  Parts.resize(NumRegs);
812  for (unsigned i = 0; i != NumRegs; ++i) {
813  SDValue P;
814  if (!Flag) {
815  P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
816  } else {
817  P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
818  *Flag = P.getValue(2);
819  }
820 
821  Chain = P.getValue(1);
822  Parts[i] = P;
823 
824  // If the source register was virtual and if we know something about it,
825  // add an assert node.
827  !RegisterVT.isInteger())
828  continue;
829 
831  FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
832  if (!LOI)
833  continue;
834 
835  unsigned RegSize = RegisterVT.getScalarSizeInBits();
836  unsigned NumSignBits = LOI->NumSignBits;
837  unsigned NumZeroBits = LOI->Known.countMinLeadingZeros();
838 
839  if (NumZeroBits == RegSize) {
840  // The current value is a zero.
841  // Explicitly express that as it would be easier for
842  // optimizations to kick in.
843  Parts[i] = DAG.getConstant(0, dl, RegisterVT);
844  continue;
845  }
846 
847  // FIXME: We capture more information than the dag can represent. For
848  // now, just use the tightest assertzext/assertsext possible.
849  bool isSExt;
850  EVT FromVT(MVT::Other);
851  if (NumZeroBits) {
852  FromVT = EVT::getIntegerVT(*DAG.getContext(), RegSize - NumZeroBits);
853  isSExt = false;
854  } else if (NumSignBits > 1) {
855  FromVT =
856  EVT::getIntegerVT(*DAG.getContext(), RegSize - NumSignBits + 1);
857  isSExt = true;
858  } else {
859  continue;
860  }
861  // Add an assertion node.
862  assert(FromVT != MVT::Other);
863  Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
864  RegisterVT, P, DAG.getValueType(FromVT));
865  }
866 
867  Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), NumRegs,
868  RegisterVT, ValueVT, V, CallConv);
869  Part += NumRegs;
870  Parts.clear();
871  }
872 
873  return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
874 }
875 
877  const SDLoc &dl, SDValue &Chain, SDValue *Flag,
878  const Value *V,
879  ISD::NodeType PreferredExtendType) const {
880  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
881  ISD::NodeType ExtendKind = PreferredExtendType;
882 
883  // Get the list of the values's legal parts.
884  unsigned NumRegs = Regs.size();
885  SmallVector<SDValue, 8> Parts(NumRegs);
886  for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
887  unsigned NumParts = RegCount[Value];
888 
889  MVT RegisterVT = isABIMangled() ? TLI.getRegisterTypeForCallingConv(
890  *DAG.getContext(),
891  CallConv.getValue(), RegVTs[Value])
892  : RegVTs[Value];
893 
894  if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
895  ExtendKind = ISD::ZERO_EXTEND;
896 
897  getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), &Parts[Part],
898  NumParts, RegisterVT, V, CallConv, ExtendKind);
899  Part += NumParts;
900  }
901 
902  // Copy the parts into the registers.
903  SmallVector<SDValue, 8> Chains(NumRegs);
904  for (unsigned i = 0; i != NumRegs; ++i) {
905  SDValue Part;
906  if (!Flag) {
907  Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
908  } else {
909  Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
910  *Flag = Part.getValue(1);
911  }
912 
913  Chains[i] = Part.getValue(0);
914  }
915 
916  if (NumRegs == 1 || Flag)
917  // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
918  // flagged to it. That is the CopyToReg nodes and the user are considered
919  // a single scheduling unit. If we create a TokenFactor and return it as
920  // chain, then the TokenFactor is both a predecessor (operand) of the
921  // user as well as a successor (the TF operands are flagged to the user).
922  // c1, f1 = CopyToReg
923  // c2, f2 = CopyToReg
924  // c3 = TokenFactor c1, c2
925  // ...
926  // = op c3, ..., f2
927  Chain = Chains[NumRegs-1];
928  else
929  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
930 }
931 
932 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
933  unsigned MatchingIdx, const SDLoc &dl,
934  SelectionDAG &DAG,
935  std::vector<SDValue> &Ops) const {
936  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
937 
938  unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
939  if (HasMatching)
940  Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
941  else if (!Regs.empty() &&
943  // Put the register class of the virtual registers in the flag word. That
944  // way, later passes can recompute register class constraints for inline
945  // assembly as well as normal instructions.
946  // Don't do this for tied operands that can use the regclass information
947  // from the def.
949  const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
950  Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
951  }
952 
953  SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
954  Ops.push_back(Res);
955 
956  if (Code == InlineAsm::Kind_Clobber) {
957  // Clobbers should always have a 1:1 mapping with registers, and may
958  // reference registers that have illegal (e.g. vector) types. Hence, we
959  // shouldn't try to apply any sort of splitting logic to them.
960  assert(Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() &&
961  "No 1:1 mapping from clobbers to regs?");
962  unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
963  (void)SP;
964  for (unsigned I = 0, E = ValueVTs.size(); I != E; ++I) {
965  Ops.push_back(DAG.getRegister(Regs[I], RegVTs[I]));
966  assert(
967  (Regs[I] != SP ||
969  "If we clobbered the stack pointer, MFI should know about it.");
970  }
971  return;
972  }
973 
974  for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
975  unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
976  MVT RegisterVT = RegVTs[Value];
977  for (unsigned i = 0; i != NumRegs; ++i) {
978  assert(Reg < Regs.size() && "Mismatch in # registers expected");
979  unsigned TheReg = Regs[Reg++];
980  Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
981  }
982  }
983 }
984 
988  unsigned I = 0;
989  for (auto CountAndVT : zip_first(RegCount, RegVTs)) {
990  unsigned RegCount = std::get<0>(CountAndVT);
991  MVT RegisterVT = std::get<1>(CountAndVT);
992  unsigned RegisterSize = RegisterVT.getSizeInBits();
993  for (unsigned E = I + RegCount; I != E; ++I)
994  OutVec.push_back(std::make_pair(Regs[I], RegisterSize));
995  }
996  return OutVec;
997 }
998 
1000  const TargetLibraryInfo *li) {
1001  AA = aa;
1002  GFI = gfi;
1003  LibInfo = li;
1004  DL = &DAG.getDataLayout();
1005  Context = DAG.getContext();
1006  LPadToCallSiteMap.clear();
1007 }
1008 
1010  NodeMap.clear();
1011  UnusedArgNodeMap.clear();
1012  PendingLoads.clear();
1013  PendingExports.clear();
1014  CurInst = nullptr;
1015  HasTailCall = false;
1016  SDNodeOrder = LowestSDNodeOrder;
1017  StatepointLowering.clear();
1018 }
1019 
1021  DanglingDebugInfoMap.clear();
1022 }
1023 
1025  if (PendingLoads.empty())
1026  return DAG.getRoot();
1027 
1028  if (PendingLoads.size() == 1) {
1029  SDValue Root = PendingLoads[0];
1030  DAG.setRoot(Root);
1031  PendingLoads.clear();
1032  return Root;
1033  }
1034 
1035  // Otherwise, we have to make a token factor node.
1036  SDValue Root = DAG.getTokenFactor(getCurSDLoc(), PendingLoads);
1037  PendingLoads.clear();
1038  DAG.setRoot(Root);
1039  return Root;
1040 }
1041 
1043  SDValue Root = DAG.getRoot();
1044 
1045  if (PendingExports.empty())
1046  return Root;
1047 
1048  // Turn all of the CopyToReg chains into one factored node.
1049  if (Root.getOpcode() != ISD::EntryToken) {
1050  unsigned i = 0, e = PendingExports.size();
1051  for (; i != e; ++i) {
1052  assert(PendingExports[i].getNode()->getNumOperands() > 1);
1053  if (PendingExports[i].getNode()->getOperand(0) == Root)
1054  break; // Don't add the root if we already indirectly depend on it.
1055  }
1056 
1057  if (i == e)
1058  PendingExports.push_back(Root);
1059  }
1060 
1061  Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
1062  PendingExports);
1063  PendingExports.clear();
1064  DAG.setRoot(Root);
1065  return Root;
1066 }
1067 
1069  // Set up outgoing PHI node register values before emitting the terminator.
1070  if (I.isTerminator()) {
1071  HandlePHINodesInSuccessorBlocks(I.getParent());
1072  }
1073 
1074  // Increase the SDNodeOrder if dealing with a non-debug instruction.
1075  if (!isa<DbgInfoIntrinsic>(I))
1076  ++SDNodeOrder;
1077 
1078  CurInst = &I;
1079 
1080  visit(I.getOpcode(), I);
1081 
1082  if (auto *FPMO = dyn_cast<FPMathOperator>(&I)) {
1083  // Propagate the fast-math-flags of this IR instruction to the DAG node that
1084  // maps to this instruction.
1085  // TODO: We could handle all flags (nsw, etc) here.
1086  // TODO: If an IR instruction maps to >1 node, only the final node will have
1087  // flags set.
1088  if (SDNode *Node = getNodeForIRValue(&I)) {
1089  SDNodeFlags IncomingFlags;
1090  IncomingFlags.copyFMF(*FPMO);
1091  if (!Node->getFlags().isDefined())
1092  Node->setFlags(IncomingFlags);
1093  else
1094  Node->intersectFlagsWith(IncomingFlags);
1095  }
1096  }
1097 
1098  if (!I.isTerminator() && !HasTailCall &&
1099  !isStatepoint(&I)) // statepoints handle their exports internally
1100  CopyToExportRegsIfNeeded(&I);
1101 
1102  CurInst = nullptr;
1103 }
1104 
1105 void SelectionDAGBuilder::visitPHI(const PHINode &) {
1106  llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
1107 }
1108 
1109 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
1110  // Note: this doesn't use InstVisitor, because it has to work with
1111  // ConstantExpr's in addition to instructions.
1112  switch (Opcode) {
1113  default: llvm_unreachable("Unknown instruction type encountered!");
1114  // Build the switch statement using the Instruction.def file.
1115 #define HANDLE_INST(NUM, OPCODE, CLASS) \
1116  case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
1117 #include "llvm/IR/Instruction.def"
1118  }
1119 }
1120 
1122  const DIExpression *Expr) {
1123  auto isMatchingDbgValue = [&](DanglingDebugInfo &DDI) {
1124  const DbgValueInst *DI = DDI.getDI();
1125  DIVariable *DanglingVariable = DI->getVariable();
1126  DIExpression *DanglingExpr = DI->getExpression();
1127  if (DanglingVariable == Variable && Expr->fragmentsOverlap(DanglingExpr)) {
1128  LLVM_DEBUG(dbgs() << "Dropping dangling debug info for " << *DI << "\n");
1129  return true;
1130  }
1131  return false;
1132  };
1133 
1134  for (auto &DDIMI : DanglingDebugInfoMap) {
1135  DanglingDebugInfoVector &DDIV = DDIMI.second;
1136 
1137  // If debug info is to be dropped, run it through final checks to see
1138  // whether it can be salvaged.
1139  for (auto &DDI : DDIV)
1140  if (isMatchingDbgValue(DDI))
1141  salvageUnresolvedDbgValue(DDI);
1142 
1143  DDIV.erase(remove_if(DDIV, isMatchingDbgValue), DDIV.end());
1144  }
1145 }
1146 
1147 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
1148 // generate the debug data structures now that we've seen its definition.
1150  SDValue Val) {
1151  auto DanglingDbgInfoIt = DanglingDebugInfoMap.find(V);
1152  if (DanglingDbgInfoIt == DanglingDebugInfoMap.end())
1153  return;
1154 
1155  DanglingDebugInfoVector &DDIV = DanglingDbgInfoIt->second;
1156  for (auto &DDI : DDIV) {
1157  const DbgValueInst *DI = DDI.getDI();
1158  assert(DI && "Ill-formed DanglingDebugInfo");
1159  DebugLoc dl = DDI.getdl();
1160  unsigned ValSDNodeOrder = Val.getNode()->getIROrder();
1161  unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1162  DILocalVariable *Variable = DI->getVariable();
1163  DIExpression *Expr = DI->getExpression();
1164  assert(Variable->isValidLocationForIntrinsic(dl) &&
1165  "Expected inlined-at fields to agree");
1166  SDDbgValue *SDV;
1167  if (Val.getNode()) {
1168  // FIXME: I doubt that it is correct to resolve a dangling DbgValue as a
1169  // FuncArgumentDbgValue (it would be hoisted to the function entry, and if
1170  // we couldn't resolve it directly when examining the DbgValue intrinsic
1171  // in the first place we should not be more successful here). Unless we
1172  // have some test case that prove this to be correct we should avoid
1173  // calling EmitFuncArgumentDbgValue here.
1174  if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, false, Val)) {
1175  LLVM_DEBUG(dbgs() << "Resolve dangling debug info [order="
1176  << DbgSDNodeOrder << "] for:\n " << *DI << "\n");
1177  LLVM_DEBUG(dbgs() << " By mapping to:\n "; Val.dump());
1178  // Increase the SDNodeOrder for the DbgValue here to make sure it is
1179  // inserted after the definition of Val when emitting the instructions
1180  // after ISel. An alternative could be to teach
1181  // ScheduleDAGSDNodes::EmitSchedule to delay the insertion properly.
1182  LLVM_DEBUG(if (ValSDNodeOrder > DbgSDNodeOrder) dbgs()
1183  << "changing SDNodeOrder from " << DbgSDNodeOrder << " to "
1184  << ValSDNodeOrder << "\n");
1185  SDV = getDbgValue(Val, Variable, Expr, dl,
1186  std::max(DbgSDNodeOrder, ValSDNodeOrder));
1187  DAG.AddDbgValue(SDV, Val.getNode(), false);
1188  } else
1189  LLVM_DEBUG(dbgs() << "Resolved dangling debug info for " << *DI
1190  << "in EmitFuncArgumentDbgValue\n");
1191  } else {
1192  LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1193  auto Undef =
1194  UndefValue::get(DDI.getDI()->getVariableLocation()->getType());
1195  auto SDV =
1196  DAG.getConstantDbgValue(Variable, Expr, Undef, dl, DbgSDNodeOrder);
1197  DAG.AddDbgValue(SDV, nullptr, false);
1198  }
1199  }
1200  DDIV.clear();
1201 }
1202 
1204  Value *V = DDI.getDI()->getValue();
1205  DILocalVariable *Var = DDI.getDI()->getVariable();
1206  DIExpression *Expr = DDI.getDI()->getExpression();
1207  DebugLoc DL = DDI.getdl();
1208  DebugLoc InstDL = DDI.getDI()->getDebugLoc();
1209  unsigned SDOrder = DDI.getSDNodeOrder();
1210 
1211  // Currently we consider only dbg.value intrinsics -- we tell the salvager
1212  // that DW_OP_stack_value is desired.
1213  assert(isa<DbgValueInst>(DDI.getDI()));
1214  bool StackValue = true;
1215 
1216  // Can this Value can be encoded without any further work?
1217  if (handleDebugValue(V, Var, Expr, DL, InstDL, SDOrder))
1218  return;
1219 
1220  // Attempt to salvage back through as many instructions as possible. Bail if
1221  // a non-instruction is seen, such as a constant expression or global
1222  // variable. FIXME: Further work could recover those too.
1223  while (isa<Instruction>(V)) {
1224  Instruction &VAsInst = *cast<Instruction>(V);
1225  DIExpression *NewExpr = salvageDebugInfoImpl(VAsInst, Expr, StackValue);
1226 
1227  // If we cannot salvage any further, and haven't yet found a suitable debug
1228  // expression, bail out.
1229  if (!NewExpr)
1230  break;
1231 
1232  // New value and expr now represent this debuginfo.
1233  V = VAsInst.getOperand(0);
1234  Expr = NewExpr;
1235 
1236  // Some kind of simplification occurred: check whether the operand of the
1237  // salvaged debug expression can be encoded in this DAG.
1238  if (handleDebugValue(V, Var, Expr, DL, InstDL, SDOrder)) {
1239  LLVM_DEBUG(dbgs() << "Salvaged debug location info for:\n "
1240  << DDI.getDI() << "\nBy stripping back to:\n " << V);
1241  return;
1242  }
1243  }
1244 
1245  // This was the final opportunity to salvage this debug information, and it
1246  // couldn't be done. Place an undef DBG_VALUE at this location to terminate
1247  // any earlier variable location.
1248  auto Undef = UndefValue::get(DDI.getDI()->getVariableLocation()->getType());
1249  auto SDV = DAG.getConstantDbgValue(Var, Expr, Undef, DL, SDNodeOrder);
1250  DAG.AddDbgValue(SDV, nullptr, false);
1251 
1252  LLVM_DEBUG(dbgs() << "Dropping debug value info for:\n " << DDI.getDI()
1253  << "\n");
1254  LLVM_DEBUG(dbgs() << " Last seen at:\n " << *DDI.getDI()->getOperand(0)
1255  << "\n");
1256 }
1257 
1259  DIExpression *Expr, DebugLoc dl,
1260  DebugLoc InstDL, unsigned Order) {
1261  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1262  SDDbgValue *SDV;
1263  if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V) ||
1264  isa<ConstantPointerNull>(V)) {
1265  SDV = DAG.getConstantDbgValue(Var, Expr, V, dl, SDNodeOrder);
1266  DAG.AddDbgValue(SDV, nullptr, false);
1267  return true;
1268  }
1269 
1270  // If the Value is a frame index, we can create a FrameIndex debug value
1271  // without relying on the DAG at all.
1272  if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1273  auto SI = FuncInfo.StaticAllocaMap.find(AI);
1274  if (SI != FuncInfo.StaticAllocaMap.end()) {
1275  auto SDV =
1276  DAG.getFrameIndexDbgValue(Var, Expr, SI->second,
1277  /*IsIndirect*/ false, dl, SDNodeOrder);
1278  // Do not attach the SDNodeDbgValue to an SDNode: this variable location
1279  // is still available even if the SDNode gets optimized out.
1280  DAG.AddDbgValue(SDV, nullptr, false);
1281  return true;
1282  }
1283  }
1284 
1285  // Do not use getValue() in here; we don't want to generate code at
1286  // this point if it hasn't been done yet.
1287  SDValue N = NodeMap[V];
1288  if (!N.getNode() && isa<Argument>(V)) // Check unused arguments map.
1289  N = UnusedArgNodeMap[V];
1290  if (N.getNode()) {
1291  if (EmitFuncArgumentDbgValue(V, Var, Expr, dl, false, N))
1292  return true;
1293  SDV = getDbgValue(N, Var, Expr, dl, SDNodeOrder);
1294  DAG.AddDbgValue(SDV, N.getNode(), false);
1295  return true;
1296  }
1297 
1298  // Special rules apply for the first dbg.values of parameter variables in a
1299  // function. Identify them by the fact they reference Argument Values, that
1300  // they're parameters, and they are parameters of the current function. We
1301  // need to let them dangle until they get an SDNode.
1302  bool IsParamOfFunc = isa<Argument>(V) && Var->isParameter() &&
1303  !InstDL.getInlinedAt();
1304  if (!IsParamOfFunc) {
1305  // The value is not used in this block yet (or it would have an SDNode).
1306  // We still want the value to appear for the user if possible -- if it has
1307  // an associated VReg, we can refer to that instead.
1308  auto VMI = FuncInfo.ValueMap.find(V);
1309  if (VMI != FuncInfo.ValueMap.end()) {
1310  unsigned Reg = VMI->second;
1311  // If this is a PHI node, it may be split up into several MI PHI nodes
1312  // (in FunctionLoweringInfo::set).
1313  RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
1314  V->getType(), None);
1315  if (RFV.occupiesMultipleRegs()) {
1316  unsigned Offset = 0;
1317  unsigned BitsToDescribe = 0;
1318  if (auto VarSize = Var->getSizeInBits())
1319  BitsToDescribe = *VarSize;
1320  if (auto Fragment = Expr->getFragmentInfo())
1321  BitsToDescribe = Fragment->SizeInBits;
1322  for (auto RegAndSize : RFV.getRegsAndSizes()) {
1323  unsigned RegisterSize = RegAndSize.second;
1324  // Bail out if all bits are described already.
1325  if (Offset >= BitsToDescribe)
1326  break;
1327  unsigned FragmentSize = (Offset + RegisterSize > BitsToDescribe)
1328  ? BitsToDescribe - Offset
1329  : RegisterSize;
1330  auto FragmentExpr = DIExpression::createFragmentExpression(
1331  Expr, Offset, FragmentSize);
1332  if (!FragmentExpr)
1333  continue;
1334  SDV = DAG.getVRegDbgValue(Var, *FragmentExpr, RegAndSize.first,
1335  false, dl, SDNodeOrder);
1336  DAG.AddDbgValue(SDV, nullptr, false);
1337  Offset += RegisterSize;
1338  }
1339  } else {
1340  SDV = DAG.getVRegDbgValue(Var, Expr, Reg, false, dl, SDNodeOrder);
1341  DAG.AddDbgValue(SDV, nullptr, false);
1342  }
1343  return true;
1344  }
1345  }
1346 
1347  return false;
1348 }
1349 
1351  // Try to fixup any remaining dangling debug info -- and drop it if we can't.
1352  for (auto &Pair : DanglingDebugInfoMap)
1353  for (auto &DDI : Pair.second)
1354  salvageUnresolvedDbgValue(DDI);
1355  clearDanglingDebugInfo();
1356 }
1357 
1358 /// getCopyFromRegs - If there was virtual register allocated for the value V
1359 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
1361  DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1362  SDValue Result;
1363 
1364  if (It != FuncInfo.ValueMap.end()) {
1365  unsigned InReg = It->second;
1366 
1367  RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
1368  DAG.getDataLayout(), InReg, Ty,
1369  None); // This is not an ABI copy.
1370  SDValue Chain = DAG.getEntryNode();
1371  Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr,
1372  V);
1373  resolveDanglingDebugInfo(V, Result);
1374  }
1375 
1376  return Result;
1377 }
1378 
1379 /// getValue - Return an SDValue for the given Value.
1381  // If we already have an SDValue for this value, use it. It's important
1382  // to do this first, so that we don't create a CopyFromReg if we already
1383  // have a regular SDValue.
1384  SDValue &N = NodeMap[V];
1385  if (N.getNode()) return N;
1386 
1387  // If there's a virtual register allocated and initialized for this
1388  // value, use it.
1389  if (SDValue copyFromReg = getCopyFromRegs(V, V->getType()))
1390  return copyFromReg;
1391 
1392  // Otherwise create a new SDValue and remember it.
1393  SDValue Val = getValueImpl(V);
1394  NodeMap[V] = Val;
1395  resolveDanglingDebugInfo(V, Val);
1396  return Val;
1397 }
1398 
1399 // Return true if SDValue exists for the given Value
1401  return (NodeMap.find(V) != NodeMap.end()) ||
1402  (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
1403 }
1404 
1405 /// getNonRegisterValue - Return an SDValue for the given Value, but
1406 /// don't look in FuncInfo.ValueMap for a virtual register.
1408  // If we already have an SDValue for this value, use it.
1409  SDValue &N = NodeMap[V];
1410  if (N.getNode()) {
1411  if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1412  // Remove the debug location from the node as the node is about to be used
1413  // in a location which may differ from the original debug location. This
1414  // is relevant to Constant and ConstantFP nodes because they can appear
1415  // as constant expressions inside PHI nodes.
1416  N->setDebugLoc(DebugLoc());
1417  }
1418  return N;
1419  }
1420 
1421  // Otherwise create a new SDValue and remember it.
1422  SDValue Val = getValueImpl(V);
1423  NodeMap[V] = Val;
1424  resolveDanglingDebugInfo(V, Val);
1425  return Val;
1426 }
1427 
1428 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1429 /// Create an SDValue for the given value.
1431  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1432 
1433  if (const Constant *C = dyn_cast<Constant>(V)) {
1434  EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1435 
1436  if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1437  return DAG.getConstant(*CI, getCurSDLoc(), VT);
1438 
1439  if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1440  return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1441 
1442  if (isa<ConstantPointerNull>(C)) {
1443  unsigned AS = V->getType()->getPointerAddressSpace();
1444  return DAG.getConstant(0, getCurSDLoc(),
1445  TLI.getPointerTy(DAG.getDataLayout(), AS));
1446  }
1447 
1448  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1449  return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1450 
1451  if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1452  return DAG.getUNDEF(VT);
1453 
1454  if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1455  visit(CE->getOpcode(), *CE);
1456  SDValue N1 = NodeMap[V];
1457  assert(N1.getNode() && "visit didn't populate the NodeMap!");
1458  return N1;
1459  }
1460 
1461  if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1463  for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1464  OI != OE; ++OI) {
1465  SDNode *Val = getValue(*OI).getNode();
1466  // If the operand is an empty aggregate, there are no values.
1467  if (!Val) continue;
1468  // Add each leaf value from the operand to the Constants list
1469  // to form a flattened list of all the values.
1470  for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1471  Constants.push_back(SDValue(Val, i));
1472  }
1473 
1474  return DAG.getMergeValues(Constants, getCurSDLoc());
1475  }
1476 
1477  if (const ConstantDataSequential *CDS =
1478  dyn_cast<ConstantDataSequential>(C)) {
1480  for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1481  SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1482  // Add each leaf value from the operand to the Constants list
1483  // to form a flattened list of all the values.
1484  for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1485  Ops.push_back(SDValue(Val, i));
1486  }
1487 
1488  if (isa<ArrayType>(CDS->getType()))
1489  return DAG.getMergeValues(Ops, getCurSDLoc());
1490  return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops);
1491  }
1492 
1493  if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1494  assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1495  "Unknown struct or array constant!");
1496 
1498  ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1499  unsigned NumElts = ValueVTs.size();
1500  if (NumElts == 0)
1501  return SDValue(); // empty struct
1503  for (unsigned i = 0; i != NumElts; ++i) {
1504  EVT EltVT = ValueVTs[i];
1505  if (isa<UndefValue>(C))
1506  Constants[i] = DAG.getUNDEF(EltVT);
1507  else if (EltVT.isFloatingPoint())
1508  Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1509  else
1510  Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1511  }
1512 
1513  return DAG.getMergeValues(Constants, getCurSDLoc());
1514  }
1515 
1516  if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1517  return DAG.getBlockAddress(BA, VT);
1518 
1519  VectorType *VecTy = cast<VectorType>(V->getType());
1520  unsigned NumElements = VecTy->getNumElements();
1521 
1522  // Now that we know the number and type of the elements, get that number of
1523  // elements into the Ops array based on what kind of constant it is.
1525  if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1526  for (unsigned i = 0; i != NumElements; ++i)
1527  Ops.push_back(getValue(CV->getOperand(i)));
1528  } else {
1529  assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1530  EVT EltVT =
1531  TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1532 
1533  SDValue Op;
1534  if (EltVT.isFloatingPoint())
1535  Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1536  else
1537  Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1538  Ops.assign(NumElements, Op);
1539  }
1540 
1541  // Create a BUILD_VECTOR node.
1542  return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops);
1543  }
1544 
1545  // If this is a static alloca, generate it as the frameindex instead of
1546  // computation.
1547  if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1549  FuncInfo.StaticAllocaMap.find(AI);
1550  if (SI != FuncInfo.StaticAllocaMap.end())
1551  return DAG.getFrameIndex(SI->second,
1552  TLI.getFrameIndexTy(DAG.getDataLayout()));
1553  }
1554 
1555  // If this is an instruction which fast-isel has deferred, select it now.
1556  if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1557  unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1558 
1559  RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1560  Inst->getType(), getABIRegCopyCC(V));
1561  SDValue Chain = DAG.getEntryNode();
1562  return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1563  }
1564 
1565  llvm_unreachable("Can't get register for value!");
1566 }
1567 
1568 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1569  auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1570  bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX;
1571  bool IsCoreCLR = Pers == EHPersonality::CoreCLR;
1572  bool IsSEH = isAsynchronousEHPersonality(Pers);
1573  bool IsWasmCXX = Pers == EHPersonality::Wasm_CXX;
1574  MachineBasicBlock *CatchPadMBB = FuncInfo.MBB;
1575  if (!IsSEH)
1576  CatchPadMBB->setIsEHScopeEntry();
1577  // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues.
1578  if (IsMSVCCXX || IsCoreCLR)
1579  CatchPadMBB->setIsEHFuncletEntry();
1580  // Wasm does not need catchpads anymore
1581  if (!IsWasmCXX)
1582  DAG.setRoot(DAG.getNode(ISD::CATCHPAD, getCurSDLoc(), MVT::Other,
1583  getControlRoot()));
1584 }
1585 
1586 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1587  // Update machine-CFG edge.
1588  MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1589  FuncInfo.MBB->addSuccessor(TargetMBB);
1590 
1591  auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1592  bool IsSEH = isAsynchronousEHPersonality(Pers);
1593  if (IsSEH) {
1594  // If this is not a fall-through branch or optimizations are switched off,
1595  // emit the branch.
1596  if (TargetMBB != NextBlock(FuncInfo.MBB) ||
1597  TM.getOptLevel() == CodeGenOpt::None)
1598  DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1599  getControlRoot(), DAG.getBasicBlock(TargetMBB)));
1600  return;
1601  }
1602 
1603  // Figure out the funclet membership for the catchret's successor.
1604  // This will be used by the FuncletLayout pass to determine how to order the
1605  // BB's.
1606  // A 'catchret' returns to the outer scope's color.
1607  Value *ParentPad = I.getCatchSwitchParentPad();
1608  const BasicBlock *SuccessorColor;
1609  if (isa<ConstantTokenNone>(ParentPad))
1610  SuccessorColor = &FuncInfo.Fn->getEntryBlock();
1611  else
1612  SuccessorColor = cast<Instruction>(ParentPad)->getParent();
1613  assert(SuccessorColor && "No parent funclet for catchret!");
1614  MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor];
1615  assert(SuccessorColorMBB && "No MBB for SuccessorColor!");
1616 
1617  // Create the terminator node.
1618  SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1619  getControlRoot(), DAG.getBasicBlock(TargetMBB),
1620  DAG.getBasicBlock(SuccessorColorMBB));
1621  DAG.setRoot(Ret);
1622 }
1623 
1624 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1625  // Don't emit any special code for the cleanuppad instruction. It just marks
1626  // the start of an EH scope/funclet.
1627  FuncInfo.MBB->setIsEHScopeEntry();
1628  auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1629  if (Pers != EHPersonality::Wasm_CXX) {
1630  FuncInfo.MBB->setIsEHFuncletEntry();
1631  FuncInfo.MBB->setIsCleanupFuncletEntry();
1632  }
1633 }
1634 
1635 // For wasm, there's alwyas a single catch pad attached to a catchswitch, and
1636 // the control flow always stops at the single catch pad, as it does for a
1637 // cleanup pad. In case the exception caught is not of the types the catch pad
1638 // catches, it will be rethrown by a rethrow.
1640  FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB,
1641  BranchProbability Prob,
1642  SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>>
1643  &UnwindDests) {
1644  while (EHPadBB) {
1645  const Instruction *Pad = EHPadBB->getFirstNonPHI();
1646  if (isa<CleanupPadInst>(Pad)) {
1647  // Stop on cleanup pads.
1648  UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1649  UnwindDests.back().first->setIsEHScopeEntry();
1650  break;
1651  } else if (auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
1652  // Add the catchpad handlers to the possible destinations. We don't
1653  // continue to the unwind destination of the catchswitch for wasm.
1654  for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
1655  UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob);
1656  UnwindDests.back().first->setIsEHScopeEntry();
1657  }
1658  break;
1659  } else {
1660  continue;
1661  }
1662  }
1663 }
1664 
1665 /// When an invoke or a cleanupret unwinds to the next EH pad, there are
1666 /// many places it could ultimately go. In the IR, we have a single unwind
1667 /// destination, but in the machine CFG, we enumerate all the possible blocks.
1668 /// This function skips over imaginary basic blocks that hold catchswitch
1669 /// instructions, and finds all the "real" machine
1670 /// basic block destinations. As those destinations may not be successors of
1671 /// EHPadBB, here we also calculate the edge probability to those destinations.
1672 /// The passed-in Prob is the edge probability to EHPadBB.
1674  FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB,
1675  BranchProbability Prob,
1676  SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>>
1677  &UnwindDests) {
1678  EHPersonality Personality =
1680  bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
1681  bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
1682  bool IsWasmCXX = Personality == EHPersonality::Wasm_CXX;
1683  bool IsSEH = isAsynchronousEHPersonality(Personality);
1684 
1685  if (IsWasmCXX) {
1686  findWasmUnwindDestinations(FuncInfo, EHPadBB, Prob, UnwindDests);
1687  assert(UnwindDests.size() <= 1 &&
1688  "There should be at most one unwind destination for wasm");
1689  return;
1690  }
1691 
1692  while (EHPadBB) {
1693  const Instruction *Pad = EHPadBB->getFirstNonPHI();
1694  BasicBlock *NewEHPadBB = nullptr;
1695  if (isa<LandingPadInst>(Pad)) {
1696  // Stop on landingpads. They are not funclets.
1697  UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1698  break;
1699  } else if (isa<CleanupPadInst>(Pad)) {
1700  // Stop on cleanup pads. Cleanups are always funclet entries for all known
1701  // personalities.
1702  UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1703  UnwindDests.back().first->setIsEHScopeEntry();
1704  UnwindDests.back().first->setIsEHFuncletEntry();
1705  break;
1706  } else if (auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
1707  // Add the catchpad handlers to the possible destinations.
1708  for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
1709  UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob);
1710  // For MSVC++ and the CLR, catchblocks are funclets and need prologues.
1711  if (IsMSVCCXX || IsCoreCLR)
1712  UnwindDests.back().first->setIsEHFuncletEntry();
1713  if (!IsSEH)
1714  UnwindDests.back().first->setIsEHScopeEntry();
1715  }
1716  NewEHPadBB = CatchSwitch->getUnwindDest();
1717  } else {
1718  continue;
1719  }
1720 
1721  BranchProbabilityInfo *BPI = FuncInfo.BPI;
1722  if (BPI && NewEHPadBB)
1723  Prob *= BPI->getEdgeProbability(EHPadBB, NewEHPadBB);
1724  EHPadBB = NewEHPadBB;
1725  }
1726 }
1727 
1728 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1729  // Update successor info.
1731  auto UnwindDest = I.getUnwindDest();
1732  BranchProbabilityInfo *BPI = FuncInfo.BPI;
1733  BranchProbability UnwindDestProb =
1734  (BPI && UnwindDest)
1735  ? BPI->getEdgeProbability(FuncInfo.MBB->getBasicBlock(), UnwindDest)
1737  findUnwindDestinations(FuncInfo, UnwindDest, UnwindDestProb, UnwindDests);
1738  for (auto &UnwindDest : UnwindDests) {
1739  UnwindDest.first->setIsEHPad();
1740  addSuccessorWithProb(FuncInfo.MBB, UnwindDest.first, UnwindDest.second);
1741  }
1742  FuncInfo.MBB->normalizeSuccProbs();
1743 
1744  // Create the terminator node.
1745  SDValue Ret =
1746  DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
1747  DAG.setRoot(Ret);
1748 }
1749 
1750 void SelectionDAGBuilder::visitCatchSwitch(const CatchSwitchInst &CSI) {
1751  report_fatal_error("visitCatchSwitch not yet implemented!");
1752 }
1753 
1754 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1755  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1756  auto &DL = DAG.getDataLayout();
1757  SDValue Chain = getControlRoot();
1759  SmallVector<SDValue, 8> OutVals;
1760 
1761  // Calls to @llvm.experimental.deoptimize don't generate a return value, so
1762  // lower
1763  //
1764  // %val = call <ty> @llvm.experimental.deoptimize()
1765  // ret <ty> %val
1766  //
1767  // differently.
1769  LowerDeoptimizingReturn();
1770  return;
1771  }
1772 
1773  if (!FuncInfo.CanLowerReturn) {
1774  unsigned DemoteReg = FuncInfo.DemoteRegister;
1775  const Function *F = I.getParent()->getParent();
1776 
1777  // Emit a store of the return value through the virtual register.
1778  // Leave Outs empty so that LowerReturn won't try to load return
1779  // registers the usual way.
1780  SmallVector<EVT, 1> PtrValueVTs;
1781  ComputeValueVTs(TLI, DL,
1784  PtrValueVTs);
1785 
1786  SDValue RetPtr = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
1787  DemoteReg, PtrValueVTs[0]);
1788  SDValue RetOp = getValue(I.getOperand(0));
1789 
1792  ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1793  unsigned NumValues = ValueVTs.size();
1794 
1795  SmallVector<SDValue, 4> Chains(NumValues);
1796  for (unsigned i = 0; i != NumValues; ++i) {
1797  // An aggregate return value cannot wrap around the address space, so
1798  // offsets to its parts don't wrap either.
1799  SDValue Ptr = DAG.getObjectPtrOffset(getCurSDLoc(), RetPtr, Offsets[i]);
1800  Chains[i] = DAG.getStore(
1801  Chain, getCurSDLoc(), SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1802  // FIXME: better loc info would be nice.
1804  }
1805 
1806  Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1807  MVT::Other, Chains);
1808  } else if (I.getNumOperands() != 0) {
1810  ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1811  unsigned NumValues = ValueVTs.size();
1812  if (NumValues) {
1813  SDValue RetOp = getValue(I.getOperand(0));
1814 
1815  const Function *F = I.getParent()->getParent();
1816 
1817  bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
1818  I.getOperand(0)->getType(), F->getCallingConv(),
1819  /*IsVarArg*/ false);
1820 
1821  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1822  if (F->getAttributes().hasAttribute(AttributeList::ReturnIndex,
1823  Attribute::SExt))
1824  ExtendKind = ISD::SIGN_EXTEND;
1825  else if (F->getAttributes().hasAttribute(AttributeList::ReturnIndex,
1826  Attribute::ZExt))
1827  ExtendKind = ISD::ZERO_EXTEND;
1828 
1829  LLVMContext &Context = F->getContext();
1830  bool RetInReg = F->getAttributes().hasAttribute(
1831  AttributeList::ReturnIndex, Attribute::InReg);
1832 
1833  for (unsigned j = 0; j != NumValues; ++j) {
1834  EVT VT = ValueVTs[j];
1835 
1836  if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1837  VT = TLI.getTypeForExtReturn(Context, VT, ExtendKind);
1838 
1839  CallingConv::ID CC = F->getCallingConv();
1840 
1841  unsigned NumParts = TLI.getNumRegistersForCallingConv(Context, CC, VT);
1842  MVT PartVT = TLI.getRegisterTypeForCallingConv(Context, CC, VT);
1843  SmallVector<SDValue, 4> Parts(NumParts);
1844  getCopyToParts(DAG, getCurSDLoc(),
1845  SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1846  &Parts[0], NumParts, PartVT, &I, CC, ExtendKind);
1847 
1848  // 'inreg' on function refers to return value
1849  ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1850  if (RetInReg)
1851  Flags.setInReg();
1852 
1853  if (I.getOperand(0)->getType()->isPointerTy()) {
1854  Flags.setPointer();
1855  Flags.setPointerAddrSpace(
1856  cast<PointerType>(I.getOperand(0)->getType())->getAddressSpace());
1857  }
1858 
1859  if (NeedsRegBlock) {
1860  Flags.setInConsecutiveRegs();
1861  if (j == NumValues - 1)
1862  Flags.setInConsecutiveRegsLast();
1863  }
1864 
1865  // Propagate extension type if any
1866  if (ExtendKind == ISD::SIGN_EXTEND)
1867  Flags.setSExt();
1868  else if (ExtendKind == ISD::ZERO_EXTEND)
1869  Flags.setZExt();
1870 
1871  for (unsigned i = 0; i < NumParts; ++i) {
1872  Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1873  VT, /*isfixed=*/true, 0, 0));
1874  OutVals.push_back(Parts[i]);
1875  }
1876  }
1877  }
1878  }
1879 
1880  // Push in swifterror virtual register as the last element of Outs. This makes
1881  // sure swifterror virtual register will be returned in the swifterror
1882  // physical register.
1883  const Function *F = I.getParent()->getParent();
1884  if (TLI.supportSwiftError() &&
1885  F->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) {
1886  assert(FuncInfo.SwiftErrorArg && "Need a swift error argument");
1887  ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1888  Flags.setSwiftError();
1889  Outs.push_back(ISD::OutputArg(Flags, EVT(TLI.getPointerTy(DL)) /*vt*/,
1890  EVT(TLI.getPointerTy(DL)) /*argvt*/,
1891  true /*isfixed*/, 1 /*origidx*/,
1892  0 /*partOffs*/));
1893  // Create SDNode for the swifterror virtual register.
1894  OutVals.push_back(
1895  DAG.getRegister(FuncInfo.getOrCreateSwiftErrorVRegUseAt(
1896  &I, FuncInfo.MBB, FuncInfo.SwiftErrorArg).first,
1897  EVT(TLI.getPointerTy(DL))));
1898  }
1899 
1900  bool isVarArg = DAG.getMachineFunction().getFunction().isVarArg();
1901  CallingConv::ID CallConv =
1903  Chain = DAG.getTargetLoweringInfo().LowerReturn(
1904  Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1905 
1906  // Verify that the target's LowerReturn behaved as expected.
1907  assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1908  "LowerReturn didn't return a valid chain!");
1909 
1910  // Update the DAG with the new chain value resulting from return lowering.
1911  DAG.setRoot(Chain);
1912 }
1913 
1914 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1915 /// created for it, emit nodes to copy the value into the virtual
1916 /// registers.
1918  // Skip empty types
1919  if (V->getType()->isEmptyTy())
1920  return;
1921 
1922  DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1923  if (VMI != FuncInfo.ValueMap.end()) {
1924  assert(!V->use_empty() && "Unused value assigned virtual registers!");
1925  CopyValueToVirtualRegister(V, VMI->second);
1926  }
1927 }
1928 
1929 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1930 /// the current basic block, add it to ValueMap now so that we'll get a
1931 /// CopyTo/FromReg.
1933  // No need to export constants.
1934  if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1935 
1936  // Already exported?
1937  if (FuncInfo.isExportedInst(V)) return;
1938 
1939  unsigned Reg = FuncInfo.InitializeRegForValue(V);
1940  CopyValueToVirtualRegister(V, Reg);
1941 }
1942 
1944  const BasicBlock *FromBB) {
1945  // The operands of the setcc have to be in this block. We don't know
1946  // how to export them from some other block.
1947  if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1948  // Can export from current BB.
1949  if (VI->getParent() == FromBB)
1950  return true;
1951 
1952  // Is already exported, noop.
1953  return FuncInfo.isExportedInst(V);
1954  }
1955 
1956  // If this is an argument, we can export it if the BB is the entry block or
1957  // if it is already exported.
1958  if (isa<Argument>(V)) {
1959  if (FromBB == &FromBB->getParent()->getEntryBlock())
1960  return true;
1961 
1962  // Otherwise, can only export this if it is already exported.
1963  return FuncInfo.isExportedInst(V);
1964  }
1965 
1966  // Otherwise, constants can always be exported.
1967  return true;
1968 }
1969 
1970 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1972 SelectionDAGBuilder::getEdgeProbability(const MachineBasicBlock *Src,
1973  const MachineBasicBlock *Dst) const {
1974  BranchProbabilityInfo *BPI = FuncInfo.BPI;
1975  const BasicBlock *SrcBB = Src->getBasicBlock();
1976  const BasicBlock *DstBB = Dst->getBasicBlock();
1977  if (!BPI) {
1978  // If BPI is not available, set the default probability as 1 / N, where N is
1979  // the number of successors.
1980  auto SuccSize = std::max<uint32_t>(succ_size(SrcBB), 1);
1981  return BranchProbability(1, SuccSize);
1982  }
1983  return BPI->getEdgeProbability(SrcBB, DstBB);
1984 }
1985 
1986 void SelectionDAGBuilder::addSuccessorWithProb(MachineBasicBlock *Src,
1987  MachineBasicBlock *Dst,
1988  BranchProbability Prob) {
1989  if (!FuncInfo.BPI)
1990  Src->addSuccessorWithoutProb(Dst);
1991  else {
1992  if (Prob.isUnknown())
1993  Prob = getEdgeProbability(Src, Dst);
1994  Src->addSuccessor(Dst, Prob);
1995  }
1996 }
1997 
1998 static bool InBlock(const Value *V, const BasicBlock *BB) {
1999  if (const Instruction *I = dyn_cast<Instruction>(V))
2000  return I->getParent() == BB;
2001  return true;
2002 }
2003 
2004 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
2005 /// This function emits a branch and is used at the leaves of an OR or an
2006 /// AND operator tree.
2007 void
2009  MachineBasicBlock *TBB,
2010  MachineBasicBlock *FBB,
2011  MachineBasicBlock *CurBB,
2012  MachineBasicBlock *SwitchBB,
2013  BranchProbability TProb,
2014  BranchProbability FProb,
2015  bool InvertCond) {
2016  const BasicBlock *BB = CurBB->getBasicBlock();
2017 
2018  // If the leaf of the tree is a comparison, merge the condition into
2019  // the caseblock.
2020  if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
2021  // The operands of the cmp have to be in this block. We don't know
2022  // how to export them from some other block. If this is the first block
2023  // of the sequence, no exporting is needed.
2024  if (CurBB == SwitchBB ||
2025  (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
2026  isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
2027  ISD::CondCode Condition;
2028  if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
2029  ICmpInst::Predicate Pred =
2030  InvertCond ? IC->getInversePredicate() : IC->getPredicate();
2031  Condition = getICmpCondCode(Pred);
2032  } else {
2033  const FCmpInst *FC = cast<FCmpInst>(Cond);
2034  FCmpInst::Predicate Pred =
2035  InvertCond ? FC->getInversePredicate() : FC->getPredicate();
2036  Condition = getFCmpCondCode(Pred);
2037  if (TM.Options.NoNaNsFPMath)
2038  Condition = getFCmpCodeWithoutNaN(Condition);
2039  }
2040 
2041  CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
2042  TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb);
2043  SwitchCases.push_back(CB);
2044  return;
2045  }
2046  }
2047 
2048  // Create a CaseBlock record representing this branch.
2049  ISD::CondCode Opc = InvertCond ? ISD::SETNE : ISD::SETEQ;
2050  CaseBlock CB(Opc, Cond, ConstantInt::getTrue(*DAG.getContext()),
2051  nullptr, TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb);
2052  SwitchCases.push_back(CB);
2053 }
2054 
2056  MachineBasicBlock *TBB,
2057  MachineBasicBlock *FBB,
2058  MachineBasicBlock *CurBB,
2059  MachineBasicBlock *SwitchBB,
2061  BranchProbability TProb,
2062  BranchProbability FProb,
2063  bool InvertCond) {
2064  // Skip over not part of the tree and remember to invert op and operands at
2065  // next level.
2066  Value *NotCond;
2067  if (match(Cond, m_OneUse(m_Not(m_Value(NotCond)))) &&
2068  InBlock(NotCond, CurBB->getBasicBlock())) {
2069  FindMergedConditions(NotCond, TBB, FBB, CurBB, SwitchBB, Opc, TProb, FProb,
2070  !InvertCond);
2071  return;
2072  }
2073 
2074  const Instruction *BOp = dyn_cast<Instruction>(Cond);
2075  // Compute the effective opcode for Cond, taking into account whether it needs
2076  // to be inverted, e.g.
2077  // and (not (or A, B)), C
2078  // gets lowered as
2079  // and (and (not A, not B), C)
2080  unsigned BOpc = 0;
2081  if (BOp) {
2082  BOpc = BOp->getOpcode();
2083  if (InvertCond) {
2084  if (BOpc == Instruction::And)
2085  BOpc = Instruction::Or;
2086  else if (BOpc == Instruction::Or)
2087  BOpc = Instruction::And;
2088  }
2089  }
2090 
2091  // If this node is not part of the or/and tree, emit it as a branch.
2092  if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
2093  BOpc != unsigned(Opc) || !BOp->hasOneUse() ||
2094  BOp->getParent() != CurBB->getBasicBlock() ||
2095  !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
2096  !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
2097  EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
2098  TProb, FProb, InvertCond);
2099  return;
2100  }
2101 
2102  // Create TmpBB after CurBB.
2103  MachineFunction::iterator BBI(CurBB);
2104  MachineFunction &MF = DAG.getMachineFunction();
2106  CurBB->getParent()->insert(++BBI, TmpBB);
2107 
2108  if (Opc == Instruction::Or) {
2109  // Codegen X | Y as:
2110  // BB1:
2111  // jmp_if_X TBB
2112  // jmp TmpBB
2113  // TmpBB:
2114  // jmp_if_Y TBB
2115  // jmp FBB
2116  //
2117 
2118  // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
2119  // The requirement is that
2120  // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
2121  // = TrueProb for original BB.
2122  // Assuming the original probabilities are A and B, one choice is to set
2123  // BB1's probabilities to A/2 and A/2+B, and set TmpBB's probabilities to
2124  // A/(1+B) and 2B/(1+B). This choice assumes that
2125  // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
2126  // Another choice is to assume TrueProb for BB1 equals to TrueProb for
2127  // TmpBB, but the math is more complicated.
2128 
2129  auto NewTrueProb = TProb / 2;
2130  auto NewFalseProb = TProb / 2 + FProb;
2131  // Emit the LHS condition.
2132  FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
2133  NewTrueProb, NewFalseProb, InvertCond);
2134 
2135  // Normalize A/2 and B to get A/(1+B) and 2B/(1+B).
2136  SmallVector<BranchProbability, 2> Probs{TProb / 2, FProb};
2137  BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
2138  // Emit the RHS condition into TmpBB.
2139  FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
2140  Probs[0], Probs[1], InvertCond);
2141  } else {
2142  assert(Opc == Instruction::And && "Unknown merge op!");
2143  // Codegen X & Y as:
2144  // BB1:
2145  // jmp_if_X TmpBB
2146  // jmp FBB
2147  // TmpBB:
2148  // jmp_if_Y TBB
2149  // jmp FBB
2150  //
2151  // This requires creation of TmpBB after CurBB.
2152 
2153  // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
2154  // The requirement is that
2155  // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
2156  // = FalseProb for original BB.
2157  // Assuming the original probabilities are A and B, one choice is to set
2158  // BB1's probabilities to A+B/2 and B/2, and set TmpBB's probabilities to
2159  // 2A/(1+A) and B/(1+A). This choice assumes that FalseProb for BB1 ==
2160  // TrueProb for BB1 * FalseProb for TmpBB.
2161 
2162  auto NewTrueProb = TProb + FProb / 2;
2163  auto NewFalseProb = FProb / 2;
2164  // Emit the LHS condition.
2165  FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
2166  NewTrueProb, NewFalseProb, InvertCond);
2167 
2168  // Normalize A and B/2 to get 2A/(1+A) and B/(1+A).
2169  SmallVector<BranchProbability, 2> Probs{TProb, FProb / 2};
2170  BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
2171  // Emit the RHS condition into TmpBB.
2172  FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
2173  Probs[0], Probs[1], InvertCond);
2174  }
2175 }
2176 
2177 /// If the set of cases should be emitted as a series of branches, return true.
2178 /// If we should emit this as a bunch of and/or'd together conditions, return
2179 /// false.
2180 bool
2181 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
2182  if (Cases.size() != 2) return true;
2183 
2184  // If this is two comparisons of the same values or'd or and'd together, they
2185  // will get folded into a single comparison, so don't emit two blocks.
2186  if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
2187  Cases[0].CmpRHS == Cases[1].CmpRHS) ||
2188  (Cases[0].CmpRHS == Cases[1].CmpLHS &&
2189  Cases[0].CmpLHS == Cases[1].CmpRHS)) {
2190  return false;
2191  }
2192 
2193  // Handle: (X != null) | (Y != null) --> (X|Y) != 0
2194  // Handle: (X == null) & (Y == null) --> (X|Y) == 0
2195  if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
2196  Cases[0].CC == Cases[1].CC &&
2197  isa<Constant>(Cases[0].CmpRHS) &&
2198  cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
2199  if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
2200  return false;
2201  if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
2202  return false;
2203  }
2204 
2205  return true;
2206 }
2207 
2208 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
2209  MachineBasicBlock *BrMBB = FuncInfo.MBB;
2210 
2211  // Update machine-CFG edges.
2212  MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
2213 
2214  if (I.isUnconditional()) {
2215  // Update machine-CFG edges.
2216  BrMBB->addSuccessor(Succ0MBB);
2217 
2218  // If this is not a fall-through branch or optimizations are switched off,
2219  // emit the branch.
2220  if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
2221  DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2222  MVT::Other, getControlRoot(),
2223  DAG.getBasicBlock(Succ0MBB)));
2224 
2225  return;
2226  }
2227 
2228  // If this condition is one of the special cases we handle, do special stuff
2229  // now.
2230  const Value *CondVal = I.getCondition();
2231  MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
2232 
2233  // If this is a series of conditions that are or'd or and'd together, emit
2234  // this as a sequence of branches instead of setcc's with and/or operations.
2235  // As long as jumps are not expensive, this should improve performance.
2236  // For example, instead of something like:
2237  // cmp A, B
2238  // C = seteq
2239  // cmp D, E
2240  // F = setle
2241  // or C, F
2242  // jnz foo
2243  // Emit:
2244  // cmp A, B
2245  // je foo
2246  // cmp D, E
2247  // jle foo
2248  if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
2249  Instruction::BinaryOps Opcode = BOp->getOpcode();
2250  if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
2252  (Opcode == Instruction::And || Opcode == Instruction::Or)) {
2253  FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
2254  Opcode,
2255  getEdgeProbability(BrMBB, Succ0MBB),
2256  getEdgeProbability(BrMBB, Succ1MBB),
2257  /*InvertCond=*/false);
2258  // If the compares in later blocks need to use values not currently
2259  // exported from this block, export them now. This block should always
2260  // be the first entry.
2261  assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
2262 
2263  // Allow some cases to be rejected.
2264  if (ShouldEmitAsBranches(SwitchCases)) {
2265  for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
2266  ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
2267  ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
2268  }
2269 
2270  // Emit the branch for this block.
2271  visitSwitchCase(SwitchCases[0], BrMBB);
2272  SwitchCases.erase(SwitchCases.begin());
2273  return;
2274  }
2275 
2276  // Okay, we decided not to do this, remove any inserted MBB's and clear
2277  // SwitchCases.
2278  for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
2279  FuncInfo.MF->erase(SwitchCases[i].ThisBB);
2280 
2281  SwitchCases.clear();
2282  }
2283  }
2284 
2285  // Create a CaseBlock record representing this branch.
2286  CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
2287  nullptr, Succ0MBB, Succ1MBB, BrMBB, getCurSDLoc());
2288 
2289  // Use visitSwitchCase to actually insert the fast branch sequence for this
2290  // cond branch.
2291  visitSwitchCase(CB, BrMBB);
2292 }
2293 
2294 /// visitSwitchCase - Emits the necessary code to represent a single node in
2295 /// the binary search tree resulting from lowering a switch instruction.
2297  MachineBasicBlock *SwitchBB) {
2298  SDValue Cond;
2299  SDValue CondLHS = getValue(CB.CmpLHS);
2300  SDLoc dl = CB.DL;
2301 
2302  if (CB.CC == ISD::SETTRUE) {
2303  // Branch or fall through to TrueBB.
2304  addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb);
2305  SwitchBB->normalizeSuccProbs();
2306  if (CB.TrueBB != NextBlock(SwitchBB)) {
2307  DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, getControlRoot(),
2308  DAG.getBasicBlock(CB.TrueBB)));
2309  }
2310  return;
2311  }
2312 
2313  // Build the setcc now.
2314  if (!CB.CmpMHS) {
2315  // Fold "(X == true)" to X and "(X == false)" to !X to
2316  // handle common cases produced by branch lowering.
2317  if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
2318  CB.CC == ISD::SETEQ)
2319  Cond = CondLHS;
2320  else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
2321  CB.CC == ISD::SETEQ) {
2322  SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
2323  Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
2324  } else
2325  Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
2326  } else {
2327  assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
2328 
2329  const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
2330  const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
2331 
2332  SDValue CmpOp = getValue(CB.CmpMHS);
2333  EVT VT = CmpOp.getValueType();
2334 
2335  if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
2336  Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
2337  ISD::SETLE);
2338  } else {
2339  SDValue SUB = DAG.getNode(ISD::SUB, dl,
2340  VT, CmpOp, DAG.getConstant(Low, dl, VT));
2341  Cond = DAG.getSetCC(dl, MVT::i1, SUB,
2342  DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
2343  }
2344  }
2345 
2346  // Update successor info
2347  addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb);
2348  // TrueBB and FalseBB are always different unless the incoming IR is
2349  // degenerate. This only happens when running llc on weird IR.
2350  if (CB.TrueBB != CB.FalseBB)
2351  addSuccessorWithProb(SwitchBB, CB.FalseBB, CB.FalseProb);
2352  SwitchBB->normalizeSuccProbs();
2353 
2354  // If the lhs block is the next block, invert the condition so that we can
2355  // fall through to the lhs instead of the rhs block.
2356  if (CB.TrueBB == NextBlock(SwitchBB)) {
2357  std::swap(CB.TrueBB, CB.FalseBB);
2358  SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
2359  Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
2360  }
2361 
2362  SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2363  MVT::Other, getControlRoot(), Cond,
2364  DAG.getBasicBlock(CB.TrueBB));
2365 
2366  // Insert the false branch. Do this even if it's a fall through branch,
2367  // this makes it easier to do DAG optimizations which require inverting
2368  // the branch condition.
2369  BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
2370  DAG.getBasicBlock(CB.FalseBB));
2371 
2372  DAG.setRoot(BrCond);
2373 }
2374 
2375 /// visitJumpTable - Emit JumpTable node in the current MBB
2377  // Emit the code for the jump table
2378  assert(JT.Reg != -1U && "Should lower JT Header first!");
2380  SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
2381  JT.Reg, PTy);
2382  SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
2383  SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
2384  MVT::Other, Index.getValue(1),
2385  Table, Index);
2386  DAG.setRoot(BrJumpTable);
2387 }
2388 
2389 /// visitJumpTableHeader - This function emits necessary code to produce index
2390 /// in the JumpTable from switch case.
2392  JumpTableHeader &JTH,
2393  MachineBasicBlock *SwitchBB) {
2394  SDLoc dl = getCurSDLoc();
2395 
2396  // Subtract the lowest switch case value from the value being switched on.
2397  SDValue SwitchOp = getValue(JTH.SValue);
2398  EVT VT = SwitchOp.getValueType();
2399  SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
2400  DAG.getConstant(JTH.First, dl, VT));
2401 
2402  // The SDNode we just created, which holds the value being switched on minus
2403  // the smallest case value, needs to be copied to a virtual register so it
2404  // can be used as an index into the jump table in a subsequent basic block.
2405  // This value may be smaller or larger than the target's pointer type, and
2406  // therefore require extension or truncating.
2407  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2408  SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
2409 
2410  unsigned JumpTableReg =
2411  FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
2412  SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
2413  JumpTableReg, SwitchOp);
2414  JT.Reg = JumpTableReg;
2415 
2416  if (!JTH.OmitRangeCheck) {
2417  // Emit the range check for the jump table, and branch to the default block
2418  // for the switch statement if the value being switched on exceeds the
2419  // largest case in the switch.
2420  SDValue CMP = DAG.getSetCC(
2421  dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
2422  Sub.getValueType()),
2423  Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
2424 
2425  SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2426  MVT::Other, CopyTo, CMP,
2427  DAG.getBasicBlock(JT.Default));
2428 
2429  // Avoid emitting unnecessary branches to the next block.
2430  if (JT.MBB != NextBlock(SwitchBB))
2431  BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
2432  DAG.getBasicBlock(JT.MBB));
2433 
2434  DAG.setRoot(BrCond);
2435  } else {
2436  // Avoid emitting unnecessary branches to the next block.
2437  if (JT.MBB != NextBlock(SwitchBB))
2438  DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, CopyTo,
2439  DAG.getBasicBlock(JT.MBB)));
2440  else
2441  DAG.setRoot(CopyTo);
2442  }
2443 }
2444 
2445 /// Create a LOAD_STACK_GUARD node, and let it carry the target specific global
2446 /// variable if there exists one.
2448  SDValue &Chain) {
2449  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2450  EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
2451  MachineFunction &MF = DAG.getMachineFunction();
2452  Value *Global = TLI.getSDagStackGuard(*MF.getFunction().getParent());
2453  MachineSDNode *Node =
2454  DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD, DL, PtrTy, Chain);
2455  if (Global) {
2456  MachinePointerInfo MPInfo(Global);
2460  MPInfo, Flags, PtrTy.getSizeInBits() / 8, DAG.getEVTAlignment(PtrTy));
2461  DAG.setNodeMemRefs(Node, {MemRef});
2462  }
2463  return SDValue(Node, 0);
2464 }
2465 
2466 /// Codegen a new tail for a stack protector check ParentMBB which has had its
2467 /// tail spliced into a stack protector check success bb.
2468 ///
2469 /// For a high level explanation of how this fits into the stack protector
2470 /// generation see the comment on the declaration of class
2471 /// StackProtectorDescriptor.
2472 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
2473  MachineBasicBlock *ParentBB) {
2474 
2475  // First create the loads to the guard/stack slot for the comparison.
2476  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2477  EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
2478 
2479  MachineFrameInfo &MFI = ParentBB->getParent()->getFrameInfo();
2480  int FI = MFI.getStackProtectorIndex();
2481 
2482  SDValue Guard;
2483  SDLoc dl = getCurSDLoc();
2484  SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
2485  const Module &M = *ParentBB->getParent()->getFunction().getParent();
2486  unsigned Align = DL->getPrefTypeAlignment(Type::getInt8PtrTy(M.getContext()));
2487 
2488  // Generate code to load the content of the guard slot.
2489  SDValue GuardVal = DAG.getLoad(
2490  PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
2493 
2494  if (TLI.useStackGuardXorFP())
2495  GuardVal = TLI.emitStackGuardXorFP(DAG, GuardVal, dl);
2496 
2497  // Retrieve guard check function, nullptr if instrumentation is inlined.
2498  if (const Function *GuardCheckFn = TLI.getSSPStackGuardCheck(M)) {
2499  // The target provides a guard check function to validate the guard value.
2500  // Generate a call to that function with the content of the guard slot as
2501  // argument.
2502  FunctionType *FnTy = GuardCheckFn->getFunctionType();
2503  assert(FnTy->getNumParams() == 1 && "Invalid function signature");
2504 
2507  Entry.Node = GuardVal;
2508  Entry.Ty = FnTy->getParamType(0);
2509  if (GuardCheckFn->hasAttribute(1, Attribute::AttrKind::InReg))
2510  Entry.IsInReg = true;
2511  Args.push_back(Entry);
2512 
2514  CLI.setDebugLoc(getCurSDLoc())
2515  .setChain(DAG.getEntryNode())
2516  .setCallee(GuardCheckFn->getCallingConv(), FnTy->getReturnType(),
2517  getValue(GuardCheckFn), std::move(Args));
2518 
2519  std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
2520  DAG.setRoot(Result.second);
2521  return;
2522  }
2523 
2524  // If useLoadStackGuardNode returns true, generate LOAD_STACK_GUARD.
2525  // Otherwise, emit a volatile load to retrieve the stack guard value.
2526  SDValue Chain = DAG.getEntryNode();
2527  if (TLI.useLoadStackGuardNode()) {
2528  Guard = getLoadStackGuard(DAG, dl, Chain);
2529  } else {
2530  const Value *IRGuard = TLI.getSDagStackGuard(M);
2531  SDValue GuardPtr = getValue(IRGuard);
2532 
2533  Guard =
2534  DAG.getLoad(PtrTy, dl, Chain, GuardPtr, MachinePointerInfo(IRGuard, 0),
2536  }
2537 
2538  // Perform the comparison via a subtract/getsetcc.
2539  EVT VT = Guard.getValueType();
2540  SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, GuardVal);
2541 
2542  SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
2543  *DAG.getContext(),
2544  Sub.getValueType()),
2545  Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
2546 
2547  // If the sub is not 0, then we know the guard/stackslot do not equal, so
2548  // branch to failure MBB.
2549  SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2550  MVT::Other, GuardVal.getOperand(0),
2551  Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
2552  // Otherwise branch to success MBB.
2553  SDValue Br = DAG.getNode(ISD::BR, dl,
2554  MVT::Other, BrCond,
2555  DAG.getBasicBlock(SPD.getSuccessMBB()));
2556 
2557  DAG.setRoot(Br);
2558 }
2559 
2560 /// Codegen the failure basic block for a stack protector check.
2561 ///
2562 /// A failure stack protector machine basic block consists simply of a call to
2563 /// __stack_chk_fail().
2564 ///
2565 /// For a high level explanation of how this fits into the stack protector
2566 /// generation see the comment on the declaration of class
2567 /// StackProtectorDescriptor.
2568 void
2569 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
2570  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2571  SDValue Chain =
2572  TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
2573  None, false, getCurSDLoc(), false, false).second;
2574  // On PS4, the "return address" must still be within the calling function,
2575  // even if it's at the very end, so emit an explicit TRAP here.
2576  // Passing 'true' for doesNotReturn above won't generate the trap for us.
2577  if (TM.getTargetTriple().isPS4CPU())
2578  Chain = DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, Chain);
2579 
2580  DAG.setRoot(Chain);
2581 }
2582 
2583 /// visitBitTestHeader - This function emits necessary code to produce value
2584 /// suitable for "bit tests"
2586  MachineBasicBlock *SwitchBB) {
2587  SDLoc dl = getCurSDLoc();
2588 
2589  // Subtract the minimum value
2590  SDValue SwitchOp = getValue(B.SValue);
2591  EVT VT = SwitchOp.getValueType();
2592  SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
2593  DAG.getConstant(B.First, dl, VT));
2594 
2595  // Check range
2596  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2597  SDValue RangeCmp = DAG.getSetCC(
2598  dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
2599  Sub.getValueType()),
2600  Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
2601 
2602  // Determine the type of the test operands.
2603  bool UsePtrType = false;
2604  if (!TLI.isTypeLegal(VT))
2605  UsePtrType = true;
2606  else {
2607  for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
2608  if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
2609  // Switch table case range are encoded into series of masks.
2610  // Just use pointer type, it's guaranteed to fit.
2611  UsePtrType = true;
2612  break;
2613  }
2614  }
2615  if (UsePtrType) {
2616  VT = TLI.getPointerTy(DAG.getDataLayout());
2617  Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
2618  }
2619 
2620  B.RegVT = VT.getSimpleVT();
2621  B.Reg = FuncInfo.CreateReg(B.RegVT);
2622  SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
2623 
2624  MachineBasicBlock* MBB = B.Cases[0].ThisBB;
2625 
2626  addSuccessorWithProb(SwitchBB, B.Default, B.DefaultProb);
2627  addSuccessorWithProb(SwitchBB, MBB, B.Prob);
2628  SwitchBB->normalizeSuccProbs();
2629 
2630  SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
2631  MVT::Other, CopyTo, RangeCmp,
2632  DAG.getBasicBlock(B.Default));
2633 
2634  // Avoid emitting unnecessary branches to the next block.
2635  if (MBB != NextBlock(SwitchBB))
2636  BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
2637  DAG.getBasicBlock(MBB));
2638 
2639  DAG.setRoot(BrRange);
2640 }
2641 
2642 /// visitBitTestCase - this function produces one "bit test"
2644  MachineBasicBlock* NextMBB,
2645  BranchProbability BranchProbToNext,
2646  unsigned Reg,
2647  BitTestCase &B,
2648  MachineBasicBlock *SwitchBB) {
2649  SDLoc dl = getCurSDLoc();
2650  MVT VT = BB.RegVT;
2651  SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
2652  SDValue Cmp;
2653  unsigned PopCount = countPopulation(B.Mask);
2654  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2655  if (PopCount == 1) {
2656  // Testing for a single bit; just compare the shift count with what it
2657  // would need to be to shift a 1 bit in that position.
2658  Cmp = DAG.getSetCC(
2659  dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2660  ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2661  ISD::SETEQ);
2662  } else if (PopCount == BB.Range) {
2663  // There is only one zero bit in the range, test for it directly.
2664  Cmp = DAG.getSetCC(
2665  dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2666  ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2667  ISD::SETNE);
2668  } else {
2669  // Make desired shift
2670  SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2671  DAG.getConstant(1, dl, VT), ShiftOp);
2672 
2673  // Emit bit tests and jumps
2674  SDValue AndOp = DAG.getNode(ISD::AND, dl,
2675  VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2676  Cmp = DAG.getSetCC(
2677  dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2678  AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2679  }
2680 
2681  // The branch probability from SwitchBB to B.TargetBB is B.ExtraProb.
2682  addSuccessorWithProb(SwitchBB, B.TargetBB, B.ExtraProb);
2683  // The branch probability from SwitchBB to NextMBB is BranchProbToNext.
2684  addSuccessorWithProb(SwitchBB, NextMBB, BranchProbToNext);
2685  // It is not guaranteed that the sum of B.ExtraProb and BranchProbToNext is
2686  // one as they are relative probabilities (and thus work more like weights),
2687  // and hence we need to normalize them to let the sum of them become one.
2688  SwitchBB->normalizeSuccProbs();
2689 
2690  SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2691  MVT::Other, getControlRoot(),
2692  Cmp, DAG.getBasicBlock(B.TargetBB));
2693 
2694  // Avoid emitting unnecessary branches to the next block.
2695  if (NextMBB != NextBlock(SwitchBB))
2696  BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2697  DAG.getBasicBlock(NextMBB));
2698 
2699  DAG.setRoot(BrAnd);
2700 }
2701 
2702 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2703  MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2704 
2705  // Retrieve successors. Look through artificial IR level blocks like
2706  // catchswitch for successors.
2707  MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2708  const BasicBlock *EHPadBB = I.getSuccessor(1);
2709 
2710  // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't
2711  // have to do anything here to lower funclet bundles.
2713  {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) &&
2714  "Cannot lower invokes with arbitrary operand bundles yet!");
2715 
2716  const Value *Callee(I.getCalledValue());
2717  const Function *Fn = dyn_cast<Function>(Callee);
2718  if (isa<InlineAsm>(Callee))
2719  visitInlineAsm(&I);
2720  else if (Fn && Fn->isIntrinsic()) {
2721  switch (Fn->getIntrinsicID()) {
2722  default:
2723  llvm_unreachable("Cannot invoke this intrinsic");
2724  case Intrinsic::donothing:
2725  // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2726  break;
2727  case Intrinsic::experimental_patchpoint_void:
2728  case Intrinsic::experimental_patchpoint_i64:
2729  visitPatchpoint(&I, EHPadBB);
2730  break;
2731  case Intrinsic::experimental_gc_statepoint:
2732  LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2733  break;
2734  case Intrinsic::wasm_rethrow_in_catch: {
2735  // This is usually done in visitTargetIntrinsic, but this intrinsic is
2736  // special because it can be invoked, so we manually lower it to a DAG
2737  // node here.
2739  Ops.push_back(getRoot()); // inchain
2740  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2741  Ops.push_back(
2742  DAG.getTargetConstant(Intrinsic::wasm_rethrow_in_catch, getCurSDLoc(),
2743  TLI.getPointerTy(DAG.getDataLayout())));
2744  SDVTList VTs = DAG.getVTList(ArrayRef<EVT>({MVT::Other})); // outchain
2745  DAG.setRoot(DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops));
2746  break;
2747  }
2748  }
2750  // Currently we do not lower any intrinsic calls with deopt operand bundles.
2751  // Eventually we will support lowering the @llvm.experimental.deoptimize
2752  // intrinsic, and right now there are no plans to support other intrinsics
2753  // with deopt state.
2754  LowerCallSiteWithDeoptBundle(&I, getValue(Callee), EHPadBB);
2755  } else {
2756  LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2757  }
2758 
2759  // If the value of the invoke is used outside of its defining block, make it
2760  // available as a virtual register.
2761  // We already took care of the exported value for the statepoint instruction
2762  // during call to the LowerStatepoint.
2763  if (!isStatepoint(I)) {
2764  CopyToExportRegsIfNeeded(&I);
2765  }
2766 
2768  BranchProbabilityInfo *BPI = FuncInfo.BPI;
2769  BranchProbability EHPadBBProb =
2770  BPI ? BPI->getEdgeProbability(InvokeMBB->getBasicBlock(), EHPadBB)
2772  findUnwindDestinations(FuncInfo, EHPadBB, EHPadBBProb, UnwindDests);
2773 
2774  // Update successor info.
2775  addSuccessorWithProb(InvokeMBB, Return);
2776  for (auto &UnwindDest : UnwindDests) {
2777  UnwindDest.first->setIsEHPad();
2778  addSuccessorWithProb(InvokeMBB, UnwindDest.first, UnwindDest.second);
2779  }
2780  InvokeMBB->normalizeSuccProbs();
2781 
2782  // Drop into normal successor.
2783  DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, getControlRoot(),
2784  DAG.getBasicBlock(Return)));
2785 }
2786 
2787 void SelectionDAGBuilder::visitCallBr(const CallBrInst &I) {
2788  MachineBasicBlock *CallBrMBB = FuncInfo.MBB;
2789 
2790  // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't
2791  // have to do anything here to lower funclet bundles.
2793  {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) &&
2794  "Cannot lower callbrs with arbitrary operand bundles yet!");
2795 
2796  assert(isa<InlineAsm>(I.getCalledValue()) &&
2797  "Only know how to handle inlineasm callbr");
2798  visitInlineAsm(&I);
2799 
2800  // Retrieve successors.
2801  MachineBasicBlock *Return = FuncInfo.MBBMap[I.getDefaultDest()];
2802 
2803  // Update successor info.
2804  addSuccessorWithProb(CallBrMBB, Return);
2805  for (unsigned i = 0, e = I.getNumIndirectDests(); i < e; ++i) {
2806  MachineBasicBlock *Target = FuncInfo.MBBMap[I.getIndirectDest(i)];
2807  addSuccessorWithProb(CallBrMBB, Target);
2808  }
2809  CallBrMBB->normalizeSuccProbs();
2810 
2811  // Drop into default successor.
2812  DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2813  MVT::Other, getControlRoot(),
2814  DAG.getBasicBlock(Return)));
2815 }
2816 
2817 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2818  llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2819 }
2820 
2821 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2822  assert(FuncInfo.MBB->isEHPad() &&
2823  "Call to landingpad not in landing pad!");
2824 
2825  // If there aren't registers to copy the values into (e.g., during SjLj
2826  // exceptions), then don't bother to create these DAG nodes.
2827  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2828  const Constant *PersonalityFn = FuncInfo.Fn->getPersonalityFn();
2829  if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
2830  TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
2831  return;
2832 
2833  // If landingpad's return type is token type, we don't create DAG nodes
2834  // for its exception pointer and selector value. The extraction of exception
2835  // pointer or selector value from token type landingpads is not currently
2836  // supported.
2837  if (LP.getType()->isTokenTy())
2838  return;
2839 
2841  SDLoc dl = getCurSDLoc();
2842  ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2843  assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2844 
2845  // Get the two live-in registers as SDValues. The physregs have already been
2846  // copied into virtual registers.
2847  SDValue Ops[2];
2848  if (FuncInfo.ExceptionPointerVirtReg) {
2849  Ops[0] = DAG.getZExtOrTrunc(
2850  DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2851  FuncInfo.ExceptionPointerVirtReg,
2852  TLI.getPointerTy(DAG.getDataLayout())),
2853  dl, ValueVTs[0]);
2854  } else {
2855  Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2856  }
2857  Ops[1] = DAG.getZExtOrTrunc(
2858  DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2859  FuncInfo.ExceptionSelectorVirtReg,
2860  TLI.getPointerTy(DAG.getDataLayout())),
2861  dl, ValueVTs[1]);
2862 
2863  // Merge into one.
2864  SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2865  DAG.getVTList(ValueVTs), Ops);
2866  setValue(&LP, Res);
2867 }
2868 
2869 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2870 #ifndef NDEBUG
2871  for (const CaseCluster &CC : Clusters)
2872  assert(CC.Low == CC.High && "Input clusters must be single-case");
2873 #endif
2874 
2875  llvm::sort(Clusters, [](const CaseCluster &a, const CaseCluster &b) {
2876  return a.Low->getValue().slt(b.Low->getValue());
2877  });
2878 
2879  // Merge adjacent clusters with the same destination.
2880  const unsigned N = Clusters.size();
2881  unsigned DstIndex = 0;
2882  for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2883  CaseCluster &CC = Clusters[SrcIndex];
2884  const ConstantInt *CaseVal = CC.Low;
2885  MachineBasicBlock *Succ = CC.MBB;
2886 
2887  if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2888  (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2889  // If this case has the same successor and is a neighbour, merge it into
2890  // the previous cluster.
2891  Clusters[DstIndex - 1].High = CaseVal;
2892  Clusters[DstIndex - 1].Prob += CC.Prob;
2893  } else {
2894  std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2895  sizeof(Clusters[SrcIndex]));
2896  }
2897  }
2898  Clusters.resize(DstIndex);
2899 }
2900 
2902  MachineBasicBlock *Last) {
2903  // Update JTCases.
2904  for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2905  if (JTCases[i].first.HeaderBB == First)
2906  JTCases[i].first.HeaderBB = Last;
2907 
2908  // Update BitTestCases.
2909  for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2910  if (BitTestCases[i].Parent == First)
2911  BitTestCases[i].Parent = Last;
2912 }
2913 
2914 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2915  MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2916 
2917  // Update machine-CFG edges with unique successors.
2919  for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2920  BasicBlock *BB = I.getSuccessor(i);
2921  bool Inserted = Done.insert(BB).second;
2922  if (!Inserted)
2923  continue;
2924 
2925  MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2926  addSuccessorWithProb(IndirectBrMBB, Succ);
2927  }
2928  IndirectBrMBB->normalizeSuccProbs();
2929 
2930  DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2931  MVT::Other, getControlRoot(),
2932  getValue(I.getAddress())));
2933 }
2934 
2935 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2936  if (!DAG.getTarget().Options.TrapUnreachable)
2937  return;
2938 
2939  // We may be able to ignore unreachable behind a noreturn call.
2941  const BasicBlock &BB = *I.getParent();
2942  if (&I != &BB.front()) {
2944  std::prev(BasicBlock::const_iterator(&I));
2945  if (const CallInst *Call = dyn_cast<CallInst>(&*PredI)) {
2946  if (Call->doesNotReturn())
2947  return;
2948  }
2949  }
2950  }
2951 
2952  DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2953 }
2954 
2955 void SelectionDAGBuilder::visitFSub(const User &I) {
2956  // -0.0 - X --> fneg
2957  Type *Ty = I.getType();
2958  if (isa<Constant>(I.getOperand(0)) &&
2960  SDValue Op2 = getValue(I.getOperand(1));
2961  setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2962  Op2.getValueType(), Op2));
2963  return;
2964  }
2965 
2966  visitBinary(I, ISD::FSUB);
2967 }
2968 
2969 /// Checks if the given instruction performs a vector reduction, in which case
2970 /// we have the freedom to alter the elements in the result as long as the
2971 /// reduction of them stays unchanged.
2972 static bool isVectorReductionOp(const User *I) {
2973  const Instruction *Inst = dyn_cast<Instruction>(I);
2974  if (!Inst || !Inst->getType()->isVectorTy())
2975  return false;
2976 
2977  auto OpCode = Inst->getOpcode();
2978  switch (OpCode) {
2979  case Instruction::Add:
2980  case Instruction::Mul:
2981  case Instruction::And:
2982  case Instruction::Or:
2983  case Instruction::Xor:
2984  break;
2985  case Instruction::FAdd:
2986  case Instruction::FMul:
2987  if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(Inst))
2988  if (FPOp->getFastMathFlags().isFast())
2989  break;
2991  default:
2992  return false;
2993  }
2994 
2995  unsigned ElemNum = Inst->getType()->getVectorNumElements();
2996  // Ensure the reduction size is a power of 2.
2997  if (!isPowerOf2_32(ElemNum))
2998  return false;
2999 
3000  unsigned ElemNumToReduce = ElemNum;
3001 
3002  // Do DFS search on the def-use chain from the given instruction. We only
3003  // allow four kinds of operations during the search until we reach the
3004  // instruction that extracts the first element from the vector:
3005  //
3006  // 1. The reduction operation of the same opcode as the given instruction.
3007  //
3008  // 2. PHI node.
3009  //
3010  // 3. ShuffleVector instruction together with a reduction operation that
3011  // does a partial reduction.
3012  //
3013  // 4. ExtractElement that extracts the first element from the vector, and we
3014  // stop searching the def-use chain here.
3015  //
3016  // 3 & 4 above perform a reduction on all elements of the vector. We push defs
3017  // from 1-3 to the stack to continue the DFS. The given instruction is not
3018  // a reduction operation if we meet any other instructions other than those
3019  // listed above.
3020 
3021  SmallVector<const User *, 16> UsersToVisit{Inst};
3023  bool ReduxExtracted = false;
3024 
3025  while (!UsersToVisit.empty()) {
3026  auto User = UsersToVisit.back();
3027  UsersToVisit.pop_back();
3028  if (!Visited.insert(User).second)
3029  continue;
3030 
3031  for (const auto &U : User->users()) {
3032  auto Inst = dyn_cast<Instruction>(U);
3033  if (!Inst)
3034  return false;
3035 
3036  if (Inst->getOpcode() == OpCode || isa<PHINode>(U)) {
3037  if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(Inst))
3038  if (!isa<PHINode>(FPOp) && !FPOp->getFastMathFlags().isFast())
3039  return false;
3040  UsersToVisit.push_back(U);
3041  } else if (const ShuffleVectorInst *ShufInst =
3042  dyn_cast<ShuffleVectorInst>(U)) {
3043  // Detect the following pattern: A ShuffleVector instruction together
3044  // with a reduction that do partial reduction on the first and second
3045  // ElemNumToReduce / 2 elements, and store the result in
3046  // ElemNumToReduce / 2 elements in another vector.
3047 
3048  unsigned ResultElements = ShufInst->getType()->getVectorNumElements();
3049  if (ResultElements < ElemNum)
3050  return false;
3051 
3052  if (ElemNumToReduce == 1)
3053  return false;
3054  if (!isa<UndefValue>(U->getOperand(1)))
3055  return false;
3056  for (unsigned i = 0; i < ElemNumToReduce / 2; ++i)
3057  if (ShufInst->getMaskValue(i) != int(i + ElemNumToReduce / 2))
3058  return false;
3059  for (unsigned i = ElemNumToReduce / 2; i < ElemNum; ++i)
3060  if (ShufInst->getMaskValue(i) != -1)
3061  return false;
3062 
3063  // There is only one user of this ShuffleVector instruction, which
3064  // must be a reduction operation.
3065  if (!U->hasOneUse())
3066  return false;
3067 
3068  auto U2 = dyn_cast<Instruction>(*U->user_begin());
3069  if (!U2 || U2->getOpcode() != OpCode)
3070  return false;
3071 
3072  // Check operands of the reduction operation.
3073  if ((U2->getOperand(0) == U->getOperand(0) && U2->getOperand(1) == U) ||
3074  (U2->getOperand(1) == U->getOperand(0) && U2->getOperand(0) == U)) {
3075  UsersToVisit.push_back(U2);
3076  ElemNumToReduce /= 2;
3077  } else
3078  return false;
3079  } else if (isa<ExtractElementInst>(U)) {
3080  // At this moment we should have reduced all elements in the vector.
3081  if (ElemNumToReduce != 1)
3082  return false;
3083 
3084  const ConstantInt *Val = dyn_cast<ConstantInt>(U->getOperand(1));
3085  if (!Val || !Val->isZero())
3086  return false;
3087 
3088  ReduxExtracted = true;
3089  } else
3090  return false;
3091  }
3092  }
3093  return ReduxExtracted;
3094 }
3095 
3096 void SelectionDAGBuilder::visitUnary(const User &I, unsigned Opcode) {
3097  SDNodeFlags Flags;
3098 
3099  SDValue Op = getValue(I.getOperand(0));
3100  SDValue UnNodeValue = DAG.getNode(Opcode, getCurSDLoc(), Op.getValueType(),
3101  Op, Flags);
3102  setValue(&I, UnNodeValue);
3103 }
3104 
3105 void SelectionDAGBuilder::visitBinary(const User &I, unsigned Opcode) {
3106  SDNodeFlags Flags;
3107  if (auto *OFBinOp = dyn_cast<OverflowingBinaryOperator>(&I)) {
3108  Flags.setNoSignedWrap(OFBinOp->hasNoSignedWrap());
3109  Flags.setNoUnsignedWrap(OFBinOp->hasNoUnsignedWrap());
3110  }
3111  if (auto *ExactOp = dyn_cast<PossiblyExactOperator>(&I)) {
3112  Flags.setExact(ExactOp->isExact());
3113  }
3114  if (isVectorReductionOp(&I)) {
3115  Flags.setVectorReduction(true);
3116  LLVM_DEBUG(dbgs() << "Detected a reduction operation:" << I << "\n");
3117  }
3118 
3119  SDValue Op1 = getValue(I.getOperand(0));
3120  SDValue Op2 = getValue(I.getOperand(1));
3121  SDValue BinNodeValue = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(),
3122  Op1, Op2, Flags);
3123  setValue(&I, BinNodeValue);
3124 }
3125 
3126 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
3127  SDValue Op1 = getValue(I.getOperand(0));
3128  SDValue Op2 = getValue(I.getOperand(1));
3129 
3130  EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
3131  Op1.getValueType(), DAG.getDataLayout());
3132 
3133  // Coerce the shift amount to the right type if we can.
3134  if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
3135  unsigned ShiftSize = ShiftTy.getSizeInBits();
3136  unsigned Op2Size = Op2.getValueSizeInBits();
3137  SDLoc DL = getCurSDLoc();
3138 
3139  // If the operand is smaller than the shift count type, promote it.
3140  if (ShiftSize > Op2Size)
3141  Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
3142 
3143  // If the operand is larger than the shift count type but the shift
3144  // count type has enough bits to represent any shift value, truncate
3145  // it now. This is a common case and it exposes the truncate to
3146  // optimization early.
3147  else if (ShiftSize >= Log2_32_Ceil(Op2.getValueSizeInBits()))
3148  Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
3149  // Otherwise we'll need to temporarily settle for some other convenient
3150  // type. Type legalization will make adjustments once the shiftee is split.
3151  else
3152  Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
3153  }
3154 
3155  bool nuw = false;
3156  bool nsw = false;
3157  bool exact = false;
3158 
3159  if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
3160 
3161  if (const OverflowingBinaryOperator *OFBinOp =
3162  dyn_cast<const OverflowingBinaryOperator>(&I)) {
3163  nuw = OFBinOp->hasNoUnsignedWrap();
3164  nsw = OFBinOp->hasNoSignedWrap();
3165  }
3166  if (const PossiblyExactOperator *ExactOp =
3167  dyn_cast<const PossiblyExactOperator>(&I))
3168  exact = ExactOp->isExact();
3169  }
3170  SDNodeFlags Flags;
3171  Flags.setExact(exact);
3172  Flags.setNoSignedWrap(nsw);
3173  Flags.setNoUnsignedWrap(nuw);
3174  SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
3175  Flags);
3176  setValue(&I, Res);
3177 }
3178 
3179 void SelectionDAGBuilder::visitSDiv(const User &I) {
3180  SDValue Op1 = getValue(I.getOperand(0));
3181  SDValue Op2 = getValue(I.getOperand(1));
3182 
3183  SDNodeFlags Flags;
3184  Flags.setExact(isa<PossiblyExactOperator>(&I) &&
3185  cast<PossiblyExactOperator>(&I)->isExact());
3186  setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
3187  Op2, Flags));
3188 }
3189 
3190 void SelectionDAGBuilder::visitICmp(const User &I) {
3192  if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
3193  predicate = IC->getPredicate();
3194  else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
3195  predicate = ICmpInst::Predicate(IC->getPredicate());
3196  SDValue Op1 = getValue(I.getOperand(0));
3197  SDValue Op2 = getValue(I.getOperand(1));
3198  ISD::CondCode Opcode = getICmpCondCode(predicate);
3199 
3200  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3201  I.getType());
3202  setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
3203 }
3204 
3205 void SelectionDAGBuilder::visitFCmp(const User &I) {
3207  if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
3208  predicate = FC->getPredicate();
3209  else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
3210  predicate = FCmpInst::Predicate(FC->getPredicate());
3211  SDValue Op1 = getValue(I.getOperand(0));
3212  SDValue Op2 = getValue(I.getOperand(1));
3213 
3214  ISD::CondCode Condition = getFCmpCondCode(predicate);
3215  auto *FPMO = dyn_cast<FPMathOperator>(&I);
3216  if ((FPMO && FPMO->hasNoNaNs()) || TM.Options.NoNaNsFPMath)
3217  Condition = getFCmpCodeWithoutNaN(Condition);
3218 
3219  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3220  I.getType());
3221  setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
3222 }
3223 
3224 // Check if the condition of the select has one use or two users that are both
3225 // selects with the same condition.
3226 static bool hasOnlySelectUsers(const Value *Cond) {
3227  return llvm::all_of(Cond->users(), [](const Value *V) {
3228  return isa<SelectInst>(V);
3229  });
3230 }
3231 
3232 void SelectionDAGBuilder::visitSelect(const User &I) {
3235  ValueVTs);
3236  unsigned NumValues = ValueVTs.size();
3237  if (NumValues == 0) return;
3238 
3239  SmallVector<SDValue, 4> Values(NumValues);
3240  SDValue Cond = getValue(I.getOperand(0));
3241  SDValue LHSVal = getValue(I.getOperand(1));
3242  SDValue RHSVal = getValue(I.getOperand(2));
3243  auto BaseOps = {Cond};
3244  ISD::NodeType OpCode = Cond.getValueType().isVector() ?
3246 
3247  bool IsUnaryAbs = false;
3248 
3249  // Min/max matching is only viable if all output VTs are the same.
3250  if (is_splat(ValueVTs)) {
3251  EVT VT = ValueVTs[0];
3252  LLVMContext &Ctx = *DAG.getContext();
3253  auto &TLI = DAG.getTargetLoweringInfo();
3254 
3255  // We care about the legality of the operation after it has been type
3256  // legalized.
3257  while (TLI.getTypeAction(Ctx, VT) != TargetLoweringBase::TypeLegal &&
3258  VT != TLI.getTypeToTransformTo(Ctx, VT))
3259  VT = TLI.getTypeToTransformTo(Ctx, VT);
3260 
3261  // If the vselect is legal, assume we want to leave this as a vector setcc +
3262  // vselect. Otherwise, if this is going to be scalarized, we want to see if
3263  // min/max is legal on the scalar type.
3264  bool UseScalarMinMax = VT.isVector() &&
3265  !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT);
3266 
3267  Value *LHS, *RHS;
3268  auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
3270  switch (SPR.Flavor) {
3271  case SPF_UMAX: Opc = ISD::UMAX; break;
3272  case SPF_UMIN: Opc = ISD::UMIN; break;
3273  case SPF_SMAX: Opc = ISD::SMAX; break;
3274  case SPF_SMIN: Opc = ISD::SMIN; break;
3275  case SPF_FMINNUM:
3276  switch (SPR.NaNBehavior) {
3277  case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
3278  case SPNB_RETURNS_NAN: Opc = ISD::FMINIMUM; break;
3279  case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
3280  case SPNB_RETURNS_ANY: {
3281  if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT))
3282  Opc = ISD::FMINNUM;
3283  else if (TLI.isOperationLegalOrCustom(ISD::FMINIMUM, VT))
3284  Opc = ISD::FMINIMUM;
3285  else if (UseScalarMinMax)
3286  Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ?
3288  break;
3289  }
3290  }
3291  break;
3292  case SPF_FMAXNUM:
3293  switch (SPR.NaNBehavior) {
3294  case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
3295  case SPNB_RETURNS_NAN: Opc = ISD::FMAXIMUM; break;
3296  case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
3297  case SPNB_RETURNS_ANY:
3298 
3299  if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT))
3300  Opc = ISD::FMAXNUM;
3301  else if (TLI.isOperationLegalOrCustom(ISD::FMAXIMUM, VT))
3302  Opc = ISD::FMAXIMUM;
3303  else if (UseScalarMinMax)
3304  Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ?
3306  break;
3307  }
3308  break;
3309  case SPF_ABS:
3310  IsUnaryAbs = true;
3311  Opc = ISD::ABS;
3312  break;
3313  case SPF_NABS:
3314  // TODO: we need to produce sub(0, abs(X)).
3315  default: break;
3316  }
3317 
3318  if (!IsUnaryAbs && Opc != ISD::DELETED_NODE &&
3319  (TLI.isOperationLegalOrCustom(Opc, VT) ||
3320  (UseScalarMinMax &&
3321  TLI.isOperationLegalOrCustom(Opc, VT.getScalarType()))) &&
3322  // If the underlying comparison instruction is used by any other
3323  // instruction, the consumed instructions won't be destroyed, so it is
3324  // not profitable to convert to a min/max.
3325  hasOnlySelectUsers(cast<SelectInst>(I).getCondition())) {
3326  OpCode = Opc;
3327  LHSVal = getValue(LHS);
3328  RHSVal = getValue(RHS);
3329  BaseOps = {};
3330  }
3331 
3332  if (IsUnaryAbs) {
3333  OpCode = Opc;
3334  LHSVal = getValue(LHS);
3335  BaseOps = {};
3336  }
3337  }
3338 
3339  if (IsUnaryAbs) {
3340  for (unsigned i = 0; i != NumValues; ++i) {
3341  Values[i] =
3342  DAG.getNode(OpCode, getCurSDLoc(),
3343  LHSVal.getNode()->getValueType(LHSVal.getResNo() + i),
3344  SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
3345  }
3346  } else {
3347  for (unsigned i = 0; i != NumValues; ++i) {
3348  SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
3349  Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
3350  Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
3351  Values[i] = DAG.getNode(
3352  OpCode, getCurSDLoc(),
3353  LHSVal.getNode()->getValueType(LHSVal.getResNo() + i), Ops);
3354  }
3355  }
3356 
3357  setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3358  DAG.getVTList(ValueVTs), Values));
3359 }
3360 
3361 void SelectionDAGBuilder::visitTrunc(const User &I) {
3362  // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
3363  SDValue N = getValue(I.getOperand(0));
3364  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3365  I.getType());
3366  setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
3367 }
3368 
3369 void SelectionDAGBuilder::visitZExt(const User &I) {
3370  // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
3371  // ZExt also can't be a cast to bool for same reason. So, nothing much to do
3372  SDValue N = getValue(I.getOperand(0));
3373  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3374  I.getType());
3375  setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
3376 }
3377 
3378 void SelectionDAGBuilder::visitSExt(const User &I) {
3379  // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
3380  // SExt also can't be a cast to bool for same reason. So, nothing much to do
3381  SDValue N = getValue(I.getOperand(0));
3382  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3383  I.getType());
3384  setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
3385 }
3386 
3387 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
3388  // FPTrunc is never a no-op cast, no need to check
3389  SDValue N = getValue(I.getOperand(0));
3390  SDLoc dl = getCurSDLoc();
3391  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3392  EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3393  setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
3394  DAG.getTargetConstant(
3395  0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
3396 }
3397 
3398 void SelectionDAGBuilder::visitFPExt(const User &I) {
3399  // FPExt is never a no-op cast, no need to check
3400  SDValue N = getValue(I.getOperand(0));
3401  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3402  I.getType());
3403  setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
3404 }
3405 
3406 void SelectionDAGBuilder::visitFPToUI(const User &I) {
3407  // FPToUI is never a no-op cast, no need to check
3408  SDValue N = getValue(I.getOperand(0));
3409  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3410  I.getType());
3411  setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
3412 }
3413 
3414 void SelectionDAGBuilder::visitFPToSI(const User &I) {
3415  // FPToSI is never a no-op cast, no need to check
3416  SDValue N = getValue(I.getOperand(0));
3417  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3418  I.getType());
3419  setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
3420 }
3421 
3422 void SelectionDAGBuilder::visitUIToFP(const User &I) {
3423  // UIToFP is never a no-op cast, no need to check
3424  SDValue N = getValue(I.getOperand(0));
3425  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3426  I.getType());
3427  setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
3428 }
3429 
3430 void SelectionDAGBuilder::visitSIToFP(const User &I) {
3431  // SIToFP is never a no-op cast, no need to check
3432  SDValue N = getValue(I.getOperand(0));
3433  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3434  I.getType());
3435  setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
3436 }
3437 
3438 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
3439  // What to do depends on the size of the integer and the size of the pointer.
3440  // We can either truncate, zero extend, or no-op, accordingly.
3441  SDValue N = getValue(I.getOperand(0));
3442  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3443  I.getType());
3444  setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3445 }
3446 
3447 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
3448  // What to do depends on the size of the integer and the size of the pointer.
3449  // We can either truncate, zero extend, or no-op, accordingly.
3450  SDValue N = getValue(I.getOperand(0));
3451  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3452  I.getType());
3453  setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3454 }
3455 
3456 void SelectionDAGBuilder::visitBitCast(const User &I) {
3457  SDValue N = getValue(I.getOperand(0));
3458  SDLoc dl = getCurSDLoc();
3459  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3460  I.getType());
3461 
3462  // BitCast assures us that source and destination are the same size so this is
3463  // either a BITCAST or a no-op.
3464  if (DestVT != N.getValueType())
3465  setValue(&I, DAG.getNode(ISD::BITCAST, dl,
3466  DestVT, N)); // convert types.
3467  // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3468  // might fold any kind of constant expression to an integer constant and that
3469  // is not what we are looking for. Only recognize a bitcast of a genuine
3470  // constant integer as an opaque constant.
3471  else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3472  setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
3473  /*isOpaque*/true));
3474  else
3475  setValue(&I, N); // noop cast.
3476 }
3477 
3478 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3479  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3480  const Value *SV = I.getOperand(0);
3481  SDValue N = getValue(SV);
3482  EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3483 
3484  unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3485  unsigned DestAS = I.getType()->getPointerAddressSpace();
3486 
3487  if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3488  N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3489 
3490  setValue(&I, N);
3491 }
3492 
3493 void SelectionDAGBuilder::visitInsertElement(const User &I) {
3494  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3495  SDValue InVec = getValue(I.getOperand(0));
3496  SDValue InVal = getValue(I.getOperand(1));
3497  SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
3498  TLI.getVectorIdxTy(DAG.getDataLayout()));
3499  setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3500  TLI.getValueType(DAG.getDataLayout(), I.getType()),
3501  InVec, InVal, InIdx));
3502 }
3503 
3504 void SelectionDAGBuilder::visitExtractElement(const User &I) {
3505  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3506  SDValue InVec = getValue(I.getOperand(0));
3507  SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
3508  TLI.getVectorIdxTy(DAG.getDataLayout()));
3509  setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3510  TLI.getValueType(DAG.getDataLayout(), I.getType()),
3511  InVec, InIdx));
3512 }
3513 
3514 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3515  SDValue Src1 = getValue(I.getOperand(0));
3516  SDValue Src2 = getValue(I.getOperand(1));
3517  SDLoc DL = getCurSDLoc();
3518 
3520  ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3521  unsigned MaskNumElts = Mask.size();
3522 
3523  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3524  EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3525  EVT SrcVT = Src1.getValueType();
3526  unsigned SrcNumElts = SrcVT.getVectorNumElements();
3527 
3528  if (SrcNumElts == MaskNumElts) {
3529  setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, Mask));
3530  return;
3531  }
3532 
3533  // Normalize the shuffle vector since mask and vector length don't match.
3534  if (SrcNumElts < MaskNumElts) {
3535  // Mask is longer than the source vectors. We can use concatenate vector to
3536  // make the mask and vectors lengths match.
3537 
3538  if (MaskNumElts % SrcNumElts == 0) {
3539  // Mask length is a multiple of the source vector length.
3540  // Check if the shuffle is some kind of concatenation of the input
3541  // vectors.
3542  unsigned NumConcat = MaskNumElts / SrcNumElts;
3543  bool IsConcat = true;
3544  SmallVector<int, 8> ConcatSrcs(NumConcat, -1);
3545  for (unsigned i = 0; i != MaskNumElts; ++i) {
3546  int Idx = Mask[i];
3547  if (Idx < 0)
3548  continue;
3549  // Ensure the indices in each SrcVT sized piece are sequential and that
3550  // the same source is used for the whole piece.
3551  if ((Idx % SrcNumElts != (i % SrcNumElts)) ||
3552  (ConcatSrcs[i / SrcNumElts] >= 0 &&
3553  ConcatSrcs[i / SrcNumElts] != (int)(Idx / SrcNumElts))) {
3554  IsConcat = false;
3555  break;
3556  }
3557  // Remember which source this index came from.
3558  ConcatSrcs[i / SrcNumElts] = Idx / SrcNumElts;
3559  }
3560 
3561  // The shuffle is concatenating multiple vectors together. Just emit
3562  // a CONCAT_VECTORS operation.
3563  if (IsConcat) {
3564  SmallVector<SDValue, 8> ConcatOps;
3565  for (auto Src : ConcatSrcs) {
3566  if (Src < 0)
3567  ConcatOps.push_back(DAG.getUNDEF(SrcVT));
3568  else if (Src == 0)
3569  ConcatOps.push_back(Src1);
3570  else
3571  ConcatOps.push_back(Src2);
3572  }
3573  setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps));
3574  return;
3575  }
3576  }
3577 
3578  unsigned PaddedMaskNumElts = alignTo(MaskNumElts, SrcNumElts);
3579  unsigned NumConcat = PaddedMaskNumElts / SrcNumElts;
3580  EVT PaddedVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
3581  PaddedMaskNumElts);
3582 
3583  // Pad both vectors with undefs to make them the same length as the mask.
3584  SDValue UndefVal = DAG.getUNDEF(SrcVT);
3585 
3586  SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3587  SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3588  MOps1[0] = Src1;
3589  MOps2[0] = Src2;
3590 
3591  Src1 = Src1.isUndef()
3592  ? DAG.getUNDEF(PaddedVT)
3593  : DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1);
3594  Src2 = Src2.isUndef()
3595  ? DAG.getUNDEF(PaddedVT)
3596  : DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps2);
3597 
3598  // Readjust mask for new input vector length.
3599  SmallVector<int, 8> MappedOps(PaddedMaskNumElts, -1);
3600  for (unsigned i = 0; i != MaskNumElts; ++i) {
3601  int Idx = Mask[i];
3602  if (Idx >= (int)SrcNumElts)
3603  Idx -= SrcNumElts - PaddedMaskNumElts;
3604  MappedOps[i] = Idx;
3605  }
3606 
3607  SDValue Result = DAG.getVectorShuffle(PaddedVT, DL, Src1, Src2, MappedOps);
3608 
3609  // If the concatenated vector was padded, extract a subvector with the
3610  // correct number of elements.
3611  if (MaskNumElts != PaddedMaskNumElts)
3612  Result = DAG.getNode(
3613  ISD::EXTRACT_SUBVECTOR, DL, VT, Result,
3614  DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3615 
3616  setValue(&I, Result);
3617  return;
3618  }
3619 
3620  if (SrcNumElts > MaskNumElts) {
3621  // Analyze the access pattern of the vector to see if we can extract
3622  // two subvectors and do the shuffle.
3623  int StartIdx[2] = { -1, -1 }; // StartIdx to extract from
3624  bool CanExtract = true;
3625  for (int Idx : Mask) {
3626  unsigned Input = 0;
3627  if (Idx < 0)
3628  continue;
3629 
3630  if (Idx >= (int)SrcNumElts) {
3631  Input = 1;
3632  Idx -= SrcNumElts;
3633  }
3634 
3635  // If all the indices come from the same MaskNumElts sized portion of
3636  // the sources we can use extract. Also make sure the extract wouldn't
3637  // extract past the end of the source.
3638  int NewStartIdx = alignDown(Idx, MaskNumElts);
3639  if (NewStartIdx + MaskNumElts > SrcNumElts ||
3640  (StartIdx[Input] >= 0 && StartIdx[Input] != NewStartIdx))
3641  CanExtract = false;
3642  // Make sure we always update StartIdx as we use it to track if all
3643  // elements are undef.
3644  StartIdx[Input] = NewStartIdx;
3645  }
3646 
3647  if (StartIdx[0] < 0 && StartIdx[1] < 0) {
3648  setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3649  return;
3650  }
3651  if (CanExtract) {
3652  // Extract appropriate subvector and generate a vector shuffle
3653  for (unsigned Input = 0; Input < 2; ++Input) {
3654  SDValue &Src = Input == 0 ? Src1 : Src2;
3655  if (StartIdx[Input] < 0)
3656  Src = DAG.getUNDEF(VT);
3657  else {
3658  Src = DAG.getNode(
3659  ISD::EXTRACT_SUBVECTOR, DL, VT, Src,
3660  DAG.getConstant(StartIdx[Input], DL,
3661  TLI.getVectorIdxTy(DAG.getDataLayout())));
3662  }
3663  }
3664 
3665  // Calculate new mask.
3666  SmallVector<int, 8> MappedOps(Mask.begin(), Mask.end());
3667  for (int &Idx : MappedOps) {
3668  if (Idx >= (int)SrcNumElts)
3669  Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3670  else if (Idx >= 0)
3671  Idx -= StartIdx[0];
3672  }
3673 
3674  setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, MappedOps));
3675  return;
3676  }
3677  }
3678 
3679  // We can't use either concat vectors or extract subvectors so fall back to
3680  // replacing the shuffle with extract and build vector.
3681  // to insert and build vector.
3682  EVT EltVT = VT.getVectorElementType();
3683  EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
3685  for (int Idx : Mask) {
3686  SDValue Res;
3687 
3688  if (Idx < 0) {
3689  Res = DAG.getUNDEF(EltVT);
3690  } else {
3691  SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3692  if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3693 
3694  Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
3695  EltVT, Src, DAG.getConstant(Idx, DL, IdxVT));
3696  }
3697 
3698  Ops.push_back(Res);
3699  }
3700 
3701  setValue(&I, DAG.getBuildVector(VT, DL, Ops));
3702 }
3703 
3704 void SelectionDAGBuilder::visitInsertValue(const User &I) {
3705  ArrayRef<unsigned> Indices;
3706  if (const InsertValueInst *IV = dyn_cast<InsertValueInst>(&I))
3707  Indices = IV->getIndices();
3708  else
3709  Indices = cast<ConstantExpr>(&I)->getIndices();
3710 
3711  const Value *Op0 = I.getOperand(0);
3712  const Value *Op1 = I.getOperand(1);
3713  Type *AggTy = I.getType();
3714  Type *ValTy = Op1->getType();
3715  bool IntoUndef = isa<UndefValue>(Op0);
3716  bool FromUndef = isa<UndefValue>(Op1);
3717 
3718  unsigned LinearIndex = ComputeLinearIndex(AggTy, Indices);
3719 
3720  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3721  SmallVector<EVT, 4> AggValueVTs;
3722  ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
3723  SmallVector<EVT, 4> ValValueVTs;
3724  ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
3725 
3726  unsigned NumAggValues = AggValueVTs.size();
3727  unsigned NumValValues = ValValueVTs.size();
3728  SmallVector<SDValue, 4> Values(NumAggValues);
3729 
3730  // Ignore an insertvalue that produces an empty object
3731  if (!NumAggValues) {
3732  setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3733  return;
3734  }
3735 
3736  SDValue Agg = getValue(Op0);
3737  unsigned i = 0;
3738  // Copy the beginning value(s) from the original aggregate.
3739  for (; i != LinearIndex; ++i)
3740  Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3741  SDValue(Agg.getNode(), Agg.getResNo() + i);
3742  // Copy values from the inserted value(s).
3743  if (NumValValues) {
3744  SDValue Val = getValue(Op1);
3745  for (; i != LinearIndex + NumValValues; ++i)
3746  Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3747  SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3748  }
3749  // Copy remaining value(s) from the original aggregate.
3750  for (; i != NumAggValues; ++i)
3751  Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3752  SDValue(Agg.getNode(), Agg.getResNo() + i);
3753 
3754  setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3755  DAG.getVTList(AggValueVTs), Values));
3756 }
3757 
3758 void SelectionDAGBuilder::visitExtractValue(const User &I) {
3759  ArrayRef<unsigned> Indices;
3760  if (const ExtractValueInst *EV = dyn_cast<ExtractValueInst>(&I))
3761  Indices = EV->getIndices();
3762  else
3763  Indices = cast<ConstantExpr>(&I)->getIndices();
3764 
3765  const Value *Op0 = I.getOperand(0);
3766  Type *AggTy = Op0->getType();
3767  Type *ValTy = I.getType();
3768  bool OutOfUndef = isa<UndefValue>(Op0);
3769 
3770  unsigned LinearIndex = ComputeLinearIndex(AggTy, Indices);
3771 
3772  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3773  SmallVector<EVT, 4> ValValueVTs;
3774  ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
3775 
3776  unsigned NumValValues = ValValueVTs.size();
3777 
3778  // Ignore a extractvalue that produces an empty object
3779  if (!NumValValues) {
3780  setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3781  return;
3782  }
3783 
3784  SmallVector<SDValue, 4> Values(NumValValues);
3785 
3786  SDValue Agg = getValue(Op0);
3787  // Copy out the selected value(s).
3788  for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3789  Values[i - LinearIndex] =
3790  OutOfUndef ?
3791  DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3792  SDValue(Agg.getNode(), Agg.getResNo() + i);
3793 
3794  setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3795  DAG.getVTList(ValValueVTs), Values));
3796 }
3797 
3798 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3799  Value *Op0 = I.getOperand(0);
3800  // Note that the pointer operand may be a vector of pointers. Take the scalar
3801  // element which holds a pointer.
3802  unsigned AS = Op0->getType()->getScalarType()->getPointerAddressSpace();
3803  SDValue N = getValue(Op0);
3804  SDLoc dl = getCurSDLoc();
3805 
3806  // Normalize Vector GEP - all scalar operands should be converted to the
3807  // splat vector.
3808  unsigned VectorWidth = I.getType()->isVectorTy() ?
3809  cast<VectorType>(I.getType())->getVectorNumElements() : 0;
3810 
3811  if (VectorWidth && !N.getValueType().isVector()) {
3812  LLVMContext &Context = *DAG.getContext();
3813  EVT VT = EVT::getVectorVT(Context, N.getValueType(), VectorWidth);
3814  N = DAG.getSplatBuildVector(VT, dl, N);
3815  }
3816 
3817  for (gep_type_iterator GTI = gep_type_begin(&I), E = gep_type_end(&I);
3818  GTI != E; ++GTI) {
3819  const Value *Idx = GTI.getOperand();
3820  if (StructType *StTy = GTI.getStructTypeOrNull()) {
3821  unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3822  if (Field) {
3823  // N = N + Offset
3824  uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3825 
3826  // In an inbounds GEP with an offset that is nonnegative even when
3827  // interpreted as signed, assume there is no unsigned overflow.
3828  SDNodeFlags Flags;
3829  if (int64_t(Offset) >= 0 && cast<GEPOperator>(I).isInBounds())
3830  Flags.setNoUnsignedWrap(true);
3831 
3832  N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
3833  DAG.getConstant(Offset, dl, N.getValueType()), Flags);
3834  }
3835  } else {
3836  unsigned IdxSize = DAG.getDataLayout().getIndexSizeInBits(AS);
3837  MVT IdxTy = MVT::getIntegerVT(IdxSize);
3838  APInt ElementSize(IdxSize, DL->getTypeAllocSize(GTI.getIndexedType()));
3839 
3840  // If this is a scalar constant or a splat vector of constants,
3841  // handle it quickly.
3842  const auto *CI = dyn_cast<ConstantInt>(Idx);
3843  if (!CI && isa<ConstantDataVector>(Idx) &&
3844  cast<ConstantDataVector>(Idx)->getSplatValue())
3845  CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
3846 
3847  if (CI) {
3848  if (CI->isZero())
3849  continue;
3850  APInt Offs = ElementSize * CI->getValue().sextOrTrunc(IdxSize);
3851  LLVMContext &Context = *DAG.getContext();
3852  SDValue OffsVal = VectorWidth ?
3853  DAG.getConstant(Offs, dl, EVT::getVectorVT(Context, IdxTy, VectorWidth)) :
3854  DAG.getConstant(Offs, dl, IdxTy);
3855 
3856  // In an inbouds GEP with an offset that is nonnegative even when
3857  // interpreted as signed, assume there is no unsigned overflow.
3858  SDNodeFlags Flags;
3859  if (Offs.isNonNegative() && cast<GEPOperator>(I).isInBounds())
3860  Flags.setNoUnsignedWrap(true);
3861 
3862  N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal, Flags);
3863  continue;
3864  }
3865 
3866  // N = N + Idx * ElementSize;
3867  SDValue IdxN = getValue(Idx);
3868 
3869  if (!IdxN.getValueType().isVector() && VectorWidth) {
3870  EVT VT = EVT::getVectorVT(*Context, IdxN.getValueType(), VectorWidth);
3871  IdxN = DAG.getSplatBuildVector(VT, dl, IdxN);
3872  }
3873 
3874  // If the index is smaller or larger than intptr_t, truncate or extend
3875  // it.
3876  IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
3877 
3878  // If this is a multiply by a power of two, turn it into a shl
3879  // immediately. This is a very common case.
3880  if (ElementSize != 1) {
3881  if (ElementSize.isPowerOf2()) {
3882  unsigned Amt = ElementSize.logBase2();
3883  IdxN = DAG.getNode(ISD::SHL, dl,
3884  N.getValueType(), IdxN,
3885  DAG.getConstant(Amt, dl, IdxN.getValueType()));
3886  } else {
3887  SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
3888  IdxN = DAG.getNode(ISD::MUL, dl,
3889  N.getValueType(), IdxN, Scale);
3890  }
3891  }
3892 
3893  N = DAG.getNode(ISD::ADD, dl,
3894  N.getValueType(), N, IdxN);
3895  }
3896  }
3897 
3898  setValue(&I, N);
3899 }
3900 
3901 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3902  // If this is a fixed sized alloca in the entry block of the function,
3903  // allocate it statically on the stack.
3904  if (FuncInfo.StaticAllocaMap.count(&I))
3905  return; // getValue will auto-populate this.
3906 
3907  SDLoc dl = getCurSDLoc();
3908  Type *Ty = I.getAllocatedType();
3909  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3910  auto &DL = DAG.getDataLayout();
3911  uint64_t TySize = DL.getTypeAllocSize(Ty);
3912  unsigned Align =
3913  std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
3914 
3915  SDValue AllocSize = getValue(I.getArraySize());
3916 
3917  EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout(), DL.getAllocaAddrSpace());
3918  if (AllocSize.getValueType() != IntPtr)
3919  AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
3920 
3921  AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
3922  AllocSize,
3923  DAG.getConstant(TySize, dl, IntPtr));
3924 
3925  // Handle alignment. If the requested alignment is less than or equal to
3926  // the stack alignment, ignore it. If the size is greater than or equal to
3927  // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3928  unsigned StackAlign =
3930  if (Align <= StackAlign)
3931  Align = 0;
3932 
3933  // Round the size of the allocation up to the stack alignment size
3934  // by add SA-1 to the size. This doesn't overflow because we're computing
3935  // an address inside an alloca.
3936  SDNodeFlags Flags;
3937  Flags.setNoUnsignedWrap(true);
3938  AllocSize = DAG.getNode(ISD::ADD, dl, AllocSize.getValueType(), AllocSize,
3939  DAG.getConstant(StackAlign - 1, dl, IntPtr), Flags);
3940 
3941  // Mask out the low bits for alignment purposes.
3942  AllocSize =
3943  DAG.getNode(ISD::AND, dl, AllocSize.getValueType(), AllocSize,
3944  DAG.getConstant(~(uint64_t)(StackAlign - 1), dl, IntPtr));
3945 
3946  SDValue Ops[] = {getRoot(), AllocSize, DAG.getConstant(Align, dl, IntPtr)};
3947  SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3948  SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
3949  setValue(&I, DSA);
3950  DAG.setRoot(DSA.getValue(1));
3951 
3952  assert(FuncInfo.MF->getFrameInfo().hasVarSizedObjects());
3953 }
3954 
3955 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3956  if (I.isAtomic())
3957  return visitAtomicLoad(I);
3958 
3959  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3960  const Value *SV = I.getOperand(0);
3961  if (TLI.supportSwiftError()) {
3962  // Swifterror values can come from either a function parameter with
3963  // swifterror attribute or an alloca with swifterror attribute.
3964  if (const Argument *Arg = dyn_cast<Argument>(SV)) {
3965  if (Arg->hasSwiftErrorAttr())
3966  return visitLoadFromSwiftError(I);
3967  }
3968 
3969  if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(SV)) {
3970  if (Alloca->isSwiftError())
3971  return visitLoadFromSwiftError(I);
3972  }
3973  }
3974 
3975  SDValue Ptr = getValue(SV);
3976 
3977  Type *Ty = I.getType();
3978 
3979  bool isVolatile = I.isVolatile();
3980  bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3981  bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr;
3982  bool isDereferenceable = isDereferenceablePointer(SV, DAG.getDataLayout());
3983  unsigned Alignment = I.getAlignment();
3984 
3985  AAMDNodes AAInfo;
3986  I.getAAMetadata(AAInfo);
3987  const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3988 
3991  ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
3992  unsigned NumValues = ValueVTs.size();
3993  if (NumValues == 0)
3994  return;
3995 
3996  SDValue Root;
3997  bool ConstantMemory = false;
3998  if (isVolatile || NumValues > MaxParallelChains)
3999  // Serialize volatile loads with other side effects.
4000  Root = getRoot();
4001  else if (AA &&
4002  AA->pointsToConstantMemory(MemoryLocation(
4003  SV,
4005  AAInfo))) {
4006  // Do not serialize (non-volatile) loads of constant memory with anything.
4007  Root = DAG.getEntryNode();
4008  ConstantMemory = true;
4009  } else {
4010  // Do not serialize non-volatile loads against each other.
4011  Root = DAG.getRoot();
4012  }
4013 
4014  SDLoc dl = getCurSDLoc();
4015 
4016  if (isVolatile)
4017  Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
4018 
4019  // An aggregate load cannot wrap around the address space, so offsets to its
4020  // parts don't wrap either.
4021  SDNodeFlags Flags;
4022  Flags.setNoUnsignedWrap(true);
4023 
4024  SmallVector<SDValue, 4> Values(NumValues);
4025  SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
4026  EVT PtrVT = Ptr.getValueType();
4027  unsigned ChainI = 0;
4028  for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
4029  // Serializing loads here may result in excessive register pressure, and
4030  // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
4031  // could recover a bit by hoisting nodes upward in the chain by recognizing
4032  // they are side-effect free or do not alias. The optimizer should really
4033  // avoid this case by converting large object/array copies to llvm.memcpy
4034  // (MaxParallelChains should always remain as failsafe).
4035  if (ChainI == MaxParallelChains) {
4036  assert(PendingLoads.empty() && "PendingLoads must be serialized first");
4037  SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4038  makeArrayRef(Chains.data(), ChainI));
4039  Root = Chain;
4040  ChainI = 0;
4041  }
4042  SDValue A = DAG.getNode(ISD::ADD, dl,
4043  PtrVT, Ptr,
4044  DAG.getConstant(Offsets[i], dl, PtrVT),
4045  Flags);
4046  auto MMOFlags = MachineMemOperand::MONone;
4047  if (isVolatile)
4048  MMOFlags |= MachineMemOperand::MOVolatile;
4049  if (isNonTemporal)
4051  if (isInvariant)
4052  MMOFlags |= MachineMemOperand::MOInvariant;
4053  if (isDereferenceable)
4055  MMOFlags |= TLI.getMMOFlags(I);
4056 
4057  SDValue L = DAG.getLoad(ValueVTs[i], dl, Root, A,
4058  MachinePointerInfo(SV, Offsets[i]), Alignment,
4059  MMOFlags, AAInfo, Ranges);
4060 
4061  Values[i] = L;
4062  Chains[ChainI] = L.getValue(1);
4063  }
4064 
4065  if (!ConstantMemory) {
4066  SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4067  makeArrayRef(Chains.data(), ChainI));
4068  if (isVolatile)
4069  DAG.setRoot(Chain);
4070  else
4071  PendingLoads.push_back(Chain);
4072  }
4073 
4074  setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
4075  DAG.getVTList(ValueVTs), Values));
4076 }
4077 
4078 void SelectionDAGBuilder::visitStoreToSwiftError(const StoreInst &I) {
4080  "call visitStoreToSwiftError when backend supports swifterror");
4081 
4084  const Value *SrcV = I.getOperand(0);
4086  SrcV->getType(), ValueVTs, &Offsets);
4087  assert(ValueVTs.size() == 1 && Offsets[0] == 0 &&
4088  "expect a single EVT for swifterror");
4089 
4090  SDValue Src = getValue(SrcV);
4091  // Create a virtual register, then update the virtual register.
4092  unsigned VReg; bool CreatedVReg;
4093  std::tie(VReg, CreatedVReg) = FuncInfo.getOrCreateSwiftErrorVRegDefAt(&I);
4094  // Chain, DL, Reg, N or Chain, DL, Reg, N, Glue
4095  // Chain can be getRoot or getControlRoot.
4096  SDValue CopyNode = DAG.getCopyToReg(getRoot(), getCurSDLoc(), VReg,
4097  SDValue(Src.getNode(), Src.getResNo()));
4098  DAG.setRoot(CopyNode);
4099  if (CreatedVReg)
4100  FuncInfo.setCurrentSwiftErrorVReg(FuncInfo.MBB, I.getOperand(1), VReg);
4101 }
4102 
4103 void SelectionDAGBuilder::visitLoadFromSwiftError(const LoadInst &I) {
4105  "call visitLoadFromSwiftError when backend supports swifterror");
4106 
4107  assert(!I.isVolatile() &&
4108  I.getMetadata(LLVMContext::MD_nontemporal) == nullptr &&
4110  "Support volatile, non temporal, invariant for load_from_swift_error");
4111 
4112  const Value *SV = I.getOperand(0);
4113  Type *Ty = I.getType();
4114  AAMDNodes AAInfo;
4115  I.getAAMetadata(AAInfo);
4116  assert(
4117  (!AA ||
4118  !AA->pointsToConstantMemory(MemoryLocation(
4120  AAInfo))) &&
4121  "load_from_swift_error should not be constant memory");
4122 
4126  ValueVTs, &Offsets);
4127  assert(ValueVTs.size() == 1 && Offsets[0] == 0 &&
4128  "expect a single EVT for swifterror");
4129 
4130  // Chain, DL, Reg, VT, Glue or Chain, DL, Reg, VT
4131  SDValue L = DAG.getCopyFromReg(
4132  getRoot(), getCurSDLoc(),
4133  FuncInfo.getOrCreateSwiftErrorVRegUseAt(&I, FuncInfo.MBB, SV).first,
4134  ValueVTs[0]);
4135 
4136  setValue(&I, L);
4137 }
4138 
4139 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
4140  if (I.isAtomic())
4141  return visitAtomicStore(I);
4142 
4143  const Value *SrcV = I.getOperand(0);
4144  const Value *PtrV = I.getOperand(1);
4145 
4146  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4147  if (TLI.supportSwiftError()) {
4148  // Swifterror values can come from either a function parameter with
4149  // swifterror attribute or an alloca with swifterror attribute.
4150  if (const Argument *Arg = dyn_cast<Argument>(PtrV)) {
4151  if (Arg->hasSwiftErrorAttr())
4152  return visitStoreToSwiftError(I);
4153  }
4154 
4155  if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(PtrV)) {
4156  if (Alloca->isSwiftError())
4157  return visitStoreToSwiftError(I);
4158  }
4159  }
4160 
4164  SrcV->getType(), ValueVTs, &Offsets);
4165  unsigned NumValues = ValueVTs.size();
4166  if (NumValues == 0)
4167  return;
4168 
4169  // Get the lowered operands. Note that we do this after
4170  // checking if NumResults is zero, because with zero results
4171  // the operands won't have values in the map.
4172  SDValue Src = getValue(SrcV);
4173  SDValue Ptr = getValue(PtrV);
4174 
4175  SDValue Root = getRoot();
4176  SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
4177  SDLoc dl = getCurSDLoc();
4178  EVT PtrVT = Ptr.getValueType();
4179  unsigned Alignment = I.getAlignment();
4180  AAMDNodes AAInfo;
4181  I.getAAMetadata(AAInfo);
4182 
4183  auto MMOFlags = MachineMemOperand::MONone;
4184  if (I.isVolatile())
4185  MMOFlags |= MachineMemOperand::MOVolatile;
4186  if (I.getMetadata(LLVMContext::MD_nontemporal) != nullptr)
4188  MMOFlags |= TLI.getMMOFlags(I);
4189 
4190  // An aggregate load cannot wrap around the address space, so offsets to its
4191  // parts don't wrap either.
4192  SDNodeFlags Flags;
4193  Flags.setNoUnsignedWrap(true);
4194 
4195  unsigned ChainI = 0;
4196  for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
4197  // See visitLoad comments.
4198  if (ChainI == MaxParallelChains) {
4199  SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4200  makeArrayRef(Chains.data(), ChainI));
4201  Root = Chain;
4202  ChainI = 0;
4203  }
4204  SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
4205  DAG.getConstant(Offsets[i], dl, PtrVT), Flags);
4206  SDValue St = DAG.getStore(
4207  Root, dl, SDValue(Src.getNode(), Src.getResNo() + i), Add,
4208  MachinePointerInfo(PtrV, Offsets[i]), Alignment, MMOFlags, AAInfo);
4209  Chains[ChainI] = St;
4210  }
4211 
4212  SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4213  makeArrayRef(Chains.data(), ChainI));
4214  DAG.setRoot(StoreNode);
4215 }
4216 
4217 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I,
4218  bool IsCompressing) {
4219  SDLoc sdl = getCurSDLoc();
4220 
4221  auto getMaskedStoreOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
4222  unsigned& Alignment) {
4223  // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
4224  Src0 = I.getArgOperand(0);
4225  Ptr = I.getArgOperand(1);
4226  Alignment = cast<ConstantInt>(I.getArgOperand(2))->getZExtValue();
4227  Mask = I.getArgOperand(3);
4228  };
4229  auto getCompressingStoreOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
4230  unsigned& Alignment) {
4231  // llvm.masked.compressstore.*(Src0, Ptr, Mask)
4232  Src0 = I.getArgOperand(0);
4233  Ptr = I.getArgOperand(1);
4234  Mask = I.getArgOperand(2);
4235  Alignment = 0;
4236  };
4237 
4238  Value *PtrOperand, *MaskOperand, *Src0Operand;
4239  unsigned Alignment;
4240  if (IsCompressing)
4241  getCompressingStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4242  else
4243  getMaskedStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4244 
4245  SDValue Ptr = getValue(PtrOperand);
4246  SDValue Src0 = getValue(Src0Operand);
4247  SDValue Mask = getValue(MaskOperand);
4248 
4249  EVT VT = Src0.getValueType();
4250  if (!Alignment)
4251  Alignment = DAG.getEVTAlignment(VT);
4252 
4253  AAMDNodes AAInfo;
4254  I.getAAMetadata(AAInfo);
4255 
4256  MachineMemOperand *MMO =
4257  DAG.getMachineFunction().
4260  Alignment, AAInfo);
4261  SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
4262  MMO, false /* Truncating */,
4263  IsCompressing);
4264  DAG.setRoot(StoreNode);
4265  setValue(&I, StoreNode);
4266 }
4267 
4268 // Get a uniform base for the Gather/Scatter intrinsic.
4269 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
4270 // We try to represent it as a base pointer + vector of indices.
4271 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
4272 // The first operand of the GEP may be a single pointer or a vector of pointers
4273 // Example:
4274 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
4275 // or
4276 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
4277 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
4278 //
4279 // When the first GEP operand is a single pointer - it is the uniform base we
4280 // are looking for. If first operand of the GEP is a splat vector - we
4281 // extract the splat value and use it as a uniform base.
4282 // In all other cases the function returns 'false'.
4283 static bool getUniformBase(const Value* &Ptr, SDValue& Base, SDValue& Index,
4284  SDValue &Scale, SelectionDAGBuilder* SDB) {
4285  SelectionDAG& DAG = SDB->DAG;
4286  LLVMContext &Context = *DAG.getContext();
4287 
4288  assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type");
4290  if (!GEP)
4291  return false;
4292 
4293  const Value *GEPPtr = GEP->getPointerOperand();
4294  if (!GEPPtr->getType()->isVectorTy())
4295  Ptr = GEPPtr;
4296  else if (!(Ptr = getSplatValue(GEPPtr)))
4297  return false;
4298 
4299  unsigned FinalIndex = GEP->getNumOperands() - 1;
4300  Value *IndexVal = GEP->getOperand(FinalIndex);
4301 
4302  // Ensure all the other indices are 0.
4303  for (unsigned i = 1; i < FinalIndex; ++i) {
4304  auto *C = dyn_cast<ConstantInt>(GEP->getOperand(i));
4305  if (!C || !C->isZero())
4306  return false;
4307  }
4308 
4309  // The operands of the GEP may be defined in another basic block.
4310  // In this case we'll not find nodes for the operands.
4311  if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
4312  return false;
4313 
4314  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4315  const DataLayout &DL = DAG.getDataLayout();
4316  Scale = DAG.getTargetConstant(DL.getTypeAllocSize(GEP->getResultElementType()),
4317  SDB->getCurSDLoc(), TLI.getPointerTy(DL));
4318  Base = SDB->getValue(Ptr);
4319  Index = SDB->getValue(IndexVal);
4320 
4321  if (!Index.getValueType().isVector()) {
4322  unsigned GEPWidth = GEP->getType()->getVectorNumElements();
4323  EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
4324  Index = DAG.getSplatBuildVector(VT, SDLoc(Index), Index);
4325  }
4326  return true;
4327 }
4328 
4329 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
4330  SDLoc sdl = getCurSDLoc();
4331 
4332  // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
4333  const Value *Ptr = I.getArgOperand(1);
4334  SDValue Src0 = getValue(I.getArgOperand(0));
4335  SDValue Mask = getValue(I.getArgOperand(3));
4336  EVT VT = Src0.getValueType();
4337  unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
4338  if (!Alignment)
4339  Alignment = DAG.getEVTAlignment(VT);
4340  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4341 
4342  AAMDNodes AAInfo;
4343  I.getAAMetadata(AAInfo);
4344 
4345  SDValue Base;
4346  SDValue Index;
4347  SDValue Scale;
4348  const Value *BasePtr = Ptr;
4349  bool UniformBase = getUniformBase(BasePtr, Base, Index, Scale, this);
4350 
4351  const Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
4354  MachineMemOperand::MOStore, VT.getStoreSize(),
4355  Alignment, AAInfo);
4356  if (!UniformBase) {
4357  Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4358  Index = getValue(Ptr);
4359  Scale = DAG.getTargetConstant(1, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4360  }
4361  SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index, Scale };
4362  SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
4363  Ops, MMO);
4364  DAG.setRoot(Scatter);
4365  setValue(&I, Scatter);
4366 }
4367 
4368 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) {
4369  SDLoc sdl = getCurSDLoc();
4370 
4371  auto getMaskedLoadOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
4372  unsigned& Alignment) {
4373  // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
4374  Ptr = I.getArgOperand(0);
4375  Alignment = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4376  Mask = I.getArgOperand(2);
4377  Src0 = I.getArgOperand(3);
4378  };
4379  auto getExpandingLoadOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
4380  unsigned& Alignment) {
4381  // @llvm.masked.expandload.*(Ptr, Mask, Src0)
4382  Ptr = I.getArgOperand(0);
4383  Alignment = 0;
4384  Mask = I.getArgOperand(1);
4385  Src0 = I.getArgOperand(2);
4386  };
4387 
4388  Value *PtrOperand, *MaskOperand, *Src0Operand;
4389  unsigned Alignment;
4390  if (IsExpanding)
4391  getExpandingLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4392  else
4393  getMaskedLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4394 
4395  SDValue Ptr = getValue(PtrOperand);
4396  SDValue Src0 = getValue(Src0Operand);
4397  SDValue Mask = getValue(MaskOperand);
4398 
4399  EVT VT = Src0.getValueType();
4400  if (!Alignment)
4401  Alignment = DAG.getEVTAlignment(VT);
4402 
4403  AAMDNodes AAInfo;
4404  I.getAAMetadata(AAInfo);
4405  const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
4406 
4407  // Do not serialize masked loads of constant memory with anything.
4408  bool AddToChain =
4409  !AA || !AA->pointsToConstantMemory(MemoryLocation(
4410  PtrOperand,
4413  AAInfo));
4414  SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode();
4415 
4416  MachineMemOperand *MMO =
4417  DAG.getMachineFunction().
4420  Alignment, AAInfo, Ranges);
4421 
4422  SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
4423  ISD::NON_EXTLOAD, IsExpanding);
4424  if (AddToChain)
4425  PendingLoads.push_back(Load.getValue(1));
4426  setValue(&I, Load);
4427 }
4428 
4429 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
4430  SDLoc sdl = getCurSDLoc();
4431 
4432  // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
4433  const Value *Ptr = I.getArgOperand(0);
4434  SDValue Src0 = getValue(I.getArgOperand(3));
4435  SDValue Mask = getValue(I.getArgOperand(2));
4436 
4437  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4438  EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4439  unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
4440  if (!Alignment)
4441  Alignment = DAG.getEVTAlignment(VT);
4442 
4443  AAMDNodes AAInfo;
4444  I.getAAMetadata(AAInfo);
4445  const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
4446 
4447  SDValue Root = DAG.getRoot();
4448  SDValue Base;
4449  SDValue Index;
4450  SDValue Scale;
4451  const Value *BasePtr = Ptr;
4452  bool UniformBase = getUniformBase(BasePtr, Base, Index, Scale, this);
4453  bool ConstantMemory = false;
4454  if (UniformBase && AA &&
4455  AA->pointsToConstantMemory(
4456  MemoryLocation(BasePtr,
4459  AAInfo))) {
4460  // Do not serialize (non-volatile) loads of constant memory with anything.
4461  Root = DAG.getEntryNode();
4462  ConstantMemory = true;
4463  }
4464 
4465  MachineMemOperand *MMO =
4466  DAG.getMachineFunction().
4467  getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
4469  Alignment, AAInfo, Ranges);
4470 
4471  if (!UniformBase) {
4472  Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4473  Index = getValue(Ptr);
4474  Scale = DAG.getTargetConstant(1, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4475  }
4476  SDValue Ops[] = { Root, Src0, Mask, Base, Index, Scale };
4477  SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
4478  Ops, MMO);
4479 
4480  SDValue OutChain = Gather.getValue(1);
4481  if (!ConstantMemory)
4482  PendingLoads.push_back(OutChain);
4483  setValue(&I, Gather);
4484 }
4485 
4486 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
4487  SDLoc dl = getCurSDLoc();
4488  AtomicOrdering SuccessOrdering = I.getSuccessOrdering();
4489  AtomicOrdering FailureOrdering = I.getFailureOrdering();
4490  SyncScope::ID SSID = I.getSyncScopeID();
4491 
4492  SDValue InChain = getRoot();
4493 
4494  MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
4495  SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
4496 
4497  auto Alignment = DAG.getEVTAlignment(MemVT);
4498 
4500  if (I.isVolatile())
4502  Flags |= DAG.getTargetLoweringInfo().getMMOFlags(I);
4503 
4504  MachineFunction &MF = DAG.getMachineFunction();
4505  MachineMemOperand *MMO =
4507  Flags, MemVT.getStoreSize(), Alignment,
4508  AAMDNodes(), nullptr, SSID, SuccessOrdering,
4509  FailureOrdering);
4510 
4512  dl, MemVT, VTs, InChain,
4513  getValue(I.getPointerOperand()),
4514  getValue(I.getCompareOperand()),
4515  getValue(I.getNewValOperand()), MMO);
4516 
4517  SDValue OutChain = L.getValue(2);
4518 
4519  setValue(&I, L);
4520  DAG.setRoot(OutChain);
4521 }
4522 
4523 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
4524  SDLoc dl = getCurSDLoc();
4525  ISD::NodeType NT;
4526  switch (I.getOperation()) {
4527  default: llvm_unreachable("Unknown atomicrmw operation");
4528  case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
4529  case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
4530  case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
4531  case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
4532  case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
4533  case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
4534  case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
4535  case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
4536  case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
4537  case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
4538  case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
4539  case AtomicRMWInst::FAdd: NT = ISD::ATOMIC_LOAD_FADD; break;
4540  case AtomicRMWInst::FSub: NT = ISD::ATOMIC_LOAD_FSUB; break;
4541  }
4542  AtomicOrdering Ordering = I.getOrdering();
4543  SyncScope::ID SSID = I.getSyncScopeID();
4544 
4545  SDValue InChain = getRoot();
4546 
4547  auto MemVT = getValue(I.getValOperand()).getSimpleValueType();
4548  auto Alignment = DAG.getEVTAlignment(MemVT);
4549 
4551  if (I.isVolatile())
4553  Flags |= DAG.getTargetLoweringInfo().getMMOFlags(I);
4554 
4555  MachineFunction &MF = DAG.getMachineFunction();
4556  MachineMemOperand *MMO =
4558  MemVT.getStoreSize(), Alignment, AAMDNodes(),
4559  nullptr, SSID, Ordering);
4560 
4561  SDValue L =
4562  DAG.getAtomic(NT, dl, MemVT, InChain,
4563  getValue(I.getPointerOperand()), getValue(I.getValOperand()),
4564  MMO);
4565 
4566  SDValue OutChain = L.getValue(1);
4567 
4568  setValue(&I, L);
4569  DAG.setRoot(OutChain);
4570 }
4571 
4572 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
4573  SDLoc dl = getCurSDLoc();
4574  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4575  SDValue Ops[3];
4576  Ops[0] = getRoot();
4577  Ops[1] = DAG.getConstant((unsigned)I.getOrdering(), dl,
4578  TLI.getFenceOperandTy(DAG.getDataLayout()));
4579  Ops[2] = DAG.getConstant(I.getSyncScopeID(), dl,
4580  TLI.getFenceOperandTy(DAG.getDataLayout()));
4581  DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
4582 }
4583 
4584 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
4585  SDLoc dl = getCurSDLoc();
4586  AtomicOrdering Order = I.getOrdering();
4587  SyncScope::ID SSID = I.getSyncScopeID();
4588 
4589  SDValue InChain = getRoot();
4590 
4591  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4592  EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4593 
4594  if (!TLI.supportsUnalignedAtomics() &&
4595  I.getAlignment() < VT.getStoreSize())
4596  report_fatal_error("Cannot generate unaligned atomic load");
4597 
4598  auto Flags = MachineMemOperand::MOLoad;
4599  if (I.isVolatile())
4601  if (I.getMetadata(LLVMContext::MD_invariant_load) != nullptr)
4605 
4606  Flags |= TLI.getMMOFlags(I);
4607 
4608  MachineMemOperand *MMO =
4609  DAG.getMachineFunction().
4611  Flags, VT.getStoreSize(),
4612  I.getAlignment() ? I.getAlignment() :
4613  DAG.getEVTAlignment(VT),
4614  AAMDNodes(), nullptr, SSID, Order);
4615 
4616  InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
4617  SDValue L =
4618  DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
4619  getValue(I.getPointerOperand()), MMO);
4620 
4621  SDValue OutChain = L.getValue(1);
4622 
4623  setValue(&I, L);
4624  DAG.setRoot(OutChain);
4625 }
4626 
4627 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
4628  SDLoc dl = getCurSDLoc();
4629 
4630  AtomicOrdering Ordering = I.getOrdering();
4631  SyncScope::ID SSID = I.getSyncScopeID();
4632 
4633  SDValue InChain = getRoot();
4634 
4635  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4636  EVT VT =
4638 
4639  if (I.getAlignment() < VT.getStoreSize())
4640  report_fatal_error("Cannot generate unaligned atomic store");
4641 
4642  auto Flags = MachineMemOperand::MOStore;
4643  if (I.isVolatile())
4645  Flags |= TLI.getMMOFlags(I);
4646 
4647  MachineFunction &MF = DAG.getMachineFunction();
4648  MachineMemOperand *MMO =
4650  VT.getStoreSize(), I.getAlignment(), AAMDNodes(),
4651  nullptr, SSID, Ordering);
4652  SDValue OutChain =
4653  DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT, InChain,
4654  getValue(I.getPointerOperand()), getValue(I.getValueOperand()),
4655  MMO);
4656 
4657 
4658  DAG.setRoot(OutChain);
4659 }
4660 
4661 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
4662 /// node.
4663 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
4664  unsigned Intrinsic) {
4665  // Ignore the callsite's attributes. A specific call site may be marked with
4666  // readnone, but the lowering code will expect the chain based on the
4667  // definition.
4668  const Function *F = I.getCalledFunction();
4669  bool HasChain = !F->doesNotAccessMemory();
4670  bool OnlyLoad = HasChain && F->onlyReadsMemory();
4671 
4672  // Build the operand list.
4674  if (HasChain) { // If this intrinsic has side-effects, chainify it.
4675  if (OnlyLoad) {
4676  // We don't need to serialize loads against other loads.
4677  Ops.push_back(DAG.getRoot());
4678  } else {
4679  Ops.push_back(getRoot());
4680  }
4681  }
4682 
4683  // Info is set by getTgtMemInstrinsic
4684  TargetLowering::IntrinsicInfo Info;
4685  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4686  bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I,
4687  DAG.getMachineFunction(),
4688  Intrinsic);
4689 
4690  // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
4691  if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
4692  Info.opc == ISD::INTRINSIC_W_CHAIN)
4693  Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
4694  TLI.getPointerTy(DAG.getDataLayout())));
4695 
4696  // Add all operands of the call to the operand list.
4697  for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
4698  SDValue Op = getValue(I.getArgOperand(i));
4699  Ops.push_back(Op);
4700  }
4701 
4703  ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
4704 
4705  if (HasChain)
4706  ValueVTs.push_back(MVT::Other);
4707 
4708  SDVTList VTs = DAG.getVTList(ValueVTs);
4709 
4710  // Create the node.
4711  SDValue Result;
4712  if (IsTgtIntrinsic) {
4713  // This is target intrinsic that touches memory
4714  Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(), VTs,
4715  Ops, Info.memVT,
4716  MachinePointerInfo(Info.ptrVal, Info.offset), Info.align,
4717  Info.flags, Info.size);
4718  } else if (!HasChain) {
4719  Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
4720  } else if (!I.getType()->isVoidTy()) {
4721  Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
4722  } else {
4723  Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
4724  }
4725 
4726  if (HasChain) {
4727  SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
4728  if (OnlyLoad)
4729  PendingLoads.push_back(Chain);
4730  else
4731  DAG.setRoot(Chain);
4732  }
4733 
4734  if (!I.getType()->isVoidTy()) {
4735  if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
4736  EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
4737  Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
4738  } else
4739  Result = lowerRangeToAssertZExt(DAG, I, Result);
4740 
4741  setValue(&I, Result);
4742  }
4743 }
4744 
4745 /// GetSignificand - Get the significand and build it into a floating-point
4746 /// number with exponent of 1:
4747 ///
4748 /// Op = (Op & 0x007fffff) | 0x3f800000;
4749 ///
4750 /// where Op is the hexadecimal representation of floating point value.
4752  SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
4753  DAG.getConstant(0x007fffff, dl, MVT::i32));
4754  SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
4755  DAG.getConstant(0x3f800000, dl, MVT::i32));
4756  return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
4757 }
4758 
4759 /// GetExponent - Get the exponent:
4760 ///
4761 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
4762 ///
4763 /// where Op is the hexadecimal representation of floating point value.
4765  const TargetLowering &TLI, const SDLoc &dl) {
4766  SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
4767  DAG.getConstant(0x7f800000, dl, MVT::i32));
4768  SDValue t1 = DAG.getNode(
4769  ISD::SRL, dl, MVT::i32, t0,
4770  DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
4771  SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
4772  DAG.getConstant(127, dl, MVT::i32));
4773  return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
4774 }
4775 
4776 /// getF32Constant - Get 32-bit floating point constant.
4777 static SDValue getF32Constant(SelectionDAG &DAG, unsigned Flt,
4778  const SDLoc &dl) {
4779  return DAG.getConstantFP(APFloat(APFloat::IEEEsingle(), APInt(32, Flt)), dl,
4780  MVT::f32);
4781 }
4782 
4784  SelectionDAG &DAG) {
4785  // TODO: What fast-math-flags should be set on the floating-point nodes?
4786 
4787  // IntegerPartOfX = ((int32_t)(t0);
4788  SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4789 
4790  // FractionalPartOfX = t0 - (float)IntegerPartOfX;
4791  SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4792  SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4793 
4794  // IntegerPartOfX <<= 23;
4795  IntegerPartOfX = DAG.getNode(
4796  ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4798  DAG.getDataLayout())));
4799 
4800  SDValue TwoToFractionalPartOfX;
4801  if (LimitFloatPrecision <= 6) {
4802  // For floating-point precision of 6:
4803  //
4804  // TwoToFractionalPartOfX =
4805  // 0.997535578f +
4806  // (0.735607626f + 0.252464424f * x) * x;
4807  //
4808  // error 0.0144103317, which is 6 bits
4809  SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4810  getF32Constant(DAG, 0x3e814304, dl));
4811  SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4812  getF32Constant(DAG, 0x3f3c50c8, dl));
4813  SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4814  TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4815  getF32Constant(DAG, 0x3f7f5e7e, dl));
4816  } else if (LimitFloatPrecision <= 12) {
4817  // For floating-point precision of 12:
4818  //
4819  // TwoToFractionalPartOfX =
4820  // 0.999892986f +
4821  // (0.696457318f +
4822  // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4823  //
4824  // error 0.000107046256, which is 13 to 14 bits
4825  SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4826  getF32Constant(DAG, 0x3da235e3, dl));
4827  SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4828  getF32Constant(DAG, 0x3e65b8f3, dl));
4829  SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4830  SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4831  getF32Constant(DAG, 0x3f324b07, dl));
4832  SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4833  TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4834  getF32Constant(DAG, 0x3f7ff8fd, dl));
4835  } else { // LimitFloatPrecision <= 18
4836  // For floating-point precision of 18:
4837  //
4838  // TwoToFractionalPartOfX =
4839  // 0.999999982f +
4840  // (0.693148872f +
4841  // (0.240227044f +
4842  // (0.554906021e-1f +
4843  // (0.961591928e-2f +
4844  // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4845  // error 2.47208000*10^(-7), which is better than 18 bits
4846  SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4847  getF32Constant(DAG, 0x3924b03e, dl));
4848  SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4849  getF32Constant(DAG, 0x3ab24b87, dl));
4850  SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4851  SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4852  getF32Constant(DAG, 0x3c1d8c17, dl));
4853  SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4854  SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4855  getF32Constant(DAG, 0x3d634a1d, dl));
4856  SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4857  SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4858  getF32Constant(DAG, 0x3e75fe14, dl));
4859  SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4860  SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4861  getF32Constant(DAG, 0x3f317234, dl));
4862  SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4863  TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4864  getF32Constant(DAG, 0x3f800000, dl));
4865  }
4866 
4867  // Add the exponent into the result in integer domain.
4868  SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
4869  return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4870  DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
4871 }
4872 
4873 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
4874 /// limited-precision mode.
4875 static SDValue expandExp(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4876  const TargetLowering &TLI) {
4877  if (Op.getValueType() == MVT::f32 &&
4878  LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4879 
4880  // Put the exponent in the right bit position for later addition to the
4881  // final result:
4882  //
4883  // #define LOG2OFe 1.4426950f
4884  // t0 = Op * LOG2OFe
4885 
4886  // TODO: What fast-math-flags should be set here?
4887  SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4888  getF32Constant(DAG, 0x3fb8aa3b, dl));
4889  return getLimitedPrecisionExp2(t0, dl, DAG);
4890  }
4891 
4892  // No special expansion.
4893  return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
4894 }
4895 
4896 /// expandLog - Lower a log intrinsic. Handles the special sequences for
4897 /// limited-precision mode.
4898 static SDValue expandLog(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4899  const TargetLowering &TLI) {
4900  // TODO: What fast-math-flags should be set on the floating-point nodes?
4901 
4902  if (Op.getValueType() == MVT::f32 &&
4903  LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4904  SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4905 
4906  // Scale the exponent by log(2) [0.69314718f].
4907  SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4908  SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4909  getF32Constant(DAG, 0x3f317218, dl));
4910 
4911  // Get the significand and build it into a floating-point number with
4912  // exponent of 1.
4913  SDValue X = GetSignificand(DAG, Op1, dl);
4914 
4915  SDValue LogOfMantissa;
4916  if (LimitFloatPrecision <= 6) {
4917  // For floating-point precision of 6:
4918  //
4919  // LogofMantissa =
4920  // -1.1609546f +
4921  // (1.4034025f - 0.23903021f * x) * x;
4922  //
4923  // error 0.0034276066, which is better than 8 bits
4924  SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4925  getF32Constant(DAG, 0xbe74c456, dl));
4926  SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4927  getF32Constant(DAG, 0x3fb3a2b1, dl));
4928  SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4929  LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4930  getF32Constant(DAG, 0x3f949a29, dl));
4931  } else if (LimitFloatPrecision <= 12) {
4932  // For floating-point precision of 12:
4933  //
4934  // LogOfMantissa =
4935  // -1.7417939f +
4936  // (2.8212026f +
4937  // (-1.4699568f +
4938  // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4939  //
4940  // error 0.000061011436, which is 14 bits
4941  SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4942  getF32Constant(DAG, 0xbd67b6d6, dl));
4943  SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4944  getF32Constant(DAG, 0x3ee4f4b8, dl));
4945  SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4946  SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4947  getF32Constant(DAG, 0x3fbc278b, dl));
4948  SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4949  SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4950  getF32Constant(DAG, 0x40348e95, dl));
4951  SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4952  LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4953  getF32Constant(DAG, 0x3fdef31a, dl));
4954  } else { // LimitFloatPrecision <= 18
4955  // For floating-point precision of 18:
4956  //
4957  // LogOfMantissa =
4958  // -2.1072184f +
4959  // (4.2372794f +
4960  // (-3.7029485f +
4961  // (2.2781945f +
4962  // (-0.87823314f +
4963  // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4964  //
4965  // error 0.0000023660568, which is better than 18 bits
4966  SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4967  getF32Constant(DAG, 0xbc91e5ac, dl));
4968  SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4969  getF32Constant(DAG, 0x3e4350aa, dl));
4970  SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4971  SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4972  getF32Constant(DAG, 0x3f60d3e3, dl));
4973  SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4974  SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4975  getF32Constant(DAG, 0x4011cdf0, dl));
4976  SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4977  SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4978  getF32Constant(DAG, 0x406cfd1c, dl));
4979  SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4980  SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4981  getF32Constant(DAG, 0x408797cb, dl));
4982  SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4983  LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4984  getF32Constant(DAG, 0x4006dcab, dl));
4985  }
4986 
4987  return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4988  }
4989 
4990  // No special expansion.
4991  return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4992 }
4993 
4994 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4995 /// limited-precision mode.
4996 static SDValue expandLog2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4997  const TargetLowering &TLI) {
4998  // TODO: What fast-math-flags should be set on the floating-point nodes?
4999 
5000  if (Op.getValueType() == MVT::f32 &&
5001  LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
5002  SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
5003 
5004  // Get the exponent.
5005  SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
5006 
5007  // Get the significand and build it into a floating-point number with
5008  // exponent of 1.
5009  SDValue X = GetSignificand(DAG, Op1, dl);
5010 
5011  // Different possible minimax approximations of significand in
5012  // floating-point for various degrees of accuracy over [1,2].
5013  SDValue Log2ofMantissa;
5014  if (LimitFloatPrecision <= 6) {
5015  // For floating-point precision of 6:
5016  //
5017  // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
5018  //
5019  // error 0.0049451742, which is more than 7 bits
5020  SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5021  getF32Constant(DAG, 0xbeb08fe0, dl));
5022  SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5023  getF32Constant(DAG, 0x40019463, dl));
5024  SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5025  Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5026  getF32Constant(DAG, 0x3fd6633d, dl));
5027  } else if (LimitFloatPrecision <= 12) {
5028  // For floating-point precision of 12:
5029  //
5030  // Log2ofMantissa =
5031  // -2.51285454f +
5032  // (4.07009056f +
5033  // (-2.12067489f +
5034  // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
5035  //
5036  // error 0.0000876136000, which is better than 13 bits
5037  SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5038  getF32Constant(DAG, 0xbda7262e, dl));
5039  SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5040  getF32Constant(DAG, 0x3f25280b, dl));
5041  SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5042  SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5043  getF32Constant(DAG, 0x4007b923, dl));
5044  SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5045  SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5046  getF32Constant(DAG, 0x40823e2f, dl));
5047  SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5048  Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
5049  getF32Constant(DAG, 0x4020d29c, dl));
5050  } else { // LimitFloatPrecision <= 18
5051  // For floating-point precision of 18:
5052  //
5053  // Log2ofMantissa =
5054  // -3.0400495f +
5055  // (6.1129976f +
5056  // (-5.3420409f +
5057  // (3.2865683f +
5058  // (-1.2669343f +
5059  // (0.27515199f -
5060  // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
5061  //
5062  // error 0.0000018516, which is better than 18 bits
5063  SDValue t0 = DAG.getNode(