LLVM  9.0.0svn
SystemZRegisterInfo.cpp
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1 //===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SystemZRegisterInfo.h"
10 #include "SystemZInstrInfo.h"
11 #include "SystemZSubtarget.h"
13 #include "llvm/ADT/SmallSet.h"
18 
19 using namespace llvm;
20 
21 #define GET_REGINFO_TARGET_DESC
22 #include "SystemZGenRegisterInfo.inc"
23 
25  : SystemZGenRegisterInfo(SystemZ::R14D) {}
26 
27 // Given that MO is a GRX32 operand, return either GR32 or GRH32 if MO
28 // somehow belongs in it. Otherwise, return GRX32.
30  const VirtRegMap *VRM,
31  const MachineRegisterInfo *MRI) {
32  const TargetRegisterClass *RC = MRI->getRegClass(MO.getReg());
33 
34  if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
35  MO.getSubReg() == SystemZ::subreg_l32 ||
36  MO.getSubReg() == SystemZ::subreg_hl32)
37  return &SystemZ::GR32BitRegClass;
38  if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) ||
39  MO.getSubReg() == SystemZ::subreg_h32 ||
40  MO.getSubReg() == SystemZ::subreg_hh32)
41  return &SystemZ::GRH32BitRegClass;
42 
43  if (VRM && VRM->hasPhys(MO.getReg())) {
44  unsigned PhysReg = VRM->getPhys(MO.getReg());
45  if (SystemZ::GR32BitRegClass.contains(PhysReg))
46  return &SystemZ::GR32BitRegClass;
47  assert (SystemZ::GRH32BitRegClass.contains(PhysReg) &&
48  "Phys reg not in GR32 or GRH32?");
49  return &SystemZ::GRH32BitRegClass;
50  }
51 
52  assert (RC == &SystemZ::GRX32BitRegClass);
53  return RC;
54 }
55 
56 // Pass the registers of RC as hints while making sure that if any of these
57 // registers are copy hints (and therefore already in Hints), hint them
58 // first.
59 static void addHints(ArrayRef<MCPhysReg> Order,
61  const TargetRegisterClass *RC,
62  const MachineRegisterInfo *MRI) {
63  SmallSet<unsigned, 4> CopyHints;
64  CopyHints.insert(Hints.begin(), Hints.end());
65  Hints.clear();
66  for (MCPhysReg Reg : Order)
67  if (CopyHints.count(Reg) &&
68  RC->contains(Reg) && !MRI->isReserved(Reg))
69  Hints.push_back(Reg);
70  for (MCPhysReg Reg : Order)
71  if (!CopyHints.count(Reg) &&
72  RC->contains(Reg) && !MRI->isReserved(Reg))
73  Hints.push_back(Reg);
74 }
75 
76 bool
78  ArrayRef<MCPhysReg> Order,
80  const MachineFunction &MF,
81  const VirtRegMap *VRM,
82  const LiveRegMatrix *Matrix) const {
83  const MachineRegisterInfo *MRI = &MF.getRegInfo();
85 
86  bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
87  VirtReg, Order, Hints, MF, VRM, Matrix);
88 
89  if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) {
90  SmallVector<unsigned, 8> Worklist;
91  SmallSet<unsigned, 4> DoneRegs;
92  Worklist.push_back(VirtReg);
93  while (Worklist.size()) {
94  unsigned Reg = Worklist.pop_back_val();
95  if (!DoneRegs.insert(Reg).second)
96  continue;
97 
98  for (auto &Use : MRI->use_instructions(Reg)) {
99  // For LOCRMux, see if the other operand is already a high or low
100  // register, and in that case give the correpsonding hints for
101  // VirtReg. LOCR instructions need both operands in either high or
102  // low parts.
103  if (Use.getOpcode() == SystemZ::LOCRMux) {
104  MachineOperand &TrueMO = Use.getOperand(1);
105  MachineOperand &FalseMO = Use.getOperand(2);
106  const TargetRegisterClass *RC =
107  TRI->getCommonSubClass(getRC32(FalseMO, VRM, MRI),
108  getRC32(TrueMO, VRM, MRI));
109  if (RC && RC != &SystemZ::GRX32BitRegClass) {
110  addHints(Order, Hints, RC, MRI);
111  // Return true to make these hints the only regs available to
112  // RA. This may mean extra spilling but since the alternative is
113  // a jump sequence expansion of the LOCRMux, it is preferred.
114  return true;
115  }
116 
117  // Add the other operand of the LOCRMux to the worklist.
118  unsigned OtherReg =
119  (TrueMO.getReg() == Reg ? FalseMO.getReg() : TrueMO.getReg());
120  if (MRI->getRegClass(OtherReg) == &SystemZ::GRX32BitRegClass)
121  Worklist.push_back(OtherReg);
122  } // end LOCRMux
123  else if (Use.getOpcode() == SystemZ::CHIMux ||
124  Use.getOpcode() == SystemZ::CFIMux) {
125  if (Use.getOperand(1).getImm() == 0) {
126  bool OnlyLMuxes = true;
127  for (MachineInstr &DefMI : MRI->def_instructions(VirtReg))
128  if (DefMI.getOpcode() != SystemZ::LMux)
129  OnlyLMuxes = false;
130  if (OnlyLMuxes) {
131  addHints(Order, Hints, &SystemZ::GR32BitRegClass, MRI);
132  // Return false to make these hints preferred but not obligatory.
133  return false;
134  }
135  }
136  } // end CHIMux / CFIMux
137  }
138  }
139  }
140 
141  return BaseImplRetVal;
142 }
143 
144 const MCPhysReg *
146  const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
148  return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList
149  : CSR_SystemZ_AllRegs_SaveList;
152  Attribute::SwiftError))
153  return CSR_SystemZ_SwiftError_SaveList;
154  return CSR_SystemZ_SaveList;
155 }
156 
157 const uint32_t *
159  CallingConv::ID CC) const {
160  const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
161  if (CC == CallingConv::AnyReg)
162  return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask
163  : CSR_SystemZ_AllRegs_RegMask;
166  Attribute::SwiftError))
167  return CSR_SystemZ_SwiftError_RegMask;
168  return CSR_SystemZ_RegMask;
169 }
170 
171 BitVector
173  BitVector Reserved(getNumRegs());
174  const SystemZFrameLowering *TFI = getFrameLowering(MF);
175 
176  if (TFI->hasFP(MF)) {
177  // R11D is the frame pointer. Reserve all aliases.
178  Reserved.set(SystemZ::R11D);
179  Reserved.set(SystemZ::R11L);
180  Reserved.set(SystemZ::R11H);
181  Reserved.set(SystemZ::R10Q);
182  }
183 
184  // R15D is the stack pointer. Reserve all aliases.
185  Reserved.set(SystemZ::R15D);
186  Reserved.set(SystemZ::R15L);
187  Reserved.set(SystemZ::R15H);
188  Reserved.set(SystemZ::R14Q);
189 
190  // A0 and A1 hold the thread pointer.
191  Reserved.set(SystemZ::A0);
192  Reserved.set(SystemZ::A1);
193 
194  return Reserved;
195 }
196 
197 void
199  int SPAdj, unsigned FIOperandNum,
200  RegScavenger *RS) const {
201  assert(SPAdj == 0 && "Outgoing arguments should be part of the frame");
202 
203  MachineBasicBlock &MBB = *MI->getParent();
204  MachineFunction &MF = *MBB.getParent();
205  auto *TII =
206  static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
207  const SystemZFrameLowering *TFI = getFrameLowering(MF);
208  DebugLoc DL = MI->getDebugLoc();
209 
210  // Decompose the frame index into a base and offset.
211  int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
212  unsigned BasePtr;
213  int64_t Offset = (TFI->getFrameIndexReference(MF, FrameIndex, BasePtr) +
214  MI->getOperand(FIOperandNum + 1).getImm());
215 
216  // Special handling of dbg_value instructions.
217  if (MI->isDebugValue()) {
218  MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
219  MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
220  return;
221  }
222 
223  // See if the offset is in range, or if an equivalent instruction that
224  // accepts the offset exists.
225  unsigned Opcode = MI->getOpcode();
226  unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
227  if (OpcodeForOffset) {
228  if (OpcodeForOffset == SystemZ::LE &&
230  // If LE is ok for offset, use LDE instead on z13.
231  OpcodeForOffset = SystemZ::LDE32;
232  }
233  MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
234  }
235  else {
236  // Create an anchor point that is in range. Start at 0xffff so that
237  // can use LLILH to load the immediate.
238  int64_t OldOffset = Offset;
239  int64_t Mask = 0xffff;
240  do {
241  Offset = OldOffset & Mask;
242  OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
243  Mask >>= 1;
244  assert(Mask && "One offset must be OK");
245  } while (!OpcodeForOffset);
246 
247  unsigned ScratchReg =
248  MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);
249  int64_t HighOffset = OldOffset - Offset;
250 
251  if (MI->getDesc().TSFlags & SystemZII::HasIndex
252  && MI->getOperand(FIOperandNum + 2).getReg() == 0) {
253  // Load the offset into the scratch register and use it as an index.
254  // The scratch register then dies here.
255  TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
256  MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
257  MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
258  false, false, true);
259  } else {
260  // Load the anchor address into a scratch register.
261  unsigned LAOpcode = TII->getOpcodeForOffset(SystemZ::LA, HighOffset);
262  if (LAOpcode)
263  BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
264  .addReg(BasePtr).addImm(HighOffset).addReg(0);
265  else {
266  // Load the high offset into the scratch register and use it as
267  // an index.
268  TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
269  BuildMI(MBB, MI, DL, TII->get(SystemZ::AGR),ScratchReg)
270  .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
271  }
272 
273  // Use the scratch register as the base. It then dies here.
274  MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
275  false, false, true);
276  }
277  }
278  MI->setDesc(TII->get(OpcodeForOffset));
279  MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
280 }
281 
283  const TargetRegisterClass *SrcRC,
284  unsigned SubReg,
285  const TargetRegisterClass *DstRC,
286  unsigned DstSubReg,
287  const TargetRegisterClass *NewRC,
288  LiveIntervals &LIS) const {
289  assert (MI->isCopy() && "Only expecting COPY instructions");
290 
291  // Coalesce anything which is not a COPY involving a subreg to/from GR128.
292  if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) &&
293  (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64)))
294  return true;
295 
296  // Allow coalescing of a GR128 subreg COPY only if the live ranges are small
297  // and local to one MBB with not too much interferring registers. Otherwise
298  // regalloc may run out of registers.
299 
300  unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0);
301  unsigned GR128Reg = MI->getOperand(WideOpNo).getReg();
302  unsigned GRNarReg = MI->getOperand((WideOpNo == 1) ? 0 : 1).getReg();
303  LiveInterval &IntGR128 = LIS.getInterval(GR128Reg);
304  LiveInterval &IntGRNar = LIS.getInterval(GRNarReg);
305 
306  // Check that the two virtual registers are local to MBB.
307  MachineBasicBlock *MBB = MI->getParent();
308  MachineInstr *FirstMI_GR128 =
309  LIS.getInstructionFromIndex(IntGR128.beginIndex());
310  MachineInstr *FirstMI_GRNar =
311  LIS.getInstructionFromIndex(IntGRNar.beginIndex());
312  MachineInstr *LastMI_GR128 = LIS.getInstructionFromIndex(IntGR128.endIndex());
313  MachineInstr *LastMI_GRNar = LIS.getInstructionFromIndex(IntGRNar.endIndex());
314  if ((!FirstMI_GR128 || FirstMI_GR128->getParent() != MBB) ||
315  (!FirstMI_GRNar || FirstMI_GRNar->getParent() != MBB) ||
316  (!LastMI_GR128 || LastMI_GR128->getParent() != MBB) ||
317  (!LastMI_GRNar || LastMI_GRNar->getParent() != MBB))
318  return false;
319 
320  MachineBasicBlock::iterator MII = nullptr, MEE = nullptr;
321  if (WideOpNo == 1) {
322  MII = FirstMI_GR128;
323  MEE = LastMI_GRNar;
324  } else {
325  MII = FirstMI_GRNar;
326  MEE = LastMI_GR128;
327  }
328 
329  // Check if coalescing seems safe by finding the set of clobbered physreg
330  // pairs in the region.
331  BitVector PhysClobbered(getNumRegs());
332  MEE++;
333  for (; MII != MEE; ++MII) {
334  for (const MachineOperand &MO : MII->operands())
335  if (MO.isReg() && isPhysicalRegister(MO.getReg())) {
336  for (MCSuperRegIterator SI(MO.getReg(), this, true/*IncludeSelf*/);
337  SI.isValid(); ++SI)
338  if (NewRC->contains(*SI)) {
339  PhysClobbered.set(*SI);
340  break;
341  }
342  }
343  }
344 
345  // Demand an arbitrary margin of free regs.
346  unsigned const DemandedFreeGR128 = 3;
347  if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128))
348  return false;
349 
350  return true;
351 }
352 
353 unsigned
355  const SystemZFrameLowering *TFI = getFrameLowering(MF);
356  return TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D;
357 }
358 
359 const TargetRegisterClass *
361  if (RC == &SystemZ::CCRRegClass)
362  return &SystemZ::GR32BitRegClass;
363  return RC;
364 }
365 
virtual bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of &#39;hint&#39; registers that the register allocator should try first when allocating a physica...
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
BitVector & set()
Definition: BitVector.h:397
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned getNumRegs() const
Return the number of registers in this class.
BitVector getReservedRegs(const MachineFunction &MF) const override
virtual int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const
getFrameIndexReference - This method should return the base register and offset used to reference a f...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void push_back(const T &Elt)
Definition: SmallVector.h:211
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:637
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
unsigned getSubReg() const
virtual const TargetLowering * getTargetLowering() const
static void addHints(ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const TargetRegisterClass *RC, const MachineRegisterInfo *MRI)
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
return AArch64::GPR64RegClass contains(Reg)
Live Register Matrix
bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
MCSuperRegIterator enumerates all super-registers of Reg.
const HexagonInstrInfo * TII
A Use represents the edge between a Value definition and its users.
Definition: Use.h:55
unsigned SubReg
unsigned getFrameRegister(const MachineFunction &MF) const override
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
virtual const TargetInstrInfo * getInstrInfo() const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
SlotIndex endIndex() const
endNumber - return the maximum point of the range of the whole, exclusive.
Definition: LiveInterval.h:379
unsigned const MachineRegisterInfo * MRI
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:180
bool isCopy() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:52
static const TargetRegisterClass * getRC32(MachineOperand &MO, const VirtRegMap *VRM, const MachineRegisterInfo *MRI)
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:172
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:374
LiveInterval & getInterval(unsigned Reg)
const Function & getFunction() const
Return the LLVM function that this machine code represents.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool hasPhys(unsigned virtReg) const
returns true if the specified virtual register is mapped to a physical register
Definition: VirtRegMap.h:94
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:100
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SlotIndex beginIndex() const
beginIndex - Return the lowest numbered slot covered.
Definition: LiveInterval.h:372
iterator_range< def_instr_iterator > def_instructions(unsigned Reg) const
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
IRTranslator LLVM IR MI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164