LLVM  9.0.0svn
SystemZTargetMachine.cpp
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1 //===-- SystemZTargetMachine.cpp - Define TargetMachine for SystemZ -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SystemZTargetMachine.h"
11 #include "SystemZ.h"
15 #include "llvm/ADT/Optional.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringRef.h"
20 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/Support/CodeGen.h"
27 #include "llvm/Transforms/Scalar.h"
28 #include <string>
29 
30 using namespace llvm;
31 
32 extern "C" void LLVMInitializeSystemZTarget() {
33  // Register the target.
35 }
36 
37 // Determine whether we use the vector ABI.
38 static bool UsesVectorABI(StringRef CPU, StringRef FS) {
39  // We use the vector ABI whenever the vector facility is avaiable.
40  // This is the case by default if CPU is z13 or later, and can be
41  // overridden via "[+-]vector" feature string elements.
42  bool VectorABI = true;
43  if (CPU.empty() || CPU == "generic" ||
44  CPU == "z10" || CPU == "z196" || CPU == "zEC12")
45  VectorABI = false;
46 
48  FS.split(Features, ',', -1, false /* KeepEmpty */);
49  for (auto &Feature : Features) {
50  if (Feature == "vector" || Feature == "+vector")
51  VectorABI = true;
52  if (Feature == "-vector")
53  VectorABI = false;
54  }
55 
56  return VectorABI;
57 }
58 
59 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
60  StringRef FS) {
61  bool VectorABI = UsesVectorABI(CPU, FS);
62  std::string Ret;
63 
64  // Big endian.
65  Ret += "E";
66 
67  // Data mangling.
69 
70  // Make sure that global data has at least 16 bits of alignment by
71  // default, so that we can refer to it using LARL. We don't have any
72  // special requirements for stack variables though.
73  Ret += "-i1:8:16-i8:8:16";
74 
75  // 64-bit integers are naturally aligned.
76  Ret += "-i64:64";
77 
78  // 128-bit floats are aligned only to 64 bits.
79  Ret += "-f128:64";
80 
81  // When using the vector ABI, 128-bit vectors are also aligned to 64 bits.
82  if (VectorABI)
83  Ret += "-v128:64";
84 
85  // We prefer 16 bits of aligned for all globals; see above.
86  Ret += "-a:8:16";
87 
88  // Integer registers are 32 or 64 bits.
89  Ret += "-n32:64";
90 
91  return Ret;
92 }
93 
95  // Static code is suitable for use in a dynamic executable; there is no
96  // separate DynamicNoPIC model.
97  if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
98  return Reloc::Static;
99  return *RM;
100 }
101 
102 // For SystemZ we define the models as follows:
103 //
104 // Small: BRASL can call any function and will use a stub if necessary.
105 // Locally-binding symbols will always be in range of LARL.
106 //
107 // Medium: BRASL can call any function and will use a stub if necessary.
108 // GOT slots and locally-defined text will always be in range
109 // of LARL, but other symbols might not be.
110 //
111 // Large: Equivalent to Medium for now.
112 //
113 // Kernel: Equivalent to Medium for now.
114 //
115 // This means that any PIC module smaller than 4GB meets the
116 // requirements of Small, so Small seems like the best default there.
117 //
118 // All symbols bind locally in a non-PIC module, so the choice is less
119 // obvious. There are two cases:
120 //
121 // - When creating an executable, PLTs and copy relocations allow
122 // us to treat external symbols as part of the executable.
123 // Any executable smaller than 4GB meets the requirements of Small,
124 // so that seems like the best default.
125 //
126 // - When creating JIT code, stubs will be in range of BRASL if the
127 // image is less than 4GB in size. GOT entries will likewise be
128 // in range of LARL. However, the JIT environment has no equivalent
129 // of copy relocs, so locally-binding data symbols might not be in
130 // the range of LARL. We need the Medium model in that case.
131 static CodeModel::Model
133  bool JIT) {
134  if (CM) {
135  if (*CM == CodeModel::Tiny)
136  report_fatal_error("Target does not support the tiny CodeModel", false);
137  if (*CM == CodeModel::Kernel)
138  report_fatal_error("Target does not support the kernel CodeModel", false);
139  return *CM;
140  }
141  if (JIT)
143  return CodeModel::Small;
144 }
145 
147  StringRef CPU, StringRef FS,
148  const TargetOptions &Options,
151  CodeGenOpt::Level OL, bool JIT)
153  T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options,
156  OL),
158  Subtarget(TT, CPU, FS, *this) {
159  initAsmInfo();
160 }
161 
163 
164 namespace {
165 
166 /// SystemZ Code Generator Pass Configuration Options.
167 class SystemZPassConfig : public TargetPassConfig {
168 public:
169  SystemZPassConfig(SystemZTargetMachine &TM, PassManagerBase &PM)
170  : TargetPassConfig(TM, PM) {}
171 
172  SystemZTargetMachine &getSystemZTargetMachine() const {
173  return getTM<SystemZTargetMachine>();
174  }
175 
177  createPostMachineScheduler(MachineSchedContext *C) const override {
178  return new ScheduleDAGMI(C,
179  llvm::make_unique<SystemZPostRASchedStrategy>(C),
180  /*RemoveKillFlags=*/true);
181  }
182 
183  void addIRPasses() override;
184  bool addInstSelector() override;
185  bool addILPOpts() override;
186  void addPostRewrite() override;
187  void addPreSched2() override;
188  void addPreEmitPass() override;
189 };
190 
191 } // end anonymous namespace
192 
193 void SystemZPassConfig::addIRPasses() {
194  if (getOptLevel() != CodeGenOpt::None) {
195  addPass(createSystemZTDCPass());
196  addPass(createLoopDataPrefetchPass());
197  }
198 
200 }
201 
202 bool SystemZPassConfig::addInstSelector() {
203  addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel()));
204 
205  if (getOptLevel() != CodeGenOpt::None)
206  addPass(createSystemZLDCleanupPass(getSystemZTargetMachine()));
207 
208  return false;
209 }
210 
211 bool SystemZPassConfig::addILPOpts() {
212  addPass(&EarlyIfConverterID);
213  return true;
214 }
215 
216 void SystemZPassConfig::addPostRewrite() {
217  addPass(createSystemZPostRewritePass(getSystemZTargetMachine()));
218 }
219 
220 void SystemZPassConfig::addPreSched2() {
221  // PostRewrite needs to be run at -O0 also (in which case addPostRewrite()
222  // is not called).
223  if (getOptLevel() == CodeGenOpt::None)
224  addPass(createSystemZPostRewritePass(getSystemZTargetMachine()));
225 
226  addPass(createSystemZExpandPseudoPass(getSystemZTargetMachine()));
227 
228  if (getOptLevel() != CodeGenOpt::None)
229  addPass(&IfConverterID);
230 }
231 
232 void SystemZPassConfig::addPreEmitPass() {
233  // Do instruction shortening before compare elimination because some
234  // vector instructions will be shortened into opcodes that compare
235  // elimination recognizes.
236  if (getOptLevel() != CodeGenOpt::None)
237  addPass(createSystemZShortenInstPass(getSystemZTargetMachine()), false);
238 
239  // We eliminate comparisons here rather than earlier because some
240  // transformations can change the set of available CC values and we
241  // generally want those transformations to have priority. This is
242  // especially true in the commonest case where the result of the comparison
243  // is used by a single in-range branch instruction, since we will then
244  // be able to fuse the compare and the branch instead.
245  //
246  // For example, two-address NILF can sometimes be converted into
247  // three-address RISBLG. NILF produces a CC value that indicates whether
248  // the low word is zero, but RISBLG does not modify CC at all. On the
249  // other hand, 64-bit ANDs like NILL can sometimes be converted to RISBG.
250  // The CC value produced by NILL isn't useful for our purposes, but the
251  // value produced by RISBG can be used for any comparison with zero
252  // (not just equality). So there are some transformations that lose
253  // CC values (while still being worthwhile) and others that happen to make
254  // the CC result more useful than it was originally.
255  //
256  // Another reason is that we only want to use BRANCH ON COUNT in cases
257  // where we know that the count register is not going to be spilled.
258  //
259  // Doing it so late makes it more likely that a register will be reused
260  // between the comparison and the branch, but it isn't clear whether
261  // preventing that would be a win or not.
262  if (getOptLevel() != CodeGenOpt::None)
263  addPass(createSystemZElimComparePass(getSystemZTargetMachine()), false);
264  addPass(createSystemZLongBranchPass(getSystemZTargetMachine()));
265 
266  // Do final scheduling after all other optimizations, to get an
267  // optimal input for the decoder (branch relaxation must happen
268  // after block placement).
269  if (getOptLevel() != CodeGenOpt::None)
270  addPass(&PostMachineSchedulerID);
271 }
272 
274  return new SystemZPassConfig(*this, PM);
275 }
276 
279  return TargetTransformInfo(SystemZTTIImpl(this, F));
280 }
uint64_t CallInst * C
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
F(f)
std::enable_if<!std::is_array< T >::value, std::unique_ptr< T > >::type make_unique(Args &&... args)
Constructs a new T() with the given args and returns a unique_ptr<T> which owns the object...
Definition: STLExtras.h:1437
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:156
FunctionPass * createLoopDataPrefetchPass()
FunctionPass * createSystemZTDCPass()
FunctionPass * createSystemZISelDag(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
static std::string computeDataLayout(const Triple &TT, StringRef CPU, StringRef FS)
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
Target-Independent Code Generator Pass Configuration Options.
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
FunctionPass * createSystemZShortenInstPass(SystemZTargetMachine &TM)
static CodeModel::Model getEffectiveSystemZCodeModel(Optional< CodeModel::Model > CM, Reloc::Model RM, bool JIT)
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
static bool UsesVectorABI(StringRef CPU, StringRef FS)
FunctionPass * createSystemZPostRewritePass(SystemZTargetMachine &TM)
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
FunctionPass * createSystemZExpandPseudoPass(SystemZTargetMachine &TM)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:696
FunctionPass * createSystemZLongBranchPass(SystemZTargetMachine &TM)
void LLVMInitializeSystemZTarget()
Target - Wrapper for Target specific information.
Target & getTheSystemZTarget()
A ScheduleDAG for scheduling lists of MachineInstr.
bool hasValue() const
Definition: Optional.h:259
FunctionPass * createSystemZLDCleanupPass(SystemZTargetMachine &TM)
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
FunctionPass * createSystemZElimComparePass(SystemZTargetMachine &TM)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
This pass exposes codegen information to IR-level passes.