LLVM  9.0.0svn
TargetTransformInfo.cpp
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1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
11 #include "llvm/IR/CallSite.h"
12 #include "llvm/IR/DataLayout.h"
13 #include "llvm/IR/Instruction.h"
14 #include "llvm/IR/Instructions.h"
15 #include "llvm/IR/IntrinsicInst.h"
16 #include "llvm/IR/Module.h"
17 #include "llvm/IR/Operator.h"
18 #include "llvm/IR/PatternMatch.h"
21 #include "llvm/Analysis/CFG.h"
23 #include <utility>
24 
25 using namespace llvm;
26 using namespace PatternMatch;
27 
28 #define DEBUG_TYPE "tti"
29 
30 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
31  cl::Hidden,
32  cl::desc("Recognize reduction patterns."));
33 
34 namespace {
35 /// No-op implementation of the TTI interface using the utility base
36 /// classes.
37 ///
38 /// This is used when no target specific information is available.
39 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
40  explicit NoTTIImpl(const DataLayout &DL)
41  : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
42 };
43 }
44 
46  // If the loop has irreducible control flow, it can not be converted to
47  // Hardware loop.
48  LoopBlocksRPO RPOT(L);
49  RPOT.perform(&LI);
50  if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
51  return false;
52  return true;
53 }
54 
56  LoopInfo &LI, DominatorTree &DT,
57  bool ForceNestedLoop,
58  bool ForceHardwareLoopPHI) {
59  SmallVector<BasicBlock *, 4> ExitingBlocks;
60  L->getExitingBlocks(ExitingBlocks);
61 
62  for (SmallVectorImpl<BasicBlock *>::iterator I = ExitingBlocks.begin(),
63  IE = ExitingBlocks.end();
64  I != IE; ++I) {
65  BasicBlock *BB = *I;
66 
67  // If we pass the updated counter back through a phi, we need to know
68  // which latch the updated value will be coming from.
69  if (!L->isLoopLatch(BB)) {
70  if (ForceHardwareLoopPHI || CounterInReg)
71  continue;
72  }
73 
74  const SCEV *EC = SE.getExitCount(L, BB);
75  if (isa<SCEVCouldNotCompute>(EC))
76  continue;
77  if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
78  if (ConstEC->getValue()->isZero())
79  continue;
80  } else if (!SE.isLoopInvariant(EC, L))
81  continue;
82 
83  if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
84  continue;
85 
86  // If this exiting block is contained in a nested loop, it is not eligible
87  // for insertion of the branch-and-decrement since the inner loop would
88  // end up messing up the value in the CTR.
89  if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
90  continue;
91 
92  // We now have a loop-invariant count of loop iterations (which is not the
93  // constant zero) for which we know that this loop will not exit via this
94  // existing block.
95 
96  // We need to make sure that this block will run on every loop iteration.
97  // For this to be true, we must dominate all blocks with backedges. Such
98  // blocks are in-loop predecessors to the header block.
99  bool NotAlways = false;
100  for (pred_iterator PI = pred_begin(L->getHeader()),
101  PIE = pred_end(L->getHeader());
102  PI != PIE; ++PI) {
103  if (!L->contains(*PI))
104  continue;
105 
106  if (!DT.dominates(*I, *PI)) {
107  NotAlways = true;
108  break;
109  }
110  }
111 
112  if (NotAlways)
113  continue;
114 
115  // Make sure this blocks ends with a conditional branch.
116  Instruction *TI = BB->getTerminator();
117  if (!TI)
118  continue;
119 
120  if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
121  if (!BI->isConditional())
122  continue;
123 
124  ExitBranch = BI;
125  } else
126  continue;
127 
128  // Note that this block may not be the loop latch block, even if the loop
129  // has a latch block.
130  ExitBlock = *I;
131  ExitCount = EC;
132  break;
133  }
134 
135  if (!ExitBlock)
136  return false;
137  return true;
138 }
139 
141  : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
142 
144 
146  : TTIImpl(std::move(Arg.TTIImpl)) {}
147 
149  TTIImpl = std::move(RHS.TTIImpl);
150  return *this;
151 }
152 
154  Type *OpTy) const {
155  int Cost = TTIImpl->getOperationCost(Opcode, Ty, OpTy);
156  assert(Cost >= 0 && "TTI should not produce negative costs!");
157  return Cost;
158 }
159 
161  const User *U) const {
162  int Cost = TTIImpl->getCallCost(FTy, NumArgs, U);
163  assert(Cost >= 0 && "TTI should not produce negative costs!");
164  return Cost;
165 }
166 
169  const User *U) const {
170  int Cost = TTIImpl->getCallCost(F, Arguments, U);
171  assert(Cost >= 0 && "TTI should not produce negative costs!");
172  return Cost;
173 }
174 
176  return TTIImpl->getInliningThresholdMultiplier();
177 }
178 
179 int TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr,
180  ArrayRef<const Value *> Operands) const {
181  return TTIImpl->getGEPCost(PointeeType, Ptr, Operands);
182 }
183 
185  const Value *Src) const {
186  return TTIImpl->getExtCost(I, Src);
187 }
188 
191  const User *U) const {
192  int Cost = TTIImpl->getIntrinsicCost(IID, RetTy, Arguments, U);
193  assert(Cost >= 0 && "TTI should not produce negative costs!");
194  return Cost;
195 }
196 
197 unsigned
199  unsigned &JTSize) const {
200  return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize);
201 }
202 
204  ArrayRef<const Value *> Operands) const {
205  int Cost = TTIImpl->getUserCost(U, Operands);
206  assert(Cost >= 0 && "TTI should not produce negative costs!");
207  return Cost;
208 }
209 
211  return TTIImpl->hasBranchDivergence();
212 }
213 
215  return TTIImpl->isSourceOfDivergence(V);
216 }
217 
219  return TTIImpl->isAlwaysUniform(V);
220 }
221 
223  return TTIImpl->getFlatAddressSpace();
224 }
225 
227  return TTIImpl->isLoweredToCall(F);
228 }
229 
231  Loop *L, ScalarEvolution &SE, AssumptionCache &AC,
232  TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
233  return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
234 }
235 
237  Loop *L, ScalarEvolution &SE, UnrollingPreferences &UP) const {
238  return TTIImpl->getUnrollingPreferences(L, SE, UP);
239 }
240 
242  return TTIImpl->isLegalAddImmediate(Imm);
243 }
244 
246  return TTIImpl->isLegalICmpImmediate(Imm);
247 }
248 
250  int64_t BaseOffset,
251  bool HasBaseReg,
252  int64_t Scale,
253  unsigned AddrSpace,
254  Instruction *I) const {
255  return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
256  Scale, AddrSpace, I);
257 }
258 
260  return TTIImpl->isLSRCostLess(C1, C2);
261 }
262 
264  return TTIImpl->canMacroFuseCmp();
265 }
266 
268  ScalarEvolution *SE, LoopInfo *LI,
270  TargetLibraryInfo *LibInfo) const {
271  return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
272 }
273 
275  return TTIImpl->shouldFavorPostInc();
276 }
277 
279  return TTIImpl->shouldFavorBackedgeIndex(L);
280 }
281 
283  return TTIImpl->isLegalMaskedStore(DataType);
284 }
285 
287  return TTIImpl->isLegalMaskedLoad(DataType);
288 }
289 
291  unsigned Alignment) const {
292  return TTIImpl->isLegalNTStore(DataType, Alignment);
293 }
294 
296  unsigned Alignment) const {
297  return TTIImpl->isLegalNTLoad(DataType, Alignment);
298 }
299 
301  return TTIImpl->isLegalMaskedGather(DataType);
302 }
303 
305  return TTIImpl->isLegalMaskedScatter(DataType);
306 }
307 
309  return TTIImpl->isLegalMaskedCompressStore(DataType);
310 }
311 
313  return TTIImpl->isLegalMaskedExpandLoad(DataType);
314 }
315 
316 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
317  return TTIImpl->hasDivRemOp(DataType, IsSigned);
318 }
319 
321  unsigned AddrSpace) const {
322  return TTIImpl->hasVolatileVariant(I, AddrSpace);
323 }
324 
326  return TTIImpl->prefersVectorizedAddressing();
327 }
328 
330  int64_t BaseOffset,
331  bool HasBaseReg,
332  int64_t Scale,
333  unsigned AddrSpace) const {
334  int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
335  Scale, AddrSpace);
336  assert(Cost >= 0 && "TTI should not produce negative costs!");
337  return Cost;
338 }
339 
341  return TTIImpl->LSRWithInstrQueries();
342 }
343 
345  return TTIImpl->isTruncateFree(Ty1, Ty2);
346 }
347 
349  return TTIImpl->isProfitableToHoist(I);
350 }
351 
352 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
353 
355  return TTIImpl->isTypeLegal(Ty);
356 }
357 
359  return TTIImpl->getJumpBufAlignment();
360 }
361 
363  return TTIImpl->getJumpBufSize();
364 }
365 
367  return TTIImpl->shouldBuildLookupTables();
368 }
370  return TTIImpl->shouldBuildLookupTablesForConstant(C);
371 }
372 
374  return TTIImpl->useColdCCForColdCall(F);
375 }
376 
377 unsigned TargetTransformInfo::
378 getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const {
379  return TTIImpl->getScalarizationOverhead(Ty, Insert, Extract);
380 }
381 
382 unsigned TargetTransformInfo::
384  unsigned VF) const {
385  return TTIImpl->getOperandsScalarizationOverhead(Args, VF);
386 }
387 
389  return TTIImpl->supportsEfficientVectorElementLoadStore();
390 }
391 
392 bool TargetTransformInfo::enableAggressiveInterleaving(bool LoopHasReductions) const {
393  return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
394 }
395 
397 TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
398  return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
399 }
400 
402  return TTIImpl->enableInterleavedAccessVectorization();
403 }
404 
406  return TTIImpl->enableMaskedInterleavedAccessVectorization();
407 }
408 
410  return TTIImpl->isFPVectorizationPotentiallyUnsafe();
411 }
412 
414  unsigned BitWidth,
415  unsigned AddressSpace,
416  unsigned Alignment,
417  bool *Fast) const {
418  return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth, AddressSpace,
419  Alignment, Fast);
420 }
421 
423 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
424  return TTIImpl->getPopcntSupport(IntTyWidthInBit);
425 }
426 
428  return TTIImpl->haveFastSqrt(Ty);
429 }
430 
432  return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
433 }
434 
436  int Cost = TTIImpl->getFPOpCost(Ty);
437  assert(Cost >= 0 && "TTI should not produce negative costs!");
438  return Cost;
439 }
440 
441 int TargetTransformInfo::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
442  const APInt &Imm,
443  Type *Ty) const {
444  int Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
445  assert(Cost >= 0 && "TTI should not produce negative costs!");
446  return Cost;
447 }
448 
449 int TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty) const {
450  int Cost = TTIImpl->getIntImmCost(Imm, Ty);
451  assert(Cost >= 0 && "TTI should not produce negative costs!");
452  return Cost;
453 }
454 
455 int TargetTransformInfo::getIntImmCost(unsigned Opcode, unsigned Idx,
456  const APInt &Imm, Type *Ty) const {
457  int Cost = TTIImpl->getIntImmCost(Opcode, Idx, Imm, Ty);
458  assert(Cost >= 0 && "TTI should not produce negative costs!");
459  return Cost;
460 }
461 
463  const APInt &Imm, Type *Ty) const {
464  int Cost = TTIImpl->getIntImmCost(IID, Idx, Imm, Ty);
465  assert(Cost >= 0 && "TTI should not produce negative costs!");
466  return Cost;
467 }
468 
469 unsigned TargetTransformInfo::getNumberOfRegisters(bool Vector) const {
470  return TTIImpl->getNumberOfRegisters(Vector);
471 }
472 
473 unsigned TargetTransformInfo::getRegisterBitWidth(bool Vector) const {
474  return TTIImpl->getRegisterBitWidth(Vector);
475 }
476 
478  return TTIImpl->getMinVectorRegisterBitWidth();
479 }
480 
482  return TTIImpl->shouldMaximizeVectorBandwidth(OptSize);
483 }
484 
485 unsigned TargetTransformInfo::getMinimumVF(unsigned ElemWidth) const {
486  return TTIImpl->getMinimumVF(ElemWidth);
487 }
488 
490  const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
491  return TTIImpl->shouldConsiderAddressTypePromotion(
492  I, AllowPromotionWithoutCommonHeader);
493 }
494 
496  return TTIImpl->getCacheLineSize();
497 }
498 
500  const {
501  return TTIImpl->getCacheSize(Level);
502 }
503 
505  CacheLevel Level) const {
506  return TTIImpl->getCacheAssociativity(Level);
507 }
508 
510  return TTIImpl->getPrefetchDistance();
511 }
512 
514  return TTIImpl->getMinPrefetchStride();
515 }
516 
518  return TTIImpl->getMaxPrefetchIterationsAhead();
519 }
520 
521 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
522  return TTIImpl->getMaxInterleaveFactor(VF);
523 }
524 
527  OperandValueKind OpInfo = OK_AnyValue;
528  OpProps = OP_None;
529 
530  if (auto *CI = dyn_cast<ConstantInt>(V)) {
531  if (CI->getValue().isPowerOf2())
532  OpProps = OP_PowerOf2;
534  }
535 
536  // A broadcast shuffle creates a uniform value.
537  // TODO: Add support for non-zero index broadcasts.
538  // TODO: Add support for different source vector width.
539  if (auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
540  if (ShuffleInst->isZeroEltSplat())
541  OpInfo = OK_UniformValue;
542 
543  const Value *Splat = getSplatValue(V);
544 
545  // Check for a splat of a constant or for a non uniform vector of constants
546  // and check if the constant(s) are all powers of two.
547  if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
549  if (Splat) {
550  OpInfo = OK_UniformConstantValue;
551  if (auto *CI = dyn_cast<ConstantInt>(Splat))
552  if (CI->getValue().isPowerOf2())
553  OpProps = OP_PowerOf2;
554  } else if (auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
555  OpProps = OP_PowerOf2;
556  for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
557  if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I)))
558  if (CI->getValue().isPowerOf2())
559  continue;
560  OpProps = OP_None;
561  break;
562  }
563  }
564  }
565 
566  // Check for a splat of a uniform value. This is not loop aware, so return
567  // true only for the obviously uniform cases (argument, globalvalue)
568  if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
569  OpInfo = OK_UniformValue;
570 
571  return OpInfo;
572 }
573 
575  unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
576  OperandValueKind Opd2Info, OperandValueProperties Opd1PropInfo,
577  OperandValueProperties Opd2PropInfo,
579  int Cost = TTIImpl->getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
580  Opd1PropInfo, Opd2PropInfo, Args);
581  assert(Cost >= 0 && "TTI should not produce negative costs!");
582  return Cost;
583 }
584 
586  Type *SubTp) const {
587  int Cost = TTIImpl->getShuffleCost(Kind, Ty, Index, SubTp);
588  assert(Cost >= 0 && "TTI should not produce negative costs!");
589  return Cost;
590 }
591 
592 int TargetTransformInfo::getCastInstrCost(unsigned Opcode, Type *Dst,
593  Type *Src, const Instruction *I) const {
594  assert ((I == nullptr || I->getOpcode() == Opcode) &&
595  "Opcode should reflect passed instruction.");
596  int Cost = TTIImpl->getCastInstrCost(Opcode, Dst, Src, I);
597  assert(Cost >= 0 && "TTI should not produce negative costs!");
598  return Cost;
599 }
600 
602  VectorType *VecTy,
603  unsigned Index) const {
604  int Cost = TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
605  assert(Cost >= 0 && "TTI should not produce negative costs!");
606  return Cost;
607 }
608 
609 int TargetTransformInfo::getCFInstrCost(unsigned Opcode) const {
610  int Cost = TTIImpl->getCFInstrCost(Opcode);
611  assert(Cost >= 0 && "TTI should not produce negative costs!");
612  return Cost;
613 }
614 
615 int TargetTransformInfo::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
616  Type *CondTy, const Instruction *I) const {
617  assert ((I == nullptr || I->getOpcode() == Opcode) &&
618  "Opcode should reflect passed instruction.");
619  int Cost = TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
620  assert(Cost >= 0 && "TTI should not produce negative costs!");
621  return Cost;
622 }
623 
625  unsigned Index) const {
626  int Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
627  assert(Cost >= 0 && "TTI should not produce negative costs!");
628  return Cost;
629 }
630 
631 int TargetTransformInfo::getMemoryOpCost(unsigned Opcode, Type *Src,
632  unsigned Alignment,
633  unsigned AddressSpace,
634  const Instruction *I) const {
635  assert ((I == nullptr || I->getOpcode() == Opcode) &&
636  "Opcode should reflect passed instruction.");
637  int Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I);
638  assert(Cost >= 0 && "TTI should not produce negative costs!");
639  return Cost;
640 }
641 
643  unsigned Alignment,
644  unsigned AddressSpace) const {
645  int Cost =
646  TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
647  assert(Cost >= 0 && "TTI should not produce negative costs!");
648  return Cost;
649 }
650 
652  Value *Ptr, bool VariableMask,
653  unsigned Alignment) const {
654  int Cost = TTIImpl->getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
655  Alignment);
656  assert(Cost >= 0 && "TTI should not produce negative costs!");
657  return Cost;
658 }
659 
661  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
662  unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond,
663  bool UseMaskForGaps) const {
664  int Cost = TTIImpl->getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
665  Alignment, AddressSpace,
666  UseMaskForCond,
667  UseMaskForGaps);
668  assert(Cost >= 0 && "TTI should not produce negative costs!");
669  return Cost;
670 }
671 
674  unsigned ScalarizationCostPassed) const {
675  int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Tys, FMF,
676  ScalarizationCostPassed);
677  assert(Cost >= 0 && "TTI should not produce negative costs!");
678  return Cost;
679 }
680 
682  ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) const {
683  int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Args, FMF, VF);
684  assert(Cost >= 0 && "TTI should not produce negative costs!");
685  return Cost;
686 }
687 
689  ArrayRef<Type *> Tys) const {
690  int Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys);
691  assert(Cost >= 0 && "TTI should not produce negative costs!");
692  return Cost;
693 }
694 
696  return TTIImpl->getNumberOfParts(Tp);
697 }
698 
700  ScalarEvolution *SE,
701  const SCEV *Ptr) const {
702  int Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
703  assert(Cost >= 0 && "TTI should not produce negative costs!");
704  return Cost;
705 }
706 
708  int Cost = TTIImpl->getMemcpyCost(I);
709  assert(Cost >= 0 && "TTI should not produce negative costs!");
710  return Cost;
711 }
712 
714  bool IsPairwiseForm) const {
715  int Cost = TTIImpl->getArithmeticReductionCost(Opcode, Ty, IsPairwiseForm);
716  assert(Cost >= 0 && "TTI should not produce negative costs!");
717  return Cost;
718 }
719 
721  bool IsPairwiseForm,
722  bool IsUnsigned) const {
723  int Cost =
724  TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsPairwiseForm, IsUnsigned);
725  assert(Cost >= 0 && "TTI should not produce negative costs!");
726  return Cost;
727 }
728 
729 unsigned
731  return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
732 }
733 
735  MemIntrinsicInfo &Info) const {
736  return TTIImpl->getTgtMemIntrinsic(Inst, Info);
737 }
738 
740  return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
741 }
742 
744  IntrinsicInst *Inst, Type *ExpectedType) const {
745  return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
746 }
747 
749  Value *Length,
750  unsigned SrcAlign,
751  unsigned DestAlign) const {
752  return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAlign,
753  DestAlign);
754 }
755 
758  unsigned RemainingBytes, unsigned SrcAlign, unsigned DestAlign) const {
759  TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
760  SrcAlign, DestAlign);
761 }
762 
764  const Function *Callee) const {
765  return TTIImpl->areInlineCompatible(Caller, Callee);
766 }
767 
769  const Function *Caller, const Function *Callee,
771  return TTIImpl->areFunctionArgsABICompatible(Caller, Callee, Args);
772 }
773 
775  Type *Ty) const {
776  return TTIImpl->isIndexedLoadLegal(Mode, Ty);
777 }
778 
780  Type *Ty) const {
781  return TTIImpl->isIndexedStoreLegal(Mode, Ty);
782 }
783 
785  return TTIImpl->getLoadStoreVecRegBitWidth(AS);
786 }
787 
789  return TTIImpl->isLegalToVectorizeLoad(LI);
790 }
791 
793  return TTIImpl->isLegalToVectorizeStore(SI);
794 }
795 
797  unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
798  return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
799  AddrSpace);
800 }
801 
803  unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
804  return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
805  AddrSpace);
806 }
807 
809  unsigned LoadSize,
810  unsigned ChainSizeInBytes,
811  VectorType *VecTy) const {
812  return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
813 }
814 
816  unsigned StoreSize,
817  unsigned ChainSizeInBytes,
818  VectorType *VecTy) const {
819  return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
820 }
821 
823  Type *Ty, ReductionFlags Flags) const {
824  return TTIImpl->useReductionIntrinsic(Opcode, Ty, Flags);
825 }
826 
828  return TTIImpl->shouldExpandReduction(II);
829 }
830 
832  return TTIImpl->getGISelRematGlobalCost();
833 }
834 
835 int TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
836  return TTIImpl->getInstructionLatency(I);
837 }
838 
840  unsigned Level) {
841  // We don't need a shuffle if we just want to have element 0 in position 0 of
842  // the vector.
843  if (!SI && Level == 0 && IsLeft)
844  return true;
845  else if (!SI)
846  return false;
847 
849 
850  // Build a mask of 0, 2, ... (left) or 1, 3, ... (right) depending on whether
851  // we look at the left or right side.
852  for (unsigned i = 0, e = (1 << Level), val = !IsLeft; i != e; ++i, val += 2)
853  Mask[i] = val;
854 
855  SmallVector<int, 16> ActualMask = SI->getShuffleMask();
856  return Mask == ActualMask;
857 }
858 
859 namespace {
860 /// Kind of the reduction data.
862  RK_None, /// Not a reduction.
863  RK_Arithmetic, /// Binary reduction data.
864  RK_MinMax, /// Min/max reduction data.
865  RK_UnsignedMinMax, /// Unsigned min/max reduction data.
866 };
867 /// Contains opcode + LHS/RHS parts of the reduction operations.
868 struct ReductionData {
869  ReductionData() = delete;
870  ReductionData(ReductionKind Kind, unsigned Opcode, Value *LHS, Value *RHS)
871  : Opcode(Opcode), LHS(LHS), RHS(RHS), Kind(Kind) {
872  assert(Kind != RK_None && "expected binary or min/max reduction only.");
873  }
874  unsigned Opcode = 0;
875  Value *LHS = nullptr;
876  Value *RHS = nullptr;
877  ReductionKind Kind = RK_None;
878  bool hasSameData(ReductionData &RD) const {
879  return Kind == RD.Kind && Opcode == RD.Opcode;
880  }
881 };
882 } // namespace
883 
885  Value *L, *R;
886  if (m_BinOp(m_Value(L), m_Value(R)).match(I))
887  return ReductionData(RK_Arithmetic, I->getOpcode(), L, R);
888  if (auto *SI = dyn_cast<SelectInst>(I)) {
889  if (m_SMin(m_Value(L), m_Value(R)).match(SI) ||
890  m_SMax(m_Value(L), m_Value(R)).match(SI) ||
891  m_OrdFMin(m_Value(L), m_Value(R)).match(SI) ||
892  m_OrdFMax(m_Value(L), m_Value(R)).match(SI) ||
893  m_UnordFMin(m_Value(L), m_Value(R)).match(SI) ||
894  m_UnordFMax(m_Value(L), m_Value(R)).match(SI)) {
895  auto *CI = cast<CmpInst>(SI->getCondition());
896  return ReductionData(RK_MinMax, CI->getOpcode(), L, R);
897  }
898  if (m_UMin(m_Value(L), m_Value(R)).match(SI) ||
899  m_UMax(m_Value(L), m_Value(R)).match(SI)) {
900  auto *CI = cast<CmpInst>(SI->getCondition());
901  return ReductionData(RK_UnsignedMinMax, CI->getOpcode(), L, R);
902  }
903  }
904  return llvm::None;
905 }
906 
908  unsigned Level,
909  unsigned NumLevels) {
910  // Match one level of pairwise operations.
911  // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
912  // <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
913  // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
914  // <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
915  // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
916  if (!I)
917  return RK_None;
918 
919  assert(I->getType()->isVectorTy() && "Expecting a vector type");
920 
922  if (!RD)
923  return RK_None;
924 
926  if (!LS && Level)
927  return RK_None;
929  if (!RS && Level)
930  return RK_None;
931 
932  // On level 0 we can omit one shufflevector instruction.
933  if (!Level && !RS && !LS)
934  return RK_None;
935 
936  // Shuffle inputs must match.
937  Value *NextLevelOpL = LS ? LS->getOperand(0) : nullptr;
938  Value *NextLevelOpR = RS ? RS->getOperand(0) : nullptr;
939  Value *NextLevelOp = nullptr;
940  if (NextLevelOpR && NextLevelOpL) {
941  // If we have two shuffles their operands must match.
942  if (NextLevelOpL != NextLevelOpR)
943  return RK_None;
944 
945  NextLevelOp = NextLevelOpL;
946  } else if (Level == 0 && (NextLevelOpR || NextLevelOpL)) {
947  // On the first level we can omit the shufflevector <0, undef,...>. So the
948  // input to the other shufflevector <1, undef> must match with one of the
949  // inputs to the current binary operation.
950  // Example:
951  // %NextLevelOpL = shufflevector %R, <1, undef ...>
952  // %BinOp = fadd %NextLevelOpL, %R
953  if (NextLevelOpL && NextLevelOpL != RD->RHS)
954  return RK_None;
955  else if (NextLevelOpR && NextLevelOpR != RD->LHS)
956  return RK_None;
957 
958  NextLevelOp = NextLevelOpL ? RD->RHS : RD->LHS;
959  } else
960  return RK_None;
961 
962  // Check that the next levels binary operation exists and matches with the
963  // current one.
964  if (Level + 1 != NumLevels) {
965  Optional<ReductionData> NextLevelRD =
966  getReductionData(cast<Instruction>(NextLevelOp));
967  if (!NextLevelRD || !RD->hasSameData(*NextLevelRD))
968  return RK_None;
969  }
970 
971  // Shuffle mask for pairwise operation must match.
972  if (matchPairwiseShuffleMask(LS, /*IsLeft=*/true, Level)) {
973  if (!matchPairwiseShuffleMask(RS, /*IsLeft=*/false, Level))
974  return RK_None;
975  } else if (matchPairwiseShuffleMask(RS, /*IsLeft=*/true, Level)) {
976  if (!matchPairwiseShuffleMask(LS, /*IsLeft=*/false, Level))
977  return RK_None;
978  } else {
979  return RK_None;
980  }
981 
982  if (++Level == NumLevels)
983  return RD->Kind;
984 
985  // Match next level.
986  return matchPairwiseReductionAtLevel(cast<Instruction>(NextLevelOp), Level,
987  NumLevels);
988 }
989 
991  unsigned &Opcode, Type *&Ty) {
992  if (!EnableReduxCost)
993  return RK_None;
994 
995  // Need to extract the first element.
996  ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
997  unsigned Idx = ~0u;
998  if (CI)
999  Idx = CI->getZExtValue();
1000  if (Idx != 0)
1001  return RK_None;
1002 
1003  auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
1004  if (!RdxStart)
1005  return RK_None;
1007  if (!RD)
1008  return RK_None;
1009 
1010  Type *VecTy = RdxStart->getType();
1011  unsigned NumVecElems = VecTy->getVectorNumElements();
1012  if (!isPowerOf2_32(NumVecElems))
1013  return RK_None;
1014 
1015  // We look for a sequence of shuffle,shuffle,add triples like the following
1016  // that builds a pairwise reduction tree.
1017  //
1018  // (X0, X1, X2, X3)
1019  // (X0 + X1, X2 + X3, undef, undef)
1020  // ((X0 + X1) + (X2 + X3), undef, undef, undef)
1021  //
1022  // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
1023  // <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
1024  // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
1025  // <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
1026  // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
1027  // %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
1028  // <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
1029  // %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
1030  // <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1031  // %bin.rdx8 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1
1032  // %r = extractelement <4 x float> %bin.rdx8, i32 0
1033  if (matchPairwiseReductionAtLevel(RdxStart, 0, Log2_32(NumVecElems)) ==
1034  RK_None)
1035  return RK_None;
1036 
1037  Opcode = RD->Opcode;
1038  Ty = VecTy;
1039 
1040  return RD->Kind;
1041 }
1042 
1043 static std::pair<Value *, ShuffleVectorInst *>
1045  ShuffleVectorInst *S = nullptr;
1046 
1047  if ((S = dyn_cast<ShuffleVectorInst>(L)))
1048  return std::make_pair(R, S);
1049 
1050  S = dyn_cast<ShuffleVectorInst>(R);
1051  return std::make_pair(L, S);
1052 }
1053 
1054 static ReductionKind
1056  unsigned &Opcode, Type *&Ty) {
1057  if (!EnableReduxCost)
1058  return RK_None;
1059 
1060  // Need to extract the first element.
1061  ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
1062  unsigned Idx = ~0u;
1063  if (CI)
1064  Idx = CI->getZExtValue();
1065  if (Idx != 0)
1066  return RK_None;
1067 
1068  auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
1069  if (!RdxStart)
1070  return RK_None;
1072  if (!RD)
1073  return RK_None;
1074 
1075  Type *VecTy = ReduxRoot->getOperand(0)->getType();
1076  unsigned NumVecElems = VecTy->getVectorNumElements();
1077  if (!isPowerOf2_32(NumVecElems))
1078  return RK_None;
1079 
1080  // We look for a sequence of shuffles and adds like the following matching one
1081  // fadd, shuffle vector pair at a time.
1082  //
1083  // %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
1084  // <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
1085  // %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf
1086  // %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
1087  // <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1088  // %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7
1089  // %r = extractelement <4 x float> %bin.rdx8, i32 0
1090 
1091  unsigned MaskStart = 1;
1092  Instruction *RdxOp = RdxStart;
1093  SmallVector<int, 32> ShuffleMask(NumVecElems, 0);
1094  unsigned NumVecElemsRemain = NumVecElems;
1095  while (NumVecElemsRemain - 1) {
1096  // Check for the right reduction operation.
1097  if (!RdxOp)
1098  return RK_None;
1099  Optional<ReductionData> RDLevel = getReductionData(RdxOp);
1100  if (!RDLevel || !RDLevel->hasSameData(*RD))
1101  return RK_None;
1102 
1103  Value *NextRdxOp;
1104  ShuffleVectorInst *Shuffle;
1105  std::tie(NextRdxOp, Shuffle) =
1106  getShuffleAndOtherOprd(RDLevel->LHS, RDLevel->RHS);
1107 
1108  // Check the current reduction operation and the shuffle use the same value.
1109  if (Shuffle == nullptr)
1110  return RK_None;
1111  if (Shuffle->getOperand(0) != NextRdxOp)
1112  return RK_None;
1113 
1114  // Check that shuffle masks matches.
1115  for (unsigned j = 0; j != MaskStart; ++j)
1116  ShuffleMask[j] = MaskStart + j;
1117  // Fill the rest of the mask with -1 for undef.
1118  std::fill(&ShuffleMask[MaskStart], ShuffleMask.end(), -1);
1119 
1121  if (ShuffleMask != Mask)
1122  return RK_None;
1123 
1124  RdxOp = dyn_cast<Instruction>(NextRdxOp);
1125  NumVecElemsRemain /= 2;
1126  MaskStart *= 2;
1127  }
1128 
1129  Opcode = RD->Opcode;
1130  Ty = VecTy;
1131  return RD->Kind;
1132 }
1133 
1134 int TargetTransformInfo::getInstructionThroughput(const Instruction *I) const {
1135  switch (I->getOpcode()) {
1136  case Instruction::GetElementPtr:
1137  return getUserCost(I);
1138 
1139  case Instruction::Ret:
1140  case Instruction::PHI:
1141  case Instruction::Br: {
1142  return getCFInstrCost(I->getOpcode());
1143  }
1144  case Instruction::Add:
1145  case Instruction::FAdd:
1146  case Instruction::Sub:
1147  case Instruction::FSub:
1148  case Instruction::Mul:
1149  case Instruction::FMul:
1150  case Instruction::UDiv:
1151  case Instruction::SDiv:
1152  case Instruction::FDiv:
1153  case Instruction::URem:
1154  case Instruction::SRem:
1155  case Instruction::FRem:
1156  case Instruction::Shl:
1157  case Instruction::LShr:
1158  case Instruction::AShr:
1159  case Instruction::And:
1160  case Instruction::Or:
1161  case Instruction::Xor: {
1164  Op1VK = getOperandInfo(I->getOperand(0), Op1VP);
1165  Op2VK = getOperandInfo(I->getOperand(1), Op2VP);
1167  return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1168  Op1VP, Op2VP, Operands);
1169  }
1170  case Instruction::FNeg: {
1173  Op1VK = getOperandInfo(I->getOperand(0), Op1VP);
1174  Op2VK = OK_AnyValue;
1175  Op2VP = OP_None;
1177  return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1178  Op1VP, Op2VP, Operands);
1179  }
1180  case Instruction::Select: {
1181  const SelectInst *SI = cast<SelectInst>(I);
1182  Type *CondTy = SI->getCondition()->getType();
1183  return getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy, I);
1184  }
1185  case Instruction::ICmp:
1186  case Instruction::FCmp: {
1187  Type *ValTy = I->getOperand(0)->getType();
1188  return getCmpSelInstrCost(I->getOpcode(), ValTy, I->getType(), I);
1189  }
1190  case Instruction::Store: {
1191  const StoreInst *SI = cast<StoreInst>(I);
1192  Type *ValTy = SI->getValueOperand()->getType();
1193  return getMemoryOpCost(I->getOpcode(), ValTy,
1194  SI->getAlignment(),
1195  SI->getPointerAddressSpace(), I);
1196  }
1197  case Instruction::Load: {
1198  const LoadInst *LI = cast<LoadInst>(I);
1199  return getMemoryOpCost(I->getOpcode(), I->getType(),
1200  LI->getAlignment(),
1201  LI->getPointerAddressSpace(), I);
1202  }
1203  case Instruction::ZExt:
1204  case Instruction::SExt:
1205  case Instruction::FPToUI:
1206  case Instruction::FPToSI:
1207  case Instruction::FPExt:
1208  case Instruction::PtrToInt:
1209  case Instruction::IntToPtr:
1210  case Instruction::SIToFP:
1211  case Instruction::UIToFP:
1212  case Instruction::Trunc:
1213  case Instruction::FPTrunc:
1214  case Instruction::BitCast:
1215  case Instruction::AddrSpaceCast: {
1216  Type *SrcTy = I->getOperand(0)->getType();
1217  return getCastInstrCost(I->getOpcode(), I->getType(), SrcTy, I);
1218  }
1219  case Instruction::ExtractElement: {
1220  const ExtractElementInst * EEI = cast<ExtractElementInst>(I);
1222  unsigned Idx = -1;
1223  if (CI)
1224  Idx = CI->getZExtValue();
1225 
1226  // Try to match a reduction sequence (series of shufflevector and vector
1227  // adds followed by a extractelement).
1228  unsigned ReduxOpCode;
1229  Type *ReduxType;
1230 
1231  switch (matchVectorSplittingReduction(EEI, ReduxOpCode, ReduxType)) {
1232  case RK_Arithmetic:
1233  return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1234  /*IsPairwiseForm=*/false);
1235  case RK_MinMax:
1236  return getMinMaxReductionCost(
1237  ReduxType, CmpInst::makeCmpResultType(ReduxType),
1238  /*IsPairwiseForm=*/false, /*IsUnsigned=*/false);
1239  case RK_UnsignedMinMax:
1240  return getMinMaxReductionCost(
1241  ReduxType, CmpInst::makeCmpResultType(ReduxType),
1242  /*IsPairwiseForm=*/false, /*IsUnsigned=*/true);
1243  case RK_None:
1244  break;
1245  }
1246 
1247  switch (matchPairwiseReduction(EEI, ReduxOpCode, ReduxType)) {
1248  case RK_Arithmetic:
1249  return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1250  /*IsPairwiseForm=*/true);
1251  case RK_MinMax:
1252  return getMinMaxReductionCost(
1253  ReduxType, CmpInst::makeCmpResultType(ReduxType),
1254  /*IsPairwiseForm=*/true, /*IsUnsigned=*/false);
1255  case RK_UnsignedMinMax:
1256  return getMinMaxReductionCost(
1257  ReduxType, CmpInst::makeCmpResultType(ReduxType),
1258  /*IsPairwiseForm=*/true, /*IsUnsigned=*/true);
1259  case RK_None:
1260  break;
1261  }
1262 
1263  return getVectorInstrCost(I->getOpcode(),
1264  EEI->getOperand(0)->getType(), Idx);
1265  }
1266  case Instruction::InsertElement: {
1267  const InsertElementInst * IE = cast<InsertElementInst>(I);
1268  ConstantInt *CI = dyn_cast<ConstantInt>(IE->getOperand(2));
1269  unsigned Idx = -1;
1270  if (CI)
1271  Idx = CI->getZExtValue();
1272  return getVectorInstrCost(I->getOpcode(),
1273  IE->getType(), Idx);
1274  }
1275  case Instruction::ShuffleVector: {
1276  const ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
1277  Type *Ty = Shuffle->getType();
1278  Type *SrcTy = Shuffle->getOperand(0)->getType();
1279 
1280  // TODO: Identify and add costs for insert subvector, etc.
1281  int SubIndex;
1282  if (Shuffle->isExtractSubvectorMask(SubIndex))
1283  return TTIImpl->getShuffleCost(SK_ExtractSubvector, SrcTy, SubIndex, Ty);
1284 
1285  if (Shuffle->changesLength())
1286  return -1;
1287 
1288  if (Shuffle->isIdentity())
1289  return 0;
1290 
1291  if (Shuffle->isReverse())
1292  return TTIImpl->getShuffleCost(SK_Reverse, Ty, 0, nullptr);
1293 
1294  if (Shuffle->isSelect())
1295  return TTIImpl->getShuffleCost(SK_Select, Ty, 0, nullptr);
1296 
1297  if (Shuffle->isTranspose())
1298  return TTIImpl->getShuffleCost(SK_Transpose, Ty, 0, nullptr);
1299 
1300  if (Shuffle->isZeroEltSplat())
1301  return TTIImpl->getShuffleCost(SK_Broadcast, Ty, 0, nullptr);
1302 
1303  if (Shuffle->isSingleSource())
1304  return TTIImpl->getShuffleCost(SK_PermuteSingleSrc, Ty, 0, nullptr);
1305 
1306  return TTIImpl->getShuffleCost(SK_PermuteTwoSrc, Ty, 0, nullptr);
1307  }
1308  case Instruction::Call:
1309  if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
1310  SmallVector<Value *, 4> Args(II->arg_operands());
1311 
1312  FastMathFlags FMF;
1313  if (auto *FPMO = dyn_cast<FPMathOperator>(II))
1314  FMF = FPMO->getFastMathFlags();
1315 
1316  return getIntrinsicInstrCost(II->getIntrinsicID(), II->getType(),
1317  Args, FMF);
1318  }
1319  return -1;
1320  default:
1321  // We don't have any information on this instruction.
1322  return -1;
1323  }
1324 }
1325 
1327 
1328 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1329 
1331  std::function<Result(const Function &)> TTICallback)
1332  : TTICallback(std::move(TTICallback)) {}
1333 
1336  return TTICallback(F);
1337 }
1338 
1339 AnalysisKey TargetIRAnalysis::Key;
1340 
1341 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1342  return Result(F.getParent()->getDataLayout());
1343 }
1344 
1345 // Register the basic pass.
1347  "Target Transform Information", false, true)
1349 
1350 void TargetTransformInfoWrapperPass::anchor() {}
1351 
1353  : ImmutablePass(ID) {
1356 }
1357 
1359  TargetIRAnalysis TIRA)
1360  : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1363 }
1364 
1366  FunctionAnalysisManager DummyFAM;
1367  TTI = TIRA.run(F, DummyFAM);
1368  return *TTI;
1369 }
1370 
1371 ImmutablePass *
1373  return new TargetTransformInfoWrapperPass(std::move(TIRA));
1374 }
MaxMin_match< ICmpInst, LHS, RHS, umin_pred_ty > m_UMin(const LHS &L, const RHS &R)
uint64_t CallInst * C
Value * getValueOperand()
Definition: Instructions.h:409
bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Definition: PatternMatch.h:70
static bool matchPairwiseShuffleMask(ShuffleVectorInst *SI, bool IsLeft, unsigned Level)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
LLVMContext & Context
static ReductionKind matchPairwiseReduction(const ExtractElementInst *ReduxRoot, unsigned &Opcode, Type *&Ty)
TargetTransformInfo & operator=(TargetTransformInfo &&RHS)
SI Whole Quad Mode
static Type * makeCmpResultType(Type *opnd_type)
Create a result type for fcmp/icmp.
Definition: InstrTypes.h:975
This class represents lattice values for constants.
Definition: AllocatorList.h:23
int getCallCost(FunctionType *FTy, int NumArgs=-1, const User *U=nullptr) const
Estimate the cost of a function call when lowered.
bool isLegalAddImmediate(int64_t Imm) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
bool isFPVectorizationPotentiallyUnsafe() const
Indicate that it is potentially unsafe to automatically vectorize floating-point operations because t...
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
const Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
bool supportsEfficientVectorElementLoadStore() const
If target has efficient vector element load/store instructions, it can return true here so that inser...
static ReductionKind matchPairwiseReductionAtLevel(Instruction *I, unsigned Level, unsigned NumLevels)
bool useColdCCForColdCall(Function &F) const
Return true if the input function which is cold at all call sites, should use coldcc calling conventi...
The main scalar evolution driver.
TargetTransformInfoWrapperPass()
We must provide a default constructor for the pass but it should never be used.
int getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value *> Operands) const
Estimate the cost of a GEP operation when lowered.
MemIndexedMode
The type of load/store indexing.
unsigned getNumberOfRegisters(bool Vector) const
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
bool isReverse() const
Return true if this shuffle swaps the order of elements from exactly one source vector.
A cache of @llvm.assume calls within a function.
Analysis pass providing the TargetTransformInfo.
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAlign, unsigned DestAlign) const
This instruction constructs a fixed permutation of two input vectors.
uint64_t getTypeSizeInBits(Type *Ty) const
Return the size in bits of the specified type, for which isSCEVable must return true.
bool isLoopInvariant(const SCEV *S, const Loop *L)
Return true if the value of the given SCEV is unchanging in the specified loop.
int getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type *> Tys) const
int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond=false, bool UseMaskForGaps=false) const
F(f)
An instruction for reading from memory.
Definition: Instructions.h:167
MaxMin_match< FCmpInst, LHS, RHS, ufmax_pred_ty > m_UnordFMax(const LHS &L, const RHS &R)
Match an &#39;unordered&#39; floating point maximum function.
bool canMacroFuseCmp() const
Return true if the target can fuse a compare and branch.
const Instruction * getTerminator() const LLVM_READONLY
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
Definition: BasicBlock.cpp:137
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:229
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
bool enableAggressiveInterleaving(bool LoopHasReductions) const
Don&#39;t restrict interleaved unrolling to small loops.
llvm::Optional< unsigned > getCacheAssociativity(CacheLevel Level) const
bool isSingleSource() const
Return true if this shuffle chooses elements from exactly one source vector without changing the leng...
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
This file provides helpers for the implementation of a TargetTransformInfo-conforming class...
PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Return hardware support for population count.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
unsigned getJumpBufSize() const
Returns the target&#39;s jmp_buf size in bytes.
unsigned getMaxInterleaveFactor(unsigned VF) const
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class...
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:47
bool enableMaskedInterleavedAccessVectorization() const
Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore v...
bool isLegalICmpImmediate(int64_t Imm) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: BitVector.h:937
bool isLegalNTLoad(Type *DataType, unsigned Alignment) const
Return true if the target supports nontemporal load.
int getOperationCost(unsigned Opcode, Type *Ty, Type *OpTy=nullptr) const
Estimate the cost of a specific operation when lowered.
bool hasBranchDivergence() const
Return true if branch divergence exists.
This class represents the LLVM &#39;select&#39; instruction.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:369
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize) const
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
Definition: LoopInfo.h:897
bool shouldBuildLookupTablesForConstant(Constant *C) const
Return true if switches should be turned into lookup tables containing this constant value for the ta...
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, const Instruction *I=nullptr) const
static AnalysisKey * ID()
Returns an opaque, unique ID for this analysis type.
Definition: PassManager.h:405
bool isLegalNTStore(Type *DataType, unsigned Alignment) const
Return true if the target supports nontemporal store.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool shouldBuildLookupTables() const
Return true if switches should be turned into lookup tables for the target.
MaxMin_match< FCmpInst, LHS, RHS, ufmin_pred_ty > m_UnordFMin(const LHS &L, const RHS &R)
Match an &#39;unordered&#39; floating point minimum function.
bool isLegalMaskedScatter(Type *DataType) const
Return true if the target supports masked scatter.
unsigned getPointerAddressSpace() const
Returns the address space of the pointer operand.
Definition: Instructions.h:418
Class to represent function types.
Definition: DerivedTypes.h:103
unsigned getMinVectorRegisterBitWidth() const
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const
bool isTruncateFree(Type *Ty1, Type *Ty2) const
Return true if it&#39;s free to truncate a value of type Ty1 to type Ty2.
MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
PopcntSupportKind
Flags indicating the kind of support for population count.
bool hasDivRemOp(Type *DataType, bool IsSigned) const
Return true if the target has a unified operation to calculate division and remainder.
MaxMin_match< FCmpInst, LHS, RHS, ofmin_pred_ty > m_OrdFMin(const LHS &L, const RHS &R)
Match an &#39;ordered&#39; floating point minimum function.
MaxMin_match< ICmpInst, LHS, RHS, smin_pred_ty > m_SMin(const LHS &L, const RHS &R)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
Selects elements from the corresponding lane of either source operand.
int getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy, ArrayRef< Value *> Args, FastMathFlags FMF, unsigned VF=1) const
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:125
An instruction for storing to memory.
Definition: Instructions.h:320
void initializeTargetTransformInfoWrapperPassPass(PassRegistry &)
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Return true if the given instruction (assumed to be a memory access instruction) has a volatile varia...
int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index=-1) const
bool isSelect() const
Return true if this shuffle chooses elements from its source vectors without lane crossings and all o...
bool isLegalToVectorizeLoad(LoadInst *LI) const
Reverse the order of the vector.
VectorType * getType() const
Overload to return most specific vector type.
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree...
Definition: Dominators.h:144
int getAddressComputationCost(Type *Ty, ScalarEvolution *SE=nullptr, const SCEV *Ptr=nullptr) const
unsigned getJumpBufAlignment() const
Returns the target&#39;s jmp_buf alignment in bytes.
Value * getOperand(unsigned i) const
Definition: User.h:169
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
int getExtCost(const Instruction *I, const Value *Src) const
Estimate the cost of a EXT operation when lowered.
static bool isExtractSubvectorMask(ArrayRef< int > Mask, int NumSrcElts, int &Index)
Return true if this shuffle mask is an extract subvector mask.
bool isTypeLegal(Type *Ty) const
Return true if this type is legal.
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const
ExtractSubvector Index indicates start offset.
static cl::opt< bool > EnableReduxCost("costmodel-reduxcost", cl::init(false), cl::Hidden, cl::desc("Recognize reduction patterns."))
unsigned getMaxPrefetchIterationsAhead() const
bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
This instruction inserts a single (scalar) element into a VectorType value.
int getGatherScatterOpCost(unsigned Opcode, Type *DataTy, Value *Ptr, bool VariableMask, unsigned Alignment) const
Returns options for expansion of memcmp. IsZeroCmp is.
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:148
Wrapper pass for TargetTransformInfo.
MaxMin_match< ICmpInst, LHS, RHS, umax_pred_ty > m_UMax(const LHS &L, const RHS &R)
bool isLegalToVectorizeStore(StoreInst *SI) const
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:428
unsigned getRegisterBitWidth(bool Vector) const
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
Flags describing the kind of vector reduction.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
bool isAlwaysUniform(const Value *V) const
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
Conditional or Unconditional Branch instruction.
unsigned getNumberOfParts(Type *Tp) const
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:41
bool isIdentity() const
Return true if this shuffle chooses elements from exactly one source vector without lane crossings an...
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
AMDGPU Lower Kernel Arguments
Interval::pred_iterator pred_begin(Interval *I)
pred_begin/pred_end - define methods so that Intervals may be used just like BasicBlocks can with the...
Definition: Interval.h:112
int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target...
TargetIRAnalysis()
Default construct a target IR analysis.
int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy=nullptr, const Instruction *I=nullptr) const
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Interval::pred_iterator pred_end(Interval *I)
Definition: Interval.h:115
bool isLegalMaskedStore(Type *DataType) const
Return true if the target supports masked load.
Merge elements from two source vectors into one with any shuffle mask.
class_match< BinaryOperator > m_BinOp()
Match an arbitrary binary operation and ignore it.
Definition: PatternMatch.h:73
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
Attributes of a target dependent hardware loop.
const Value * getCondition() const
bool haveFastSqrt(Type *Ty) const
Return true if the hardware has a fast square-root instruction.
bool areFunctionArgsABICompatible(const Function *Caller, const Function *Callee, SmallPtrSetImpl< Argument *> &Args) const
static std::pair< Value *, ShuffleVectorInst * > getShuffleAndOtherOprd(Value *L, Value *R)
bool isLegalMaskedCompressStore(Type *DataType) const
Return true if the target supports masked compress store.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:33
OperandValueProperties
Additional properties of an operand&#39;s values.
bool isProfitableToHoist(Instruction *I) const
Return true if it is profitable to hoist instruction in the then/else to before if.
ReductionKind
Kind of the reduction data.
int getFPOpCost(Type *Ty) const
Return the expected cost of supporting the floating point operation of the specified type...
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
ImmutablePass class - This class is used to provide information that does not need to be run...
Definition: Pass.h:255
Type * getType() const
Return the LLVM type of this SCEV expression.
bool isLSRCostLess(TargetTransformInfo::LSRCost &C1, TargetTransformInfo::LSRCost &C2) const
Return true if LSR cost of C1 is lower than C1.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
int getArithmeticReductionCost(unsigned Opcode, Type *Ty, bool IsPairwiseForm) const
Calculate the cost of performing a vector reduction.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
bool dominates(const Instruction *Def, const Use &U) const
Return true if Def dominates a use in User.
Definition: Dominators.cpp:248
Module.h This file contains the declarations for the Module class.
unsigned getCostOfKeepingLiveOverCall(ArrayRef< Type *> Tys) const
static void getShuffleMask(const Constant *Mask, SmallVectorImpl< int > &Result)
Convert the input shuffle mask operand to a vector of integers.
int getIntImmCost(const APInt &Imm, Type *Ty) const
Return the expected cost of materializing for the given integer immediate of the specified type...
Provides information about what library functions are available for the current target.
bool isLegalMaskedGather(Type *DataType) const
Return true if the target supports masked gather.
AddressSpace
Definition: NVPTXBaseInfo.h:21
int getMaskedMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, unsigned AddressSpace) const
bool changesLength() const
Return true if this shuffle returns a vector with a different number of elements than its source vect...
bool isSourceOfDivergence(const Value *V) const
Returns whether V is a source of divergence.
bool LSRWithInstrQueries() const
Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAdd...
static ReductionKind matchVectorSplittingReduction(const ExtractElementInst *ReduxRoot, unsigned &Opcode, Type *&Ty)
bool canAnalyze(LoopInfo &LI)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:538
unsigned getVectorNumElements() const
Definition: DerivedTypes.h:535
bool isZeroEltSplat() const
Return true if all elements of this shuffle are the same value as the first element of exactly one so...
Class to represent vector types.
Definition: DerivedTypes.h:427
Class for arbitrary precision integers.
Definition: APInt.h:69
int getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index=-1) const
TargetTransformInfo(T Impl)
Construct a TTI object using a type implementing the Concept API below.
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Query the target whether it would be profitable to convert the given loop into a hardware loop...
Result run(const Function &F, FunctionAnalysisManager &)
bool shouldExpandReduction(const IntrinsicInst *II) const
int getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const
Return the expected cost for the given integer when optimising for size.
int getIntrinsicCost(Intrinsic::ID IID, Type *RetTy, ArrayRef< Type *> ParamTys, const User *U=nullptr) const
Estimate the cost of an intrinsic when lowered.
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace=0, unsigned Alignment=1, bool *Fast=nullptr) const
Determine if the target supports unaligned memory accesses.
bool isTranspose() const
Return true if this shuffle transposes the elements of its inputs without changing the length of the ...
int getMemcpyCost(const Instruction *I) const
bool isLegalMaskedLoad(Type *DataType) const
Return true if the target supports masked store.
unsigned getGISelRematGlobalCost() const
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
unsigned getAtomicMemIntrinsicMaxElementSize() const
unsigned getAlignment() const
Return the alignment of the access that is being performed.
Definition: Instructions.h:240
This class represents an analyzed expression in the program.
int getUserCost(const User *U, ArrayRef< const Value *> Operands) const
Estimate the cost of a given IR user when lowered.
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:506
Parameters that control the generic loop unrolling transformation.
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
#define I(x, y, z)
Definition: MD5.cpp:58
MaxMin_match< ICmpInst, LHS, RHS, smax_pred_ty > m_SMax(const LHS &L, const RHS &R)
iterator_range< value_op_iterator > operand_values()
Definition: User.h:261
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
This instruction extracts a single (scalar) element from a VectorType value.
int getShuffleCost(ShuffleKind Kind, Type *Tp, int Index=0, Type *SubTp=nullptr) const
int getArithmeticInstrCost(unsigned Opcode, Type *Ty, OperandValueKind Opd1Info=OK_AnyValue, OperandValueKind Opd2Info=OK_AnyValue, OperandValueProperties Opd1PropInfo=OP_None, OperandValueProperties Opd2PropInfo=OP_None, ArrayRef< const Value *> Args=ArrayRef< const Value *>()) const
This is an approximation of reciprocal throughput of a math/logic op.
unsigned getAlignment() const
Return the alignment of the access that is being performed.
Definition: Instructions.h:365
Wrapper class to LoopBlocksDFS that provides a standard begin()/end() interface for the DFS reverse p...
Definition: LoopIterator.h:172
bool isLegalMaskedExpandLoad(Type *DataType) const
Return true if the target supports masked expand load.
bool shouldMaximizeVectorBandwidth(bool OptSize) const
unsigned getPointerAddressSpace() const
Returns the address space of the pointer operand.
Definition: Instructions.h:290
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Multiway switch.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
TargetTransformInfo Result
MaxMin_match< FCmpInst, LHS, RHS, ofmax_pred_ty > m_OrdFMax(const LHS &L, const RHS &R)
Match an &#39;ordered&#39; floating point maximum function.
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:575
LLVM Value Representation.
Definition: Value.h:72
unsigned getInliningThresholdMultiplier() const
bool useReductionIntrinsic(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
bool isLoweredToCall(const Function *F) const
Test whether calls to a function lower to actual program function calls.
bool enableInterleavedAccessVectorization() const
Enable matching of interleaved access groups.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
Broadcast element 0 to all other elements.
static Optional< ReductionData > getReductionData(Instruction *I)
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type *> &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAlign, unsigned DestAlign) const
int getCFInstrCost(unsigned Opcode) const
bool shouldFavorBackedgeIndex(const Loop *L) const
Return true if LSR should make efforts to generate indexed addressing modes that operate across loop ...
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Return true if the target can save a compare for loop count, for example hardware loop saves a compar...
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a compariso...
bool prefersVectorizedAddressing() const
Return true if target doesn&#39;t mind addresses in vectors.
unsigned getOperandsScalarizationOverhead(ArrayRef< const Value *> Args, unsigned VF) const
print Print MemDeps of function
void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP) const
Get target-customized preferences for the generic loop unrolling transformation.
Convenience struct for specifying and reasoning about fast-math flags.
Definition: Operator.h:159
OperandValueKind
Additional information about an operand&#39;s possible values.
A container for analyses that lazily runs them and caches their results.
unsigned getMinimumVF(unsigned ElemWidth) const
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const
const SCEV * getExitCount(const Loop *L, BasicBlock *ExitingBlock)
Return the number of times the backedge executes before the given exit would be taken; if not exactly...
This pass exposes codegen information to IR-level passes.
TargetTransformInfo & getTTI(const Function &F)
CacheLevel
The possible cache levels.
void perform(LoopInfo *LI)
Traverse the loop blocks and store the DFS result.
Definition: LoopIterator.h:180
bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, unsigned AddressSpace, const Instruction *I=nullptr) const
VectorType * getType() const
Overload to return most specific vector type.
unsigned getFlatAddressSpace() const
Returns the address space ID for a target&#39;s &#39;flat&#39; address space.
Information about a load/store intrinsic defined by the target.
static OperandValueKind getOperandInfo(Value *V, OperandValueProperties &OpProps)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition: PassManager.h:70
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
int getMinMaxReductionCost(Type *Ty, Type *CondTy, bool IsPairwiseForm, bool IsUnsigned) const
llvm::Optional< unsigned > getCacheSize(CacheLevel Level) const
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:43
This class represents a constant integer value.
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Shuffle elements of single source vector with any shuffle mask.