LLVM 19.0.0git
TargetTransformInfo.cpp
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1//===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
10#include "llvm/Analysis/CFG.h"
14#include "llvm/IR/CFG.h"
15#include "llvm/IR/Dominators.h"
16#include "llvm/IR/Instruction.h"
19#include "llvm/IR/Module.h"
20#include "llvm/IR/Operator.h"
24#include <optional>
25#include <utility>
26
27using namespace llvm;
28using namespace PatternMatch;
29
30#define DEBUG_TYPE "tti"
31
32static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
34 cl::desc("Recognize reduction patterns."));
35
37 "cache-line-size", cl::init(0), cl::Hidden,
38 cl::desc("Use this to override the target cache line size when "
39 "specified by the user."));
40
42 "min-page-size", cl::init(0), cl::Hidden,
43 cl::desc("Use this to override the target's minimum page size."));
44
46 "predictable-branch-threshold", cl::init(99), cl::Hidden,
48 "Use this to override the target's predictable branch threshold (%)."));
49
50namespace {
51/// No-op implementation of the TTI interface using the utility base
52/// classes.
53///
54/// This is used when no target specific information is available.
55struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
56 explicit NoTTIImpl(const DataLayout &DL)
57 : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
58};
59} // namespace
60
62 // If the loop has irreducible control flow, it can not be converted to
63 // Hardware loop.
64 LoopBlocksRPO RPOT(L);
65 RPOT.perform(&LI);
66 if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
67 return false;
68 return true;
69}
70
72 Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarizationCost,
73 bool TypeBasedOnly)
74 : II(dyn_cast<IntrinsicInst>(&CI)), RetTy(CI.getType()), IID(Id),
75 ScalarizationCost(ScalarizationCost) {
76
77 if (const auto *FPMO = dyn_cast<FPMathOperator>(&CI))
78 FMF = FPMO->getFastMathFlags();
79
80 if (!TypeBasedOnly)
81 Arguments.insert(Arguments.begin(), CI.arg_begin(), CI.arg_end());
83 ParamTys.insert(ParamTys.begin(), FTy->param_begin(), FTy->param_end());
84}
85
88 FastMathFlags Flags,
89 const IntrinsicInst *I,
90 InstructionCost ScalarCost)
91 : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
92 ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
93}
94
97 : RetTy(Ty), IID(Id) {
98
99 Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
100 ParamTys.reserve(Arguments.size());
101 for (unsigned Idx = 0, Size = Arguments.size(); Idx != Size; ++Idx)
102 ParamTys.push_back(Arguments[Idx]->getType());
103}
104
108 FastMathFlags Flags,
109 const IntrinsicInst *I,
110 InstructionCost ScalarCost)
111 : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
112 ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
113 Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
114}
115
117 // Match default options:
118 // - hardware-loop-counter-bitwidth = 32
119 // - hardware-loop-decrement = 1
121 LoopDecrement = ConstantInt::get(CountType, 1);
122}
123
125 LoopInfo &LI, DominatorTree &DT,
126 bool ForceNestedLoop,
128 SmallVector<BasicBlock *, 4> ExitingBlocks;
129 L->getExitingBlocks(ExitingBlocks);
130
131 for (BasicBlock *BB : ExitingBlocks) {
132 // If we pass the updated counter back through a phi, we need to know
133 // which latch the updated value will be coming from.
134 if (!L->isLoopLatch(BB)) {
136 continue;
137 }
138
139 const SCEV *EC = SE.getExitCount(L, BB);
140 if (isa<SCEVCouldNotCompute>(EC))
141 continue;
142 if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
143 if (ConstEC->getValue()->isZero())
144 continue;
145 } else if (!SE.isLoopInvariant(EC, L))
146 continue;
147
148 if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
149 continue;
150
151 // If this exiting block is contained in a nested loop, it is not eligible
152 // for insertion of the branch-and-decrement since the inner loop would
153 // end up messing up the value in the CTR.
154 if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
155 continue;
156
157 // We now have a loop-invariant count of loop iterations (which is not the
158 // constant zero) for which we know that this loop will not exit via this
159 // existing block.
160
161 // We need to make sure that this block will run on every loop iteration.
162 // For this to be true, we must dominate all blocks with backedges. Such
163 // blocks are in-loop predecessors to the header block.
164 bool NotAlways = false;
165 for (BasicBlock *Pred : predecessors(L->getHeader())) {
166 if (!L->contains(Pred))
167 continue;
168
169 if (!DT.dominates(BB, Pred)) {
170 NotAlways = true;
171 break;
172 }
173 }
174
175 if (NotAlways)
176 continue;
177
178 // Make sure this blocks ends with a conditional branch.
179 Instruction *TI = BB->getTerminator();
180 if (!TI)
181 continue;
182
183 if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
184 if (!BI->isConditional())
185 continue;
186
187 ExitBranch = BI;
188 } else
189 continue;
190
191 // Note that this block may not be the loop latch block, even if the loop
192 // has a latch block.
193 ExitBlock = BB;
194 ExitCount = EC;
195 break;
196 }
197
198 if (!ExitBlock)
199 return false;
200 return true;
201}
202
204 : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
205
207
209 : TTIImpl(std::move(Arg.TTIImpl)) {}
210
212 TTIImpl = std::move(RHS.TTIImpl);
213 return *this;
214}
215
217 return TTIImpl->getInliningThresholdMultiplier();
218}
219
220unsigned
222 return TTIImpl->getInliningCostBenefitAnalysisSavingsMultiplier();
223}
224
225unsigned
227 const {
228 return TTIImpl->getInliningCostBenefitAnalysisProfitableMultiplier();
229}
230
231unsigned
233 return TTIImpl->adjustInliningThreshold(CB);
234}
235
237 const AllocaInst *AI) const {
238 return TTIImpl->getCallerAllocaCost(CB, AI);
239}
240
242 return TTIImpl->getInlinerVectorBonusPercent();
243}
244
246 Type *PointeeType, const Value *Ptr, ArrayRef<const Value *> Operands,
247 Type *AccessType, TTI::TargetCostKind CostKind) const {
248 return TTIImpl->getGEPCost(PointeeType, Ptr, Operands, AccessType, CostKind);
249}
250
253 const TTI::PointersChainInfo &Info, Type *AccessTy,
255 assert((Base || !Info.isSameBase()) &&
256 "If pointers have same base address it has to be provided.");
257 return TTIImpl->getPointersChainCost(Ptrs, Base, Info, AccessTy, CostKind);
258}
259
261 const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI,
262 BlockFrequencyInfo *BFI) const {
263 return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
264}
265
269 enum TargetCostKind CostKind) const {
270 InstructionCost Cost = TTIImpl->getInstructionCost(U, Operands, CostKind);
272 "TTI should not produce negative costs!");
273 return Cost;
274}
275
277 return PredictableBranchThreshold.getNumOccurrences() > 0
279 : TTIImpl->getPredictableBranchThreshold();
280}
281
283 return TTIImpl->hasBranchDivergence(F);
284}
285
287 return TTIImpl->isSourceOfDivergence(V);
288}
289
291 return TTIImpl->isAlwaysUniform(V);
292}
293
295 unsigned ToAS) const {
296 return TTIImpl->isValidAddrSpaceCast(FromAS, ToAS);
297}
298
300 unsigned ToAS) const {
301 return TTIImpl->addrspacesMayAlias(FromAS, ToAS);
302}
303
305 return TTIImpl->getFlatAddressSpace();
306}
307
309 SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const {
310 return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
311}
312
314 unsigned ToAS) const {
315 return TTIImpl->isNoopAddrSpaceCast(FromAS, ToAS);
316}
317
319 unsigned AS) const {
320 return TTIImpl->canHaveNonUndefGlobalInitializerInAddressSpace(AS);
321}
322
324 return TTIImpl->getAssumedAddrSpace(V);
325}
326
328 return TTIImpl->isSingleThreaded();
329}
330
331std::pair<const Value *, unsigned>
333 return TTIImpl->getPredicatedAddrSpace(V);
334}
335
337 IntrinsicInst *II, Value *OldV, Value *NewV) const {
338 return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
339}
340
342 return TTIImpl->isLoweredToCall(F);
343}
344
347 TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
348 return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
349}
350
352 TailFoldingInfo *TFI) const {
353 return TTIImpl->preferPredicateOverEpilogue(TFI);
354}
355
357 bool IVUpdateMayOverflow) const {
358 return TTIImpl->getPreferredTailFoldingStyle(IVUpdateMayOverflow);
359}
360
361std::optional<Instruction *>
363 IntrinsicInst &II) const {
364 return TTIImpl->instCombineIntrinsic(IC, II);
365}
366
368 InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,
369 bool &KnownBitsComputed) const {
370 return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
371 KnownBitsComputed);
372}
373
375 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
376 APInt &UndefElts2, APInt &UndefElts3,
377 std::function<void(Instruction *, unsigned, APInt, APInt &)>
378 SimplifyAndSetOp) const {
379 return TTIImpl->simplifyDemandedVectorEltsIntrinsic(
380 IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
381 SimplifyAndSetOp);
382}
383
386 OptimizationRemarkEmitter *ORE) const {
387 return TTIImpl->getUnrollingPreferences(L, SE, UP, ORE);
388}
389
391 PeelingPreferences &PP) const {
392 return TTIImpl->getPeelingPreferences(L, SE, PP);
393}
394
396 return TTIImpl->isLegalAddImmediate(Imm);
397}
398
400 return TTIImpl->isLegalAddScalableImmediate(Imm);
401}
402
404 return TTIImpl->isLegalICmpImmediate(Imm);
405}
406
408 int64_t BaseOffset,
409 bool HasBaseReg, int64_t Scale,
410 unsigned AddrSpace,
411 Instruction *I,
412 int64_t ScalableOffset) const {
413 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
414 Scale, AddrSpace, I, ScalableOffset);
415}
416
418 const LSRCost &C2) const {
419 return TTIImpl->isLSRCostLess(C1, C2);
420}
421
423 return TTIImpl->isNumRegsMajorCostOfLSR();
424}
425
427 return TTIImpl->shouldFoldTerminatingConditionAfterLSR();
428}
429
431 return TTIImpl->isProfitableLSRChainElement(I);
432}
433
435 return TTIImpl->canMacroFuseCmp();
436}
437
439 ScalarEvolution *SE, LoopInfo *LI,
441 TargetLibraryInfo *LibInfo) const {
442 return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
443}
444
447 ScalarEvolution *SE) const {
448 return TTIImpl->getPreferredAddressingMode(L, SE);
449}
450
452 Align Alignment) const {
453 return TTIImpl->isLegalMaskedStore(DataType, Alignment);
454}
455
457 Align Alignment) const {
458 return TTIImpl->isLegalMaskedLoad(DataType, Alignment);
459}
460
462 Align Alignment) const {
463 return TTIImpl->isLegalNTStore(DataType, Alignment);
464}
465
466bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const {
467 return TTIImpl->isLegalNTLoad(DataType, Alignment);
468}
469
471 ElementCount NumElements) const {
472 return TTIImpl->isLegalBroadcastLoad(ElementTy, NumElements);
473}
474
476 Align Alignment) const {
477 return TTIImpl->isLegalMaskedGather(DataType, Alignment);
478}
479
481 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
482 const SmallBitVector &OpcodeMask) const {
483 return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask);
484}
485
487 Align Alignment) const {
488 return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
489}
490
492 Align Alignment) const {
493 return TTIImpl->forceScalarizeMaskedGather(DataType, Alignment);
494}
495
497 Align Alignment) const {
498 return TTIImpl->forceScalarizeMaskedScatter(DataType, Alignment);
499}
500
502 Align Alignment) const {
503 return TTIImpl->isLegalMaskedCompressStore(DataType, Alignment);
504}
505
507 Align Alignment) const {
508 return TTIImpl->isLegalMaskedExpandLoad(DataType, Alignment);
509}
510
512 Align Alignment) const {
513 return TTIImpl->isLegalStridedLoadStore(DataType, Alignment);
514}
515
517 return TTIImpl->enableOrderedReductions();
518}
519
520bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
521 return TTIImpl->hasDivRemOp(DataType, IsSigned);
522}
523
525 unsigned AddrSpace) const {
526 return TTIImpl->hasVolatileVariant(I, AddrSpace);
527}
528
530 return TTIImpl->prefersVectorizedAddressing();
531}
532
534 Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg,
535 int64_t Scale, unsigned AddrSpace) const {
536 InstructionCost Cost = TTIImpl->getScalingFactorCost(
537 Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace);
538 assert(Cost >= 0 && "TTI should not produce negative costs!");
539 return Cost;
540}
541
543 return TTIImpl->LSRWithInstrQueries();
544}
545
547 return TTIImpl->isTruncateFree(Ty1, Ty2);
548}
549
551 return TTIImpl->isProfitableToHoist(I);
552}
553
554bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
555
557 return TTIImpl->isTypeLegal(Ty);
558}
559
561 return TTIImpl->getRegUsageForType(Ty);
562}
563
565 return TTIImpl->shouldBuildLookupTables();
566}
567
569 Constant *C) const {
570 return TTIImpl->shouldBuildLookupTablesForConstant(C);
571}
572
574 return TTIImpl->shouldBuildRelLookupTables();
575}
576
578 return TTIImpl->useColdCCForColdCall(F);
579}
580
582 VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract,
584 return TTIImpl->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract,
585 CostKind);
586}
587
591 return TTIImpl->getOperandsScalarizationOverhead(Args, Tys, CostKind);
592}
593
595 return TTIImpl->supportsEfficientVectorElementLoadStore();
596}
597
599 return TTIImpl->supportsTailCalls();
600}
601
603 return TTIImpl->supportsTailCallFor(CB);
604}
605
607 bool LoopHasReductions) const {
608 return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
609}
610
612TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
613 return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
614}
615
617 return TTIImpl->enableSelectOptimize();
618}
619
621 const Instruction *I) const {
622 return TTIImpl->shouldTreatInstructionLikeSelect(I);
623}
624
626 return TTIImpl->enableInterleavedAccessVectorization();
627}
628
630 return TTIImpl->enableMaskedInterleavedAccessVectorization();
631}
632
634 return TTIImpl->isFPVectorizationPotentiallyUnsafe();
635}
636
637bool
639 unsigned BitWidth,
640 unsigned AddressSpace,
641 Align Alignment,
642 unsigned *Fast) const {
643 return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth,
644 AddressSpace, Alignment, Fast);
645}
646
648TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
649 return TTIImpl->getPopcntSupport(IntTyWidthInBit);
650}
651
653 return TTIImpl->haveFastSqrt(Ty);
654}
655
657 const Instruction *I) const {
658 return TTIImpl->isExpensiveToSpeculativelyExecute(I);
659}
660
662 return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
663}
664
666 InstructionCost Cost = TTIImpl->getFPOpCost(Ty);
667 assert(Cost >= 0 && "TTI should not produce negative costs!");
668 return Cost;
669}
670
672 unsigned Idx,
673 const APInt &Imm,
674 Type *Ty) const {
675 InstructionCost Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
676 assert(Cost >= 0 && "TTI should not produce negative costs!");
677 return Cost;
678}
679
683 InstructionCost Cost = TTIImpl->getIntImmCost(Imm, Ty, CostKind);
684 assert(Cost >= 0 && "TTI should not produce negative costs!");
685 return Cost;
686}
687
689 unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty,
692 TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst);
693 assert(Cost >= 0 && "TTI should not produce negative costs!");
694 return Cost;
695}
696
699 const APInt &Imm, Type *Ty,
702 TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);
703 assert(Cost >= 0 && "TTI should not produce negative costs!");
704 return Cost;
705}
706
708 const Instruction &Inst, const Function &Fn) const {
709 return TTIImpl->preferToKeepConstantsAttached(Inst, Fn);
710}
711
712unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const {
713 return TTIImpl->getNumberOfRegisters(ClassID);
714}
715
717 Type *Ty) const {
718 return TTIImpl->getRegisterClassForType(Vector, Ty);
719}
720
721const char *TargetTransformInfo::getRegisterClassName(unsigned ClassID) const {
722 return TTIImpl->getRegisterClassName(ClassID);
723}
724
727 return TTIImpl->getRegisterBitWidth(K);
728}
729
731 return TTIImpl->getMinVectorRegisterBitWidth();
732}
733
734std::optional<unsigned> TargetTransformInfo::getMaxVScale() const {
735 return TTIImpl->getMaxVScale();
736}
737
738std::optional<unsigned> TargetTransformInfo::getVScaleForTuning() const {
739 return TTIImpl->getVScaleForTuning();
740}
741
743 return TTIImpl->isVScaleKnownToBeAPowerOfTwo();
744}
745
748 return TTIImpl->shouldMaximizeVectorBandwidth(K);
749}
750
752 bool IsScalable) const {
753 return TTIImpl->getMinimumVF(ElemWidth, IsScalable);
754}
755
756unsigned TargetTransformInfo::getMaximumVF(unsigned ElemWidth,
757 unsigned Opcode) const {
758 return TTIImpl->getMaximumVF(ElemWidth, Opcode);
759}
760
761unsigned TargetTransformInfo::getStoreMinimumVF(unsigned VF, Type *ScalarMemTy,
762 Type *ScalarValTy) const {
763 return TTIImpl->getStoreMinimumVF(VF, ScalarMemTy, ScalarValTy);
764}
765
767 const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
768 return TTIImpl->shouldConsiderAddressTypePromotion(
769 I, AllowPromotionWithoutCommonHeader);
770}
771
773 return CacheLineSize.getNumOccurrences() > 0 ? CacheLineSize
774 : TTIImpl->getCacheLineSize();
775}
776
777std::optional<unsigned>
779 return TTIImpl->getCacheSize(Level);
780}
781
782std::optional<unsigned>
784 return TTIImpl->getCacheAssociativity(Level);
785}
786
787std::optional<unsigned> TargetTransformInfo::getMinPageSize() const {
788 return MinPageSize.getNumOccurrences() > 0 ? MinPageSize
789 : TTIImpl->getMinPageSize();
790}
791
793 return TTIImpl->getPrefetchDistance();
794}
795
797 unsigned NumMemAccesses, unsigned NumStridedMemAccesses,
798 unsigned NumPrefetches, bool HasCall) const {
799 return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
800 NumPrefetches, HasCall);
801}
802
804 return TTIImpl->getMaxPrefetchIterationsAhead();
805}
806
808 return TTIImpl->enableWritePrefetching();
809}
810
812 return TTIImpl->shouldPrefetchAddressSpace(AS);
813}
814
816 return TTIImpl->getMaxInterleaveFactor(VF);
817}
818
823
824 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
825 if (const auto *CI = dyn_cast<ConstantInt>(V)) {
826 if (CI->getValue().isPowerOf2())
827 OpProps = OP_PowerOf2;
828 else if (CI->getValue().isNegatedPowerOf2())
829 OpProps = OP_NegatedPowerOf2;
830 }
831 return {OK_UniformConstantValue, OpProps};
832 }
833
834 // A broadcast shuffle creates a uniform value.
835 // TODO: Add support for non-zero index broadcasts.
836 // TODO: Add support for different source vector width.
837 if (const auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
838 if (ShuffleInst->isZeroEltSplat())
839 OpInfo = OK_UniformValue;
840
841 const Value *Splat = getSplatValue(V);
842
843 // Check for a splat of a constant or for a non uniform vector of constants
844 // and check if the constant(s) are all powers of two.
845 if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
847 if (Splat) {
849 if (auto *CI = dyn_cast<ConstantInt>(Splat)) {
850 if (CI->getValue().isPowerOf2())
851 OpProps = OP_PowerOf2;
852 else if (CI->getValue().isNegatedPowerOf2())
853 OpProps = OP_NegatedPowerOf2;
854 }
855 } else if (const auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
856 bool AllPow2 = true, AllNegPow2 = true;
857 for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
858 if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I))) {
859 AllPow2 &= CI->getValue().isPowerOf2();
860 AllNegPow2 &= CI->getValue().isNegatedPowerOf2();
861 if (AllPow2 || AllNegPow2)
862 continue;
863 }
864 AllPow2 = AllNegPow2 = false;
865 break;
866 }
867 OpProps = AllPow2 ? OP_PowerOf2 : OpProps;
868 OpProps = AllNegPow2 ? OP_NegatedPowerOf2 : OpProps;
869 }
870 }
871
872 // Check for a splat of a uniform value. This is not loop aware, so return
873 // true only for the obviously uniform cases (argument, globalvalue)
874 if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
875 OpInfo = OK_UniformValue;
876
877 return {OpInfo, OpProps};
878}
879
881 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
882 OperandValueInfo Op1Info, OperandValueInfo Op2Info,
883 ArrayRef<const Value *> Args, const Instruction *CxtI,
884 const TargetLibraryInfo *TLibInfo) const {
885
886 // Use call cost for frem intructions that have platform specific vector math
887 // functions, as those will be replaced with calls later by SelectionDAG or
888 // ReplaceWithVecLib pass.
889 if (TLibInfo && Opcode == Instruction::FRem) {
890 VectorType *VecTy = dyn_cast<VectorType>(Ty);
891 LibFunc Func;
892 if (VecTy &&
893 TLibInfo->getLibFunc(Instruction::FRem, Ty->getScalarType(), Func) &&
894 TLibInfo->isFunctionVectorizable(TLibInfo->getName(Func),
895 VecTy->getElementCount()))
896 return getCallInstrCost(nullptr, VecTy, {VecTy, VecTy}, CostKind);
897 }
898
900 TTIImpl->getArithmeticInstrCost(Opcode, Ty, CostKind,
901 Op1Info, Op2Info,
902 Args, CxtI);
903 assert(Cost >= 0 && "TTI should not produce negative costs!");
904 return Cost;
905}
906
908 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
909 const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind) const {
911 TTIImpl->getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind);
912 assert(Cost >= 0 && "TTI should not produce negative costs!");
913 return Cost;
914}
915
917 ShuffleKind Kind, VectorType *Ty, ArrayRef<int> Mask,
919 ArrayRef<const Value *> Args, const Instruction *CxtI) const {
920 InstructionCost Cost = TTIImpl->getShuffleCost(Kind, Ty, Mask, CostKind,
921 Index, SubTp, Args, CxtI);
922 assert(Cost >= 0 && "TTI should not produce negative costs!");
923 return Cost;
924}
925
928 if (!I)
930
931 auto getLoadStoreKind = [](const Value *V, unsigned LdStOp, unsigned MaskedOp,
932 unsigned GatScatOp) {
933 const Instruction *I = dyn_cast<Instruction>(V);
934 if (!I)
936
937 if (I->getOpcode() == LdStOp)
939
940 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
941 if (II->getIntrinsicID() == MaskedOp)
943 if (II->getIntrinsicID() == GatScatOp)
945 }
946
948 };
949
950 switch (I->getOpcode()) {
951 case Instruction::ZExt:
952 case Instruction::SExt:
953 case Instruction::FPExt:
954 return getLoadStoreKind(I->getOperand(0), Instruction::Load,
955 Intrinsic::masked_load, Intrinsic::masked_gather);
956 case Instruction::Trunc:
957 case Instruction::FPTrunc:
958 if (I->hasOneUse())
959 return getLoadStoreKind(*I->user_begin(), Instruction::Store,
960 Intrinsic::masked_store,
961 Intrinsic::masked_scatter);
962 break;
963 default:
965 }
966
968}
969
971 unsigned Opcode, Type *Dst, Type *Src, CastContextHint CCH,
973 assert((I == nullptr || I->getOpcode() == Opcode) &&
974 "Opcode should reflect passed instruction.");
976 TTIImpl->getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
977 assert(Cost >= 0 && "TTI should not produce negative costs!");
978 return Cost;
979}
980
982 unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const {
984 TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
985 assert(Cost >= 0 && "TTI should not produce negative costs!");
986 return Cost;
987}
988
990 unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I) const {
991 assert((I == nullptr || I->getOpcode() == Opcode) &&
992 "Opcode should reflect passed instruction.");
993 InstructionCost Cost = TTIImpl->getCFInstrCost(Opcode, CostKind, I);
994 assert(Cost >= 0 && "TTI should not produce negative costs!");
995 return Cost;
996}
997
999 unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred,
1000 TTI::TargetCostKind CostKind, const Instruction *I) const {
1001 assert((I == nullptr || I->getOpcode() == Opcode) &&
1002 "Opcode should reflect passed instruction.");
1004 TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
1005 assert(Cost >= 0 && "TTI should not produce negative costs!");
1006 return Cost;
1007}
1008
1010 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index,
1011 Value *Op0, Value *Op1) const {
1012 // FIXME: Assert that Opcode is either InsertElement or ExtractElement.
1013 // This is mentioned in the interface description and respected by all
1014 // callers, but never asserted upon.
1016 TTIImpl->getVectorInstrCost(Opcode, Val, CostKind, Index, Op0, Op1);
1017 assert(Cost >= 0 && "TTI should not produce negative costs!");
1018 return Cost;
1019}
1020
1024 unsigned Index) const {
1025 // FIXME: Assert that Opcode is either InsertElement or ExtractElement.
1026 // This is mentioned in the interface description and respected by all
1027 // callers, but never asserted upon.
1028 InstructionCost Cost = TTIImpl->getVectorInstrCost(I, Val, CostKind, Index);
1029 assert(Cost >= 0 && "TTI should not produce negative costs!");
1030 return Cost;
1031}
1032
1034 Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts,
1036 InstructionCost Cost = TTIImpl->getReplicationShuffleCost(
1037 EltTy, ReplicationFactor, VF, DemandedDstElts, CostKind);
1038 assert(Cost >= 0 && "TTI should not produce negative costs!");
1039 return Cost;
1040}
1041
1043 unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
1045 const Instruction *I) const {
1046 assert((I == nullptr || I->getOpcode() == Opcode) &&
1047 "Opcode should reflect passed instruction.");
1048 InstructionCost Cost = TTIImpl->getMemoryOpCost(
1049 Opcode, Src, Alignment, AddressSpace, CostKind, OpInfo, I);
1050 assert(Cost >= 0 && "TTI should not produce negative costs!");
1051 return Cost;
1052}
1053
1055 unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
1057 InstructionCost Cost = TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment,
1059 assert(Cost >= 0 && "TTI should not produce negative costs!");
1060 return Cost;
1061}
1062
1064 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
1065 Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) const {
1066 InstructionCost Cost = TTIImpl->getGatherScatterOpCost(
1067 Opcode, DataTy, Ptr, VariableMask, Alignment, CostKind, I);
1068 assert((!Cost.isValid() || Cost >= 0) &&
1069 "TTI should not produce negative costs!");
1070 return Cost;
1071}
1072
1074 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
1075 Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) const {
1076 InstructionCost Cost = TTIImpl->getStridedMemoryOpCost(
1077 Opcode, DataTy, Ptr, VariableMask, Alignment, CostKind, I);
1078 assert(Cost >= 0 && "TTI should not produce negative costs!");
1079 return Cost;
1080}
1081
1083 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
1084 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
1085 bool UseMaskForCond, bool UseMaskForGaps) const {
1086 InstructionCost Cost = TTIImpl->getInterleavedMemoryOpCost(
1087 Opcode, VecTy, Factor, Indices, Alignment, AddressSpace, CostKind,
1088 UseMaskForCond, UseMaskForGaps);
1089 assert(Cost >= 0 && "TTI should not produce negative costs!");
1090 return Cost;
1091}
1092
1096 InstructionCost Cost = TTIImpl->getIntrinsicInstrCost(ICA, CostKind);
1097 assert(Cost >= 0 && "TTI should not produce negative costs!");
1098 return Cost;
1099}
1100
1103 ArrayRef<Type *> Tys,
1105 InstructionCost Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys, CostKind);
1106 assert(Cost >= 0 && "TTI should not produce negative costs!");
1107 return Cost;
1108}
1109
1111 return TTIImpl->getNumberOfParts(Tp);
1112}
1113
1116 const SCEV *Ptr) const {
1117 InstructionCost Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
1118 assert(Cost >= 0 && "TTI should not produce negative costs!");
1119 return Cost;
1120}
1121
1123 InstructionCost Cost = TTIImpl->getMemcpyCost(I);
1124 assert(Cost >= 0 && "TTI should not produce negative costs!");
1125 return Cost;
1126}
1127
1129 return TTIImpl->getMaxMemIntrinsicInlineSizeThreshold();
1130}
1131
1133 unsigned Opcode, VectorType *Ty, std::optional<FastMathFlags> FMF,
1136 TTIImpl->getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);
1137 assert(Cost >= 0 && "TTI should not produce negative costs!");
1138 return Cost;
1139}
1140
1145 TTIImpl->getMinMaxReductionCost(IID, Ty, FMF, CostKind);
1146 assert(Cost >= 0 && "TTI should not produce negative costs!");
1147 return Cost;
1148}
1149
1151 unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty,
1153 return TTIImpl->getExtendedReductionCost(Opcode, IsUnsigned, ResTy, Ty, FMF,
1154 CostKind);
1155}
1156
1158 bool IsUnsigned, Type *ResTy, VectorType *Ty,
1160 return TTIImpl->getMulAccReductionCost(IsUnsigned, ResTy, Ty, CostKind);
1161}
1162
1165 return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
1166}
1167
1169 MemIntrinsicInfo &Info) const {
1170 return TTIImpl->getTgtMemIntrinsic(Inst, Info);
1171}
1172
1174 return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
1175}
1176
1178 IntrinsicInst *Inst, Type *ExpectedType) const {
1179 return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
1180}
1181
1183 LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
1184 unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign,
1185 std::optional<uint32_t> AtomicElementSize) const {
1186 return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
1187 DestAddrSpace, SrcAlign, DestAlign,
1188 AtomicElementSize);
1189}
1190
1192 SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
1193 unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
1194 unsigned SrcAlign, unsigned DestAlign,
1195 std::optional<uint32_t> AtomicCpySize) const {
1196 TTIImpl->getMemcpyLoopResidualLoweringType(
1197 OpsOut, Context, RemainingBytes, SrcAddrSpace, DestAddrSpace, SrcAlign,
1198 DestAlign, AtomicCpySize);
1199}
1200
1202 const Function *Callee) const {
1203 return TTIImpl->areInlineCompatible(Caller, Callee);
1204}
1205
1206unsigned
1208 const CallBase &Call,
1209 unsigned DefaultCallPenalty) const {
1210 return TTIImpl->getInlineCallPenalty(F, Call, DefaultCallPenalty);
1211}
1212
1214 const Function *Caller, const Function *Callee,
1215 const ArrayRef<Type *> &Types) const {
1216 return TTIImpl->areTypesABICompatible(Caller, Callee, Types);
1217}
1218
1220 Type *Ty) const {
1221 return TTIImpl->isIndexedLoadLegal(Mode, Ty);
1222}
1223
1225 Type *Ty) const {
1226 return TTIImpl->isIndexedStoreLegal(Mode, Ty);
1227}
1228
1230 return TTIImpl->getLoadStoreVecRegBitWidth(AS);
1231}
1232
1234 return TTIImpl->isLegalToVectorizeLoad(LI);
1235}
1236
1238 return TTIImpl->isLegalToVectorizeStore(SI);
1239}
1240
1242 unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1243 return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
1244 AddrSpace);
1245}
1246
1248 unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1249 return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
1250 AddrSpace);
1251}
1252
1254 const RecurrenceDescriptor &RdxDesc, ElementCount VF) const {
1255 return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF);
1256}
1257
1259 return TTIImpl->isElementTypeLegalForScalableVector(Ty);
1260}
1261
1263 unsigned LoadSize,
1264 unsigned ChainSizeInBytes,
1265 VectorType *VecTy) const {
1266 return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
1267}
1268
1270 unsigned StoreSize,
1271 unsigned ChainSizeInBytes,
1272 VectorType *VecTy) const {
1273 return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
1274}
1275
1277 ReductionFlags Flags) const {
1278 return TTIImpl->preferInLoopReduction(Opcode, Ty, Flags);
1279}
1280
1282 unsigned Opcode, Type *Ty, ReductionFlags Flags) const {
1283 return TTIImpl->preferPredicatedReductionSelect(Opcode, Ty, Flags);
1284}
1285
1287 return TTIImpl->preferEpilogueVectorization();
1288}
1289
1292 return TTIImpl->getVPLegalizationStrategy(VPI);
1293}
1294
1296 return TTIImpl->hasArmWideBranch(Thumb);
1297}
1298
1300 return TTIImpl->getMaxNumArgs();
1301}
1302
1304 return TTIImpl->shouldExpandReduction(II);
1305}
1306
1308 return TTIImpl->getGISelRematGlobalCost();
1309}
1310
1312 return TTIImpl->getMinTripCountTailFoldingThreshold();
1313}
1314
1316 return TTIImpl->supportsScalableVectors();
1317}
1318
1320 return TTIImpl->enableScalableVectorization();
1321}
1322
1323bool TargetTransformInfo::hasActiveVectorLength(unsigned Opcode, Type *DataType,
1324 Align Alignment) const {
1325 return TTIImpl->hasActiveVectorLength(Opcode, DataType, Alignment);
1326}
1327
1329
1330TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1331
1333 std::function<Result(const Function &)> TTICallback)
1334 : TTICallback(std::move(TTICallback)) {}
1335
1338 return TTICallback(F);
1339}
1340
1341AnalysisKey TargetIRAnalysis::Key;
1342
1343TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1344 return Result(F.getParent()->getDataLayout());
1345}
1346
1347// Register the basic pass.
1349 "Target Transform Information", false, true)
1351
1352void TargetTransformInfoWrapperPass::anchor() {}
1353
1355 : ImmutablePass(ID) {
1358}
1359
1361 TargetIRAnalysis TIRA)
1362 : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1365}
1366
1368 FunctionAnalysisManager DummyFAM;
1369 TTI = TIRA.run(F, DummyFAM);
1370 return *TTI;
1371}
1372
1375 return new TargetTransformInfoWrapperPass(std::move(TIRA));
1376}
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
return RetTy
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Size
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
mir Rename Register Operands
Module.h This file contains the declarations for the Module class.
LLVMContext & Context
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static SymbolRef::Type getType(const Symbol *Sym)
Definition: TapiFile.cpp:40
This file provides helpers for the implementation of a TargetTransformInfo-conforming class.
static cl::opt< unsigned > PredictableBranchThreshold("predictable-branch-threshold", cl::init(99), cl::Hidden, cl::desc("Use this to override the target's predictable branch threshold (%)."))
static cl::opt< bool > EnableReduxCost("costmodel-reduxcost", cl::init(false), cl::Hidden, cl::desc("Recognize reduction patterns."))
static cl::opt< unsigned > MinPageSize("min-page-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target's minimum page size."))
static cl::opt< unsigned > CacheLineSize("cache-line-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target cache line size when " "specified by the user."))
This pass exposes codegen information to IR-level passes.
Value * RHS
Class for arbitrary precision integers.
Definition: APInt.h:76
an instruction to allocate memory on the stack
Definition: Instructions.h:59
A container for analyses that lazily runs them and caches their results.
Definition: PassManager.h:321
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
iterator end() const
Definition: ArrayRef.h:154
iterator begin() const
Definition: ArrayRef.h:153
A cache of @llvm.assume calls within a function.
LLVM Basic Block Representation.
Definition: BasicBlock.h:60
LLVMContext & getContext() const
Get the context in which this basic block lives.
Definition: BasicBlock.cpp:168
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Conditional or Unconditional Branch instruction.
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1494
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation or the function signa...
Definition: InstrTypes.h:1742
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
Definition: InstrTypes.h:1662
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
Definition: InstrTypes.h:1668
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:993
This is an important base class in LLVM.
Definition: Constant.h:41
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:162
bool dominates(const BasicBlock *BB, const Use &U) const
Return true if the (end of the) basic block BB dominates the use U.
Definition: Dominators.cpp:122
Convenience struct for specifying and reasoning about fast-math flags.
Definition: FMF.h:20
Class to represent function types.
Definition: DerivedTypes.h:103
param_iterator param_begin() const
Definition: DerivedTypes.h:128
param_iterator param_end() const
Definition: DerivedTypes.h:129
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:201
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:282
The core instruction combiner logic.
Definition: InstCombiner.h:47
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Definition: DerivedTypes.h:72
IntrinsicCostAttributes(Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarCost=InstructionCost::getInvalid(), bool TypeBasedOnly=false)
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:47
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:54
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:184
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
void getExitingBlocks(SmallVectorImpl< BlockT * > &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
BlockT * getHeader() const
bool isLoopLatch(const BlockT *BB) const
Wrapper class to LoopBlocksDFS that provides a standard begin()/end() interface for the DFS reverse p...
Definition: LoopIterator.h:172
void perform(const LoopInfo *LI)
Traverse the loop blocks and store the DFS result.
Definition: LoopIterator.h:180
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:44
The optimization diagnostic interface.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Analysis providing profile information.
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:71
This class represents a constant integer value.
This class represents an analyzed expression in the program.
The main scalar evolution driver.
uint64_t getTypeSizeInBits(Type *Ty) const
Return the size in bits of the specified type, for which isSCEVable must return true.
bool isLoopInvariant(const SCEV *S, const Loop *L)
Return true if the value of the given SCEV is unchanging in the specified loop.
const SCEV * getExitCount(const Loop *L, const BasicBlock *ExitingBlock, ExitCountKind Kind=Exact)
Return the number of times the backedge executes before the given exit would be taken; if not exactly...
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
An instruction for storing to memory.
Definition: Instructions.h:317
Multiway switch.
Analysis pass providing the TargetTransformInfo.
Result run(const Function &F, FunctionAnalysisManager &)
TargetTransformInfo Result
TargetIRAnalysis()
Default construct a target IR analysis.
Provides information about what library functions are available for the current target.
bool getLibFunc(StringRef funcName, LibFunc &F) const
Searches for a particular function name.
StringRef getName(LibFunc F) const
bool isFunctionVectorizable(StringRef F, const ElementCount &VF) const
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Wrapper pass for TargetTransformInfo.
TargetTransformInfoWrapperPass()
We must provide a default constructor for the pass but it should never be used.
TargetTransformInfo & getTTI(const Function &F)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
bool isLegalToVectorizeLoad(LoadInst *LI) const
std::optional< unsigned > getVScaleForTuning() const
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const
Return false if a AS0 address cannot possibly alias a AS1 address.
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Return true if the target supports masked scatter.
InstructionCost getStridedMemoryOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
bool shouldBuildLookupTables() const
Return true if switches should be turned into lookup tables for the target.
bool isLegalToVectorizeStore(StoreInst *SI) const
bool enableAggressiveInterleaving(bool LoopHasReductions) const
Don't restrict interleaved unrolling to small loops.
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, std::optional< uint32_t > AtomicCpySize=std::nullopt) const
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a compariso...
bool preferInLoopReduction(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
bool supportsEfficientVectorElementLoadStore() const
If target has efficient vector element load/store instructions, it can return true here so that inser...
bool isAlwaysUniform(const Value *V) const
unsigned getAssumedAddrSpace(const Value *V) const
bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2) const
Return true if LSR cost of C1 is lower than C2.
bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const
Return true if the target supports masked expand load.
bool prefersVectorizedAddressing() const
Return true if target doesn't mind addresses in vectors.
bool hasBranchDivergence(const Function *F=nullptr) const
Return true if branch divergence exists.
MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE=nullptr, const SCEV *Ptr=nullptr) const
void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const
Get target-customized preferences for the generic loop unrolling transformation.
bool shouldBuildLookupTablesForConstant(Constant *C) const
Return true if switches should be turned into lookup tables containing this constant value for the ta...
bool shouldFoldTerminatingConditionAfterLSR() const
Return true if LSR should attempts to replace a use of an otherwise dead primary IV in the latch cond...
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
Estimate the overhead of scalarizing an instructions unique non-constant operands.
bool supportsTailCallFor(const CallBase *CB) const
If target supports tail call on CB.
std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Targets can implement their own combinations for target-specific intrinsics.
bool isProfitableLSRChainElement(Instruction *I) const
TypeSize getRegisterBitWidth(RegisterKind K) const
unsigned getInlineCallPenalty(const Function *F, const CallBase &Call, unsigned DefaultCallPenalty) const
Returns a penalty for invoking call Call in F.
bool isExpensiveToSpeculativelyExecute(const Instruction *I) const
Return true if the cost of the instruction is too high to speculatively execute and should be kept be...
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Return true if the target supports masked gather.
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, OperandValueInfo OpdInfo={OK_AnyValue, OP_None}, const Instruction *I=nullptr) const
std::optional< unsigned > getMaxVScale() const
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, bool UseMaskForCond=false, bool UseMaskForGaps=false) const
std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Can be used to implement target-specific instruction combining.
bool enableOrderedReductions() const
Return true if we should be enabling ordered reductions for the target.
unsigned getInliningCostBenefitAnalysisProfitableMultiplier() const
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of vector reduction intrinsics.
unsigned getAtomicMemIntrinsicMaxElementSize() const
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
bool LSRWithInstrQueries() const
Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAdd...
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
bool shouldTreatInstructionLikeSelect(const Instruction *I) const
Should the Select Optimization pass treat the given instruction like a select, potentially converting...
bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
TailFoldingStyle getPreferredTailFoldingStyle(bool IVUpdateMayOverflow=true) const
Query the target what the preferred style of tail folding is.
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, Type *AccessType=nullptr, TargetCostKind CostKind=TCK_SizeAndLatency) const
Estimate the cost of a GEP operation when lowered.
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
unsigned getRegUsageForType(Type *Ty) const
Returns the estimated number of registers required to represent Ty.
bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
\Returns true if the target supports broadcasting a load to a vector of type <NumElements x ElementTy...
bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const
std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of a reduc...
static OperandValueInfo getOperandInfo(const Value *V)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of an Add ...
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0, Instruction *I=nullptr, int64_t ScalableOffset=0) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Return hardware support for population count.
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
bool isElementTypeLegalForScalableVector(Type *Ty) const
bool forceScalarizeMaskedGather(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.gather intrinsics.
unsigned getMaxPrefetchIterationsAhead() const
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Return true if globals in this address space can have initializers other than undef.
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
bool enableMaskedInterleavedAccessVectorization() const
Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore v...
InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind, Instruction *Inst=nullptr) const
Return the expected cost of materialization for the given integer immediate of the specified type for...
bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const
Return true if the target supports strided load.
TargetTransformInfo & operator=(TargetTransformInfo &&RHS)
InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF=FastMathFlags(), TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
TargetCostKind
The kind of cost model.
@ TCK_RecipThroughput
Reciprocal throughput.
bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
bool enableSelectOptimize() const
Should the Select Optimization pass be enabled and ran.
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Return any intrinsic address operand indexes which may be rewritten if they use a flat address space ...
OperandValueProperties
Additional properties of an operand's values.
InstructionCost getPointersChainCost(ArrayRef< const Value * > Ptrs, const Value *Base, const PointersChainInfo &Info, Type *AccessTy, TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Estimate the cost of a chain of pointers (typically pointer operands of a chain of loads or stores wi...
bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
bool isSourceOfDivergence(const Value *V) const
Returns whether V is a source of divergence.
bool isLegalICmpImmediate(int64_t Imm) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
bool isTypeLegal(Type *Ty) const
Return true if this type is legal.
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
std::optional< unsigned > getCacheAssociativity(CacheLevel Level) const
bool isLegalNTLoad(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal load.
InstructionCost getMemcpyCost(const Instruction *I) const
unsigned adjustInliningThreshold(const CallBase *CB) const
bool isLegalAddImmediate(int64_t Imm) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Return true if the target can save a compare for loop count, for example hardware loop saves a compar...
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Rewrite intrinsic call II such that OldV will be replaced with NewV, which has a different address sp...
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Some HW prefetchers can handle accesses up to a certain constant stride.
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
bool shouldPrefetchAddressSpace(unsigned AS) const
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Return the expected cost of materializing for the given integer immediate of the specified type.
unsigned getMinVectorRegisterBitWidth() const
bool isLegalNTStore(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal store.
unsigned getFlatAddressSpace() const
Returns the address space ID for a target's 'flat' address space.
bool preferToKeepConstantsAttached(const Instruction &Inst, const Function &Fn) const
It can be advantageous to detach complex constants from their uses to make their generation cheaper.
bool hasArmWideBranch(bool Thumb) const
const char * getRegisterClassName(unsigned ClassID) const
bool preferEpilogueVectorization() const
Return true if the loop vectorizer should consider vectorizing an otherwise scalar epilogue loop.
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor,...
unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr, const TargetLibraryInfo *TLibInfo=nullptr) const
This is an approximation of reciprocal throughput of a math/logic op.
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace=0, Align Alignment=Align(1), unsigned *Fast=nullptr) const
Determine if the target supports unaligned memory accesses.
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
bool hasActiveVectorLength(unsigned Opcode, Type *DataType, Align Alignment) const
PopcntSupportKind
Flags indicating the kind of support for population count.
InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const
Return the expected cost for the given integer when optimising for size.
AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Return the preferred addressing mode LSR should make efforts to generate.
bool isLoweredToCall(const Function *F) const
Test whether calls to a function lower to actual program function calls.
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Query the target whether it would be profitable to convert the given loop into a hardware loop.
unsigned getInliningThresholdMultiplier() const
unsigned getNumberOfRegisters(unsigned ClassID) const
bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
Return true if this is an alternating opcode pattern that can be lowered to a single instruction on t...
bool isProfitableToHoist(Instruction *I) const
Return true if it is profitable to hoist instruction in the then/else to before if.
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Return true if the given instruction (assumed to be a memory access instruction) has a volatile varia...
bool isLegalMaskedCompressStore(Type *DataType, Align Alignment) const
Return true if the target supports masked compress store.
std::optional< unsigned > getMinPageSize() const
bool isFPVectorizationPotentiallyUnsafe() const
Indicate that it is potentially unsafe to automatically vectorize floating-point operations because t...
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
Return true if the target supports masked store.
bool shouldBuildRelLookupTables() const
Return true if lookup tables should be turned into relative lookup tables.
unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, Type *ScalarValTy) const
std::optional< unsigned > getCacheSize(CacheLevel Level) const
std::optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Can be used to implement target-specific instruction combining.
bool isLegalAddScalableImmediate(int64_t Imm) const
Return true if adding the specified scalable immediate is legal, that is the target has add instructi...
bool hasDivRemOp(Type *DataType, bool IsSigned) const
Return true if the target has a unified operation to calculate division and remainder.
InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Returns the cost estimation for alternating opcode pattern that can be lowered to a single instructio...
bool enableInterleavedAccessVectorization() const
Enable matching of interleaved access groups.
unsigned getMinTripCountTailFoldingThreshold() const
InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TargetCostKind CostKind) const
Estimate the cost of a given IR user when lowered.
unsigned getMaxInterleaveFactor(ElementCount VF) const
bool isNumRegsMajorCostOfLSR() const
Return true if LSR major cost is number of registers.
unsigned getInliningCostBenefitAnalysisSavingsMultiplier() const
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const
unsigned getGISelRematGlobalCost() const
MemIndexedMode
The type of load/store indexing.
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
bool useColdCCForColdCall(Function &F) const
Return true if the input function which is cold at all call sites, should use coldcc calling conventi...
InstructionCost getFPOpCost(Type *Ty) const
Return the expected cost of supporting the floating point operation of the specified type.
bool supportsTailCalls() const
If the target supports tail calls.
bool canMacroFuseCmp() const
Return true if the target can fuse a compare and branch.
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
Query the target whether the specified address space cast from FromAS to ToAS is valid.
unsigned getNumberOfParts(Type *Tp) const
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, std::optional< uint32_t > AtomicElementSize=std::nullopt) const
bool isTruncateFree(Type *Ty1, Type *Ty2) const
Return true if it's free to truncate a value of type Ty1 to type Ty2.
InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask=std::nullopt, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, int Index=0, VectorType *SubTp=nullptr, ArrayRef< const Value * > Args=std::nullopt, const Instruction *CxtI=nullptr) const
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind) const
Estimate the overhead of scalarizing an instruction.
bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const
Query the target whether it would be prefered to create a predicated vector loop, which can avoid the...
bool forceScalarizeMaskedScatter(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.scatter intrinsics.
bool haveFastSqrt(Type *Ty) const
Return true if the hardware has a fast square-root instruction.
bool shouldExpandReduction(const IntrinsicInst *II) const
TargetTransformInfo(T Impl)
Construct a TTI object using a type implementing the Concept API below.
uint64_t getMaxMemIntrinsicInlineSizeThreshold() const
Returns the maximum memset / memcpy size in bytes that still makes it profitable to inline the call.
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index=-1, Value *Op0=nullptr, Value *Op1=nullptr) const
ShuffleKind
The various kinds of shuffle patterns for vector queries.
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, PeelingPreferences &PP) const
Get target-customized preferences for the generic loop peeling transformation.
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency) const
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
CastContextHint
Represents a hint about the context in which a cast is used.
@ Masked
The cast is used with a masked load/store.
@ None
The cast is not used with a load/store of any kind.
@ Normal
The cast is used with a normal load/store.
@ GatherScatter
The cast is used with a gather/scatter.
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
OperandValueKind
Additional information about an operand's possible values.
CacheLevel
The possible cache levels.
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
Return true if the target supports masked load.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
static IntegerType * getInt32Ty(LLVMContext &C)
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:348
This is the common base class for vector predication intrinsics.
LLVM Value Representation.
Definition: Value.h:74
Base class of all SIMD vector types.
Definition: DerivedTypes.h:403
ElementCount getElementCount() const
Return an ElementCount instance to represent the (possibly scalable) number of elements in the vector...
Definition: DerivedTypes.h:641
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Length
Definition: DWP.cpp:456
void initializeTargetTransformInfoWrapperPassPass(PassRegistry &)
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition: Casting.h:649
AddressSpace
Definition: NVPTXBaseInfo.h:21
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:191
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1849
auto predecessors(const MachineBasicBlock *BB)
InstructionCost Cost
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition: Analysis.h:26
Attributes of a target dependent hardware loop.
bool canAnalyze(LoopInfo &LI)
bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
Information about a load/store intrinsic defined by the target.
Returns options for expansion of memcmp. IsZeroCmp is.
Describe known properties for a set of pointers.
Flags describing the kind of vector reduction.
Parameters that control the generic loop unrolling transformation.