65#define DEBUG_TYPE "twoaddressinstruction"
67STATISTIC(NumTwoAddressInstrs,
"Number of two-address instructions");
68STATISTIC(NumCommuted ,
"Number of instructions commuted to coalesce");
69STATISTIC(NumAggrCommuted ,
"Number of instructions aggressively commuted");
70STATISTIC(NumConvertedTo3Addr,
"Number of instructions promoted to 3-address");
71STATISTIC(NumReSchedUps,
"Number of instructions re-scheduled up");
72STATISTIC(NumReSchedDowns,
"Number of instructions re-scheduled down");
77 cl::desc(
"Coalesce copies by rescheduling (default=true)"),
84 cl::desc(
"Maximum number of dataflow edges to traverse when evaluating "
85 "the benefit of commuting operands"));
123 bool noUseAfterLastDef(
Register Reg,
unsigned Dist,
unsigned &LastDef);
126 bool &IsSrcPhys,
bool &IsDstPhys)
const;
136 bool &IsDstPhys)
const;
151 unsigned RegBIdx,
unsigned RegCIdx,
unsigned Dist);
168 unsigned SrcIdx,
unsigned DstIdx,
169 unsigned &Dist,
bool shouldOnlyCommute);
184 void processTiedPairs(
MachineInstr *
MI, TiedPairList&,
unsigned &Dist);
186 bool processStatepoint(
MachineInstr *
MI, TiedOperandMap &TiedOperands);
213char TwoAddressInstructionPass::ID = 0;
218 "Two-Address instruction pass",
false,
false)
225TwoAddressInstructionPass::getSingleDef(
Register Reg,
229 if (
DefMI.getParent() != BB ||
DefMI.isDebugValue())
233 else if (Ret != &
DefMI)
246bool TwoAddressInstructionPass::isRevCopyChain(
Register FromReg,
Register ToReg,
249 for (
int i = 0; i < Maxlen; i++) {
251 if (!Def || !
Def->isCopy())
254 TmpReg =
Def->getOperand(1).getReg();
266bool TwoAddressInstructionPass::noUseAfterLastDef(
Register Reg,
unsigned Dist,
269 unsigned LastUse = Dist;
272 if (
MI->getParent() !=
MBB ||
MI->isDebugValue())
275 if (DI == DistanceMap.
end())
277 if (MO.isUse() && DI->second < LastUse)
278 LastUse = DI->second;
279 if (MO.isDef() && DI->second > LastDef)
280 LastDef = DI->second;
283 return !(LastUse > LastDef && LastUse < Dist);
291 bool &IsDstPhys)
const {
295 DstReg =
MI.getOperand(0).getReg();
296 SrcReg =
MI.getOperand(1).getReg();
297 }
else if (
MI.isInsertSubreg() ||
MI.isSubregToReg()) {
298 DstReg =
MI.getOperand(0).getReg();
299 SrcReg =
MI.getOperand(2).getReg();
309bool TwoAddressInstructionPass::isPlainlyKilled(
const MachineInstr *
MI,
317 assert(
I != LR.
end() &&
"Reg must be live-in to use.");
323bool TwoAddressInstructionPass::isPlainlyKilled(
const MachineInstr *
MI,
335 if (
MRI->isReserved(Reg))
338 return isPlainlyKilled(MI, LIS->getRegUnit(U));
342 return MI->killsRegister(Reg);
347bool TwoAddressInstructionPass::isPlainlyKilled(
370 bool allowFalsePositives)
const {
374 if (
Reg.isPhysical() && (allowFalsePositives ||
MRI->hasOneUse(Reg)))
376 if (!isPlainlyKilled(
DefMI, Reg))
378 if (
Reg.isPhysical())
383 if (std::next(Begin) !=
MRI->def_end())
386 bool IsSrcPhys, IsDstPhys;
390 if (!isCopyToReg(*
DefMI, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
399 for (
unsigned i = 0, NumOps =
MI.getNumOperands(); i != NumOps; ++i) {
404 if (
MI.isRegTiedToDefOperand(i, &ti)) {
405 DstReg =
MI.getOperand(ti).getReg();
414MachineInstr *TwoAddressInstructionPass::findOnlyInterestingUse(
416 bool &IsDstPhys)
const {
420 if (
MI->getParent() !=
MBB)
422 if (isPlainlyKilled(
MI, Reg))
431 if (isCopyToReg(
UseMI, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
440 if (
UseMI.isCommutable()) {
443 if (
TII->findCommutedOpIndices(
UseMI, Src1, Src2)) {
459 while (Reg.isVirtual()) {
461 if (SI == RegMap.
end())
465 if (Reg.isPhysical())
471bool TwoAddressInstructionPass::regsAreCompatible(
Register RegA,
477 return TRI->regsOverlap(RegA, RegB);
481void TwoAddressInstructionPass::removeMapRegEntry(
485 "removeMapRegEntry must be called with a register or regmask operand.");
488 for (
auto SI : RegMap) {
495 if (
TRI->regsOverlap(ToReg, Reg))
501 for (
auto SrcReg : Srcs)
502 RegMap.erase(SrcReg);
513void TwoAddressInstructionPass::removeClobberedSrcRegMap(
MachineInstr *
MI) {
526 if (!Dst || Dst.isVirtual())
530 if (regsAreCompatible(Dst,
getMappedReg(Src, SrcRegMap)))
536 removeMapRegEntry(MO, SrcRegMap);
542 if (!Reg ||
Reg.isVirtual())
544 removeMapRegEntry(MO, SrcRegMap);
549bool TwoAddressInstructionPass::regOverlapsSet(
551 for (
unsigned R : Set)
552 if (
TRI->regsOverlap(R, Reg))
560bool TwoAddressInstructionPass::isProfitableToCommute(
Register RegA,
565 if (OptLevel == CodeGenOptLevel::None)
586 if (!isPlainlyKilled(
MI, RegC))
603 bool CompB = FromRegB && regsAreCompatible(FromRegB, ToRegA);
604 bool CompC = FromRegC && regsAreCompatible(FromRegC, ToRegA);
610 if ((!FromRegB && CompC) || (FromRegB && !CompB && (!FromRegC || CompC)))
616 if ((!FromRegC && CompB) || (FromRegC && !CompC && (!FromRegB || CompB)))
622 unsigned LastDefC = 0;
623 if (!noUseAfterLastDef(RegC, Dist, LastDefC))
628 unsigned LastDefB = 0;
629 if (!noUseAfterLastDef(RegB, Dist, LastDefB))
655 if (
TII->hasCommutePreference(*
MI, Commute))
660 return LastDefB && LastDefC && LastDefC > LastDefB;
665bool TwoAddressInstructionPass::commuteInstruction(
MachineInstr *
MI,
670 Register RegC =
MI->getOperand(RegCIdx).getReg();
674 if (NewMI ==
nullptr) {
681 "TargetInstrInfo::commuteInstruction() should not return a new "
682 "instruction unless it was requested.");
687 Register RegA =
MI->getOperand(DstIdx).getReg();
688 SrcRegMap[RegA] = FromRegC;
696bool TwoAddressInstructionPass::isProfitableToConv3Addr(
Register RegA,
708 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA));
713bool TwoAddressInstructionPass::convertInstTo3Addr(
725 if (
auto OldInstrNum = mi->peekDebugInstrNum()) {
726 assert(mi->getNumExplicitDefs() == 1);
730 unsigned OldIdx = mi->defs().begin()->getOperandNo();
731 unsigned NewIdx = NewMI->
defs().begin()->getOperandNo();
736 std::make_pair(NewInstrNum, NewIdx));
742 DistanceMap.
insert(std::make_pair(&
MI, Dist++));
748 SrcRegMap.
erase(RegA);
749 DstRegMap.
erase(RegB);
755void TwoAddressInstructionPass::scanUses(
Register DstReg) {
762 findOnlyInterestingUse(Reg,
MBB, IsCopy, NewReg, IsDstPhys)) {
767 if (DI != DistanceMap.
end())
775 SrcRegMap[NewReg] =
Reg;
780 if (!VirtRegPairs.
empty()) {
781 unsigned ToReg = VirtRegPairs.
back();
783 while (!VirtRegPairs.
empty()) {
785 bool isNew = DstRegMap.
insert(std::make_pair(FromReg, ToReg)).second;
787 assert(DstRegMap[FromReg] == ToReg &&
"Can't map to two dst registers!");
790 bool isNew = DstRegMap.
insert(std::make_pair(DstReg, ToReg)).second;
792 assert(DstRegMap[DstReg] == ToReg &&
"Can't map to two dst registers!");
812 bool IsSrcPhys, IsDstPhys;
814 if (!isCopyToReg(*
MI, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
817 if (IsDstPhys && !IsSrcPhys) {
818 DstRegMap.
insert(std::make_pair(SrcReg, DstReg));
819 }
else if (!IsDstPhys && IsSrcPhys) {
820 bool isNew = SrcRegMap.
insert(std::make_pair(DstReg, SrcReg)).second;
822 assert(SrcRegMap[DstReg] == SrcReg &&
823 "Can't map to two src physical registers!");
834bool TwoAddressInstructionPass::rescheduleMIBelowKill(
844 if (DI == DistanceMap.
end())
852 "Reg should not have empty live interval.");
856 if (
I != LI.
end() &&
I->start < MBBEndIdx)
877 bool SeenStore =
true;
878 if (!
MI->isSafeToMove(AA, SeenStore))
897 Uses.push_back(MOReg);
898 if (MOReg != Reg && isPlainlyKilled(MO))
909 if (
End->isCopy() && regOverlapsSet(Defs,
End->getOperand(1).getReg()))
917 unsigned NumVisited = 0;
922 if (OtherMI.isDebugOrPseudoInstr())
927 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
928 OtherMI.isBranch() || OtherMI.isTerminator())
938 if (regOverlapsSet(
Uses, MOReg))
941 if (!MO.
isDead() && regOverlapsSet(Defs, MOReg))
947 if (regOverlapsSet(Defs, MOReg))
949 bool isKill = isPlainlyKilled(MO);
950 if (MOReg != Reg && ((isKill && regOverlapsSet(
Uses, MOReg)) ||
951 regOverlapsSet(Kills, MOReg)))
954 if (MOReg == Reg && !isKill)
958 assert((MOReg != Reg || &OtherMI == KillMI) &&
959 "Found multiple kills of a register in a basic block");
965 while (Begin !=
MBB->
begin() && std::prev(Begin)->isDebugInstr())
974 auto CopyMI =
MBBI++;
976 if (!CopyMI->isDebugOrPseudoInstr())
985 DistanceMap.
erase(DI);
1001bool TwoAddressInstructionPass::isDefTooClose(
Register Reg,
unsigned Dist,
1009 if (DDI == DistanceMap.
end())
1011 unsigned DefDist = DDI->second;
1012 assert(Dist > DefDist &&
"Visited def already?");
1022bool TwoAddressInstructionPass::rescheduleKillAboveMI(
1032 if (DI == DistanceMap.
end())
1040 "Reg should not have empty live interval.");
1044 if (
I != LI.
end() &&
I->start < MBBEndIdx)
1060 bool SeenStore =
true;
1075 if (isDefTooClose(MOReg, DI->second,
MI))
1077 bool isKill = isPlainlyKilled(MO);
1078 if (MOReg == Reg && !isKill)
1080 Uses.push_back(MOReg);
1081 if (isKill && MOReg != Reg)
1091 unsigned NumVisited = 0;
1095 if (OtherMI.isDebugOrPseudoInstr())
1097 if (NumVisited > 10)
1100 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
1101 OtherMI.isBranch() || OtherMI.isTerminator())
1112 if (regOverlapsSet(Defs, MOReg))
1116 if (regOverlapsSet(Kills, MOReg))
1119 if (&OtherMI !=
MI && MOReg == Reg && !isPlainlyKilled(MO))
1128 if (regOverlapsSet(
Uses, MOReg))
1130 if (MOReg.
isPhysical() && regOverlapsSet(LiveDefs, MOReg))
1139 while (InsertPos !=
MBB->
begin() && std::prev(InsertPos)->isDebugInstr())
1143 while (std::prev(
From)->isDebugInstr())
1147 nmi = std::prev(InsertPos);
1148 DistanceMap.
erase(DI);
1174bool TwoAddressInstructionPass::tryInstructionCommute(
MachineInstr *
MI,
1179 if (!
MI->isCommutable())
1182 bool MadeChange =
false;
1183 Register DstOpReg =
MI->getOperand(DstOpIdx).getReg();
1184 Register BaseOpReg =
MI->getOperand(BaseOpIdx).getReg();
1185 unsigned OpsNum =
MI->getDesc().getNumOperands();
1186 unsigned OtherOpIdx =
MI->getDesc().getNumDefs();
1187 for (; OtherOpIdx < OpsNum; OtherOpIdx++) {
1192 if (OtherOpIdx == BaseOpIdx || !
MI->getOperand(OtherOpIdx).isReg() ||
1193 !
TII->findCommutedOpIndices(*
MI, BaseOpIdx, OtherOpIdx))
1196 Register OtherOpReg =
MI->getOperand(OtherOpIdx).getReg();
1197 bool AggressiveCommute =
false;
1201 bool OtherOpKilled = isKilled(*
MI, OtherOpReg,
false);
1202 bool DoCommute = !BaseOpKilled && OtherOpKilled;
1205 isProfitableToCommute(DstOpReg, BaseOpReg, OtherOpReg,
MI, Dist)) {
1207 AggressiveCommute =
true;
1211 if (DoCommute && commuteInstruction(
MI, DstOpIdx, BaseOpIdx, OtherOpIdx,
1215 if (AggressiveCommute)
1222 BaseOpReg = OtherOpReg;
1223 BaseOpKilled = OtherOpKilled;
1226 OpsNum =
MI->getDesc().getNumOperands();
1239bool TwoAddressInstructionPass::
1242 unsigned SrcIdx,
unsigned DstIdx,
1243 unsigned &Dist,
bool shouldOnlyCommute) {
1244 if (OptLevel == CodeGenOptLevel::None)
1248 Register regA =
MI.getOperand(DstIdx).getReg();
1249 Register regB =
MI.getOperand(SrcIdx).getReg();
1251 assert(regB.
isVirtual() &&
"cannot make instruction into two-address form");
1252 bool regBKilled = isKilled(
MI, regB,
true);
1257 bool Commuted = tryInstructionCommute(&
MI, DstIdx, SrcIdx, regBKilled, Dist);
1267 if (Commuted && !
MI.isConvertibleTo3Addr())
1270 if (shouldOnlyCommute)
1283 regB =
MI.getOperand(SrcIdx).getReg();
1284 regBKilled = isKilled(
MI, regB,
true);
1287 if (
MI.isConvertibleTo3Addr()) {
1290 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
1292 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
1293 ++NumConvertedTo3Addr;
1318 if (
MI.mayLoad() && !regBKilled) {
1320 unsigned LoadRegIndex;
1322 TII->getOpcodeAfterMemoryUnfold(
MI.getOpcode(),
1332 TRI->getAllocatableClass(
1333 TII->getRegClass(UnfoldMCID, LoadRegIndex,
TRI, *MF));
1336 if (!
TII->unfoldMemoryOperand(*MF,
MI, Reg,
1343 "Unfolded a load into multiple instructions!");
1345 NewMIs[1]->addRegisterKilled(Reg,
TRI);
1351 DistanceMap.
insert(std::make_pair(NewMIs[0], Dist++));
1352 DistanceMap.
insert(std::make_pair(NewMIs[1], Dist));
1355 <<
"2addr: NEW INST: " << *NewMIs[1]);
1358 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1359 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1361 bool TransformResult =
1362 tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist,
true);
1363 (void)TransformResult;
1364 assert(!TransformResult &&
1365 "tryInstructionTransform() should return false.");
1366 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1374 if (NewMIs[0]->killsRegister(MO.
getReg()))
1378 "Kill missing after load unfold!");
1383 if (NewMIs[1]->registerDefIsDead(MO.
getReg()))
1387 "Dead flag missing after load unfold!");
1406 MI.eraseFromParent();
1422 NewMIs[0]->eraseFromParent();
1423 NewMIs[1]->eraseFromParent();
1424 DistanceMap.
erase(NewMIs[0]);
1425 DistanceMap.
erase(NewMIs[1]);
1438bool TwoAddressInstructionPass::
1439collectTiedOperands(
MachineInstr *
MI, TiedOperandMap &TiedOperands) {
1440 bool AnyOps =
false;
1441 unsigned NumOps =
MI->getNumOperands();
1443 for (
unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1444 unsigned DstIdx = 0;
1445 if (!
MI->isRegTiedToDefOperand(SrcIdx, &DstIdx))
1453 if (SrcReg == DstReg)
1456 assert(SrcReg && SrcMO.
isUse() &&
"two address instruction invalid");
1463 MRI->constrainRegClass(DstReg, RC);
1470 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));
1479 TiedPairList &TiedPairs,
1481 bool IsEarlyClobber =
llvm::any_of(TiedPairs, [
MI](
auto const &TP) {
1482 return MI->getOperand(TP.second).isEarlyClobber();
1485 bool RemovedKillFlag =
false;
1486 bool AllUsesCopied =
true;
1487 unsigned LastCopiedReg = 0;
1490 unsigned SubRegB = 0;
1491 for (
auto &TP : TiedPairs) {
1492 unsigned SrcIdx = TP.first;
1493 unsigned DstIdx = TP.second;
1500 RegB =
MI->getOperand(SrcIdx).getReg();
1501 SubRegB =
MI->getOperand(SrcIdx).getSubReg();
1507 AllUsesCopied =
false;
1510 LastCopiedReg = RegA;
1512 assert(RegB.
isVirtual() &&
"cannot make instruction into two-address form");
1518 for (
unsigned i = 0; i !=
MI->getNumOperands(); ++i)
1520 !
MI->getOperand(i).isReg() ||
1521 MI->getOperand(i).getReg() != RegA);
1526 TII->get(TargetOpcode::COPY), RegA);
1529 MIB.
addReg(RegB, 0, SubRegB);
1533 assert(
TRI->getMatchingSuperRegClass(RC,
MRI->getRegClass(RegA),
1535 "tied subregister must be a truncation");
1539 assert(
TRI->getMatchingSuperReg(RegA, SubRegB,
MRI->getRegClass(RegB))
1540 &&
"tied subregister must be a truncation");
1547 DistanceMap.
insert(std::make_pair(&*PrevMI, Dist));
1548 DistanceMap[
MI] = ++Dist;
1578 "inconsistent operand info for 2-reg pass");
1579 if (isPlainlyKilled(MO)) {
1581 RemovedKillFlag =
true;
1586 MRI->constrainRegClass(RegA, RC);
1594 if (AllUsesCopied) {
1598 if (MO.
getReg() == RegB) {
1599 if (MO.
getSubReg() == SubRegB && !IsEarlyClobber) {
1600 if (isPlainlyKilled(MO)) {
1602 RemovedKillFlag =
true;
1604 MO.
setReg(LastCopiedReg);
1607 RemainingUses |=
TRI->getSubRegIndexLaneMask(MO.
getSubReg());
1613 if (RemovedKillFlag && RemainingUses.
none() && LV &&
1620 if (RemovedKillFlag && RemainingUses.
none())
1621 SrcRegMap[LastCopiedReg] = RegB;
1630 if ((LaneMask & RemainingUses).any())
1634 S->
end = LastCopyIdx;
1639 bool ShrinkLI =
true;
1641 ShrinkLI &= Shrink(S, S.LaneMask);
1645 }
else if (RemovedKillFlag) {
1651 if (MO.
getReg() == RegB) {
1666bool TwoAddressInstructionPass::processStatepoint(
1669 bool NeedCopy =
false;
1670 for (
auto &TO : TiedOperands) {
1672 if (TO.second.size() != 1) {
1677 unsigned SrcIdx = TO.second[0].first;
1678 unsigned DstIdx = TO.second[0].second;
1683 assert(RegB ==
MI->getOperand(SrcIdx).getReg());
1696 if (DefLI.overlaps(UseLI)) {
1698 <<
" UseLI overlaps with DefLI\n");
1707 <<
" not killed by statepoint\n");
1712 if (!
MRI->constrainRegClass(RegB,
MRI->getRegClass(RegA))) {
1714 <<
" to register class of " <<
printReg(RegA,
TRI, 0)
1719 MRI->replaceRegWith(RegA, RegB);
1730 for (
auto &S :
Other) {
1739 if (
MI->getOperand(SrcIdx).isKill())
1745 for (
auto *KillMI : DstInfo.
Kills)
1753bool TwoAddressInstructionPass::runOnMachineFunction(
MachineFunction &Func) {
1760 LV = getAnalysisIfAvailable<LiveVariables>();
1761 LIS = getAnalysisIfAvailable<LiveIntervals>();
1762 if (
auto *AAPass = getAnalysisIfAvailable<AAResultsWrapperPass>())
1763 AA = &AAPass->getAAResults();
1766 OptLevel =
TM.getOptLevel();
1769 if (skipFunction(
Func.getFunction()))
1770 OptLevel = CodeGenOptLevel::None;
1772 bool MadeChange =
false;
1774 LLVM_DEBUG(
dbgs() <<
"********** REWRITING TWO-ADDR INSTRS **********\n");
1782 .
set(MachineFunctionProperties::Property::TiedOpsRewritten);
1784 TiedOperandMap TiedOperands;
1788 DistanceMap.
clear();
1796 if (mi->isDebugInstr()) {
1803 if (mi->isRegSequence())
1804 eliminateRegSequence(mi);
1806 DistanceMap.
insert(std::make_pair(&*mi, ++Dist));
1812 if (!collectTiedOperands(&*mi, TiedOperands)) {
1813 removeClobberedSrcRegMap(&*mi);
1818 ++NumTwoAddressInstrs;
1825 if (TiedOperands.size() == 1) {
1827 = TiedOperands.
begin()->second;
1828 if (TiedPairs.
size() == 1) {
1829 unsigned SrcIdx = TiedPairs[0].first;
1830 unsigned DstIdx = TiedPairs[0].second;
1831 Register SrcReg = mi->getOperand(SrcIdx).getReg();
1832 Register DstReg = mi->getOperand(DstIdx).getReg();
1833 if (SrcReg != DstReg &&
1834 tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist,
false)) {
1837 TiedOperands.clear();
1838 removeClobberedSrcRegMap(&*mi);
1845 if (mi->getOpcode() == TargetOpcode::STATEPOINT &&
1846 processStatepoint(&*mi, TiedOperands)) {
1847 TiedOperands.clear();
1854 for (
auto &TO : TiedOperands) {
1855 processTiedPairs(&*mi, TO.second, Dist);
1860 if (mi->isInsertSubreg()) {
1863 unsigned SubIdx = mi->getOperand(3).getImm();
1864 mi->removeOperand(3);
1865 assert(mi->getOperand(0).getSubReg() == 0 &&
"Unexpected subreg idx");
1866 mi->getOperand(0).setSubReg(SubIdx);
1867 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1868 mi->removeOperand(1);
1869 mi->setDesc(
TII->get(TargetOpcode::COPY));
1880 TRI->getSubRegIndexLaneMask(mi->getOperand(0).getSubReg());
1883 if ((S.LaneMask & LaneMask).none()) {
1885 if (mi->getOperand(0).isUndef()) {
1886 S.removeValNo(DefSeg->valno);
1889 S.MergeValueNumberInto(DefSeg->valno, UseSeg->valno);
1907 TiedOperands.
clear();
1908 removeClobberedSrcRegMap(&*mi);
1926void TwoAddressInstructionPass::
1935 for (
unsigned i = 1, e =
MI.getNumOperands(); i < e; i += 2)
1945 bool DefEmitted =
false;
1946 for (
unsigned i = 1, e =
MI.getNumOperands(); i < e; i += 2) {
1949 unsigned SubIdx =
MI.getOperand(i+1).getImm();
1952 UndefLanes |=
TRI->getSubRegIndexLaneMask(SubIdx);
1958 bool isKill = UseMO.
isKill();
1960 for (
unsigned j = i + 2;
j <
e;
j += 2)
1961 if (
MI.getOperand(j).getReg() == SrcReg) {
1962 MI.getOperand(j).setIsKill();
1970 TII->get(TargetOpcode::COPY))
1995 MI.setDesc(
TII->get(TargetOpcode::IMPLICIT_DEF));
1996 for (
int j =
MI.getNumOperands() - 1, ee = 0; j > ee; --j)
1997 MI.removeOperand(j);
2003 if (UndefLanes.
any() && DefVN &&
MRI->shouldTrackSubRegLiveness(DstReg)) {
2014 if ((UndefLanes & LaneMask).
any())
2023 MI.eraseFromParent();
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock MachineBasicBlock::iterator MBBI
BlockVerifier::State From
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
std::optional< std::vector< StOtherPiece > > Other
Rewrite Partial Register Uses
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
static bool isTwoAddrUse(MachineInstr &MI, Register Reg, Register &DstReg)
Return true if the specified MI uses the specified register as a two-address use.
static MCRegister getMappedReg(Register Reg, DenseMap< Register, Register > &RegMap)
Return the physical register the specified virtual register might be mapped to.
Two Address instruction pass
static cl::opt< bool > EnableRescheduling("twoaddr-reschedule", cl::desc("Coalesce copies by rescheduling (default=true)"), cl::init(true), cl::Hidden)
static cl::opt< unsigned > MaxDataFlowEdge("dataflow-edge-limit", cl::Hidden, cl::init(3), cl::desc("Maximum number of dataflow edges to traverse when evaluating " "the benefit of commuting operands"))
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
Represent the analysis usage information of a pass.
AnalysisUsage & addPreservedID(const void *ID)
AnalysisUsage & addUsedIfAvailable()
Add the specified Pass class to the set of analyses used by this pass.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Allocate memory in an ever growing pool, as if by bump-pointer.
iterator find(const_arg_type_t< KeyT > Val)
bool erase(const KeyT &Val)
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
Itinerary data supplied by a subtarget to be used by a target.
LiveInterval - This class represents the liveness of a register, or stack slot.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
iterator_range< subrange_iterator > subranges()
void repairIntervalsInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, ArrayRef< Register > OrigRegs)
Update live intervals for instructions in a range of iterators.
bool hasInterval(Register Reg) const
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
SlotIndex InsertMachineInstrInMaps(MachineInstr &MI)
void handleMove(MachineInstr &MI, bool UpdateFlags=false)
Call this method to notify LiveIntervals that instruction MI has been moved within a basic block.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
void RemoveMachineInstrFromMaps(MachineInstr &MI)
VNInfo::Allocator & getVNInfoAllocator()
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
LiveInterval & getInterval(Register Reg)
void removeInterval(Register Reg)
Interval removal.
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map.
bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)
After removing some uses of a register, shrink its live range to just the remaining uses.
LiveInterval & createAndComputeVirtRegInterval(Register Reg)
VNInfo * valueOut() const
Return the value leaving the instruction, if any.
This class represents the liveness of a register, stack slot, etc.
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
const Segment * getSegmentContaining(SlotIndex Idx) const
Return the segment that contains the specified index, or null if there is none.
VNInfo * createValueCopy(const VNInfo *orig, VNInfo::Allocator &VNInfoAllocator)
Create a copy of the given value.
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
bool hasAtLeastOneValue() const
VNInfo * getNextValue(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
iterator find(SlotIndex Pos)
find - Return an iterator pointing to the first segment that ends after Pos, or end().
void replaceKillInstruction(Register Reg, MachineInstr &OldMI, MachineInstr &NewMI)
replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one.
bool removeVirtualRegisterDead(Register Reg, MachineInstr &MI)
removeVirtualRegisterDead - Remove the specified kill of the virtual register from the live variable ...
bool removeVirtualRegisterKilled(Register Reg, MachineInstr &MI)
removeVirtualRegisterKilled - Remove the specified kill of the virtual register from the live variabl...
void addVirtualRegisterDead(Register IncomingReg, MachineInstr &MI, bool AddIfNotFound=false)
addVirtualRegisterDead - Add information about the fact that the specified register is dead after bei...
void addVirtualRegisterKilled(Register IncomingReg, MachineInstr &MI, bool AddIfNotFound=false)
addVirtualRegisterKilled - Add information about the fact that the specified register is killed after...
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
Describe properties that are true of each instruction in the target description file.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Wrapper class representing physical registers. Should be passed by value.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
void makeDebugValueSubstitution(DebugInstrOperandPair, DebugInstrOperandPair, unsigned SubReg=0)
Create a substitution between one <instr,operand> value to a different, new value.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
MachineInstrSpan provides an interface to get an iteration range containing the instruction it was in...
Representation of each machine instruction.
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
bool isCopyLike() const
Return true if the instruction behaves like a copy.
bool isCall(QueryType Type=AnyInBundle) const
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
iterator_range< mop_iterator > operands()
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
void setSubReg(unsigned subReg)
unsigned getSubReg() const
unsigned getOperandNo() const
Returns the index of this operand in the instruction that it belongs to.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
void setIsKill(bool Val=true)
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
void setIsUndef(bool Val=true)
Register getReg() const
getReg - Returns the register number.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
SlotIndex - An opaque wrapper around machine indexes.
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
static const unsigned CommuteAnyOperandIndex
Primary interface to the complete machine description for the target machine.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget.
VNInfo - Value Number Information.
unsigned id
The ID number of this value.
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
constexpr bool any(E Val)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ Define
Register definition.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
NodeAddr< DefNode * > Def
NodeAddr< FuncNode * > Func
This is an optimization pass for GlobalISel generic memory operations.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
IterT skipDebugInstructionsForward(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator.
void erase(Container &C, ValueType V)
Wrapper function to remove a value from a container:
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
void initializeTwoAddressInstructionPassPass(PassRegistry &)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
CodeGenOptLevel
Code generation optimization level.
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
static constexpr LaneBitmask getAll()
constexpr bool none() const
constexpr bool any() const
static constexpr LaneBitmask getNone()
This represents a simple continuous liveness interval for a value.
VarInfo - This represents the regions where a virtual register is live in the program.
bool removeKill(MachineInstr &MI)
removeKill - Delete a kill corresponding to the specified machine instruction.
std::vector< MachineInstr * > Kills
Kills - List of MachineInstruction's which are the last use of this virtual register (kill it) in the...
SparseBitVector AliveBlocks
AliveBlocks - Set of blocks in which this value is alive completely through.
MachineInstr * findKill(const MachineBasicBlock *MBB) const
findKill - Find a kill instruction in MBB. Return NULL if none is found.