LLVM  9.0.0svn
WebAssemblyMCTargetDesc.h
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1 //==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file provides WebAssembly-specific target descriptions.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
15 #define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
16 
17 #include "../WebAssemblySubtarget.h"
18 #include "llvm/BinaryFormat/Wasm.h"
19 #include "llvm/MC/MCInstrDesc.h"
20 #include "llvm/Support/DataTypes.h"
21 #include <memory>
22 
23 namespace llvm {
24 
25 class MCAsmBackend;
26 class MCCodeEmitter;
27 class MCContext;
28 class MCInstrInfo;
29 class MCObjectTargetWriter;
30 class MCSubtargetInfo;
31 class MVT;
32 class Target;
33 class Triple;
34 class raw_pwrite_stream;
35 
36 MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII);
37 
38 MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT);
39 
40 std::unique_ptr<MCObjectTargetWriter>
42 
43 namespace WebAssembly {
45  /// Basic block label in a branch construct.
47  /// Local index.
49  /// Global index.
51  /// 32-bit integer immediates.
53  /// 64-bit integer immediates.
55  /// 32-bit floating-point immediates.
57  /// 64-bit floating-point immediates.
59  /// 8-bit vector lane immediate
61  /// 16-bit vector lane immediate
63  /// 32-bit vector lane immediate
65  /// 64-bit vector lane immediate
67  /// 32-bit unsigned function indices.
69  /// 32-bit unsigned memory offsets.
71  /// p2align immediate for load and store address alignment.
73  /// signature immediate for block/loop.
75  /// type signature immediate for call_indirect.
77  /// Event index.
79  /// A list of branch targets for br_list.
81 };
82 } // end namespace WebAssembly
83 
84 namespace WebAssemblyII {
85 
86 /// Target Operand Flag enum.
87 enum TOF {
89 
90  // On a symbol operand this indicates that the immediate is a wasm global
91  // index. The value of the wasm global will be set to the symbol address at
92  // runtime. This adds a level of indirection similar to the GOT on native
93  // platforms.
95 
96  // On a symbol operand this indicates that the immediate is the symbol
97  // address relative the __memory_base wasm global.
98  // Only applicable to data symbols.
100 
101  // On a symbol operand this indicates that the immediate is the symbol
102  // address relative the __table_base wasm global.
103  // Only applicable to function symbols.
105 };
106 
107 } // end namespace WebAssemblyII
108 
109 } // end namespace llvm
110 
111 // Defines symbolic names for WebAssembly registers. This defines a mapping from
112 // register name to register number.
113 //
114 #define GET_REGINFO_ENUM
115 #include "WebAssemblyGenRegisterInfo.inc"
116 
117 // Defines symbolic names for the WebAssembly instructions.
118 //
119 #define GET_INSTRINFO_ENUM
120 #include "WebAssemblyGenInstrInfo.inc"
121 
122 namespace llvm {
123 namespace WebAssembly {
124 
125 /// Return the default p2align value for a load or store with the given opcode.
126 inline unsigned GetDefaultP2Align(unsigned Opcode) {
127  switch (Opcode) {
128  case WebAssembly::LOAD8_S_I32:
129  case WebAssembly::LOAD8_S_I32_S:
130  case WebAssembly::LOAD8_U_I32:
131  case WebAssembly::LOAD8_U_I32_S:
132  case WebAssembly::LOAD8_S_I64:
133  case WebAssembly::LOAD8_S_I64_S:
134  case WebAssembly::LOAD8_U_I64:
135  case WebAssembly::LOAD8_U_I64_S:
136  case WebAssembly::ATOMIC_LOAD8_U_I32:
137  case WebAssembly::ATOMIC_LOAD8_U_I32_S:
138  case WebAssembly::ATOMIC_LOAD8_U_I64:
139  case WebAssembly::ATOMIC_LOAD8_U_I64_S:
140  case WebAssembly::STORE8_I32:
141  case WebAssembly::STORE8_I32_S:
142  case WebAssembly::STORE8_I64:
143  case WebAssembly::STORE8_I64_S:
144  case WebAssembly::ATOMIC_STORE8_I32:
145  case WebAssembly::ATOMIC_STORE8_I32_S:
146  case WebAssembly::ATOMIC_STORE8_I64:
147  case WebAssembly::ATOMIC_STORE8_I64_S:
148  case WebAssembly::ATOMIC_RMW8_U_ADD_I32:
149  case WebAssembly::ATOMIC_RMW8_U_ADD_I32_S:
150  case WebAssembly::ATOMIC_RMW8_U_ADD_I64:
151  case WebAssembly::ATOMIC_RMW8_U_ADD_I64_S:
152  case WebAssembly::ATOMIC_RMW8_U_SUB_I32:
153  case WebAssembly::ATOMIC_RMW8_U_SUB_I32_S:
154  case WebAssembly::ATOMIC_RMW8_U_SUB_I64:
155  case WebAssembly::ATOMIC_RMW8_U_SUB_I64_S:
156  case WebAssembly::ATOMIC_RMW8_U_AND_I32:
157  case WebAssembly::ATOMIC_RMW8_U_AND_I32_S:
158  case WebAssembly::ATOMIC_RMW8_U_AND_I64:
159  case WebAssembly::ATOMIC_RMW8_U_AND_I64_S:
160  case WebAssembly::ATOMIC_RMW8_U_OR_I32:
161  case WebAssembly::ATOMIC_RMW8_U_OR_I32_S:
162  case WebAssembly::ATOMIC_RMW8_U_OR_I64:
163  case WebAssembly::ATOMIC_RMW8_U_OR_I64_S:
164  case WebAssembly::ATOMIC_RMW8_U_XOR_I32:
165  case WebAssembly::ATOMIC_RMW8_U_XOR_I32_S:
166  case WebAssembly::ATOMIC_RMW8_U_XOR_I64:
167  case WebAssembly::ATOMIC_RMW8_U_XOR_I64_S:
168  case WebAssembly::ATOMIC_RMW8_U_XCHG_I32:
169  case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_S:
170  case WebAssembly::ATOMIC_RMW8_U_XCHG_I64:
171  case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_S:
172  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32:
173  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_S:
174  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64:
175  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_S:
176  return 0;
177  case WebAssembly::LOAD16_S_I32:
178  case WebAssembly::LOAD16_S_I32_S:
179  case WebAssembly::LOAD16_U_I32:
180  case WebAssembly::LOAD16_U_I32_S:
181  case WebAssembly::LOAD16_S_I64:
182  case WebAssembly::LOAD16_S_I64_S:
183  case WebAssembly::LOAD16_U_I64:
184  case WebAssembly::LOAD16_U_I64_S:
185  case WebAssembly::ATOMIC_LOAD16_U_I32:
186  case WebAssembly::ATOMIC_LOAD16_U_I32_S:
187  case WebAssembly::ATOMIC_LOAD16_U_I64:
188  case WebAssembly::ATOMIC_LOAD16_U_I64_S:
189  case WebAssembly::STORE16_I32:
190  case WebAssembly::STORE16_I32_S:
191  case WebAssembly::STORE16_I64:
192  case WebAssembly::STORE16_I64_S:
193  case WebAssembly::ATOMIC_STORE16_I32:
194  case WebAssembly::ATOMIC_STORE16_I32_S:
195  case WebAssembly::ATOMIC_STORE16_I64:
196  case WebAssembly::ATOMIC_STORE16_I64_S:
197  case WebAssembly::ATOMIC_RMW16_U_ADD_I32:
198  case WebAssembly::ATOMIC_RMW16_U_ADD_I32_S:
199  case WebAssembly::ATOMIC_RMW16_U_ADD_I64:
200  case WebAssembly::ATOMIC_RMW16_U_ADD_I64_S:
201  case WebAssembly::ATOMIC_RMW16_U_SUB_I32:
202  case WebAssembly::ATOMIC_RMW16_U_SUB_I32_S:
203  case WebAssembly::ATOMIC_RMW16_U_SUB_I64:
204  case WebAssembly::ATOMIC_RMW16_U_SUB_I64_S:
205  case WebAssembly::ATOMIC_RMW16_U_AND_I32:
206  case WebAssembly::ATOMIC_RMW16_U_AND_I32_S:
207  case WebAssembly::ATOMIC_RMW16_U_AND_I64:
208  case WebAssembly::ATOMIC_RMW16_U_AND_I64_S:
209  case WebAssembly::ATOMIC_RMW16_U_OR_I32:
210  case WebAssembly::ATOMIC_RMW16_U_OR_I32_S:
211  case WebAssembly::ATOMIC_RMW16_U_OR_I64:
212  case WebAssembly::ATOMIC_RMW16_U_OR_I64_S:
213  case WebAssembly::ATOMIC_RMW16_U_XOR_I32:
214  case WebAssembly::ATOMIC_RMW16_U_XOR_I32_S:
215  case WebAssembly::ATOMIC_RMW16_U_XOR_I64:
216  case WebAssembly::ATOMIC_RMW16_U_XOR_I64_S:
217  case WebAssembly::ATOMIC_RMW16_U_XCHG_I32:
218  case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_S:
219  case WebAssembly::ATOMIC_RMW16_U_XCHG_I64:
220  case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_S:
221  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32:
222  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_S:
223  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64:
224  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_S:
225  return 1;
226  case WebAssembly::LOAD_I32:
227  case WebAssembly::LOAD_I32_S:
228  case WebAssembly::LOAD_F32:
229  case WebAssembly::LOAD_F32_S:
230  case WebAssembly::STORE_I32:
231  case WebAssembly::STORE_I32_S:
232  case WebAssembly::STORE_F32:
233  case WebAssembly::STORE_F32_S:
234  case WebAssembly::LOAD32_S_I64:
235  case WebAssembly::LOAD32_S_I64_S:
236  case WebAssembly::LOAD32_U_I64:
237  case WebAssembly::LOAD32_U_I64_S:
238  case WebAssembly::STORE32_I64:
239  case WebAssembly::STORE32_I64_S:
240  case WebAssembly::ATOMIC_LOAD_I32:
241  case WebAssembly::ATOMIC_LOAD_I32_S:
242  case WebAssembly::ATOMIC_LOAD32_U_I64:
243  case WebAssembly::ATOMIC_LOAD32_U_I64_S:
244  case WebAssembly::ATOMIC_STORE_I32:
245  case WebAssembly::ATOMIC_STORE_I32_S:
246  case WebAssembly::ATOMIC_STORE32_I64:
247  case WebAssembly::ATOMIC_STORE32_I64_S:
248  case WebAssembly::ATOMIC_RMW_ADD_I32:
249  case WebAssembly::ATOMIC_RMW_ADD_I32_S:
250  case WebAssembly::ATOMIC_RMW32_U_ADD_I64:
251  case WebAssembly::ATOMIC_RMW32_U_ADD_I64_S:
252  case WebAssembly::ATOMIC_RMW_SUB_I32:
253  case WebAssembly::ATOMIC_RMW_SUB_I32_S:
254  case WebAssembly::ATOMIC_RMW32_U_SUB_I64:
255  case WebAssembly::ATOMIC_RMW32_U_SUB_I64_S:
256  case WebAssembly::ATOMIC_RMW_AND_I32:
257  case WebAssembly::ATOMIC_RMW_AND_I32_S:
258  case WebAssembly::ATOMIC_RMW32_U_AND_I64:
259  case WebAssembly::ATOMIC_RMW32_U_AND_I64_S:
260  case WebAssembly::ATOMIC_RMW_OR_I32:
261  case WebAssembly::ATOMIC_RMW_OR_I32_S:
262  case WebAssembly::ATOMIC_RMW32_U_OR_I64:
263  case WebAssembly::ATOMIC_RMW32_U_OR_I64_S:
264  case WebAssembly::ATOMIC_RMW_XOR_I32:
265  case WebAssembly::ATOMIC_RMW_XOR_I32_S:
266  case WebAssembly::ATOMIC_RMW32_U_XOR_I64:
267  case WebAssembly::ATOMIC_RMW32_U_XOR_I64_S:
268  case WebAssembly::ATOMIC_RMW_XCHG_I32:
269  case WebAssembly::ATOMIC_RMW_XCHG_I32_S:
270  case WebAssembly::ATOMIC_RMW32_U_XCHG_I64:
271  case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_S:
272  case WebAssembly::ATOMIC_RMW_CMPXCHG_I32:
273  case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_S:
274  case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64:
275  case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_S:
276  case WebAssembly::ATOMIC_NOTIFY:
277  case WebAssembly::ATOMIC_NOTIFY_S:
278  case WebAssembly::ATOMIC_WAIT_I32:
279  case WebAssembly::ATOMIC_WAIT_I32_S:
280  return 2;
281  case WebAssembly::LOAD_I64:
282  case WebAssembly::LOAD_I64_S:
283  case WebAssembly::LOAD_F64:
284  case WebAssembly::LOAD_F64_S:
285  case WebAssembly::STORE_I64:
286  case WebAssembly::STORE_I64_S:
287  case WebAssembly::STORE_F64:
288  case WebAssembly::STORE_F64_S:
289  case WebAssembly::ATOMIC_LOAD_I64:
290  case WebAssembly::ATOMIC_LOAD_I64_S:
291  case WebAssembly::ATOMIC_STORE_I64:
292  case WebAssembly::ATOMIC_STORE_I64_S:
293  case WebAssembly::ATOMIC_RMW_ADD_I64:
294  case WebAssembly::ATOMIC_RMW_ADD_I64_S:
295  case WebAssembly::ATOMIC_RMW_SUB_I64:
296  case WebAssembly::ATOMIC_RMW_SUB_I64_S:
297  case WebAssembly::ATOMIC_RMW_AND_I64:
298  case WebAssembly::ATOMIC_RMW_AND_I64_S:
299  case WebAssembly::ATOMIC_RMW_OR_I64:
300  case WebAssembly::ATOMIC_RMW_OR_I64_S:
301  case WebAssembly::ATOMIC_RMW_XOR_I64:
302  case WebAssembly::ATOMIC_RMW_XOR_I64_S:
303  case WebAssembly::ATOMIC_RMW_XCHG_I64:
304  case WebAssembly::ATOMIC_RMW_XCHG_I64_S:
305  case WebAssembly::ATOMIC_RMW_CMPXCHG_I64:
306  case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_S:
307  case WebAssembly::ATOMIC_WAIT_I64:
308  case WebAssembly::ATOMIC_WAIT_I64_S:
309  return 3;
310  case WebAssembly::LOAD_v16i8:
311  case WebAssembly::LOAD_v16i8_S:
312  case WebAssembly::LOAD_v8i16:
313  case WebAssembly::LOAD_v8i16_S:
314  case WebAssembly::LOAD_v4i32:
315  case WebAssembly::LOAD_v4i32_S:
316  case WebAssembly::LOAD_v2i64:
317  case WebAssembly::LOAD_v2i64_S:
318  case WebAssembly::LOAD_v4f32:
319  case WebAssembly::LOAD_v4f32_S:
320  case WebAssembly::LOAD_v2f64:
321  case WebAssembly::LOAD_v2f64_S:
322  case WebAssembly::STORE_v16i8:
323  case WebAssembly::STORE_v16i8_S:
324  case WebAssembly::STORE_v8i16:
325  case WebAssembly::STORE_v8i16_S:
326  case WebAssembly::STORE_v4i32:
327  case WebAssembly::STORE_v4i32_S:
328  case WebAssembly::STORE_v2i64:
329  case WebAssembly::STORE_v2i64_S:
330  case WebAssembly::STORE_v4f32:
331  case WebAssembly::STORE_v4f32_S:
332  case WebAssembly::STORE_v2f64:
333  case WebAssembly::STORE_v2f64_S:
334  return 4;
335  default:
336  llvm_unreachable("Only loads and stores have p2align values");
337  }
338 }
339 
340 /// This is used to indicate block signatures.
341 enum class ExprType : unsigned {
342  Void = 0x40,
343  I32 = 0x7F,
344  I64 = 0x7E,
345  F32 = 0x7D,
346  F64 = 0x7C,
347  V128 = 0x7B,
348  ExceptRef = 0x68,
349  Invalid = 0x00
350 };
351 
352 /// Instruction opcodes emitted via means other than CodeGen.
353 static const unsigned Nop = 0x01;
354 static const unsigned End = 0x0b;
355 
356 wasm::ValType toValType(const MVT &Ty);
357 
358 } // end namespace WebAssembly
359 } // end namespace llvm
360 
361 #endif
32-bit floating-point immediates.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
std::unique_ptr< MCObjectTargetWriter > createWebAssemblyWasmObjectWriter(bool Is64Bit)
32-bit unsigned memory offsets.
Basic block label in a branch construct.
A list of branch targets for br_list.
signature immediate for block/loop.
wasm::ValType toValType(const MVT &Ty)
Machine Value Type.
MCCodeEmitter * createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII)
TOF
Target Operand Flag enum.
static const unsigned End
unsigned GetDefaultP2Align(unsigned Opcode)
Return the default p2align value for a load or store with the given opcode.
type signature immediate for call_indirect.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
ExprType
This is used to indicate block signatures.
MCAsmBackend * createWebAssemblyAsmBackend(const Triple &TT)
64-bit floating-point immediates.
32-bit unsigned function indices.
p2align immediate for load and store address alignment.
static const unsigned Nop
Instruction opcodes emitted via means other than CodeGen.