42class X86AlignBranchKind {
44 uint8_t AlignBranchKind = 0;
47 void operator=(
const std::string &Val) {
52 for (
auto BranchType : BranchTypes) {
53 if (BranchType ==
"fused")
55 else if (BranchType ==
"jcc")
57 else if (BranchType ==
"jmp")
59 else if (BranchType ==
"call")
61 else if (BranchType ==
"ret")
63 else if (BranchType ==
"indirect")
67 <<
" to -x86-align-branch=; each element must be one of: fused, "
68 "jcc, jmp, call, ret, indirect.(plus separated)\n";
73 operator uint8_t()
const {
return AlignBranchKind; }
77X86AlignBranchKind X86AlignBranchKindLoc;
80 "x86-align-branch-boundary",
cl::init(0),
82 "Control how the assembler should align branches with NOP. If the "
83 "boundary's size is not 0, it should be a power of 2 and no less "
84 "than 32. Branches will be aligned to prevent from being across or "
85 "against the boundary of specified size. The default value 0 does not "
91 "Specify types of branches to align (plus separated list of types):"
92 "\njcc indicates conditional jumps"
93 "\nfused indicates fused conditional jumps"
94 "\njmp indicates direct unconditional jumps"
95 "\ncall indicates direct and indirect calls"
96 "\nret indicates rets"
97 "\nindirect indicates indirect unconditional jumps"),
101 "x86-branches-within-32B-boundaries",
cl::init(
false),
103 "Align selected instructions to mitigate negative performance impact "
104 "of Intel's micro code update for errata skx102. May break "
105 "assumptions about labels corresponding to particular instructions, "
106 "and should be used with caution."));
109 "x86-pad-max-prefix-size",
cl::init(0),
110 cl::desc(
"Maximum number of prefixes to use for padding"));
114 cl::desc(
"Pad previous instructions to implement align directives"));
118 cl::desc(
"Pad previous instructions to implement branch alignment"));
122 std::unique_ptr<const MCInstrInfo> MCII;
123 X86AlignBranchKind AlignBranchType;
125 unsigned TargetPrefixMax = 0;
129 std::pair<MCFragment *, size_t> PrevInstPosition;
130 bool CanPadInst =
false;
132 uint8_t determinePaddingPrefix(
const MCInst &Inst)
const;
134 bool needAlign(
const MCInst &Inst)
const;
142 if (X86AlignBranchWithin32BBoundaries) {
153 if (X86AlignBranchBoundary.getNumOccurrences())
155 if (X86AlignBranch.getNumOccurrences())
156 AlignBranchType = X86AlignBranchKindLoc;
157 if (X86PadMaxPrefixSize.getNumOccurrences())
158 TargetPrefixMax = X86PadMaxPrefixSize;
196 unsigned &RemainingSize)
const;
199 unsigned &RemainingSize)
const;
202 unsigned &RemainingSize)
const;
214 return Opcode == X86::JCC_1 || Opcode == X86::JMP_1;
218 bool Is16BitMode =
false) {
223 return (Is16BitMode) ? X86::JCC_2 : X86::JCC_4;
225 return (Is16BitMode) ? X86::JMP_2 : X86::JMP_4;
230 unsigned Opcode =
MI.getOpcode();
237 unsigned Opcode =
MI.getOpcode();
244 MI.getOperand(
Desc.getNumOperands() - 1).getImm());
252 return classifySecondCondCodeInMacroFusion(
CC);
257 unsigned Opcode =
MI.getOpcode();
262 if (MemoryOperand < 0)
265 unsigned BaseReg =
MI.getOperand(BaseRegNum).getReg();
266 return (BaseReg == X86::RIP);
282 return FIK != X86::FirstMacroFusionInstKind::Invalid;
294uint8_t X86AsmBackend::determinePaddingPrefix(
const MCInst &Inst)
const {
296 "Prefixes can be added only in 32-bit or 64-bit mode.");
302 if (MemoryOperand != -1)
305 unsigned SegmentReg = 0;
306 if (MemoryOperand >= 0) {
339 if (MemoryOperand >= 0) {
342 if (BaseReg == X86::ESP || BaseReg == X86::EBP)
349bool X86AsmBackend::isMacroFused(
const MCInst &Cmp,
const MCInst &Jcc)
const {
364 for (
auto &Operand :
MI) {
365 if (!Operand.isExpr())
367 const MCExpr &Expr = *Operand.getExpr();
375bool X86AsmBackend::allowAutoPadding()
const {
379bool X86AsmBackend::allowEnhancedRelaxation()
const {
380 return allowAutoPadding() && TargetPrefixMax != 0 && X86PadForBranchAlign;
407 const std::pair<MCFragment *, size_t> &PrevInstPosition) {
412 for (; isa_and_nonnull<MCDataFragment>(
F);
F =
F->getPrevNode())
413 if (cast<MCDataFragment>(
F)->getContents().size() != 0)
426 if (
auto *
DF = dyn_cast_or_null<MCDataFragment>(
F))
427 return DF != PrevInstPosition.first ||
428 DF->getContents().size() != PrevInstPosition.second;
435 if (!
F || !
F->hasInstructions())
438 switch (
F->getKind()) {
442 return cast<MCDataFragment>(*F).getContents().size();
444 return cast<MCRelaxableFragment>(*F).getContents().size();
446 return cast<MCCompactEncodedInstFragment>(*F).getContents().size();
482 if (!
OS.getAllowAutoPadding())
484 assert(allowAutoPadding() &&
"incorrect initialization!");
487 if (!
OS.getCurrentSectionOnly()->getKind().isText())
491 if (
OS.getAssembler().isBundlingEnabled())
502bool X86AsmBackend::needAlign(
const MCInst &Inst)
const {
504 return (
Desc.isConditionalBranch() &&
506 (
Desc.isUnconditionalBranch() &&
510 (
Desc.isIndirectBranch() &&
517 CanPadInst = canPadInst(Inst,
OS);
519 if (!canPadBranches(
OS))
529 if (PendingBA &&
OS.getCurrentFragment()->getPrevNode() == PendingBA) {
564 if (
auto *
F = dyn_cast_or_null<MCRelaxableFragment>(CF))
565 F->setAllowAutoPadding(CanPadInst);
567 if (!canPadBranches(
OS))
570 if (!needAlign(Inst) || !PendingBA)
581 if (isa_and_nonnull<MCDataFragment>(CF))
589std::optional<MCFixupKind> X86AsmBackend::getFixupKind(
StringRef Name)
const {
594#define ELF_RELOC(X, Y) .Case(#X, Y)
595#include "llvm/BinaryFormat/ELFRelocs/x86_64.def"
597 .
Case(
"BFD_RELOC_NONE", ELF::R_X86_64_NONE)
598 .
Case(
"BFD_RELOC_8", ELF::R_X86_64_8)
599 .
Case(
"BFD_RELOC_16", ELF::R_X86_64_16)
600 .
Case(
"BFD_RELOC_32", ELF::R_X86_64_32)
601 .
Case(
"BFD_RELOC_64", ELF::R_X86_64_64)
605#define ELF_RELOC(X, Y) .Case(#X, Y)
606#include "llvm/BinaryFormat/ELFRelocs/i386.def"
608 .
Case(
"BFD_RELOC_NONE", ELF::R_386_NONE)
609 .
Case(
"BFD_RELOC_8", ELF::R_386_8)
610 .
Case(
"BFD_RELOC_16", ELF::R_386_16)
611 .
Case(
"BFD_RELOC_32", ELF::R_386_32)
627 {
"reloc_signed_4byte", 0, 32, 0},
628 {
"reloc_signed_4byte_relax", 0, 32, 0},
629 {
"reloc_global_offset_table", 0, 32, 0},
630 {
"reloc_global_offset_table8", 0, 64, 0},
648bool X86AsmBackend::shouldForceRelocation(
const MCAssembler &,
698 assert(
Fixup.getOffset() +
Size <= Data.size() &&
"Invalid fixup offset!");
700 int64_t SignedValue =
static_cast<int64_t
>(
Value);
701 if ((
Target.isAbsolute() || IsResolved) &&
702 getFixupKindInfo(
Fixup.getKind()).Flags &
706 Asm.getContext().reportError(
707 Fixup.getLoc(),
"value of " +
Twine(SignedValue) +
708 " is too large for field of " +
Twine(
Size) +
709 ((
Size == 1) ?
" byte." :
" bytes."));
716 "Value does not fit in the Fixup field");
719 for (
unsigned i = 0; i !=
Size; ++i)
720 Data[
Fixup.getOffset() + i] = uint8_t(
Value >> (i * 8));
723bool X86AsmBackend::mayNeedRelaxation(
const MCInst &
MI,
725 unsigned Opcode =
MI.getOpcode();
728 MI.getOperand(
MI.getNumOperands() - 1).isExpr());
731bool X86AsmBackend::fixupNeedsRelaxation(
const MCFixup &
Fixup,
736 return !isInt<8>(
Value);
741void X86AsmBackend::relaxInstruction(
MCInst &Inst,
744 bool Is16BitMode = STI.
hasFeature(X86::Is16Bit);
760 unsigned &RemainingSize)
const {
774 const unsigned MaxPossiblePad = std::min(15 - OldSize, RemainingSize);
775 const unsigned RemainingPrefixSize = [&]() ->
unsigned {
778 assert(
Code.size() < 15 &&
"The number of prefixes must be less than 15.");
785 unsigned ExistingPrefixSize =
Code.size();
786 if (TargetPrefixMax <= ExistingPrefixSize)
788 return TargetPrefixMax - ExistingPrefixSize;
790 const unsigned PrefixBytesToAdd =
791 std::min(MaxPossiblePad, RemainingPrefixSize);
792 if (PrefixBytesToAdd == 0)
798 Code.append(PrefixBytesToAdd, Prefix);
804 F.setOffset(
F.getOffset() + PrefixBytesToAdd);
807 RemainingSize -= PrefixBytesToAdd;
813 unsigned &RemainingSize)
const {
826 const unsigned NewSize =
Code.size();
827 assert(NewSize >= OldSize &&
"size decrease during relaxation?");
828 unsigned Delta = NewSize - OldSize;
829 if (Delta > RemainingSize)
834 RemainingSize -= Delta;
840 unsigned &RemainingSize)
const {
841 bool Changed =
false;
842 if (RemainingSize != 0)
843 Changed |= padInstructionViaRelaxation(RF,
Emitter, RemainingSize);
844 if (RemainingSize != 0)
845 Changed |= padInstructionViaPrefix(RF,
Emitter, RemainingSize);
849void X86AsmBackend::finishLayout(
MCAssembler const &Asm,
857 if (!X86PadForAlign && !X86PadForBranchAlign)
865 LabeledFragments.
insert(S.getFragment(
false));
875 if (LabeledFragments.
count(&
F))
884 auto &RF = cast<MCRelaxableFragment>(*
I);
890 switch (
F.getKind()) {
894 return X86PadForAlign;
896 return X86PadForBranchAlign;
908 const uint64_t OrigSize =
Asm.computeFragmentSize(Layout,
F);
915 unsigned RemainingSize = OrigSize;
916 while (!Relaxable.
empty() && RemainingSize != 0) {
921 if (padInstructionEncoding(RF,
Asm.getEmitter(), RemainingSize))
922 FirstChangedFragment = &RF;
935 if (FirstChangedFragment) {
944 cast<MCBoundaryAlignFragment>(
F).setSize(RemainingSize);
948 const uint64_t FinalSize =
Asm.computeFragmentSize(Layout,
F);
949 assert(OrigOffset + OrigSize == FinalOffset + FinalSize &&
950 "can't move start of next fragment!");
951 assert(FinalSize == RemainingSize &&
"inconsistent size computation?");
957 if (
auto *BF = dyn_cast<MCBoundaryAlignFragment>(&
F)) {
958 const MCFragment *LastFragment = BF->getLastFragment();
961 while (&*
I != LastFragment)
968 for (
unsigned int i = 0, n = Layout.
getSectionOrder().size(); i != n; ++i) {
971 Asm.computeFragmentSize(Layout, *
Section.getFragmentList().rbegin());
975unsigned X86AsmBackend::getMaximumNopSize(
const MCSubtargetInfo &STI)
const {
997 static const char Nops32Bit[10][11] = {
1007 "\x0f\x1f\x44\x00\x00",
1009 "\x66\x0f\x1f\x44\x00\x00",
1011 "\x0f\x1f\x80\x00\x00\x00\x00",
1013 "\x0f\x1f\x84\x00\x00\x00\x00\x00",
1015 "\x66\x0f\x1f\x84\x00\x00\x00\x00\x00",
1017 "\x66\x2e\x0f\x1f\x84\x00\x00\x00\x00\x00",
1021 static const char Nops16Bit[4][11] = {
1032 const char(*Nops)[11] =
1033 STI->
hasFeature(X86::Is16Bit) ? Nops16Bit : Nops32Bit;
1040 const uint8_t ThisNopLength = (uint8_t) std::min(Count, MaxNopLength);
1041 const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
1042 for (uint8_t i = 0; i < Prefixes; i++)
1044 const uint8_t Rest = ThisNopLength - Prefixes;
1046 OS.
write(Nops[Rest - 1], Rest);
1047 Count -= ThisNopLength;
1048 }
while (Count != 0);
1057class ELFX86AsmBackend :
public X86AsmBackend {
1061 : X86AsmBackend(
T, STI), OSABI(OSABI) {}
1064class ELFX86_32AsmBackend :
public ELFX86AsmBackend {
1066 ELFX86_32AsmBackend(
const Target &
T, uint8_t OSABI,
1068 : ELFX86AsmBackend(
T, OSABI, STI) {}
1070 std::unique_ptr<MCObjectTargetWriter>
1071 createObjectTargetWriter()
const override {
1076class ELFX86_X32AsmBackend :
public ELFX86AsmBackend {
1078 ELFX86_X32AsmBackend(
const Target &
T, uint8_t OSABI,
1080 : ELFX86AsmBackend(
T, OSABI, STI) {}
1082 std::unique_ptr<MCObjectTargetWriter>
1083 createObjectTargetWriter()
const override {
1089class ELFX86_IAMCUAsmBackend :
public ELFX86AsmBackend {
1091 ELFX86_IAMCUAsmBackend(
const Target &
T, uint8_t OSABI,
1093 : ELFX86AsmBackend(
T, OSABI, STI) {}
1095 std::unique_ptr<MCObjectTargetWriter>
1096 createObjectTargetWriter()
const override {
1102class ELFX86_64AsmBackend :
public ELFX86AsmBackend {
1104 ELFX86_64AsmBackend(
const Target &
T, uint8_t OSABI,
1106 : ELFX86AsmBackend(
T, OSABI, STI) {}
1108 std::unique_ptr<MCObjectTargetWriter>
1109 createObjectTargetWriter()
const override {
1114class WindowsX86AsmBackend :
public X86AsmBackend {
1120 : X86AsmBackend(
T, STI)
1124 std::optional<MCFixupKind> getFixupKind(
StringRef Name)
const override {
1132 std::unique_ptr<MCObjectTargetWriter>
1133 createObjectTargetWriter()
const override {
1144 UNWIND_MODE_BP_FRAME = 0x01000000,
1147 UNWIND_MODE_STACK_IMMD = 0x02000000,
1150 UNWIND_MODE_STACK_IND = 0x03000000,
1153 UNWIND_MODE_DWARF = 0x04000000,
1156 UNWIND_BP_FRAME_REGISTERS = 0x00007FFF,
1159 UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF
1164class DarwinX86AsmBackend :
public X86AsmBackend {
1168 enum { CU_NUM_SAVED_REGS = 6 };
1170 mutable unsigned SavedRegs[CU_NUM_SAVED_REGS];
1174 unsigned OffsetSize;
1175 unsigned MoveInstrSize;
1176 unsigned StackDivide;
1179 unsigned PushInstrSize(
unsigned Reg)
const {
1202 int getCompactUnwindRegNum(
unsigned Reg)
const {
1203 static const MCPhysReg CU32BitRegs[7] = {
1204 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
1206 static const MCPhysReg CU64BitRegs[] = {
1207 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
1209 const MCPhysReg *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
1210 for (
int Idx = 1; *CURegs; ++CURegs, ++
Idx)
1219 uint32_t encodeCompactUnwindRegistersWithFrame()
const {
1224 for (
int i = 0,
Idx = 0; i != CU_NUM_SAVED_REGS; ++i) {
1225 unsigned Reg = SavedRegs[i];
1226 if (Reg == 0)
break;
1228 int CURegNum = getCompactUnwindRegNum(Reg);
1229 if (CURegNum == -1)
return ~0
U;
1233 RegEnc |= (CURegNum & 0x7) << (
Idx++ * 3);
1236 assert((RegEnc & 0x3FFFF) == RegEnc &&
1237 "Invalid compact register encoding!");
1244 uint32_t encodeCompactUnwindRegistersWithoutFrame(
unsigned RegCount)
const {
1258 for (
unsigned i = 0; i < RegCount; ++i) {
1259 int CUReg = getCompactUnwindRegNum(SavedRegs[i]);
1260 if (CUReg == -1)
return ~0
U;
1261 SavedRegs[i] = CUReg;
1265 std::reverse(&SavedRegs[0], &SavedRegs[CU_NUM_SAVED_REGS]);
1267 uint32_t RenumRegs[CU_NUM_SAVED_REGS];
1268 for (
unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){
1269 unsigned Countless = 0;
1270 for (
unsigned j = CU_NUM_SAVED_REGS - RegCount;
j < i; ++
j)
1271 if (SavedRegs[j] < SavedRegs[i])
1274 RenumRegs[i] = SavedRegs[i] - Countless - 1;
1281 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
1282 + 6 * RenumRegs[2] + 2 * RenumRegs[3]
1286 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
1287 + 6 * RenumRegs[3] + 2 * RenumRegs[4]
1291 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
1292 + 3 * RenumRegs[4] + RenumRegs[5];
1295 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
1299 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
1302 permutationEncoding |= RenumRegs[5];
1306 assert((permutationEncoding & 0x3FF) == permutationEncoding &&
1307 "Invalid compact register encoding!");
1308 return permutationEncoding;
1314 : X86AsmBackend(
T, STI),
MRI(
MRI),
TT(STI.getTargetTriple()),
1315 Is64Bit(
TT.isArch64Bit()) {
1316 memset(SavedRegs, 0,
sizeof(SavedRegs));
1317 OffsetSize = Is64Bit ? 8 : 4;
1318 MoveInstrSize = Is64Bit ? 3 : 2;
1319 StackDivide = Is64Bit ? 8 : 4;
1322 std::unique_ptr<MCObjectTargetWriter>
1323 createObjectTargetWriter()
const override {
1334 if (Instrs.
empty())
return 0;
1335 if (!isDarwinCanonicalPersonality(FI->
Personality) &&
1337 return CU::UNWIND_MODE_DWARF;
1340 unsigned SavedRegIdx = 0;
1341 memset(SavedRegs, 0,
sizeof(SavedRegs));
1346 uint32_t CompactUnwindEncoding = 0;
1348 unsigned SubtractInstrIdx = Is64Bit ? 3 : 2;
1349 unsigned InstrOffset = 0;
1350 unsigned StackAdjust = 0;
1351 unsigned StackSize = 0;
1352 int MinAbsOffset = std::numeric_limits<int>::max();
1355 switch (Inst.getOperation()) {
1359 return CU::UNWIND_MODE_DWARF;
1371 if (*
MRI.getLLVMRegNum(Inst.getRegister(),
true) !=
1372 (Is64Bit ? X86::RBP : X86::EBP))
1373 return CU::UNWIND_MODE_DWARF;
1376 memset(SavedRegs, 0,
sizeof(SavedRegs));
1379 MinAbsOffset = std::numeric_limits<int>::max();
1380 InstrOffset += MoveInstrSize;
1398 StackSize = Inst.getOffset() / StackDivide;
1414 if (SavedRegIdx == CU_NUM_SAVED_REGS)
1417 return CU::UNWIND_MODE_DWARF;
1419 unsigned Reg = *
MRI.getLLVMRegNum(Inst.getRegister(),
true);
1420 SavedRegs[SavedRegIdx++] =
Reg;
1421 StackAdjust += OffsetSize;
1422 MinAbsOffset = std::min(MinAbsOffset,
abs(Inst.getOffset()));
1423 InstrOffset += PushInstrSize(Reg);
1429 StackAdjust /= StackDivide;
1432 if ((StackAdjust & 0xFF) != StackAdjust)
1434 return CU::UNWIND_MODE_DWARF;
1438 if (SavedRegIdx != 0 && MinAbsOffset != 3 * (
int)OffsetSize)
1439 return CU::UNWIND_MODE_DWARF;
1442 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame();
1443 if (RegEnc == ~0U)
return CU::UNWIND_MODE_DWARF;
1445 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
1446 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
1447 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
1449 SubtractInstrIdx += InstrOffset;
1452 if ((StackSize & 0xFF) == StackSize) {
1454 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
1457 CompactUnwindEncoding |= (StackSize & 0xFF) << 16;
1459 if ((StackAdjust & 0x7) != StackAdjust)
1461 return CU::UNWIND_MODE_DWARF;
1464 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
1468 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
1471 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
1475 std::reverse(&SavedRegs[0], &SavedRegs[SavedRegIdx]);
1476 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
1480 uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx);
1481 if (RegEnc == ~0U)
return CU::UNWIND_MODE_DWARF;
1484 CompactUnwindEncoding |=
1485 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
1488 return CompactUnwindEncoding;
1500 return new DarwinX86AsmBackend(
T,
MRI, STI);
1503 return new WindowsX86AsmBackend(
T,
false, STI);
1508 return new ELFX86_IAMCUAsmBackend(
T, OSABI, STI);
1510 return new ELFX86_32AsmBackend(
T, OSABI, STI);
1519 return new DarwinX86AsmBackend(
T,
MRI, STI);
1522 return new WindowsX86AsmBackend(
T,
true, STI);
1524 if (TheTriple.
isUEFI()) {
1526 "Only COFF format is supported in UEFI environment.");
1527 return new WindowsX86AsmBackend(
T,
true, STI);
1532 if (TheTriple.
isX32())
1533 return new ELFX86_X32AsmBackend(
T, OSABI, STI);
1534 return new ELFX86_64AsmBackend(
T, OSABI, STI);
unsigned const MachineRegisterInfo * MRI
dxil DXContainer Global Emitter
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static MCInstrInfo * createMCInstrInfo()
static unsigned getRelaxedOpcodeBranch(unsigned Opcode, bool Is16BitMode=false)
static X86::SecondMacroFusionInstKind classifySecondInstInMacroFusion(const MCInst &MI, const MCInstrInfo &MCII)
static size_t getSizeForInstFragment(const MCFragment *F)
static bool isRIPRelative(const MCInst &MI, const MCInstrInfo &MCII)
Check if the instruction uses RIP relative addressing.
static bool isRightAfterData(MCFragment *CurrentFragment, const std::pair< MCFragment *, size_t > &PrevInstPosition)
Check if the instruction to be emitted is right after any data.
static bool isPrefix(const MCInst &MI, const MCInstrInfo &MCII)
Check if the instruction is a prefix.
static bool hasInterruptDelaySlot(const MCInst &Inst)
X86 has certain instructions which enable interrupts exactly one instruction after the instruction wh...
static bool isFirstMacroFusibleInst(const MCInst &Inst, const MCInstrInfo &MCII)
Check if the instruction is valid as the first instruction in macro fusion.
static X86::CondCode getCondFromBranch(const MCInst &MI, const MCInstrInfo &MCII)
static unsigned getRelaxedOpcode(const MCInst &MI, bool Is16BitMode)
static unsigned getFixupKindSize(unsigned Kind)
static bool isRelaxableBranch(unsigned Opcode)
static bool hasVariantSymbol(const MCInst &MI)
Check if the instruction has a variant symbol operand.
static bool is64Bit(const char *name)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool empty() const
empty - Check if the array is empty.
Implements a dense probed hash-table based set.
Generic interface to target specific assembler backends.
virtual bool allowEnhancedRelaxation() const
Return true if this target allows an unrelaxable instruction to be emitted into RelaxableFragment and...
virtual unsigned getMaximumNopSize(const MCSubtargetInfo &STI) const
Returns the maximum size of a nop in bytes on this target.
virtual bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const =0
Write an (optimal) nop sequence of Count bytes to the given output.
virtual void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const
Relax the instruction in the given fragment to the next wider instruction.
virtual bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const
Check whether the given instruction may need relaxation.
virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const =0
Simple predicate for targets where !Resolved implies requiring relaxation.
virtual void finishLayout(MCAssembler const &Asm, MCAsmLayout &Layout) const
Give backend an opportunity to finish layout after relaxation.
virtual void emitInstructionEnd(MCObjectStreamer &OS, const MCInst &Inst)
virtual void emitInstructionBegin(MCObjectStreamer &OS, const MCInst &Inst, const MCSubtargetInfo &STI)
Give the target a chance to manipulate state related to instruction alignment (e.g.
virtual bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, const MCSubtargetInfo *STI)
Hook to check if a relocation is needed for some target specific reason.
virtual unsigned getNumFixupKinds() const =0
Get the number of target specific fixup kinds.
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
virtual std::optional< MCFixupKind > getFixupKind(StringRef Name) const
Map a relocation name used in .reloc to a fixup kind.
virtual void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const =0
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
virtual bool allowAutoPadding() const
Return true if this target might automatically pad instructions and thus need to emit padding enable/...
Encapsulates the layout of an assembly file at a particular point in time.
void invalidateFragmentsFrom(MCFragment *F)
Invalidate the fragments starting with F because it has been resized.
llvm::SmallVectorImpl< MCSection * > & getSectionOrder()
uint64_t getFragmentOffset(const MCFragment *F) const
Get the offset of the given fragment inside its containing section.
Represents required padding such that a particular other set of fragments does not cross a particular...
void setLastFragment(const MCFragment *F)
MCCodeEmitter - Generic instruction encoding interface.
Context object for machine code objects.
bool emitCompactUnwindNonCanonical() const
Fragment for data and encoded instructions.
SmallVectorImpl< char > & getContents()
SmallVectorImpl< MCFixup > & getFixups()
const MCSubtargetInfo * getSubtargetInfo() const
Retrieve the MCSubTargetInfo in effect when the instruction was encoded.
Base class for the full range of assembler expressions which are needed for parsing.
@ SymbolRef
References to labels and assigned expressions.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Instances of this class represent a single low-level machine instruction.
void dump_pretty(raw_ostream &OS, const MCInstPrinter *Printer=nullptr, StringRef Separator=" ", const MCRegisterInfo *RegInfo=nullptr) const
Dump the MCInst as prettily as possible using the additional MC structures, if given.
unsigned getOpcode() const
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Streaming object file generation interface.
unsigned getReg() const
Returns the register number.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
bool getAllowAutoPadding() const
const MCInst & getInst() const
void setInst(const MCInst &Value)
Instances of this class represent a uniqued identifier for a section in the current translation unit.
void ensureMinAlignment(Align MinAlignment)
Makes sure that Alignment is at least MinAlignment.
SectionKind getKind() const
FragmentListType::iterator iterator
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
This represents an "assembler immediate".
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
bool isX32() const
Tests whether the target is X32.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
OSType getOS() const
Get the parsed operating system type of this triple.
ArchType getArch() const
Get the parsed architecture type of this triple.
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
bool isUEFI() const
Tests whether the OS is UEFI.
bool isOSWindows() const
Tests whether the OS is Windows.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
std::pair< iterator, bool > insert(const ValueT &V)
size_type count(const_arg_type_t< ValueT > V) const
Return 1 if the specified key is in the set, 0 otherwise.
This class implements an extremely fast bulk output stream that can only output to a stream.
raw_ostream & write(unsigned char C)
A raw_ostream that writes to an SmallVector or SmallString.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
CompactUnwindEncodings
Compact unwind encoding values.
Expected< uint32_t > getCPUSubType(const Triple &T)
Expected< uint32_t > getCPUType(const Triple &T)
Reg
All possible values of the reg field in the ModR/M byte.
bool isPrefix(uint64_t TSFlags)
@ RawFrmDstSrc
RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...
@ RawFrmSrc
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
@ RawFrmMemOffs
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
int getMemoryOperandNo(uint64_t TSFlags)
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
FirstMacroFusionInstKind classifyFirstOpcodeInMacroFusion(unsigned Opcode)
AlignBranchBoundaryKind
Defines the possible values of the branch boundary alignment mask.
SecondMacroFusionInstKind
unsigned getOpcodeForLongImmediateForm(unsigned Opcode)
EncodingOfSegmentOverridePrefix getSegmentOverridePrefixForReg(unsigned Reg)
Given a segment register, return the encoding of the segment override prefix for it.
bool isMacroFused(FirstMacroFusionInstKind FirstKind, SecondMacroFusionInstKind SecondKind)
@ reloc_global_offset_table8
@ reloc_signed_4byte_relax
@ reloc_branch_4byte_pcrel
@ reloc_riprel_4byte_relax
@ reloc_riprel_4byte_relax_rex
@ reloc_global_offset_table
@ reloc_riprel_4byte_movq_load
initializer< Ty > init(const Ty &Val)
LocationClass< Ty > location(Ty &L)
NodeAddr< CodeNode * > Code
This is an optimization pass for GlobalISel generic memory operations.
APFloat abs(APFloat X)
Returns the absolute value of the argument.
MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createX86WinCOFFObjectWriter(bool Is64Bit)
Construct an X86 Win COFF object writer.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ FK_PCRel_4
A four-byte pc relative fixup.
@ FK_PCRel_2
A two-byte pc relative fixup.
@ FK_SecRel_2
A two-byte section relative fixup.
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
@ FK_Data_8
A eight-byte fixup.
@ FK_Data_1
A one-byte fixup.
@ FK_Data_4
A four-byte fixup.
@ FK_SecRel_8
A eight-byte section relative fixup.
@ FK_PCRel_8
A eight-byte pc relative fixup.
@ FK_SecRel_4
A four-byte section relative fixup.
@ FK_PCRel_1
A one-byte pc relative fixup.
@ FK_SecRel_1
A one-byte section relative fixup.
@ FK_Data_2
A two-byte fixup.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
std::unique_ptr< MCObjectTargetWriter > createX86MachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
Construct an X86 Mach-O object writer.
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
std::unique_ptr< MCObjectTargetWriter > createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine)
Construct an X86 ELF object writer.
Align assumeAligned(uint64_t Value)
Treats the value 0 as a 1, so Align is always at least 1.
MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Description of the encoding of one expression Op.
const MCSymbol * Personality
std::vector< MCCFIInstruction > Instructions
Target independent information on a fixup kind.
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...