LLVM  9.0.0svn
X86AsmParser.cpp
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1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
11 #include "MCTargetDesc/X86MCExpr.h"
13 #include "X86AsmParserCommon.h"
14 #include "X86Operand.h"
15 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/ADT/SmallString.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
28 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/MC/MCSection.h"
30 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/MC/MCSymbol.h"
33 #include "llvm/Support/SourceMgr.h"
36 #include <algorithm>
37 #include <memory>
38 
39 using namespace llvm;
40 
41 static bool checkScale(unsigned Scale, StringRef &ErrMsg) {
42  if (Scale != 1 && Scale != 2 && Scale != 4 && Scale != 8) {
43  ErrMsg = "scale factor in address must be 1, 2, 4 or 8";
44  return true;
45  }
46  return false;
47 }
48 
49 namespace {
50 
51 static const char OpPrecedence[] = {
52  0, // IC_OR
53  1, // IC_XOR
54  2, // IC_AND
55  3, // IC_LSHIFT
56  3, // IC_RSHIFT
57  4, // IC_PLUS
58  4, // IC_MINUS
59  5, // IC_MULTIPLY
60  5, // IC_DIVIDE
61  5, // IC_MOD
62  6, // IC_NOT
63  7, // IC_NEG
64  8, // IC_RPAREN
65  9, // IC_LPAREN
66  0, // IC_IMM
67  0 // IC_REGISTER
68 };
69 
70 class X86AsmParser : public MCTargetAsmParser {
71  ParseInstructionInfo *InstInfo;
72  bool Code16GCC;
73 
74 private:
75  SMLoc consumeToken() {
76  MCAsmParser &Parser = getParser();
77  SMLoc Result = Parser.getTok().getLoc();
78  Parser.Lex();
79  return Result;
80  }
81 
82  X86TargetStreamer &getTargetStreamer() {
83  assert(getParser().getStreamer().getTargetStreamer() &&
84  "do not have a target streamer");
85  MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
86  return static_cast<X86TargetStreamer &>(TS);
87  }
88 
89  unsigned MatchInstruction(const OperandVector &Operands, MCInst &Inst,
90  uint64_t &ErrorInfo, FeatureBitset &MissingFeatures,
91  bool matchingInlineAsm, unsigned VariantID = 0) {
92  // In Code16GCC mode, match as 32-bit.
93  if (Code16GCC)
94  SwitchMode(X86::Mode32Bit);
95  unsigned rv = MatchInstructionImpl(Operands, Inst, ErrorInfo,
96  MissingFeatures, matchingInlineAsm,
97  VariantID);
98  if (Code16GCC)
99  SwitchMode(X86::Mode16Bit);
100  return rv;
101  }
102 
103  enum InfixCalculatorTok {
104  IC_OR = 0,
105  IC_XOR,
106  IC_AND,
107  IC_LSHIFT,
108  IC_RSHIFT,
109  IC_PLUS,
110  IC_MINUS,
111  IC_MULTIPLY,
112  IC_DIVIDE,
113  IC_MOD,
114  IC_NOT,
115  IC_NEG,
116  IC_RPAREN,
117  IC_LPAREN,
118  IC_IMM,
119  IC_REGISTER
120  };
121 
122  enum IntelOperatorKind {
123  IOK_INVALID = 0,
124  IOK_LENGTH,
125  IOK_SIZE,
126  IOK_TYPE,
127  IOK_OFFSET
128  };
129 
130  class InfixCalculator {
131  typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
132  SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
133  SmallVector<ICToken, 4> PostfixStack;
134 
135  bool isUnaryOperator(const InfixCalculatorTok Op) {
136  return Op == IC_NEG || Op == IC_NOT;
137  }
138 
139  public:
140  int64_t popOperand() {
141  assert (!PostfixStack.empty() && "Poped an empty stack!");
142  ICToken Op = PostfixStack.pop_back_val();
143  if (!(Op.first == IC_IMM || Op.first == IC_REGISTER))
144  return -1; // The invalid Scale value will be caught later by checkScale
145  return Op.second;
146  }
147  void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) {
148  assert ((Op == IC_IMM || Op == IC_REGISTER) &&
149  "Unexpected operand!");
150  PostfixStack.push_back(std::make_pair(Op, Val));
151  }
152 
153  void popOperator() { InfixOperatorStack.pop_back(); }
154  void pushOperator(InfixCalculatorTok Op) {
155  // Push the new operator if the stack is empty.
156  if (InfixOperatorStack.empty()) {
157  InfixOperatorStack.push_back(Op);
158  return;
159  }
160 
161  // Push the new operator if it has a higher precedence than the operator
162  // on the top of the stack or the operator on the top of the stack is a
163  // left parentheses.
164  unsigned Idx = InfixOperatorStack.size() - 1;
165  InfixCalculatorTok StackOp = InfixOperatorStack[Idx];
166  if (OpPrecedence[Op] > OpPrecedence[StackOp] || StackOp == IC_LPAREN) {
167  InfixOperatorStack.push_back(Op);
168  return;
169  }
170 
171  // The operator on the top of the stack has higher precedence than the
172  // new operator.
173  unsigned ParenCount = 0;
174  while (1) {
175  // Nothing to process.
176  if (InfixOperatorStack.empty())
177  break;
178 
179  Idx = InfixOperatorStack.size() - 1;
180  StackOp = InfixOperatorStack[Idx];
181  if (!(OpPrecedence[StackOp] >= OpPrecedence[Op] || ParenCount))
182  break;
183 
184  // If we have an even parentheses count and we see a left parentheses,
185  // then stop processing.
186  if (!ParenCount && StackOp == IC_LPAREN)
187  break;
188 
189  if (StackOp == IC_RPAREN) {
190  ++ParenCount;
191  InfixOperatorStack.pop_back();
192  } else if (StackOp == IC_LPAREN) {
193  --ParenCount;
194  InfixOperatorStack.pop_back();
195  } else {
196  InfixOperatorStack.pop_back();
197  PostfixStack.push_back(std::make_pair(StackOp, 0));
198  }
199  }
200  // Push the new operator.
201  InfixOperatorStack.push_back(Op);
202  }
203 
204  int64_t execute() {
205  // Push any remaining operators onto the postfix stack.
206  while (!InfixOperatorStack.empty()) {
207  InfixCalculatorTok StackOp = InfixOperatorStack.pop_back_val();
208  if (StackOp != IC_LPAREN && StackOp != IC_RPAREN)
209  PostfixStack.push_back(std::make_pair(StackOp, 0));
210  }
211 
212  if (PostfixStack.empty())
213  return 0;
214 
215  SmallVector<ICToken, 16> OperandStack;
216  for (unsigned i = 0, e = PostfixStack.size(); i != e; ++i) {
217  ICToken Op = PostfixStack[i];
218  if (Op.first == IC_IMM || Op.first == IC_REGISTER) {
219  OperandStack.push_back(Op);
220  } else if (isUnaryOperator(Op.first)) {
221  assert (OperandStack.size() > 0 && "Too few operands.");
222  ICToken Operand = OperandStack.pop_back_val();
223  assert (Operand.first == IC_IMM &&
224  "Unary operation with a register!");
225  switch (Op.first) {
226  default:
227  report_fatal_error("Unexpected operator!");
228  break;
229  case IC_NEG:
230  OperandStack.push_back(std::make_pair(IC_IMM, -Operand.second));
231  break;
232  case IC_NOT:
233  OperandStack.push_back(std::make_pair(IC_IMM, ~Operand.second));
234  break;
235  }
236  } else {
237  assert (OperandStack.size() > 1 && "Too few operands.");
238  int64_t Val;
239  ICToken Op2 = OperandStack.pop_back_val();
240  ICToken Op1 = OperandStack.pop_back_val();
241  switch (Op.first) {
242  default:
243  report_fatal_error("Unexpected operator!");
244  break;
245  case IC_PLUS:
246  Val = Op1.second + Op2.second;
247  OperandStack.push_back(std::make_pair(IC_IMM, Val));
248  break;
249  case IC_MINUS:
250  Val = Op1.second - Op2.second;
251  OperandStack.push_back(std::make_pair(IC_IMM, Val));
252  break;
253  case IC_MULTIPLY:
254  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
255  "Multiply operation with an immediate and a register!");
256  Val = Op1.second * Op2.second;
257  OperandStack.push_back(std::make_pair(IC_IMM, Val));
258  break;
259  case IC_DIVIDE:
260  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
261  "Divide operation with an immediate and a register!");
262  assert (Op2.second != 0 && "Division by zero!");
263  Val = Op1.second / Op2.second;
264  OperandStack.push_back(std::make_pair(IC_IMM, Val));
265  break;
266  case IC_MOD:
267  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
268  "Modulo operation with an immediate and a register!");
269  Val = Op1.second % Op2.second;
270  OperandStack.push_back(std::make_pair(IC_IMM, Val));
271  break;
272  case IC_OR:
273  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
274  "Or operation with an immediate and a register!");
275  Val = Op1.second | Op2.second;
276  OperandStack.push_back(std::make_pair(IC_IMM, Val));
277  break;
278  case IC_XOR:
279  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
280  "Xor operation with an immediate and a register!");
281  Val = Op1.second ^ Op2.second;
282  OperandStack.push_back(std::make_pair(IC_IMM, Val));
283  break;
284  case IC_AND:
285  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
286  "And operation with an immediate and a register!");
287  Val = Op1.second & Op2.second;
288  OperandStack.push_back(std::make_pair(IC_IMM, Val));
289  break;
290  case IC_LSHIFT:
291  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
292  "Left shift operation with an immediate and a register!");
293  Val = Op1.second << Op2.second;
294  OperandStack.push_back(std::make_pair(IC_IMM, Val));
295  break;
296  case IC_RSHIFT:
297  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
298  "Right shift operation with an immediate and a register!");
299  Val = Op1.second >> Op2.second;
300  OperandStack.push_back(std::make_pair(IC_IMM, Val));
301  break;
302  }
303  }
304  }
305  assert (OperandStack.size() == 1 && "Expected a single result.");
306  return OperandStack.pop_back_val().second;
307  }
308  };
309 
310  enum IntelExprState {
311  IES_INIT,
312  IES_OR,
313  IES_XOR,
314  IES_AND,
315  IES_LSHIFT,
316  IES_RSHIFT,
317  IES_PLUS,
318  IES_MINUS,
319  IES_NOT,
320  IES_MULTIPLY,
321  IES_DIVIDE,
322  IES_MOD,
323  IES_LBRAC,
324  IES_RBRAC,
325  IES_LPAREN,
326  IES_RPAREN,
327  IES_REGISTER,
328  IES_INTEGER,
329  IES_IDENTIFIER,
330  IES_ERROR
331  };
332 
333  class IntelExprStateMachine {
334  IntelExprState State, PrevState;
335  unsigned BaseReg, IndexReg, TmpReg, Scale;
336  int64_t Imm;
337  const MCExpr *Sym;
338  StringRef SymName;
339  InfixCalculator IC;
341  short BracCount;
342  bool MemExpr;
343 
344  public:
345  IntelExprStateMachine()
346  : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0),
347  TmpReg(0), Scale(0), Imm(0), Sym(nullptr), BracCount(0),
348  MemExpr(false) {}
349 
350  void addImm(int64_t imm) { Imm += imm; }
351  short getBracCount() { return BracCount; }
352  bool isMemExpr() { return MemExpr; }
353  unsigned getBaseReg() { return BaseReg; }
354  unsigned getIndexReg() { return IndexReg; }
355  unsigned getScale() { return Scale; }
356  const MCExpr *getSym() { return Sym; }
357  StringRef getSymName() { return SymName; }
358  int64_t getImm() { return Imm + IC.execute(); }
359  bool isValidEndState() {
360  return State == IES_RBRAC || State == IES_INTEGER;
361  }
362  bool hadError() { return State == IES_ERROR; }
363  InlineAsmIdentifierInfo &getIdentifierInfo() { return Info; }
364 
365  void onOr() {
366  IntelExprState CurrState = State;
367  switch (State) {
368  default:
369  State = IES_ERROR;
370  break;
371  case IES_INTEGER:
372  case IES_RPAREN:
373  case IES_REGISTER:
374  State = IES_OR;
375  IC.pushOperator(IC_OR);
376  break;
377  }
378  PrevState = CurrState;
379  }
380  void onXor() {
381  IntelExprState CurrState = State;
382  switch (State) {
383  default:
384  State = IES_ERROR;
385  break;
386  case IES_INTEGER:
387  case IES_RPAREN:
388  case IES_REGISTER:
389  State = IES_XOR;
390  IC.pushOperator(IC_XOR);
391  break;
392  }
393  PrevState = CurrState;
394  }
395  void onAnd() {
396  IntelExprState CurrState = State;
397  switch (State) {
398  default:
399  State = IES_ERROR;
400  break;
401  case IES_INTEGER:
402  case IES_RPAREN:
403  case IES_REGISTER:
404  State = IES_AND;
405  IC.pushOperator(IC_AND);
406  break;
407  }
408  PrevState = CurrState;
409  }
410  void onLShift() {
411  IntelExprState CurrState = State;
412  switch (State) {
413  default:
414  State = IES_ERROR;
415  break;
416  case IES_INTEGER:
417  case IES_RPAREN:
418  case IES_REGISTER:
419  State = IES_LSHIFT;
420  IC.pushOperator(IC_LSHIFT);
421  break;
422  }
423  PrevState = CurrState;
424  }
425  void onRShift() {
426  IntelExprState CurrState = State;
427  switch (State) {
428  default:
429  State = IES_ERROR;
430  break;
431  case IES_INTEGER:
432  case IES_RPAREN:
433  case IES_REGISTER:
434  State = IES_RSHIFT;
435  IC.pushOperator(IC_RSHIFT);
436  break;
437  }
438  PrevState = CurrState;
439  }
440  bool onPlus(StringRef &ErrMsg) {
441  IntelExprState CurrState = State;
442  switch (State) {
443  default:
444  State = IES_ERROR;
445  break;
446  case IES_INTEGER:
447  case IES_RPAREN:
448  case IES_REGISTER:
449  State = IES_PLUS;
450  IC.pushOperator(IC_PLUS);
451  if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
452  // If we already have a BaseReg, then assume this is the IndexReg with
453  // no explicit scale.
454  if (!BaseReg) {
455  BaseReg = TmpReg;
456  } else {
457  if (IndexReg) {
458  ErrMsg = "BaseReg/IndexReg already set!";
459  return true;
460  }
461  IndexReg = TmpReg;
462  Scale = 0;
463  }
464  }
465  break;
466  }
467  PrevState = CurrState;
468  return false;
469  }
470  bool onMinus(StringRef &ErrMsg) {
471  IntelExprState CurrState = State;
472  switch (State) {
473  default:
474  State = IES_ERROR;
475  break;
476  case IES_OR:
477  case IES_XOR:
478  case IES_AND:
479  case IES_LSHIFT:
480  case IES_RSHIFT:
481  case IES_PLUS:
482  case IES_NOT:
483  case IES_MULTIPLY:
484  case IES_DIVIDE:
485  case IES_MOD:
486  case IES_LPAREN:
487  case IES_RPAREN:
488  case IES_LBRAC:
489  case IES_RBRAC:
490  case IES_INTEGER:
491  case IES_REGISTER:
492  case IES_INIT:
493  State = IES_MINUS;
494  // push minus operator if it is not a negate operator
495  if (CurrState == IES_REGISTER || CurrState == IES_RPAREN ||
496  CurrState == IES_INTEGER || CurrState == IES_RBRAC)
497  IC.pushOperator(IC_MINUS);
498  else if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
499  // We have negate operator for Scale: it's illegal
500  ErrMsg = "Scale can't be negative";
501  return true;
502  } else
503  IC.pushOperator(IC_NEG);
504  if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
505  // If we already have a BaseReg, then assume this is the IndexReg with
506  // no explicit scale.
507  if (!BaseReg) {
508  BaseReg = TmpReg;
509  } else {
510  if (IndexReg) {
511  ErrMsg = "BaseReg/IndexReg already set!";
512  return true;
513  }
514  IndexReg = TmpReg;
515  Scale = 0;
516  }
517  }
518  break;
519  }
520  PrevState = CurrState;
521  return false;
522  }
523  void onNot() {
524  IntelExprState CurrState = State;
525  switch (State) {
526  default:
527  State = IES_ERROR;
528  break;
529  case IES_OR:
530  case IES_XOR:
531  case IES_AND:
532  case IES_LSHIFT:
533  case IES_RSHIFT:
534  case IES_PLUS:
535  case IES_MINUS:
536  case IES_NOT:
537  case IES_MULTIPLY:
538  case IES_DIVIDE:
539  case IES_MOD:
540  case IES_LPAREN:
541  case IES_LBRAC:
542  case IES_INIT:
543  State = IES_NOT;
544  IC.pushOperator(IC_NOT);
545  break;
546  }
547  PrevState = CurrState;
548  }
549 
550  bool onRegister(unsigned Reg, StringRef &ErrMsg) {
551  IntelExprState CurrState = State;
552  switch (State) {
553  default:
554  State = IES_ERROR;
555  break;
556  case IES_PLUS:
557  case IES_LPAREN:
558  case IES_LBRAC:
559  State = IES_REGISTER;
560  TmpReg = Reg;
561  IC.pushOperand(IC_REGISTER);
562  break;
563  case IES_MULTIPLY:
564  // Index Register - Scale * Register
565  if (PrevState == IES_INTEGER) {
566  if (IndexReg) {
567  ErrMsg = "BaseReg/IndexReg already set!";
568  return true;
569  }
570  State = IES_REGISTER;
571  IndexReg = Reg;
572  // Get the scale and replace the 'Scale * Register' with '0'.
573  Scale = IC.popOperand();
574  if (checkScale(Scale, ErrMsg))
575  return true;
576  IC.pushOperand(IC_IMM);
577  IC.popOperator();
578  } else {
579  State = IES_ERROR;
580  }
581  break;
582  }
583  PrevState = CurrState;
584  return false;
585  }
586  bool onIdentifierExpr(const MCExpr *SymRef, StringRef SymRefName,
587  const InlineAsmIdentifierInfo &IDInfo,
588  bool ParsingInlineAsm, StringRef &ErrMsg) {
589  // InlineAsm: Treat an enum value as an integer
590  if (ParsingInlineAsm)
592  return onInteger(IDInfo.Enum.EnumVal, ErrMsg);
593  // Treat a symbolic constant like an integer
594  if (auto *CE = dyn_cast<MCConstantExpr>(SymRef))
595  return onInteger(CE->getValue(), ErrMsg);
596  PrevState = State;
597  bool HasSymbol = Sym != nullptr;
598  switch (State) {
599  default:
600  State = IES_ERROR;
601  break;
602  case IES_PLUS:
603  case IES_MINUS:
604  case IES_NOT:
605  case IES_INIT:
606  case IES_LBRAC:
607  MemExpr = true;
608  State = IES_INTEGER;
609  Sym = SymRef;
610  SymName = SymRefName;
611  IC.pushOperand(IC_IMM);
612  if (ParsingInlineAsm)
613  Info = IDInfo;
614  break;
615  }
616  if (HasSymbol)
617  ErrMsg = "cannot use more than one symbol in memory operand";
618  return HasSymbol;
619  }
620  bool onInteger(int64_t TmpInt, StringRef &ErrMsg) {
621  IntelExprState CurrState = State;
622  switch (State) {
623  default:
624  State = IES_ERROR;
625  break;
626  case IES_PLUS:
627  case IES_MINUS:
628  case IES_NOT:
629  case IES_OR:
630  case IES_XOR:
631  case IES_AND:
632  case IES_LSHIFT:
633  case IES_RSHIFT:
634  case IES_DIVIDE:
635  case IES_MOD:
636  case IES_MULTIPLY:
637  case IES_LPAREN:
638  case IES_INIT:
639  case IES_LBRAC:
640  State = IES_INTEGER;
641  if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
642  // Index Register - Register * Scale
643  if (IndexReg) {
644  ErrMsg = "BaseReg/IndexReg already set!";
645  return true;
646  }
647  IndexReg = TmpReg;
648  Scale = TmpInt;
649  if (checkScale(Scale, ErrMsg))
650  return true;
651  // Get the scale and replace the 'Register * Scale' with '0'.
652  IC.popOperator();
653  } else {
654  IC.pushOperand(IC_IMM, TmpInt);
655  }
656  break;
657  }
658  PrevState = CurrState;
659  return false;
660  }
661  void onStar() {
662  PrevState = State;
663  switch (State) {
664  default:
665  State = IES_ERROR;
666  break;
667  case IES_INTEGER:
668  case IES_REGISTER:
669  case IES_RPAREN:
670  State = IES_MULTIPLY;
671  IC.pushOperator(IC_MULTIPLY);
672  break;
673  }
674  }
675  void onDivide() {
676  PrevState = State;
677  switch (State) {
678  default:
679  State = IES_ERROR;
680  break;
681  case IES_INTEGER:
682  case IES_RPAREN:
683  State = IES_DIVIDE;
684  IC.pushOperator(IC_DIVIDE);
685  break;
686  }
687  }
688  void onMod() {
689  PrevState = State;
690  switch (State) {
691  default:
692  State = IES_ERROR;
693  break;
694  case IES_INTEGER:
695  case IES_RPAREN:
696  State = IES_MOD;
697  IC.pushOperator(IC_MOD);
698  break;
699  }
700  }
701  bool onLBrac() {
702  if (BracCount)
703  return true;
704  PrevState = State;
705  switch (State) {
706  default:
707  State = IES_ERROR;
708  break;
709  case IES_RBRAC:
710  case IES_INTEGER:
711  case IES_RPAREN:
712  State = IES_PLUS;
713  IC.pushOperator(IC_PLUS);
714  break;
715  case IES_INIT:
716  assert(!BracCount && "BracCount should be zero on parsing's start");
717  State = IES_LBRAC;
718  break;
719  }
720  MemExpr = true;
721  BracCount++;
722  return false;
723  }
724  bool onRBrac() {
725  IntelExprState CurrState = State;
726  switch (State) {
727  default:
728  State = IES_ERROR;
729  break;
730  case IES_INTEGER:
731  case IES_REGISTER:
732  case IES_RPAREN:
733  if (BracCount-- != 1)
734  return true;
735  State = IES_RBRAC;
736  if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
737  // If we already have a BaseReg, then assume this is the IndexReg with
738  // no explicit scale.
739  if (!BaseReg) {
740  BaseReg = TmpReg;
741  } else {
742  assert (!IndexReg && "BaseReg/IndexReg already set!");
743  IndexReg = TmpReg;
744  Scale = 0;
745  }
746  }
747  break;
748  }
749  PrevState = CurrState;
750  return false;
751  }
752  void onLParen() {
753  IntelExprState CurrState = State;
754  switch (State) {
755  default:
756  State = IES_ERROR;
757  break;
758  case IES_PLUS:
759  case IES_MINUS:
760  case IES_NOT:
761  case IES_OR:
762  case IES_XOR:
763  case IES_AND:
764  case IES_LSHIFT:
765  case IES_RSHIFT:
766  case IES_MULTIPLY:
767  case IES_DIVIDE:
768  case IES_MOD:
769  case IES_LPAREN:
770  case IES_INIT:
771  case IES_LBRAC:
772  State = IES_LPAREN;
773  IC.pushOperator(IC_LPAREN);
774  break;
775  }
776  PrevState = CurrState;
777  }
778  void onRParen() {
779  PrevState = State;
780  switch (State) {
781  default:
782  State = IES_ERROR;
783  break;
784  case IES_INTEGER:
785  case IES_REGISTER:
786  case IES_RPAREN:
787  State = IES_RPAREN;
788  IC.pushOperator(IC_RPAREN);
789  break;
790  }
791  }
792  };
793 
794  bool Error(SMLoc L, const Twine &Msg, SMRange Range = None,
795  bool MatchingInlineAsm = false) {
796  MCAsmParser &Parser = getParser();
797  if (MatchingInlineAsm) {
798  if (!getLexer().isAtStartOfStatement())
799  Parser.eatToEndOfStatement();
800  return false;
801  }
802  return Parser.Error(L, Msg, Range);
803  }
804 
805  std::nullptr_t ErrorOperand(SMLoc Loc, StringRef Msg, SMRange R = SMRange()) {
806  Error(Loc, Msg, R);
807  return nullptr;
808  }
809 
810  std::unique_ptr<X86Operand> DefaultMemSIOperand(SMLoc Loc);
811  std::unique_ptr<X86Operand> DefaultMemDIOperand(SMLoc Loc);
812  bool IsSIReg(unsigned Reg);
813  unsigned GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, bool IsSIReg);
814  void
815  AddDefaultSrcDestOperands(OperandVector &Operands,
816  std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
817  std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst);
818  bool VerifyAndAdjustOperands(OperandVector &OrigOperands,
819  OperandVector &FinalOperands);
820  std::unique_ptr<X86Operand> ParseOperand();
821  std::unique_ptr<X86Operand> ParseATTOperand();
822  std::unique_ptr<X86Operand> ParseIntelOperand();
823  std::unique_ptr<X86Operand> ParseIntelOffsetOfOperator();
824  bool ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End);
825  unsigned IdentifyIntelInlineAsmOperator(StringRef Name);
826  unsigned ParseIntelInlineAsmOperator(unsigned OpKind);
827  std::unique_ptr<X86Operand> ParseRoundingModeOp(SMLoc Start);
828  bool ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM);
829  void RewriteIntelExpression(IntelExprStateMachine &SM, SMLoc Start,
830  SMLoc End);
831  bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
832  bool ParseIntelInlineAsmIdentifier(const MCExpr *&Val, StringRef &Identifier,
834  bool IsUnevaluatedOperand, SMLoc &End);
835 
836  std::unique_ptr<X86Operand> ParseMemOperand(unsigned SegReg,
837  const MCExpr *&Disp,
838  const SMLoc &StartLoc,
839  SMLoc &EndLoc);
840 
841  bool ParseIntelMemoryOperandSize(unsigned &Size);
842  std::unique_ptr<X86Operand>
843  CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
844  unsigned IndexReg, unsigned Scale, SMLoc Start,
845  SMLoc End, unsigned Size, StringRef Identifier,
846  const InlineAsmIdentifierInfo &Info);
847 
848  bool parseDirectiveEven(SMLoc L);
849  bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
850 
851  /// CodeView FPO data directives.
852  bool parseDirectiveFPOProc(SMLoc L);
853  bool parseDirectiveFPOSetFrame(SMLoc L);
854  bool parseDirectiveFPOPushReg(SMLoc L);
855  bool parseDirectiveFPOStackAlloc(SMLoc L);
856  bool parseDirectiveFPOStackAlign(SMLoc L);
857  bool parseDirectiveFPOEndPrologue(SMLoc L);
858  bool parseDirectiveFPOEndProc(SMLoc L);
859  bool parseDirectiveFPOData(SMLoc L);
860 
861  bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
862  bool processInstruction(MCInst &Inst, const OperandVector &Ops);
863 
864  /// Wrapper around MCStreamer::EmitInstruction(). Possibly adds
865  /// instrumentation around Inst.
866  void EmitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out);
867 
868  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
869  OperandVector &Operands, MCStreamer &Out,
870  uint64_t &ErrorInfo,
871  bool MatchingInlineAsm) override;
872 
873  void MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op, OperandVector &Operands,
874  MCStreamer &Out, bool MatchingInlineAsm);
875 
876  bool ErrorMissingFeature(SMLoc IDLoc, const FeatureBitset &MissingFeatures,
877  bool MatchingInlineAsm);
878 
879  bool MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
880  OperandVector &Operands, MCStreamer &Out,
881  uint64_t &ErrorInfo,
882  bool MatchingInlineAsm);
883 
884  bool MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
885  OperandVector &Operands, MCStreamer &Out,
886  uint64_t &ErrorInfo,
887  bool MatchingInlineAsm);
888 
889  bool OmitRegisterFromClobberLists(unsigned RegNo) override;
890 
891  /// Parses AVX512 specific operand primitives: masked registers ({%k<NUM>}, {z})
892  /// and memory broadcasting ({1to<NUM>}) primitives, updating Operands vector if required.
893  /// return false if no parsing errors occurred, true otherwise.
894  bool HandleAVX512Operand(OperandVector &Operands,
895  const MCParsedAsmOperand &Op);
896 
897  bool ParseZ(std::unique_ptr<X86Operand> &Z, const SMLoc &StartLoc);
898 
899  bool is64BitMode() const {
900  // FIXME: Can tablegen auto-generate this?
901  return getSTI().getFeatureBits()[X86::Mode64Bit];
902  }
903  bool is32BitMode() const {
904  // FIXME: Can tablegen auto-generate this?
905  return getSTI().getFeatureBits()[X86::Mode32Bit];
906  }
907  bool is16BitMode() const {
908  // FIXME: Can tablegen auto-generate this?
909  return getSTI().getFeatureBits()[X86::Mode16Bit];
910  }
911  void SwitchMode(unsigned mode) {
912  MCSubtargetInfo &STI = copySTI();
913  FeatureBitset AllModes({X86::Mode64Bit, X86::Mode32Bit, X86::Mode16Bit});
914  FeatureBitset OldMode = STI.getFeatureBits() & AllModes;
915  FeatureBitset FB = ComputeAvailableFeatures(
916  STI.ToggleFeature(OldMode.flip(mode)));
917  setAvailableFeatures(FB);
918 
919  assert(FeatureBitset({mode}) == (STI.getFeatureBits() & AllModes));
920  }
921 
922  unsigned getPointerWidth() {
923  if (is16BitMode()) return 16;
924  if (is32BitMode()) return 32;
925  if (is64BitMode()) return 64;
926  llvm_unreachable("invalid mode");
927  }
928 
929  bool isParsingIntelSyntax() {
930  return getParser().getAssemblerDialect();
931  }
932 
933  /// @name Auto-generated Matcher Functions
934  /// {
935 
936 #define GET_ASSEMBLER_HEADER
937 #include "X86GenAsmMatcher.inc"
938 
939  /// }
940 
941 public:
942 
943  X86AsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser,
944  const MCInstrInfo &mii, const MCTargetOptions &Options)
945  : MCTargetAsmParser(Options, sti, mii), InstInfo(nullptr),
946  Code16GCC(false) {
947 
948  Parser.addAliasForDirective(".word", ".2byte");
949 
950  // Initialize the set of available features.
951  setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
952  }
953 
954  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
955 
956  bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) override;
957 
958  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
959  SMLoc NameLoc, OperandVector &Operands) override;
960 
961  bool ParseDirective(AsmToken DirectiveID) override;
962 };
963 } // end anonymous namespace
964 
965 /// @name Auto-generated Match Functions
966 /// {
967 
968 static unsigned MatchRegisterName(StringRef Name);
969 
970 /// }
971 
972 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,
973  unsigned Scale, bool Is64BitMode,
974  StringRef &ErrMsg) {
975  // If we have both a base register and an index register make sure they are
976  // both 64-bit or 32-bit registers.
977  // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
978 
979  if (BaseReg != 0 &&
980  !(BaseReg == X86::RIP || BaseReg == X86::EIP ||
981  X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) ||
982  X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) ||
983  X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg))) {
984  ErrMsg = "invalid base+index expression";
985  return true;
986  }
987 
988  if (IndexReg != 0 &&
989  !(IndexReg == X86::EIZ || IndexReg == X86::RIZ ||
990  X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
991  X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
992  X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||
993  X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||
994  X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||
995  X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg))) {
996  ErrMsg = "invalid base+index expression";
997  return true;
998  }
999 
1000  if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) ||
1001  IndexReg == X86::EIP || IndexReg == X86::RIP ||
1002  IndexReg == X86::ESP || IndexReg == X86::RSP) {
1003  ErrMsg = "invalid base+index expression";
1004  return true;
1005  }
1006 
1007  // Check for use of invalid 16-bit registers. Only BX/BP/SI/DI are allowed,
1008  // and then only in non-64-bit modes.
1009  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
1010  (Is64BitMode || (BaseReg != X86::BX && BaseReg != X86::BP &&
1011  BaseReg != X86::SI && BaseReg != X86::DI))) {
1012  ErrMsg = "invalid 16-bit base register";
1013  return true;
1014  }
1015 
1016  if (BaseReg == 0 &&
1017  X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {
1018  ErrMsg = "16-bit memory operand may not include only index register";
1019  return true;
1020  }
1021 
1022  if (BaseReg != 0 && IndexReg != 0) {
1023  if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
1024  (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1025  X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1026  IndexReg == X86::EIZ)) {
1027  ErrMsg = "base register is 64-bit, but index register is not";
1028  return true;
1029  }
1030  if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
1031  (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1032  X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||
1033  IndexReg == X86::RIZ)) {
1034  ErrMsg = "base register is 32-bit, but index register is not";
1035  return true;
1036  }
1037  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) {
1038  if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1039  X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {
1040  ErrMsg = "base register is 16-bit, but index register is not";
1041  return true;
1042  }
1043  if ((BaseReg != X86::BX && BaseReg != X86::BP) ||
1044  (IndexReg != X86::SI && IndexReg != X86::DI)) {
1045  ErrMsg = "invalid 16-bit base/index register combination";
1046  return true;
1047  }
1048  }
1049  }
1050 
1051  // RIP/EIP-relative addressing is only supported in 64-bit mode.
1052  if (!Is64BitMode && BaseReg != 0 &&
1053  (BaseReg == X86::RIP || BaseReg == X86::EIP)) {
1054  ErrMsg = "IP-relative addressing requires 64-bit mode";
1055  return true;
1056  }
1057 
1058  return checkScale(Scale, ErrMsg);
1059 }
1060 
1061 bool X86AsmParser::ParseRegister(unsigned &RegNo,
1062  SMLoc &StartLoc, SMLoc &EndLoc) {
1063  MCAsmParser &Parser = getParser();
1064  RegNo = 0;
1065  const AsmToken &PercentTok = Parser.getTok();
1066  StartLoc = PercentTok.getLoc();
1067 
1068  // If we encounter a %, ignore it. This code handles registers with and
1069  // without the prefix, unprefixed registers can occur in cfi directives.
1070  if (!isParsingIntelSyntax() && PercentTok.is(AsmToken::Percent))
1071  Parser.Lex(); // Eat percent token.
1072 
1073  const AsmToken &Tok = Parser.getTok();
1074  EndLoc = Tok.getEndLoc();
1075 
1076  if (Tok.isNot(AsmToken::Identifier)) {
1077  if (isParsingIntelSyntax()) return true;
1078  return Error(StartLoc, "invalid register name",
1079  SMRange(StartLoc, EndLoc));
1080  }
1081 
1082  RegNo = MatchRegisterName(Tok.getString());
1083 
1084  // If the match failed, try the register name as lowercase.
1085  if (RegNo == 0)
1086  RegNo = MatchRegisterName(Tok.getString().lower());
1087 
1088  // The "flags" register cannot be referenced directly.
1089  // Treat it as an identifier instead.
1090  if (isParsingInlineAsm() && isParsingIntelSyntax() && RegNo == X86::EFLAGS)
1091  RegNo = 0;
1092 
1093  if (!is64BitMode()) {
1094  // FIXME: This should be done using Requires<Not64BitMode> and
1095  // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
1096  // checked.
1097  // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
1098  // REX prefix.
1099  if (RegNo == X86::RIZ || RegNo == X86::RIP ||
1100  X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
1102  X86II::isX86_64ExtendedReg(RegNo)) {
1103  StringRef RegName = Tok.getString();
1104  Parser.Lex(); // Eat register name.
1105  return Error(StartLoc,
1106  "register %" + RegName + " is only available in 64-bit mode",
1107  SMRange(StartLoc, EndLoc));
1108  }
1109  }
1110 
1111  // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
1112  if (RegNo == X86::ST0) {
1113  Parser.Lex(); // Eat 'st'
1114 
1115  // Check to see if we have '(4)' after %st.
1116  if (getLexer().isNot(AsmToken::LParen))
1117  return false;
1118  // Lex the paren.
1119  getParser().Lex();
1120 
1121  const AsmToken &IntTok = Parser.getTok();
1122  if (IntTok.isNot(AsmToken::Integer))
1123  return Error(IntTok.getLoc(), "expected stack index");
1124  switch (IntTok.getIntVal()) {
1125  case 0: RegNo = X86::ST0; break;
1126  case 1: RegNo = X86::ST1; break;
1127  case 2: RegNo = X86::ST2; break;
1128  case 3: RegNo = X86::ST3; break;
1129  case 4: RegNo = X86::ST4; break;
1130  case 5: RegNo = X86::ST5; break;
1131  case 6: RegNo = X86::ST6; break;
1132  case 7: RegNo = X86::ST7; break;
1133  default: return Error(IntTok.getLoc(), "invalid stack index");
1134  }
1135 
1136  if (getParser().Lex().isNot(AsmToken::RParen))
1137  return Error(Parser.getTok().getLoc(), "expected ')'");
1138 
1139  EndLoc = Parser.getTok().getEndLoc();
1140  Parser.Lex(); // Eat ')'
1141  return false;
1142  }
1143 
1144  EndLoc = Parser.getTok().getEndLoc();
1145 
1146  // If this is "db[0-15]", match it as an alias
1147  // for dr[0-15].
1148  if (RegNo == 0 && Tok.getString().startswith("db")) {
1149  if (Tok.getString().size() == 3) {
1150  switch (Tok.getString()[2]) {
1151  case '0': RegNo = X86::DR0; break;
1152  case '1': RegNo = X86::DR1; break;
1153  case '2': RegNo = X86::DR2; break;
1154  case '3': RegNo = X86::DR3; break;
1155  case '4': RegNo = X86::DR4; break;
1156  case '5': RegNo = X86::DR5; break;
1157  case '6': RegNo = X86::DR6; break;
1158  case '7': RegNo = X86::DR7; break;
1159  case '8': RegNo = X86::DR8; break;
1160  case '9': RegNo = X86::DR9; break;
1161  }
1162  } else if (Tok.getString().size() == 4 && Tok.getString()[2] == '1') {
1163  switch (Tok.getString()[3]) {
1164  case '0': RegNo = X86::DR10; break;
1165  case '1': RegNo = X86::DR11; break;
1166  case '2': RegNo = X86::DR12; break;
1167  case '3': RegNo = X86::DR13; break;
1168  case '4': RegNo = X86::DR14; break;
1169  case '5': RegNo = X86::DR15; break;
1170  }
1171  }
1172 
1173  if (RegNo != 0) {
1174  EndLoc = Parser.getTok().getEndLoc();
1175  Parser.Lex(); // Eat it.
1176  return false;
1177  }
1178  }
1179 
1180  if (RegNo == 0) {
1181  if (isParsingIntelSyntax()) return true;
1182  return Error(StartLoc, "invalid register name",
1183  SMRange(StartLoc, EndLoc));
1184  }
1185 
1186  Parser.Lex(); // Eat identifier token.
1187  return false;
1188 }
1189 
1190 std::unique_ptr<X86Operand> X86AsmParser::DefaultMemSIOperand(SMLoc Loc) {
1191  bool Parse32 = is32BitMode() || Code16GCC;
1192  unsigned Basereg = is64BitMode() ? X86::RSI : (Parse32 ? X86::ESI : X86::SI);
1193  const MCExpr *Disp = MCConstantExpr::create(0, getContext());
1194  return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
1195  /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
1196  Loc, Loc, 0);
1197 }
1198 
1199 std::unique_ptr<X86Operand> X86AsmParser::DefaultMemDIOperand(SMLoc Loc) {
1200  bool Parse32 = is32BitMode() || Code16GCC;
1201  unsigned Basereg = is64BitMode() ? X86::RDI : (Parse32 ? X86::EDI : X86::DI);
1202  const MCExpr *Disp = MCConstantExpr::create(0, getContext());
1203  return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
1204  /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
1205  Loc, Loc, 0);
1206 }
1207 
1208 bool X86AsmParser::IsSIReg(unsigned Reg) {
1209  switch (Reg) {
1210  default: llvm_unreachable("Only (R|E)SI and (R|E)DI are expected!");
1211  case X86::RSI:
1212  case X86::ESI:
1213  case X86::SI:
1214  return true;
1215  case X86::RDI:
1216  case X86::EDI:
1217  case X86::DI:
1218  return false;
1219  }
1220 }
1221 
1222 unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg,
1223  bool IsSIReg) {
1224  switch (RegClassID) {
1225  default: llvm_unreachable("Unexpected register class");
1226  case X86::GR64RegClassID:
1227  return IsSIReg ? X86::RSI : X86::RDI;
1228  case X86::GR32RegClassID:
1229  return IsSIReg ? X86::ESI : X86::EDI;
1230  case X86::GR16RegClassID:
1231  return IsSIReg ? X86::SI : X86::DI;
1232  }
1233 }
1234 
1235 void X86AsmParser::AddDefaultSrcDestOperands(
1236  OperandVector& Operands, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
1237  std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst) {
1238  if (isParsingIntelSyntax()) {
1239  Operands.push_back(std::move(Dst));
1240  Operands.push_back(std::move(Src));
1241  }
1242  else {
1243  Operands.push_back(std::move(Src));
1244  Operands.push_back(std::move(Dst));
1245  }
1246 }
1247 
1248 bool X86AsmParser::VerifyAndAdjustOperands(OperandVector &OrigOperands,
1249  OperandVector &FinalOperands) {
1250 
1251  if (OrigOperands.size() > 1) {
1252  // Check if sizes match, OrigOperands also contains the instruction name
1253  assert(OrigOperands.size() == FinalOperands.size() + 1 &&
1254  "Operand size mismatch");
1255 
1257  // Verify types match
1258  int RegClassID = -1;
1259  for (unsigned int i = 0; i < FinalOperands.size(); ++i) {
1260  X86Operand &OrigOp = static_cast<X86Operand &>(*OrigOperands[i + 1]);
1261  X86Operand &FinalOp = static_cast<X86Operand &>(*FinalOperands[i]);
1262 
1263  if (FinalOp.isReg() &&
1264  (!OrigOp.isReg() || FinalOp.getReg() != OrigOp.getReg()))
1265  // Return false and let a normal complaint about bogus operands happen
1266  return false;
1267 
1268  if (FinalOp.isMem()) {
1269 
1270  if (!OrigOp.isMem())
1271  // Return false and let a normal complaint about bogus operands happen
1272  return false;
1273 
1274  unsigned OrigReg = OrigOp.Mem.BaseReg;
1275  unsigned FinalReg = FinalOp.Mem.BaseReg;
1276 
1277  // If we've already encounterd a register class, make sure all register
1278  // bases are of the same register class
1279  if (RegClassID != -1 &&
1280  !X86MCRegisterClasses[RegClassID].contains(OrigReg)) {
1281  return Error(OrigOp.getStartLoc(),
1282  "mismatching source and destination index registers");
1283  }
1284 
1285  if (X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg))
1286  RegClassID = X86::GR64RegClassID;
1287  else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg))
1288  RegClassID = X86::GR32RegClassID;
1289  else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg))
1290  RegClassID = X86::GR16RegClassID;
1291  else
1292  // Unexpected register class type
1293  // Return false and let a normal complaint about bogus operands happen
1294  return false;
1295 
1296  bool IsSI = IsSIReg(FinalReg);
1297  FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI);
1298 
1299  if (FinalReg != OrigReg) {
1300  std::string RegName = IsSI ? "ES:(R|E)SI" : "ES:(R|E)DI";
1301  Warnings.push_back(std::make_pair(
1302  OrigOp.getStartLoc(),
1303  "memory operand is only for determining the size, " + RegName +
1304  " will be used for the location"));
1305  }
1306 
1307  FinalOp.Mem.Size = OrigOp.Mem.Size;
1308  FinalOp.Mem.SegReg = OrigOp.Mem.SegReg;
1309  FinalOp.Mem.BaseReg = FinalReg;
1310  }
1311  }
1312 
1313  // Produce warnings only if all the operands passed the adjustment - prevent
1314  // legal cases like "movsd (%rax), %xmm0" mistakenly produce warnings
1315  for (auto &WarningMsg : Warnings) {
1316  Warning(WarningMsg.first, WarningMsg.second);
1317  }
1318 
1319  // Remove old operands
1320  for (unsigned int i = 0; i < FinalOperands.size(); ++i)
1321  OrigOperands.pop_back();
1322  }
1323  // OrigOperands.append(FinalOperands.begin(), FinalOperands.end());
1324  for (unsigned int i = 0; i < FinalOperands.size(); ++i)
1325  OrigOperands.push_back(std::move(FinalOperands[i]));
1326 
1327  return false;
1328 }
1329 
1330 std::unique_ptr<X86Operand> X86AsmParser::ParseOperand() {
1331  if (isParsingIntelSyntax())
1332  return ParseIntelOperand();
1333  return ParseATTOperand();
1334 }
1335 
1336 std::unique_ptr<X86Operand> X86AsmParser::CreateMemForInlineAsm(
1337  unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,
1338  unsigned Scale, SMLoc Start, SMLoc End, unsigned Size, StringRef Identifier,
1339  const InlineAsmIdentifierInfo &Info) {
1340  // If we found a decl other than a VarDecl, then assume it is a FuncDecl or
1341  // some other label reference.
1343  // Insert an explicit size if the user didn't have one.
1344  if (!Size) {
1345  Size = getPointerWidth();
1346  InstInfo->AsmRewrites->emplace_back(AOK_SizeDirective, Start,
1347  /*Len=*/0, Size);
1348  }
1349  // Create an absolute memory reference in order to match against
1350  // instructions taking a PC relative operand.
1351  return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size,
1352  Identifier, Info.Label.Decl);
1353  }
1354  // We either have a direct symbol reference, or an offset from a symbol. The
1355  // parser always puts the symbol on the LHS, so look there for size
1356  // calculation purposes.
1357  unsigned FrontendSize = 0;
1358  void *Decl = nullptr;
1359  bool IsGlobalLV = false;
1361  // Size is in terms of bits in this context.
1362  FrontendSize = Info.Var.Type * 8;
1363  Decl = Info.Var.Decl;
1364  IsGlobalLV = Info.Var.IsGlobalLV;
1365  }
1366  // It is widely common for MS InlineAsm to use a global variable and one/two
1367  // registers in a mmory expression, and though unaccessible via rip/eip.
1368  if (IsGlobalLV && (BaseReg || IndexReg)) {
1369  return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End);
1370  // Otherwise, we set the base register to a non-zero value
1371  // if we don't know the actual value at this time. This is necessary to
1372  // get the matching correct in some cases.
1373  } else {
1374  BaseReg = BaseReg ? BaseReg : 1;
1375  return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,
1376  IndexReg, Scale, Start, End, Size, Identifier,
1377  Decl, FrontendSize);
1378  }
1379 }
1380 
1381 // Some binary bitwise operators have a named synonymous
1382 // Query a candidate string for being such a named operator
1383 // and if so - invoke the appropriate handler
1384 bool X86AsmParser::ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM) {
1385  // A named operator should be either lower or upper case, but not a mix
1386  if (Name.compare(Name.lower()) && Name.compare(Name.upper()))
1387  return false;
1388  if (Name.equals_lower("not"))
1389  SM.onNot();
1390  else if (Name.equals_lower("or"))
1391  SM.onOr();
1392  else if (Name.equals_lower("shl"))
1393  SM.onLShift();
1394  else if (Name.equals_lower("shr"))
1395  SM.onRShift();
1396  else if (Name.equals_lower("xor"))
1397  SM.onXor();
1398  else if (Name.equals_lower("and"))
1399  SM.onAnd();
1400  else if (Name.equals_lower("mod"))
1401  SM.onMod();
1402  else
1403  return false;
1404  return true;
1405 }
1406 
1407 bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
1408  MCAsmParser &Parser = getParser();
1409  const AsmToken &Tok = Parser.getTok();
1410  StringRef ErrMsg;
1411 
1413  bool Done = false;
1414  while (!Done) {
1415  bool UpdateLocLex = true;
1416  AsmToken::TokenKind TK = getLexer().getKind();
1417 
1418  switch (TK) {
1419  default:
1420  if ((Done = SM.isValidEndState()))
1421  break;
1422  return Error(Tok.getLoc(), "unknown token in expression");
1424  Done = true;
1425  break;
1426  case AsmToken::Real:
1427  // DotOperator: [ebx].0
1428  UpdateLocLex = false;
1429  if (ParseIntelDotOperator(SM, End))
1430  return true;
1431  break;
1432  case AsmToken::At:
1433  case AsmToken::String:
1434  case AsmToken::Identifier: {
1435  SMLoc IdentLoc = Tok.getLoc();
1436  StringRef Identifier = Tok.getString();
1437  UpdateLocLex = false;
1438  // Register
1439  unsigned Reg;
1440  if (Tok.is(AsmToken::Identifier) && !ParseRegister(Reg, IdentLoc, End)) {
1441  if (SM.onRegister(Reg, ErrMsg))
1442  return Error(Tok.getLoc(), ErrMsg);
1443  break;
1444  }
1445  // Operator synonymous ("not", "or" etc.)
1446  if ((UpdateLocLex = ParseIntelNamedOperator(Identifier, SM)))
1447  break;
1448  // Symbol reference, when parsing assembly content
1450  const MCExpr *Val;
1451  if (!isParsingInlineAsm()) {
1452  if (getParser().parsePrimaryExpr(Val, End)) {
1453  return Error(Tok.getLoc(), "Unexpected identifier!");
1454  } else if (SM.onIdentifierExpr(Val, Identifier, Info, false, ErrMsg)) {
1455  return Error(IdentLoc, ErrMsg);
1456  } else
1457  break;
1458  }
1459  // MS InlineAsm operators (TYPE/LENGTH/SIZE)
1460  if (unsigned OpKind = IdentifyIntelInlineAsmOperator(Identifier)) {
1461  if (OpKind == IOK_OFFSET)
1462  return Error(IdentLoc, "Dealing OFFSET operator as part of"
1463  "a compound immediate expression is yet to be supported");
1464  if (int64_t Val = ParseIntelInlineAsmOperator(OpKind)) {
1465  if (SM.onInteger(Val, ErrMsg))
1466  return Error(IdentLoc, ErrMsg);
1467  } else
1468  return true;
1469  break;
1470  }
1471  // MS Dot Operator expression
1472  if (Identifier.count('.') && PrevTK == AsmToken::RBrac) {
1473  if (ParseIntelDotOperator(SM, End))
1474  return true;
1475  break;
1476  }
1477  // MS InlineAsm identifier
1478  // Call parseIdentifier() to combine @ with the identifier behind it.
1479  if (TK == AsmToken::At && Parser.parseIdentifier(Identifier))
1480  return Error(IdentLoc, "expected identifier");
1481  if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info, false, End))
1482  return true;
1483  else if (SM.onIdentifierExpr(Val, Identifier, Info, true, ErrMsg))
1484  return Error(IdentLoc, ErrMsg);
1485  break;
1486  }
1487  case AsmToken::Integer: {
1488  // Look for 'b' or 'f' following an Integer as a directional label
1489  SMLoc Loc = getTok().getLoc();
1490  int64_t IntVal = getTok().getIntVal();
1491  End = consumeToken();
1492  UpdateLocLex = false;
1493  if (getLexer().getKind() == AsmToken::Identifier) {
1494  StringRef IDVal = getTok().getString();
1495  if (IDVal == "f" || IDVal == "b") {
1496  MCSymbol *Sym =
1497  getContext().getDirectionalLocalSymbol(IntVal, IDVal == "b");
1499  const MCExpr *Val =
1500  MCSymbolRefExpr::create(Sym, Variant, getContext());
1501  if (IDVal == "b" && Sym->isUndefined())
1502  return Error(Loc, "invalid reference to undefined symbol");
1503  StringRef Identifier = Sym->getName();
1505  if (SM.onIdentifierExpr(Val, Identifier, Info,
1506  isParsingInlineAsm(), ErrMsg))
1507  return Error(Loc, ErrMsg);
1508  End = consumeToken();
1509  } else {
1510  if (SM.onInteger(IntVal, ErrMsg))
1511  return Error(Loc, ErrMsg);
1512  }
1513  } else {
1514  if (SM.onInteger(IntVal, ErrMsg))
1515  return Error(Loc, ErrMsg);
1516  }
1517  break;
1518  }
1519  case AsmToken::Plus:
1520  if (SM.onPlus(ErrMsg))
1521  return Error(getTok().getLoc(), ErrMsg);
1522  break;
1523  case AsmToken::Minus:
1524  if (SM.onMinus(ErrMsg))
1525  return Error(getTok().getLoc(), ErrMsg);
1526  break;
1527  case AsmToken::Tilde: SM.onNot(); break;
1528  case AsmToken::Star: SM.onStar(); break;
1529  case AsmToken::Slash: SM.onDivide(); break;
1530  case AsmToken::Percent: SM.onMod(); break;
1531  case AsmToken::Pipe: SM.onOr(); break;
1532  case AsmToken::Caret: SM.onXor(); break;
1533  case AsmToken::Amp: SM.onAnd(); break;
1534  case AsmToken::LessLess:
1535  SM.onLShift(); break;
1537  SM.onRShift(); break;
1538  case AsmToken::LBrac:
1539  if (SM.onLBrac())
1540  return Error(Tok.getLoc(), "unexpected bracket encountered");
1541  break;
1542  case AsmToken::RBrac:
1543  if (SM.onRBrac())
1544  return Error(Tok.getLoc(), "unexpected bracket encountered");
1545  break;
1546  case AsmToken::LParen: SM.onLParen(); break;
1547  case AsmToken::RParen: SM.onRParen(); break;
1548  }
1549  if (SM.hadError())
1550  return Error(Tok.getLoc(), "unknown token in expression");
1551 
1552  if (!Done && UpdateLocLex)
1553  End = consumeToken();
1554 
1555  PrevTK = TK;
1556  }
1557  return false;
1558 }
1559 
1560 void X86AsmParser::RewriteIntelExpression(IntelExprStateMachine &SM,
1561  SMLoc Start, SMLoc End) {
1562  SMLoc Loc = Start;
1563  unsigned ExprLen = End.getPointer() - Start.getPointer();
1564  // Skip everything before a symbol displacement (if we have one)
1565  if (SM.getSym()) {
1566  StringRef SymName = SM.getSymName();
1567  if (unsigned Len = SymName.data() - Start.getPointer())
1568  InstInfo->AsmRewrites->emplace_back(AOK_Skip, Start, Len);
1569  Loc = SMLoc::getFromPointer(SymName.data() + SymName.size());
1570  ExprLen = End.getPointer() - (SymName.data() + SymName.size());
1571  // If we have only a symbol than there's no need for complex rewrite,
1572  // simply skip everything after it
1573  if (!(SM.getBaseReg() || SM.getIndexReg() || SM.getImm())) {
1574  if (ExprLen)
1575  InstInfo->AsmRewrites->emplace_back(AOK_Skip, Loc, ExprLen);
1576  return;
1577  }
1578  }
1579  // Build an Intel Expression rewrite
1580  StringRef BaseRegStr;
1581  StringRef IndexRegStr;
1582  if (SM.getBaseReg())
1583  BaseRegStr = X86IntelInstPrinter::getRegisterName(SM.getBaseReg());
1584  if (SM.getIndexReg())
1585  IndexRegStr = X86IntelInstPrinter::getRegisterName(SM.getIndexReg());
1586  // Emit it
1587  IntelExpr Expr(BaseRegStr, IndexRegStr, SM.getScale(), SM.getImm(), SM.isMemExpr());
1588  InstInfo->AsmRewrites->emplace_back(Loc, ExprLen, Expr);
1589 }
1590 
1591 // Inline assembly may use variable names with namespace alias qualifiers.
1592 bool X86AsmParser::ParseIntelInlineAsmIdentifier(const MCExpr *&Val,
1593  StringRef &Identifier,
1595  bool IsUnevaluatedOperand,
1596  SMLoc &End) {
1597  MCAsmParser &Parser = getParser();
1598  assert(isParsingInlineAsm() && "Expected to be parsing inline assembly.");
1599  Val = nullptr;
1600 
1601  StringRef LineBuf(Identifier.data());
1602  SemaCallback->LookupInlineAsmIdentifier(LineBuf, Info, IsUnevaluatedOperand);
1603 
1604  const AsmToken &Tok = Parser.getTok();
1605  SMLoc Loc = Tok.getLoc();
1606 
1607  // Advance the token stream until the end of the current token is
1608  // after the end of what the frontend claimed.
1609  const char *EndPtr = Tok.getLoc().getPointer() + LineBuf.size();
1610  do {
1611  End = Tok.getEndLoc();
1612  getLexer().Lex();
1613  } while (End.getPointer() < EndPtr);
1614  Identifier = LineBuf;
1615 
1616  // The frontend should end parsing on an assembler token boundary, unless it
1617  // failed parsing.
1618  assert((End.getPointer() == EndPtr ||
1620  "frontend claimed part of a token?");
1621 
1622  // If the identifier lookup was unsuccessful, assume that we are dealing with
1623  // a label.
1625  StringRef InternalName =
1626  SemaCallback->LookupInlineAsmLabel(Identifier, getSourceManager(),
1627  Loc, false);
1628  assert(InternalName.size() && "We should have an internal name here.");
1629  // Push a rewrite for replacing the identifier name with the internal name.
1630  InstInfo->AsmRewrites->emplace_back(AOK_Label, Loc, Identifier.size(),
1631  InternalName);
1633  return false;
1634  // Create the symbol reference.
1635  MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
1637  Val = MCSymbolRefExpr::create(Sym, Variant, getParser().getContext());
1638  return false;
1639 }
1640 
1641 //ParseRoundingModeOp - Parse AVX-512 rounding mode operand
1642 std::unique_ptr<X86Operand>
1643 X86AsmParser::ParseRoundingModeOp(SMLoc Start) {
1644  MCAsmParser &Parser = getParser();
1645  const AsmToken &Tok = Parser.getTok();
1646  // Eat "{" and mark the current place.
1647  const SMLoc consumedToken = consumeToken();
1648  if (Tok.isNot(AsmToken::Identifier))
1649  return ErrorOperand(Tok.getLoc(), "Expected an identifier after {");
1650  if (Tok.getIdentifier().startswith("r")){
1651  int rndMode = StringSwitch<int>(Tok.getIdentifier())
1656  .Default(-1);
1657  if (-1 == rndMode)
1658  return ErrorOperand(Tok.getLoc(), "Invalid rounding mode.");
1659  Parser.Lex(); // Eat "r*" of r*-sae
1660  if (!getLexer().is(AsmToken::Minus))
1661  return ErrorOperand(Tok.getLoc(), "Expected - at this point");
1662  Parser.Lex(); // Eat "-"
1663  Parser.Lex(); // Eat the sae
1664  if (!getLexer().is(AsmToken::RCurly))
1665  return ErrorOperand(Tok.getLoc(), "Expected } at this point");
1666  SMLoc End = Tok.getEndLoc();
1667  Parser.Lex(); // Eat "}"
1668  const MCExpr *RndModeOp =
1669  MCConstantExpr::create(rndMode, Parser.getContext());
1670  return X86Operand::CreateImm(RndModeOp, Start, End);
1671  }
1672  if(Tok.getIdentifier().equals("sae")){
1673  Parser.Lex(); // Eat the sae
1674  if (!getLexer().is(AsmToken::RCurly))
1675  return ErrorOperand(Tok.getLoc(), "Expected } at this point");
1676  Parser.Lex(); // Eat "}"
1677  return X86Operand::CreateToken("{sae}", consumedToken);
1678  }
1679  return ErrorOperand(Tok.getLoc(), "unknown token in expression");
1680 }
1681 
1682 /// Parse the '.' operator.
1683 bool X86AsmParser::ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End) {
1684  const AsmToken &Tok = getTok();
1685  unsigned Offset;
1686 
1687  // Drop the optional '.'.
1688  StringRef DotDispStr = Tok.getString();
1689  if (DotDispStr.startswith("."))
1690  DotDispStr = DotDispStr.drop_front(1);
1691 
1692  // .Imm gets lexed as a real.
1693  if (Tok.is(AsmToken::Real)) {
1694  APInt DotDisp;
1695  DotDispStr.getAsInteger(10, DotDisp);
1696  Offset = DotDisp.getZExtValue();
1697  } else if (isParsingInlineAsm() && Tok.is(AsmToken::Identifier)) {
1698  std::pair<StringRef, StringRef> BaseMember = DotDispStr.split('.');
1699  if (SemaCallback->LookupInlineAsmField(BaseMember.first, BaseMember.second,
1700  Offset))
1701  return Error(Tok.getLoc(), "Unable to lookup field reference!");
1702  } else
1703  return Error(Tok.getLoc(), "Unexpected token type!");
1704 
1705  // Eat the DotExpression and update End
1706  End = SMLoc::getFromPointer(DotDispStr.data());
1707  const char *DotExprEndLoc = DotDispStr.data() + DotDispStr.size();
1708  while (Tok.getLoc().getPointer() < DotExprEndLoc)
1709  Lex();
1710  SM.addImm(Offset);
1711  return false;
1712 }
1713 
1714 /// Parse the 'offset' operator. This operator is used to specify the
1715 /// location rather then the content of a variable.
1716 std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOffsetOfOperator() {
1717  MCAsmParser &Parser = getParser();
1718  const AsmToken &Tok = Parser.getTok();
1719  SMLoc OffsetOfLoc = Tok.getLoc();
1720  Parser.Lex(); // Eat offset.
1721 
1722  const MCExpr *Val;
1724  SMLoc Start = Tok.getLoc(), End;
1725  StringRef Identifier = Tok.getString();
1726  if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info,
1727  /*Unevaluated=*/false, End))
1728  return nullptr;
1729 
1730  void *Decl = nullptr;
1731  // FIXME: MS evaluates "offset <Constant>" to the underlying integral
1733  return ErrorOperand(Start, "offset operator cannot yet handle constants");
1734  else if (Info.isKind(InlineAsmIdentifierInfo::IK_Var))
1735  Decl = Info.Var.Decl;
1736  // Don't emit the offset operator.
1737  InstInfo->AsmRewrites->emplace_back(AOK_Skip, OffsetOfLoc, 7);
1738 
1739  // The offset operator will have an 'r' constraint, thus we need to create
1740  // register operand to ensure proper matching. Just pick a GPR based on
1741  // the size of a pointer.
1742  bool Parse32 = is32BitMode() || Code16GCC;
1743  unsigned RegNo = is64BitMode() ? X86::RBX : (Parse32 ? X86::EBX : X86::BX);
1744 
1745  return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true,
1746  OffsetOfLoc, Identifier, Decl);
1747 }
1748 
1749 // Query a candidate string for being an Intel assembly operator
1750 // Report back its kind, or IOK_INVALID if does not evaluated as a known one
1751 unsigned X86AsmParser::IdentifyIntelInlineAsmOperator(StringRef Name) {
1753  .Cases("TYPE","type",IOK_TYPE)
1754  .Cases("SIZE","size",IOK_SIZE)
1755  .Cases("LENGTH","length",IOK_LENGTH)
1756  .Cases("OFFSET","offset",IOK_OFFSET)
1757  .Default(IOK_INVALID);
1758 }
1759 
1760 /// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator
1761 /// returns the number of elements in an array. It returns the value 1 for
1762 /// non-array variables. The SIZE operator returns the size of a C or C++
1763 /// variable. A variable's size is the product of its LENGTH and TYPE. The
1764 /// TYPE operator returns the size of a C or C++ type or variable. If the
1765 /// variable is an array, TYPE returns the size of a single element.
1766 unsigned X86AsmParser::ParseIntelInlineAsmOperator(unsigned OpKind) {
1767  MCAsmParser &Parser = getParser();
1768  const AsmToken &Tok = Parser.getTok();
1769  Parser.Lex(); // Eat operator.
1770 
1771  const MCExpr *Val = nullptr;
1773  SMLoc Start = Tok.getLoc(), End;
1774  StringRef Identifier = Tok.getString();
1775  if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info,
1776  /*Unevaluated=*/true, End))
1777  return 0;
1778 
1780  Error(Start, "unable to lookup expression");
1781  return 0;
1782  }
1783 
1784  unsigned CVal = 0;
1785  switch(OpKind) {
1786  default: llvm_unreachable("Unexpected operand kind!");
1787  case IOK_LENGTH: CVal = Info.Var.Length; break;
1788  case IOK_SIZE: CVal = Info.Var.Size; break;
1789  case IOK_TYPE: CVal = Info.Var.Type; break;
1790  }
1791 
1792  return CVal;
1793 }
1794 
1795 bool X86AsmParser::ParseIntelMemoryOperandSize(unsigned &Size) {
1796  Size = StringSwitch<unsigned>(getTok().getString())
1797  .Cases("BYTE", "byte", 8)
1798  .Cases("WORD", "word", 16)
1799  .Cases("DWORD", "dword", 32)
1800  .Cases("FLOAT", "float", 32)
1801  .Cases("LONG", "long", 32)
1802  .Cases("FWORD", "fword", 48)
1803  .Cases("DOUBLE", "double", 64)
1804  .Cases("QWORD", "qword", 64)
1805  .Cases("MMWORD","mmword", 64)
1806  .Cases("XWORD", "xword", 80)
1807  .Cases("TBYTE", "tbyte", 80)
1808  .Cases("XMMWORD", "xmmword", 128)
1809  .Cases("YMMWORD", "ymmword", 256)
1810  .Cases("ZMMWORD", "zmmword", 512)
1811  .Default(0);
1812  if (Size) {
1813  const AsmToken &Tok = Lex(); // Eat operand size (e.g., byte, word).
1814  if (!(Tok.getString().equals("PTR") || Tok.getString().equals("ptr")))
1815  return Error(Tok.getLoc(), "Expected 'PTR' or 'ptr' token!");
1816  Lex(); // Eat ptr.
1817  }
1818  return false;
1819 }
1820 
1821 std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOperand() {
1822  MCAsmParser &Parser = getParser();
1823  const AsmToken &Tok = Parser.getTok();
1824  SMLoc Start, End;
1825 
1826  // FIXME: Offset operator
1827  // Should be handled as part of immediate expression, as other operators
1828  // Currently, only supported as a stand-alone operand
1829  if (isParsingInlineAsm())
1830  if (IdentifyIntelInlineAsmOperator(Tok.getString()) == IOK_OFFSET)
1831  return ParseIntelOffsetOfOperator();
1832 
1833  // Parse optional Size directive.
1834  unsigned Size;
1835  if (ParseIntelMemoryOperandSize(Size))
1836  return nullptr;
1837  bool PtrInOperand = bool(Size);
1838 
1839  Start = Tok.getLoc();
1840 
1841  // Rounding mode operand.
1842  if (getLexer().is(AsmToken::LCurly))
1843  return ParseRoundingModeOp(Start);
1844 
1845  // Register operand.
1846  unsigned RegNo = 0;
1847  if (Tok.is(AsmToken::Identifier) && !ParseRegister(RegNo, Start, End)) {
1848  if (RegNo == X86::RIP)
1849  return ErrorOperand(Start, "rip can only be used as a base register");
1850  // A Register followed by ':' is considered a segment override
1851  if (Tok.isNot(AsmToken::Colon))
1852  return !PtrInOperand ? X86Operand::CreateReg(RegNo, Start, End) :
1853  ErrorOperand(Start, "expected memory operand after 'ptr', "
1854  "found register operand instead");
1855  // An alleged segment override. check if we have a valid segment register
1856  if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo))
1857  return ErrorOperand(Start, "invalid segment register");
1858  // Eat ':' and update Start location
1859  Start = Lex().getLoc();
1860  }
1861 
1862  // Immediates and Memory
1863  IntelExprStateMachine SM;
1864  if (ParseIntelExpression(SM, End))
1865  return nullptr;
1866 
1867  if (isParsingInlineAsm())
1868  RewriteIntelExpression(SM, Start, Tok.getLoc());
1869 
1870  int64_t Imm = SM.getImm();
1871  const MCExpr *Disp = SM.getSym();
1872  const MCExpr *ImmDisp = MCConstantExpr::create(Imm, getContext());
1873  if (Disp && Imm)
1874  Disp = MCBinaryExpr::createAdd(Disp, ImmDisp, getContext());
1875  if (!Disp)
1876  Disp = ImmDisp;
1877 
1878  // RegNo != 0 specifies a valid segment register,
1879  // and we are parsing a segment override
1880  if (!SM.isMemExpr() && !RegNo)
1881  return X86Operand::CreateImm(Disp, Start, End);
1882 
1883  StringRef ErrMsg;
1884  unsigned BaseReg = SM.getBaseReg();
1885  unsigned IndexReg = SM.getIndexReg();
1886  unsigned Scale = SM.getScale();
1887 
1888  if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP &&
1889  (IndexReg == X86::ESP || IndexReg == X86::RSP))
1890  std::swap(BaseReg, IndexReg);
1891 
1892  // If BaseReg is a vector register and IndexReg is not, swap them unless
1893  // Scale was specified in which case it would be an error.
1894  if (Scale == 0 &&
1895  !(X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||
1896  X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||
1897  X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg)) &&
1898  (X86MCRegisterClasses[X86::VR128XRegClassID].contains(BaseReg) ||
1899  X86MCRegisterClasses[X86::VR256XRegClassID].contains(BaseReg) ||
1900  X86MCRegisterClasses[X86::VR512RegClassID].contains(BaseReg)))
1901  std::swap(BaseReg, IndexReg);
1902 
1903  if (Scale != 0 &&
1904  X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg))
1905  return ErrorOperand(Start, "16-bit addresses cannot have a scale");
1906 
1907  // If there was no explicit scale specified, change it to 1.
1908  if (Scale == 0)
1909  Scale = 1;
1910 
1911  // If this is a 16-bit addressing mode with the base and index in the wrong
1912  // order, swap them so CheckBaseRegAndIndexRegAndScale doesn't fail. It is
1913  // shared with att syntax where order matters.
1914  if ((BaseReg == X86::SI || BaseReg == X86::DI) &&
1915  (IndexReg == X86::BX || IndexReg == X86::BP))
1916  std::swap(BaseReg, IndexReg);
1917 
1918  if ((BaseReg || IndexReg) &&
1919  CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),
1920  ErrMsg))
1921  return ErrorOperand(Start, ErrMsg);
1922  if (isParsingInlineAsm())
1923  return CreateMemForInlineAsm(RegNo, Disp, BaseReg, IndexReg,
1924  Scale, Start, End, Size, SM.getSymName(),
1925  SM.getIdentifierInfo());
1926  if (!(BaseReg || IndexReg || RegNo))
1927  return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size);
1928  return X86Operand::CreateMem(getPointerWidth(), RegNo, Disp,
1929  BaseReg, IndexReg, Scale, Start, End, Size);
1930 }
1931 
1932 std::unique_ptr<X86Operand> X86AsmParser::ParseATTOperand() {
1933  MCAsmParser &Parser = getParser();
1934  switch (getLexer().getKind()) {
1935  case AsmToken::Dollar: {
1936  // $42 or $ID -> immediate.
1937  SMLoc Start = Parser.getTok().getLoc(), End;
1938  Parser.Lex();
1939  const MCExpr *Val;
1940  // This is an immediate, so we should not parse a register. Do a precheck
1941  // for '%' to supercede intra-register parse errors.
1942  SMLoc L = Parser.getTok().getLoc();
1943  if (check(getLexer().is(AsmToken::Percent), L,
1944  "expected immediate expression") ||
1945  getParser().parseExpression(Val, End) ||
1946  check(isa<X86MCExpr>(Val), L, "expected immediate expression"))
1947  return nullptr;
1948  return X86Operand::CreateImm(Val, Start, End);
1949  }
1950  case AsmToken::LCurly: {
1951  SMLoc Start = Parser.getTok().getLoc();
1952  return ParseRoundingModeOp(Start);
1953  }
1954  default: {
1955  // This a memory operand or a register. We have some parsing complications
1956  // as a '(' may be part of an immediate expression or the addressing mode
1957  // block. This is complicated by the fact that an assembler-level variable
1958  // may refer either to a register or an immediate expression.
1959 
1960  SMLoc Loc = Parser.getTok().getLoc(), EndLoc;
1961  const MCExpr *Expr = nullptr;
1962  unsigned Reg = 0;
1963  if (getLexer().isNot(AsmToken::LParen)) {
1964  // No '(' so this is either a displacement expression or a register.
1965  if (Parser.parseExpression(Expr, EndLoc))
1966  return nullptr;
1967  if (auto *RE = dyn_cast<X86MCExpr>(Expr)) {
1968  // Segment Register. Reset Expr and copy value to register.
1969  Expr = nullptr;
1970  Reg = RE->getRegNo();
1971 
1972  // Sanity check register.
1973  if (Reg == X86::EIZ || Reg == X86::RIZ)
1974  return ErrorOperand(
1975  Loc, "%eiz and %riz can only be used as index registers",
1976  SMRange(Loc, EndLoc));
1977  if (Reg == X86::RIP)
1978  return ErrorOperand(Loc, "%rip can only be used as a base register",
1979  SMRange(Loc, EndLoc));
1980  // Return register that are not segment prefixes immediately.
1981  if (!Parser.parseOptionalToken(AsmToken::Colon))
1982  return X86Operand::CreateReg(Reg, Loc, EndLoc);
1983  if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(Reg))
1984  return ErrorOperand(Loc, "invalid segment register");
1985  }
1986  }
1987  // This is a Memory operand.
1988  return ParseMemOperand(Reg, Expr, Loc, EndLoc);
1989  }
1990  }
1991 }
1992 
1993 // true on failure, false otherwise
1994 // If no {z} mark was found - Parser doesn't advance
1995 bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z,
1996  const SMLoc &StartLoc) {
1997  MCAsmParser &Parser = getParser();
1998  // Assuming we are just pass the '{' mark, quering the next token
1999  // Searched for {z}, but none was found. Return false, as no parsing error was
2000  // encountered
2001  if (!(getLexer().is(AsmToken::Identifier) &&
2002  (getLexer().getTok().getIdentifier() == "z")))
2003  return false;
2004  Parser.Lex(); // Eat z
2005  // Query and eat the '}' mark
2006  if (!getLexer().is(AsmToken::RCurly))
2007  return Error(getLexer().getLoc(), "Expected } at this point");
2008  Parser.Lex(); // Eat '}'
2009  // Assign Z with the {z} mark opernad
2010  Z = X86Operand::CreateToken("{z}", StartLoc);
2011  return false;
2012 }
2013 
2014 // true on failure, false otherwise
2015 bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands,
2016  const MCParsedAsmOperand &Op) {
2017  MCAsmParser &Parser = getParser();
2018  if (getLexer().is(AsmToken::LCurly)) {
2019  // Eat "{" and mark the current place.
2020  const SMLoc consumedToken = consumeToken();
2021  // Distinguish {1to<NUM>} from {%k<NUM>}.
2022  if(getLexer().is(AsmToken::Integer)) {
2023  // Parse memory broadcasting ({1to<NUM>}).
2024  if (getLexer().getTok().getIntVal() != 1)
2025  return TokError("Expected 1to<NUM> at this point");
2026  Parser.Lex(); // Eat "1" of 1to8
2027  if (!getLexer().is(AsmToken::Identifier) ||
2028  !getLexer().getTok().getIdentifier().startswith("to"))
2029  return TokError("Expected 1to<NUM> at this point");
2030  // Recognize only reasonable suffixes.
2031  const char *BroadcastPrimitive =
2032  StringSwitch<const char*>(getLexer().getTok().getIdentifier())
2033  .Case("to2", "{1to2}")
2034  .Case("to4", "{1to4}")
2035  .Case("to8", "{1to8}")
2036  .Case("to16", "{1to16}")
2037  .Default(nullptr);
2038  if (!BroadcastPrimitive)
2039  return TokError("Invalid memory broadcast primitive.");
2040  Parser.Lex(); // Eat "toN" of 1toN
2041  if (!getLexer().is(AsmToken::RCurly))
2042  return TokError("Expected } at this point");
2043  Parser.Lex(); // Eat "}"
2044  Operands.push_back(X86Operand::CreateToken(BroadcastPrimitive,
2045  consumedToken));
2046  // No AVX512 specific primitives can pass
2047  // after memory broadcasting, so return.
2048  return false;
2049  } else {
2050  // Parse either {k}{z}, {z}{k}, {k} or {z}
2051  // last one have no meaning, but GCC accepts it
2052  // Currently, we're just pass a '{' mark
2053  std::unique_ptr<X86Operand> Z;
2054  if (ParseZ(Z, consumedToken))
2055  return true;
2056  // Reaching here means that parsing of the allegadly '{z}' mark yielded
2057  // no errors.
2058  // Query for the need of further parsing for a {%k<NUM>} mark
2059  if (!Z || getLexer().is(AsmToken::LCurly)) {
2060  SMLoc StartLoc = Z ? consumeToken() : consumedToken;
2061  // Parse an op-mask register mark ({%k<NUM>}), which is now to be
2062  // expected
2063  unsigned RegNo;
2064  SMLoc RegLoc;
2065  if (!ParseRegister(RegNo, RegLoc, StartLoc) &&
2066  X86MCRegisterClasses[X86::VK1RegClassID].contains(RegNo)) {
2067  if (RegNo == X86::K0)
2068  return Error(RegLoc, "Register k0 can't be used as write mask");
2069  if (!getLexer().is(AsmToken::RCurly))
2070  return Error(getLexer().getLoc(), "Expected } at this point");
2071  Operands.push_back(X86Operand::CreateToken("{", StartLoc));
2072  Operands.push_back(
2073  X86Operand::CreateReg(RegNo, StartLoc, StartLoc));
2074  Operands.push_back(X86Operand::CreateToken("}", consumeToken()));
2075  } else
2076  return Error(getLexer().getLoc(),
2077  "Expected an op-mask register at this point");
2078  // {%k<NUM>} mark is found, inquire for {z}
2079  if (getLexer().is(AsmToken::LCurly) && !Z) {
2080  // Have we've found a parsing error, or found no (expected) {z} mark
2081  // - report an error
2082  if (ParseZ(Z, consumeToken()) || !Z)
2083  return Error(getLexer().getLoc(),
2084  "Expected a {z} mark at this point");
2085 
2086  }
2087  // '{z}' on its own is meaningless, hence should be ignored.
2088  // on the contrary - have it been accompanied by a K register,
2089  // allow it.
2090  if (Z)
2091  Operands.push_back(std::move(Z));
2092  }
2093  }
2094  }
2095  return false;
2096 }
2097 
2098 /// ParseMemOperand: 'seg : disp(basereg, indexreg, scale)'. The '%ds:' prefix
2099 /// has already been parsed if present. disp may be provided as well.
2100 std::unique_ptr<X86Operand> X86AsmParser::ParseMemOperand(unsigned SegReg,
2101  const MCExpr *&Disp,
2102  const SMLoc &StartLoc,
2103  SMLoc &EndLoc) {
2104  MCAsmParser &Parser = getParser();
2105  SMLoc Loc;
2106  // Based on the initial passed values, we may be in any of these cases, we are
2107  // in one of these cases (with current position (*)):
2108 
2109  // 1. seg : * disp (base-index-scale-expr)
2110  // 2. seg : *(disp) (base-index-scale-expr)
2111  // 3. seg : *(base-index-scale-expr)
2112  // 4. disp *(base-index-scale-expr)
2113  // 5. *(disp) (base-index-scale-expr)
2114  // 6. *(base-index-scale-expr)
2115  // 7. disp *
2116  // 8. *(disp)
2117 
2118  // If we do not have an displacement yet, check if we're in cases 4 or 6 by
2119  // checking if the first object after the parenthesis is a register (or an
2120  // identifier referring to a register) and parse the displacement or default
2121  // to 0 as appropriate.
2122  auto isAtMemOperand = [this]() {
2123  if (this->getLexer().isNot(AsmToken::LParen))
2124  return false;
2125  AsmToken Buf[2];
2126  StringRef Id;
2127  auto TokCount = this->getLexer().peekTokens(Buf, true);
2128  if (TokCount == 0)
2129  return false;
2130  switch (Buf[0].getKind()) {
2131  case AsmToken::Percent:
2132  case AsmToken::Comma:
2133  return true;
2134  // These lower cases are doing a peekIdentifier.
2135  case AsmToken::At:
2136  case AsmToken::Dollar:
2137  if ((TokCount > 1) &&
2138  (Buf[1].is(AsmToken::Identifier) || Buf[1].is(AsmToken::String)) &&
2139  (Buf[0].getLoc().getPointer() + 1 == Buf[1].getLoc().getPointer()))
2140  Id = StringRef(Buf[0].getLoc().getPointer(),
2141  Buf[1].getIdentifier().size() + 1);
2142  break;
2143  case AsmToken::Identifier:
2144  case AsmToken::String:
2145  Id = Buf[0].getIdentifier();
2146  break;
2147  default:
2148  return false;
2149  }
2150  // We have an ID. Check if it is bound to a register.
2151  if (!Id.empty()) {
2152  MCSymbol *Sym = this->getContext().getOrCreateSymbol(Id);
2153  if (Sym->isVariable()) {
2154  auto V = Sym->getVariableValue(/*SetUsed*/ false);
2155  return isa<X86MCExpr>(V);
2156  }
2157  }
2158  return false;
2159  };
2160 
2161  if (!Disp) {
2162  // Parse immediate if we're not at a mem operand yet.
2163  if (!isAtMemOperand()) {
2164  if (Parser.parseTokenLoc(Loc) || Parser.parseExpression(Disp, EndLoc))
2165  return nullptr;
2166  assert(!isa<X86MCExpr>(Disp) && "Expected non-register here.");
2167  } else {
2168  // Disp is implicitly zero if we haven't parsed it yet.
2169  Disp = MCConstantExpr::create(0, Parser.getContext());
2170  }
2171  }
2172 
2173  // We are now either at the end of the operand or at the '(' at the start of a
2174  // base-index-scale-expr.
2175 
2176  if (!parseOptionalToken(AsmToken::LParen)) {
2177  if (SegReg == 0)
2178  return X86Operand::CreateMem(getPointerWidth(), Disp, StartLoc, EndLoc);
2179  return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, 0, 0, 1,
2180  StartLoc, EndLoc);
2181  }
2182 
2183  // If we reached here, then eat the '(' and Process
2184  // the rest of the memory operand.
2185  unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
2186  SMLoc BaseLoc = getLexer().getLoc();
2187  const MCExpr *E;
2188  StringRef ErrMsg;
2189 
2190  // Parse BaseReg if one is provided.
2191  if (getLexer().isNot(AsmToken::Comma) && getLexer().isNot(AsmToken::RParen)) {
2192  if (Parser.parseExpression(E, EndLoc) ||
2193  check(!isa<X86MCExpr>(E), BaseLoc, "expected register here"))
2194  return nullptr;
2195 
2196  // Sanity check register.
2197  BaseReg = cast<X86MCExpr>(E)->getRegNo();
2198  if (BaseReg == X86::EIZ || BaseReg == X86::RIZ)
2199  return ErrorOperand(BaseLoc,
2200  "eiz and riz can only be used as index registers",
2201  SMRange(BaseLoc, EndLoc));
2202  }
2203 
2204  if (parseOptionalToken(AsmToken::Comma)) {
2205  // Following the comma we should have either an index register, or a scale
2206  // value. We don't support the later form, but we want to parse it
2207  // correctly.
2208  //
2209  // Even though it would be completely consistent to support syntax like
2210  // "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
2211  if (getLexer().isNot(AsmToken::RParen)) {
2212  if (Parser.parseTokenLoc(Loc) || Parser.parseExpression(E, EndLoc))
2213  return nullptr;
2214 
2215  if (!isa<X86MCExpr>(E)) {
2216  // We've parsed an unexpected Scale Value instead of an index
2217  // register. Interpret it as an absolute.
2218  int64_t ScaleVal;
2219  if (!E->evaluateAsAbsolute(ScaleVal, getStreamer().getAssemblerPtr()))
2220  return ErrorOperand(Loc, "expected absolute expression");
2221  if (ScaleVal != 1)
2222  Warning(Loc, "scale factor without index register is ignored");
2223  Scale = 1;
2224  } else { // IndexReg Found.
2225  IndexReg = cast<X86MCExpr>(E)->getRegNo();
2226 
2227  if (BaseReg == X86::RIP)
2228  return ErrorOperand(
2229  Loc, "%rip as base register can not have an index register");
2230  if (IndexReg == X86::RIP)
2231  return ErrorOperand(Loc, "%rip is not allowed as an index register");
2232 
2233  if (parseOptionalToken(AsmToken::Comma)) {
2234  // Parse the scale amount:
2235  // ::= ',' [scale-expression]
2236 
2237  // A scale amount without an index is ignored.
2238  if (getLexer().isNot(AsmToken::RParen)) {
2239  int64_t ScaleVal;
2240  if (Parser.parseTokenLoc(Loc) ||
2241  Parser.parseAbsoluteExpression(ScaleVal))
2242  return ErrorOperand(Loc, "expected scale expression");
2243  Scale = (unsigned)ScaleVal;
2244  // Validate the scale amount.
2245  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
2246  Scale != 1)
2247  return ErrorOperand(Loc,
2248  "scale factor in 16-bit address must be 1");
2249  if (checkScale(Scale, ErrMsg))
2250  return ErrorOperand(Loc, ErrMsg);
2251  }
2252  }
2253  }
2254  }
2255  }
2256 
2257  // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
2258  if (parseToken(AsmToken::RParen, "unexpected token in memory operand"))
2259  return nullptr;
2260 
2261  // This is to support otherwise illegal operand (%dx) found in various
2262  // unofficial manuals examples (e.g. "out[s]?[bwl]? %al, (%dx)") and must now
2263  // be supported. Mark such DX variants separately fix only in special cases.
2264  if (BaseReg == X86::DX && IndexReg == 0 && Scale == 1 && SegReg == 0 &&
2265  isa<MCConstantExpr>(Disp) && cast<MCConstantExpr>(Disp)->getValue() == 0)
2266  return X86Operand::CreateDXReg(BaseLoc, BaseLoc);
2267 
2268  if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),
2269  ErrMsg))
2270  return ErrorOperand(BaseLoc, ErrMsg);
2271 
2272  if (SegReg || BaseReg || IndexReg)
2273  return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,
2274  IndexReg, Scale, StartLoc, EndLoc);
2275  return X86Operand::CreateMem(getPointerWidth(), Disp, StartLoc, EndLoc);
2276 }
2277 
2278 // Parse either a standard primary expression or a register.
2279 bool X86AsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
2280  MCAsmParser &Parser = getParser();
2281  // See if this is a register first.
2282  if (getTok().is(AsmToken::Percent) ||
2283  (isParsingIntelSyntax() && getTok().is(AsmToken::Identifier) &&
2284  MatchRegisterName(Parser.getTok().getString()))) {
2285  SMLoc StartLoc = Parser.getTok().getLoc();
2286  unsigned RegNo;
2287  if (ParseRegister(RegNo, StartLoc, EndLoc))
2288  return true;
2289  Res = X86MCExpr::create(RegNo, Parser.getContext());
2290  return false;
2291  }
2292  return Parser.parsePrimaryExpr(Res, EndLoc);
2293 }
2294 
2295 bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
2296  SMLoc NameLoc, OperandVector &Operands) {
2297  MCAsmParser &Parser = getParser();
2298  InstInfo = &Info;
2299  StringRef PatchedName = Name;
2300 
2301  if ((Name.equals("jmp") || Name.equals("jc") || Name.equals("jz")) &&
2302  isParsingIntelSyntax() && isParsingInlineAsm()) {
2303  StringRef NextTok = Parser.getTok().getString();
2304  if (NextTok == "short") {
2305  SMLoc NameEndLoc =
2306  NameLoc.getFromPointer(NameLoc.getPointer() + Name.size());
2307  // Eat the short keyword
2308  Parser.Lex();
2309  // MS ignores the short keyword, it determines the jmp type based
2310  // on the distance of the label
2311  InstInfo->AsmRewrites->emplace_back(AOK_Skip, NameEndLoc,
2312  NextTok.size() + 1);
2313  }
2314  }
2315 
2316  // FIXME: Hack to recognize setneb as setne.
2317  if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
2318  PatchedName != "setb" && PatchedName != "setnb")
2319  PatchedName = PatchedName.substr(0, Name.size()-1);
2320 
2321  // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
2322  if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
2323  (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
2324  PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
2325  bool IsVCMP = PatchedName[0] == 'v';
2326  unsigned CCIdx = IsVCMP ? 4 : 3;
2327  unsigned ComparisonCode = StringSwitch<unsigned>(
2328  PatchedName.slice(CCIdx, PatchedName.size() - 2))
2329  .Case("eq", 0x00)
2330  .Case("eq_oq", 0x00)
2331  .Case("lt", 0x01)
2332  .Case("lt_os", 0x01)
2333  .Case("le", 0x02)
2334  .Case("le_os", 0x02)
2335  .Case("unord", 0x03)
2336  .Case("unord_q", 0x03)
2337  .Case("neq", 0x04)
2338  .Case("neq_uq", 0x04)
2339  .Case("nlt", 0x05)
2340  .Case("nlt_us", 0x05)
2341  .Case("nle", 0x06)
2342  .Case("nle_us", 0x06)
2343  .Case("ord", 0x07)
2344  .Case("ord_q", 0x07)
2345  /* AVX only from here */
2346  .Case("eq_uq", 0x08)
2347  .Case("nge", 0x09)
2348  .Case("nge_us", 0x09)
2349  .Case("ngt", 0x0A)
2350  .Case("ngt_us", 0x0A)
2351  .Case("false", 0x0B)
2352  .Case("false_oq", 0x0B)
2353  .Case("neq_oq", 0x0C)
2354  .Case("ge", 0x0D)
2355  .Case("ge_os", 0x0D)
2356  .Case("gt", 0x0E)
2357  .Case("gt_os", 0x0E)
2358  .Case("true", 0x0F)
2359  .Case("true_uq", 0x0F)
2360  .Case("eq_os", 0x10)
2361  .Case("lt_oq", 0x11)
2362  .Case("le_oq", 0x12)
2363  .Case("unord_s", 0x13)
2364  .Case("neq_us", 0x14)
2365  .Case("nlt_uq", 0x15)
2366  .Case("nle_uq", 0x16)
2367  .Case("ord_s", 0x17)
2368  .Case("eq_us", 0x18)
2369  .Case("nge_uq", 0x19)
2370  .Case("ngt_uq", 0x1A)
2371  .Case("false_os", 0x1B)
2372  .Case("neq_os", 0x1C)
2373  .Case("ge_oq", 0x1D)
2374  .Case("gt_oq", 0x1E)
2375  .Case("true_us", 0x1F)
2376  .Default(~0U);
2377  if (ComparisonCode != ~0U && (IsVCMP || ComparisonCode < 8)) {
2378 
2379  Operands.push_back(X86Operand::CreateToken(PatchedName.slice(0, CCIdx),
2380  NameLoc));
2381 
2382  const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode,
2383  getParser().getContext());
2384  Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
2385 
2386  PatchedName = PatchedName.substr(PatchedName.size() - 2);
2387  }
2388  }
2389 
2390  unsigned ComparisonCode = ~0U;
2391 
2392  // FIXME: Hack to recognize vpcmp<comparison code>{ub,uw,ud,uq,b,w,d,q}.
2393  if (PatchedName.startswith("vpcmp") &&
2394  (PatchedName.back() == 'b' || PatchedName.back() == 'w' ||
2395  PatchedName.back() == 'd' || PatchedName.back() == 'q')) {
2396  unsigned SuffixSize = PatchedName.drop_back().back() == 'u' ? 2 : 1;
2397  unsigned CC = StringSwitch<unsigned>(
2398  PatchedName.slice(5, PatchedName.size() - SuffixSize))
2399  .Case("eq", 0x0) // Only allowed on unsigned. Checked below.
2400  .Case("lt", 0x1)
2401  .Case("le", 0x2)
2402  //.Case("false", 0x3) // Not a documented alias.
2403  .Case("neq", 0x4)
2404  .Case("nlt", 0x5)
2405  .Case("nle", 0x6)
2406  //.Case("true", 0x7) // Not a documented alias.
2407  .Default(~0U);
2408  if (CC != ~0U && (CC != 0 || SuffixSize == 2)) {
2409  switch (PatchedName.back()) {
2410  default: llvm_unreachable("Unexpected character!");
2411  case 'b': PatchedName = SuffixSize == 2 ? "vpcmpub" : "vpcmpb"; break;
2412  case 'w': PatchedName = SuffixSize == 2 ? "vpcmpuw" : "vpcmpw"; break;
2413  case 'd': PatchedName = SuffixSize == 2 ? "vpcmpud" : "vpcmpd"; break;
2414  case 'q': PatchedName = SuffixSize == 2 ? "vpcmpuq" : "vpcmpq"; break;
2415  }
2416  // Set up the immediate to push into the operands later.
2417  ComparisonCode = CC;
2418  }
2419  }
2420 
2421  // FIXME: Hack to recognize vpcom<comparison code>{ub,uw,ud,uq,b,w,d,q}.
2422  if (PatchedName.startswith("vpcom") &&
2423  (PatchedName.back() == 'b' || PatchedName.back() == 'w' ||
2424  PatchedName.back() == 'd' || PatchedName.back() == 'q')) {
2425  unsigned SuffixSize = PatchedName.drop_back().back() == 'u' ? 2 : 1;
2426  unsigned CC = StringSwitch<unsigned>(
2427  PatchedName.slice(5, PatchedName.size() - SuffixSize))
2428  .Case("lt", 0x0)
2429  .Case("le", 0x1)
2430  .Case("gt", 0x2)
2431  .Case("ge", 0x3)
2432  .Case("eq", 0x4)
2433  .Case("neq", 0x5)
2434  .Case("false", 0x6)
2435  .Case("true", 0x7)
2436  .Default(~0U);
2437  if (CC != ~0U) {
2438  switch (PatchedName.back()) {
2439  default: llvm_unreachable("Unexpected character!");
2440  case 'b': PatchedName = SuffixSize == 2 ? "vpcomub" : "vpcomb"; break;
2441  case 'w': PatchedName = SuffixSize == 2 ? "vpcomuw" : "vpcomw"; break;
2442  case 'd': PatchedName = SuffixSize == 2 ? "vpcomud" : "vpcomd"; break;
2443  case 'q': PatchedName = SuffixSize == 2 ? "vpcomuq" : "vpcomq"; break;
2444  }
2445  // Set up the immediate to push into the operands later.
2446  ComparisonCode = CC;
2447  }
2448  }
2449 
2450 
2451  // Determine whether this is an instruction prefix.
2452  // FIXME:
2453  // Enhance prefixes integrity robustness. for example, following forms
2454  // are currently tolerated:
2455  // repz repnz <insn> ; GAS errors for the use of two similar prefixes
2456  // lock addq %rax, %rbx ; Destination operand must be of memory type
2457  // xacquire <insn> ; xacquire must be accompanied by 'lock'
2459  .Cases("rex64", "data32", "data16", true)
2460  .Cases("xacquire", "xrelease", true)
2461  .Cases("acquire", "release", isParsingIntelSyntax())
2462  .Default(false);
2463 
2464  auto isLockRepeatNtPrefix = [](StringRef N) {
2465  return StringSwitch<bool>(N)
2466  .Cases("lock", "rep", "repe", "repz", "repne", "repnz", "notrack", true)
2467  .Default(false);
2468  };
2469 
2470  bool CurlyAsEndOfStatement = false;
2471 
2472  unsigned Flags = X86::IP_NO_PREFIX;
2473  while (isLockRepeatNtPrefix(Name.lower())) {
2474  unsigned Prefix =
2476  .Cases("lock", "lock", X86::IP_HAS_LOCK)
2477  .Cases("rep", "repe", "repz", X86::IP_HAS_REPEAT)
2478  .Cases("repne", "repnz", X86::IP_HAS_REPEAT_NE)
2479  .Cases("notrack", "notrack", X86::IP_HAS_NOTRACK)
2480  .Default(X86::IP_NO_PREFIX); // Invalid prefix (impossible)
2481  Flags |= Prefix;
2482  if (getLexer().is(AsmToken::EndOfStatement)) {
2483  // We don't have real instr with the given prefix
2484  // let's use the prefix as the instr.
2485  // TODO: there could be several prefixes one after another
2486  Flags = X86::IP_NO_PREFIX;
2487  break;
2488  }
2489  Name = Parser.getTok().getString();
2490  Parser.Lex(); // eat the prefix
2491  // Hack: we could have something like "rep # some comment" or
2492  // "lock; cmpxchg16b $1" or "lock\0A\09incl" or "lock/incl"
2493  while (Name.startswith(";") || Name.startswith("\n") ||
2494  Name.startswith("#") || Name.startswith("\t") ||
2495  Name.startswith("/")) {
2496  Name = Parser.getTok().getString();
2497  Parser.Lex(); // go to next prefix or instr
2498  }
2499  }
2500 
2501  if (Flags)
2502  PatchedName = Name;
2503 
2504  // Hacks to handle 'data16' and 'data32'
2505  if (PatchedName == "data16" && is16BitMode()) {
2506  return Error(NameLoc, "redundant data16 prefix");
2507  }
2508  if (PatchedName == "data32") {
2509  if (is32BitMode())
2510  return Error(NameLoc, "redundant data32 prefix");
2511  if (is64BitMode())
2512  return Error(NameLoc, "'data32' is not supported in 64-bit mode");
2513  // Hack to 'data16' for the table lookup.
2514  PatchedName = "data16";
2515  }
2516 
2517  Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
2518 
2519  // Push the immediate if we extracted one from the mnemonic.
2520  if (ComparisonCode != ~0U && !isParsingIntelSyntax()) {
2521  const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode,
2522  getParser().getContext());
2523  Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
2524  }
2525 
2526  // This does the actual operand parsing. Don't parse any more if we have a
2527  // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
2528  // just want to parse the "lock" as the first instruction and the "incl" as
2529  // the next one.
2530  if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
2531  // Parse '*' modifier.
2532  if (getLexer().is(AsmToken::Star))
2533  Operands.push_back(X86Operand::CreateToken("*", consumeToken()));
2534 
2535  // Read the operands.
2536  while(1) {
2537  if (std::unique_ptr<X86Operand> Op = ParseOperand()) {
2538  Operands.push_back(std::move(Op));
2539  if (HandleAVX512Operand(Operands, *Operands.back()))
2540  return true;
2541  } else {
2542  return true;
2543  }
2544  // check for comma and eat it
2545  if (getLexer().is(AsmToken::Comma))
2546  Parser.Lex();
2547  else
2548  break;
2549  }
2550 
2551  // In MS inline asm curly braces mark the beginning/end of a block,
2552  // therefore they should be interepreted as end of statement
2553  CurlyAsEndOfStatement =
2554  isParsingIntelSyntax() && isParsingInlineAsm() &&
2555  (getLexer().is(AsmToken::LCurly) || getLexer().is(AsmToken::RCurly));
2556  if (getLexer().isNot(AsmToken::EndOfStatement) && !CurlyAsEndOfStatement)
2557  return TokError("unexpected token in argument list");
2558  }
2559 
2560  // Push the immediate if we extracted one from the mnemonic.
2561  if (ComparisonCode != ~0U && isParsingIntelSyntax()) {
2562  const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode,
2563  getParser().getContext());
2564  Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
2565  }
2566 
2567  // Consume the EndOfStatement or the prefix separator Slash
2568  if (getLexer().is(AsmToken::EndOfStatement) ||
2569  (isPrefix && getLexer().is(AsmToken::Slash)))
2570  Parser.Lex();
2571  else if (CurlyAsEndOfStatement)
2572  // Add an actual EndOfStatement before the curly brace
2573  Info.AsmRewrites->emplace_back(AOK_EndOfStatement,
2574  getLexer().getTok().getLoc(), 0);
2575 
2576  // This is for gas compatibility and cannot be done in td.
2577  // Adding "p" for some floating point with no argument.
2578  // For example: fsub --> fsubp
2579  bool IsFp =
2580  Name == "fsub" || Name == "fdiv" || Name == "fsubr" || Name == "fdivr";
2581  if (IsFp && Operands.size() == 1) {
2582  const char *Repl = StringSwitch<const char *>(Name)
2583  .Case("fsub", "fsubp")
2584  .Case("fdiv", "fdivp")
2585  .Case("fsubr", "fsubrp")
2586  .Case("fdivr", "fdivrp");
2587  static_cast<X86Operand &>(*Operands[0]).setTokenValue(Repl);
2588  }
2589 
2590  // Moving a 32 or 16 bit value into a segment register has the same
2591  // behavior. Modify such instructions to always take shorter form.
2592  if ((Name == "mov" || Name == "movw" || Name == "movl") &&
2593  (Operands.size() == 3)) {
2594  X86Operand &Op1 = (X86Operand &)*Operands[1];
2595  X86Operand &Op2 = (X86Operand &)*Operands[2];
2596  SMLoc Loc = Op1.getEndLoc();
2597  if (Op1.isReg() && Op2.isReg() &&
2598  X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(
2599  Op2.getReg()) &&
2600  (X86MCRegisterClasses[X86::GR16RegClassID].contains(Op1.getReg()) ||
2601  X86MCRegisterClasses[X86::GR32RegClassID].contains(Op1.getReg()))) {
2602  // Change instruction name to match new instruction.
2603  if (Name != "mov" && Name[3] == (is16BitMode() ? 'l' : 'w')) {
2604  Name = is16BitMode() ? "movw" : "movl";
2605  Operands[0] = X86Operand::CreateToken(Name, NameLoc);
2606  }
2607  // Select the correct equivalent 16-/32-bit source register.
2608  unsigned Reg =
2609  getX86SubSuperRegisterOrZero(Op1.getReg(), is16BitMode() ? 16 : 32);
2610  Operands[1] = X86Operand::CreateReg(Reg, Loc, Loc);
2611  }
2612  }
2613 
2614  // This is a terrible hack to handle "out[s]?[bwl]? %al, (%dx)" ->
2615  // "outb %al, %dx". Out doesn't take a memory form, but this is a widely
2616  // documented form in various unofficial manuals, so a lot of code uses it.
2617  if ((Name == "outb" || Name == "outsb" || Name == "outw" || Name == "outsw" ||
2618  Name == "outl" || Name == "outsl" || Name == "out" || Name == "outs") &&
2619  Operands.size() == 3) {
2620  X86Operand &Op = (X86Operand &)*Operands.back();
2621  if (Op.isDXReg())
2622  Operands.back() = X86Operand::CreateReg(X86::DX, Op.getStartLoc(),
2623  Op.getEndLoc());
2624  }
2625  // Same hack for "in[s]?[bwl]? (%dx), %al" -> "inb %dx, %al".
2626  if ((Name == "inb" || Name == "insb" || Name == "inw" || Name == "insw" ||
2627  Name == "inl" || Name == "insl" || Name == "in" || Name == "ins") &&
2628  Operands.size() == 3) {
2629  X86Operand &Op = (X86Operand &)*Operands[1];
2630  if (Op.isDXReg())
2631  Operands[1] = X86Operand::CreateReg(X86::DX, Op.getStartLoc(),
2632  Op.getEndLoc());
2633  }
2634 
2636  bool HadVerifyError = false;
2637 
2638  // Append default arguments to "ins[bwld]"
2639  if (Name.startswith("ins") &&
2640  (Operands.size() == 1 || Operands.size() == 3) &&
2641  (Name == "insb" || Name == "insw" || Name == "insl" || Name == "insd" ||
2642  Name == "ins")) {
2643 
2644  AddDefaultSrcDestOperands(TmpOperands,
2645  X86Operand::CreateReg(X86::DX, NameLoc, NameLoc),
2646  DefaultMemDIOperand(NameLoc));
2647  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2648  }
2649 
2650  // Append default arguments to "outs[bwld]"
2651  if (Name.startswith("outs") &&
2652  (Operands.size() == 1 || Operands.size() == 3) &&
2653  (Name == "outsb" || Name == "outsw" || Name == "outsl" ||
2654  Name == "outsd" || Name == "outs")) {
2655  AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc),
2656  X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
2657  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2658  }
2659 
2660  // Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate
2661  // values of $SIREG according to the mode. It would be nice if this
2662  // could be achieved with InstAlias in the tables.
2663  if (Name.startswith("lods") &&
2664  (Operands.size() == 1 || Operands.size() == 2) &&
2665  (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
2666  Name == "lodsl" || Name == "lodsd" || Name == "lodsq")) {
2667  TmpOperands.push_back(DefaultMemSIOperand(NameLoc));
2668  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2669  }
2670 
2671  // Transform "stos[bwlq]" into "stos[bwlq] ($DIREG)" for appropriate
2672  // values of $DIREG according to the mode. It would be nice if this
2673  // could be achieved with InstAlias in the tables.
2674  if (Name.startswith("stos") &&
2675  (Operands.size() == 1 || Operands.size() == 2) &&
2676  (Name == "stos" || Name == "stosb" || Name == "stosw" ||
2677  Name == "stosl" || Name == "stosd" || Name == "stosq")) {
2678  TmpOperands.push_back(DefaultMemDIOperand(NameLoc));
2679  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2680  }
2681 
2682  // Transform "scas[bwlq]" into "scas[bwlq] ($DIREG)" for appropriate
2683  // values of $DIREG according to the mode. It would be nice if this
2684  // could be achieved with InstAlias in the tables.
2685  if (Name.startswith("scas") &&
2686  (Operands.size() == 1 || Operands.size() == 2) &&
2687  (Name == "scas" || Name == "scasb" || Name == "scasw" ||
2688  Name == "scasl" || Name == "scasd" || Name == "scasq")) {
2689  TmpOperands.push_back(DefaultMemDIOperand(NameLoc));
2690  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2691  }
2692 
2693  // Add default SI and DI operands to "cmps[bwlq]".
2694  if (Name.startswith("cmps") &&
2695  (Operands.size() == 1 || Operands.size() == 3) &&
2696  (Name == "cmps" || Name == "cmpsb" || Name == "cmpsw" ||
2697  Name == "cmpsl" || Name == "cmpsd" || Name == "cmpsq")) {
2698  AddDefaultSrcDestOperands(TmpOperands, DefaultMemDIOperand(NameLoc),
2699  DefaultMemSIOperand(NameLoc));
2700  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2701  }
2702 
2703  // Add default SI and DI operands to "movs[bwlq]".
2704  if (((Name.startswith("movs") &&
2705  (Name == "movs" || Name == "movsb" || Name == "movsw" ||
2706  Name == "movsl" || Name == "movsd" || Name == "movsq")) ||
2707  (Name.startswith("smov") &&
2708  (Name == "smov" || Name == "smovb" || Name == "smovw" ||
2709  Name == "smovl" || Name == "smovd" || Name == "smovq"))) &&
2710  (Operands.size() == 1 || Operands.size() == 3)) {
2711  if (Name == "movsd" && Operands.size() == 1 && !isParsingIntelSyntax())
2712  Operands.back() = X86Operand::CreateToken("movsl", NameLoc);
2713  AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc),
2714  DefaultMemDIOperand(NameLoc));
2715  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2716  }
2717 
2718  // Check if we encountered an error for one the string insturctions
2719  if (HadVerifyError) {
2720  return HadVerifyError;
2721  }
2722 
2723  // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
2724  // "shift <op>".
2725  if ((Name.startswith("shr") || Name.startswith("sar") ||
2726  Name.startswith("shl") || Name.startswith("sal") ||
2727  Name.startswith("rcl") || Name.startswith("rcr") ||
2728  Name.startswith("rol") || Name.startswith("ror")) &&
2729  Operands.size() == 3) {
2730  if (isParsingIntelSyntax()) {
2731  // Intel syntax
2732  X86Operand &Op1 = static_cast<X86Operand &>(*Operands[2]);
2733  if (Op1.isImm() && isa<MCConstantExpr>(Op1.getImm()) &&
2734  cast<MCConstantExpr>(Op1.getImm())->getValue() == 1)
2735  Operands.pop_back();
2736  } else {
2737  X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
2738  if (Op1.isImm() && isa<MCConstantExpr>(Op1.getImm()) &&
2739  cast<MCConstantExpr>(Op1.getImm())->getValue() == 1)
2740  Operands.erase(Operands.begin() + 1);
2741  }
2742  }
2743 
2744  // Transforms "int $3" into "int3" as a size optimization. We can't write an
2745  // instalias with an immediate operand yet.
2746  if (Name == "int" && Operands.size() == 2) {
2747  X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
2748  if (Op1.isImm())
2749  if (auto *CE = dyn_cast<MCConstantExpr>(Op1.getImm()))
2750  if (CE->getValue() == 3) {
2751  Operands.erase(Operands.begin() + 1);
2752  static_cast<X86Operand &>(*Operands[0]).setTokenValue("int3");
2753  }
2754  }
2755 
2756  // Transforms "xlat mem8" into "xlatb"
2757  if ((Name == "xlat" || Name == "xlatb") && Operands.size() == 2) {
2758  X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
2759  if (Op1.isMem8()) {
2760  Warning(Op1.getStartLoc(), "memory operand is only for determining the "
2761  "size, (R|E)BX will be used for the location");
2762  Operands.pop_back();
2763  static_cast<X86Operand &>(*Operands[0]).setTokenValue("xlatb");
2764  }
2765  }
2766 
2767  if (Flags)
2768  Operands.push_back(X86Operand::CreatePrefix(Flags, NameLoc, NameLoc));
2769  return false;
2770 }
2771 
2772 bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
2773  return false;
2774 }
2775 
2776 bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
2777  const MCRegisterInfo *MRI = getContext().getRegisterInfo();
2778 
2779  switch (Inst.getOpcode()) {
2780  case X86::VGATHERDPDYrm:
2781  case X86::VGATHERDPDrm:
2782  case X86::VGATHERDPSYrm:
2783  case X86::VGATHERDPSrm:
2784  case X86::VGATHERQPDYrm:
2785  case X86::VGATHERQPDrm:
2786  case X86::VGATHERQPSYrm:
2787  case X86::VGATHERQPSrm:
2788  case X86::VPGATHERDDYrm:
2789  case X86::VPGATHERDDrm:
2790  case X86::VPGATHERDQYrm:
2791  case X86::VPGATHERDQrm:
2792  case X86::VPGATHERQDYrm:
2793  case X86::VPGATHERQDrm:
2794  case X86::VPGATHERQQYrm:
2795  case X86::VPGATHERQQrm: {
2796  unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg());
2797  unsigned Mask = MRI->getEncodingValue(Inst.getOperand(1).getReg());
2798  unsigned Index =
2800  if (Dest == Mask || Dest == Index || Mask == Index)
2801  return Warning(Ops[0]->getStartLoc(), "mask, index, and destination "
2802  "registers should be distinct");
2803  break;
2804  }
2805  case X86::VGATHERDPDZ128rm:
2806  case X86::VGATHERDPDZ256rm:
2807  case X86::VGATHERDPDZrm:
2808  case X86::VGATHERDPSZ128rm:
2809  case X86::VGATHERDPSZ256rm:
2810  case X86::VGATHERDPSZrm:
2811  case X86::VGATHERQPDZ128rm:
2812  case X86::VGATHERQPDZ256rm:
2813  case X86::VGATHERQPDZrm:
2814  case X86::VGATHERQPSZ128rm:
2815  case X86::VGATHERQPSZ256rm:
2816  case X86::VGATHERQPSZrm:
2817  case X86::VPGATHERDDZ128rm:
2818  case X86::VPGATHERDDZ256rm:
2819  case X86::VPGATHERDDZrm:
2820  case X86::VPGATHERDQZ128rm:
2821  case X86::VPGATHERDQZ256rm:
2822  case X86::VPGATHERDQZrm:
2823  case X86::VPGATHERQDZ128rm:
2824  case X86::VPGATHERQDZ256rm:
2825  case X86::VPGATHERQDZrm:
2826  case X86::VPGATHERQQZ128rm:
2827  case X86::VPGATHERQQZ256rm:
2828  case X86::VPGATHERQQZrm: {
2829  unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg());
2830  unsigned Index =
2832  if (Dest == Index)
2833  return Warning(Ops[0]->getStartLoc(), "index and destination registers "
2834  "should be distinct");
2835  break;
2836  }
2837  case X86::V4FMADDPSrm:
2838  case X86::V4FMADDPSrmk:
2839  case X86::V4FMADDPSrmkz:
2840  case X86::V4FMADDSSrm:
2841  case X86::V4FMADDSSrmk:
2842  case X86::V4FMADDSSrmkz:
2843  case X86::V4FNMADDPSrm:
2844  case X86::V4FNMADDPSrmk:
2845  case X86::V4FNMADDPSrmkz:
2846  case X86::V4FNMADDSSrm:
2847  case X86::V4FNMADDSSrmk:
2848  case X86::V4FNMADDSSrmkz:
2849  case X86::VP4DPWSSDSrm:
2850  case X86::VP4DPWSSDSrmk:
2851  case X86::VP4DPWSSDSrmkz:
2852  case X86::VP4DPWSSDrm:
2853  case X86::VP4DPWSSDrmk:
2854  case X86::VP4DPWSSDrmkz: {
2855  unsigned Src2 = Inst.getOperand(Inst.getNumOperands() -
2857  unsigned Src2Enc = MRI->getEncodingValue(Src2);
2858  if (Src2Enc % 4 != 0) {
2860  unsigned GroupStart = (Src2Enc / 4) * 4;
2861  unsigned GroupEnd = GroupStart + 3;
2862  return Warning(Ops[0]->getStartLoc(),
2863  "source register '" + RegName + "' implicitly denotes '" +
2864  RegName.take_front(3) + Twine(GroupStart) + "' to '" +
2865  RegName.take_front(3) + Twine(GroupEnd) +
2866  "' source group");
2867  }
2868  break;
2869  }
2870  }
2871 
2872  return false;
2873 }
2874 
2875 static const char *getSubtargetFeatureName(uint64_t Val);
2876 
2877 void X86AsmParser::EmitInstruction(MCInst &Inst, OperandVector &Operands,
2878  MCStreamer &Out) {
2879  Out.EmitInstruction(Inst, getSTI());
2880 }
2881 
2882 bool X86AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
2883  OperandVector &Operands,
2884  MCStreamer &Out, uint64_t &ErrorInfo,
2885  bool MatchingInlineAsm) {
2886  if (isParsingIntelSyntax())
2887  return MatchAndEmitIntelInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo,
2888  MatchingInlineAsm);
2889  return MatchAndEmitATTInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo,
2890  MatchingInlineAsm);
2891 }
2892 
2893 void X86AsmParser::MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op,
2894  OperandVector &Operands, MCStreamer &Out,
2895  bool MatchingInlineAsm) {
2896  // FIXME: This should be replaced with a real .td file alias mechanism.
2897  // Also, MatchInstructionImpl should actually *do* the EmitInstruction
2898  // call.
2899  const char *Repl = StringSwitch<const char *>(Op.getToken())
2900  .Case("finit", "fninit")
2901  .Case("fsave", "fnsave")
2902  .Case("fstcw", "fnstcw")
2903  .Case("fstcww", "fnstcw")
2904  .Case("fstenv", "fnstenv")
2905  .Case("fstsw", "fnstsw")
2906  .Case("fstsww", "fnstsw")
2907  .Case("fclex", "fnclex")
2908  .Default(nullptr);
2909  if (Repl) {
2910  MCInst Inst;
2911  Inst.setOpcode(X86::WAIT);
2912  Inst.setLoc(IDLoc);
2913  if (!MatchingInlineAsm)
2914  EmitInstruction(Inst, Operands, Out);
2915  Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
2916  }
2917 }
2918 
2919 bool X86AsmParser::ErrorMissingFeature(SMLoc IDLoc,
2920  const FeatureBitset &MissingFeatures,
2921  bool MatchingInlineAsm) {
2922  assert(MissingFeatures.any() && "Unknown missing feature!");
2923  SmallString<126> Msg;
2924  raw_svector_ostream OS(Msg);
2925  OS << "instruction requires:";
2926  for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) {
2927  if (MissingFeatures[i])
2928  OS << ' ' << getSubtargetFeatureName(i);
2929  }
2930  return Error(IDLoc, OS.str(), SMRange(), MatchingInlineAsm);
2931 }
2932 
2933 static unsigned getPrefixes(OperandVector &Operands) {
2934  unsigned Result = 0;
2935  X86Operand &Prefix = static_cast<X86Operand &>(*Operands.back());
2936  if (Prefix.isPrefix()) {
2937  Result = Prefix.getPrefix();
2938  Operands.pop_back();
2939  }
2940  return Result;
2941 }
2942 
2943 bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
2944  OperandVector &Operands,
2945  MCStreamer &Out,
2946  uint64_t &ErrorInfo,
2947  bool MatchingInlineAsm) {
2948  assert(!Operands.empty() && "Unexpect empty operand list!");
2949  X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
2950  assert(Op.isToken() && "Leading operand should always be a mnemonic!");
2951  SMRange EmptyRange = None;
2952 
2953  // First, handle aliases that expand to multiple instructions.
2954  MatchFPUWaitAlias(IDLoc, Op, Operands, Out, MatchingInlineAsm);
2955 
2956  bool WasOriginallyInvalidOperand = false;
2957  unsigned Prefixes = getPrefixes(Operands);
2958 
2959  MCInst Inst;
2960 
2961  if (Prefixes)
2962  Inst.setFlags(Prefixes);
2963 
2964  // First, try a direct match.
2965  FeatureBitset MissingFeatures;
2966  switch (MatchInstruction(Operands, Inst, ErrorInfo, MissingFeatures,
2967  MatchingInlineAsm, isParsingIntelSyntax())) {
2968  default: llvm_unreachable("Unexpected match result!");
2969  case Match_Success:
2970  if (!MatchingInlineAsm && validateInstruction(Inst, Operands))
2971  return true;
2972  // Some instructions need post-processing to, for example, tweak which
2973  // encoding is selected. Loop on it while changes happen so the
2974  // individual transformations can chain off each other.
2975  if (!MatchingInlineAsm)
2976  while (processInstruction(Inst, Operands))
2977  ;
2978 
2979  Inst.setLoc(IDLoc);
2980  if (!MatchingInlineAsm)
2981  EmitInstruction(Inst, Operands, Out);
2982  Opcode = Inst.getOpcode();
2983  return false;
2984  case Match_MissingFeature:
2985  return ErrorMissingFeature(IDLoc, MissingFeatures, MatchingInlineAsm);
2986  case Match_InvalidOperand:
2987  WasOriginallyInvalidOperand = true;
2988  break;
2989  case Match_MnemonicFail:
2990  break;
2991  }
2992 
2993  // FIXME: Ideally, we would only attempt suffix matches for things which are
2994  // valid prefixes, and we could just infer the right unambiguous
2995  // type. However, that requires substantially more matcher support than the
2996  // following hack.
2997 
2998  // Change the operand to point to a temporary token.
2999  StringRef Base = Op.getToken();
3000  SmallString<16> Tmp;
3001  Tmp += Base;
3002  Tmp += ' ';
3003  Op.setTokenValue(Tmp);
3004 
3005  // If this instruction starts with an 'f', then it is a floating point stack
3006  // instruction. These come in up to three forms for 32-bit, 64-bit, and
3007  // 80-bit floating point, which use the suffixes s,l,t respectively.
3008  //
3009  // Otherwise, we assume that this may be an integer instruction, which comes
3010  // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
3011  const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
3012 
3013  // Check for the various suffix matches.
3014  uint64_t ErrorInfoIgnore;
3015  FeatureBitset ErrorInfoMissingFeatures; // Init suppresses compiler warnings.
3016  unsigned Match[4];
3017 
3018  for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I) {
3019  Tmp.back() = Suffixes[I];
3020  Match[I] = MatchInstruction(Operands, Inst, ErrorInfoIgnore,
3021  MissingFeatures, MatchingInlineAsm,
3022  isParsingIntelSyntax());
3023  // If this returned as a missing feature failure, remember that.
3024  if (Match[I] == Match_MissingFeature)
3025  ErrorInfoMissingFeatures = MissingFeatures;
3026  }
3027 
3028  // Restore the old token.
3029  Op.setTokenValue(Base);
3030 
3031  // If exactly one matched, then we treat that as a successful match (and the
3032  // instruction will already have been filled in correctly, since the failing
3033  // matches won't have modified it).
3034  unsigned NumSuccessfulMatches =
3035  std::count(std::begin(Match), std::end(Match), Match_Success);
3036  if (NumSuccessfulMatches == 1) {
3037  Inst.setLoc(IDLoc);
3038  if (!MatchingInlineAsm)
3039  EmitInstruction(Inst, Operands, Out);
3040  Opcode = Inst.getOpcode();
3041  return false;
3042  }
3043 
3044  // Otherwise, the match failed, try to produce a decent error message.
3045 
3046  // If we had multiple suffix matches, then identify this as an ambiguous
3047  // match.
3048  if (NumSuccessfulMatches > 1) {
3049  char MatchChars[4];
3050  unsigned NumMatches = 0;
3051  for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I)
3052  if (Match[I] == Match_Success)
3053  MatchChars[NumMatches++] = Suffixes[I];
3054 
3055  SmallString<126> Msg;
3056  raw_svector_ostream OS(Msg);
3057  OS << "ambiguous instructions require an explicit suffix (could be ";
3058  for (unsigned i = 0; i != NumMatches; ++i) {
3059  if (i != 0)
3060  OS << ", ";
3061  if (i + 1 == NumMatches)
3062  OS << "or ";
3063  OS << "'" << Base << MatchChars[i] << "'";
3064  }
3065  OS << ")";
3066  Error(IDLoc, OS.str(), EmptyRange, MatchingInlineAsm);
3067  return true;
3068  }
3069 
3070  // Okay, we know that none of the variants matched successfully.
3071 
3072  // If all of the instructions reported an invalid mnemonic, then the original
3073  // mnemonic was invalid.
3074  if (std::count(std::begin(Match), std::end(Match), Match_MnemonicFail) == 4) {
3075  if (!WasOriginallyInvalidOperand) {
3076  return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
3077  Op.getLocRange(), MatchingInlineAsm);
3078  }
3079 
3080  // Recover location info for the operand if we know which was the problem.
3081  if (ErrorInfo != ~0ULL) {
3082  if (ErrorInfo >= Operands.size())
3083  return Error(IDLoc, "too few operands for instruction", EmptyRange,
3084  MatchingInlineAsm);
3085 
3086  X86Operand &Operand = (X86Operand &)*Operands[ErrorInfo];
3087  if (Operand.getStartLoc().isValid()) {
3088  SMRange OperandRange = Operand.getLocRange();
3089  return Error(Operand.getStartLoc(), "invalid operand for instruction",
3090  OperandRange, MatchingInlineAsm);
3091  }
3092  }
3093 
3094  return Error(IDLoc, "invalid operand for instruction", EmptyRange,
3095  MatchingInlineAsm);
3096  }
3097 
3098  // If one instruction matched with a missing feature, report this as a
3099  // missing feature.
3100  if (std::count(std::begin(Match), std::end(Match),
3101  Match_MissingFeature) == 1) {
3102  ErrorInfo = Match_MissingFeature;
3103  return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeatures,
3104  MatchingInlineAsm);
3105  }
3106 
3107  // If one instruction matched with an invalid operand, report this as an
3108  // operand failure.
3109  if (std::count(std::begin(Match), std::end(Match),
3110  Match_InvalidOperand) == 1) {
3111  return Error(IDLoc, "invalid operand for instruction", EmptyRange,
3112  MatchingInlineAsm);
3113  }
3114 
3115  // If all of these were an outright failure, report it in a useless way.
3116  Error(IDLoc, "unknown use of instruction mnemonic without a size suffix",
3117  EmptyRange, MatchingInlineAsm);
3118  return true;
3119 }
3120 
3121 bool X86AsmParser::MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
3122  OperandVector &Operands,
3123  MCStreamer &Out,
3124  uint64_t &ErrorInfo,
3125  bool MatchingInlineAsm) {
3126  assert(!Operands.empty() && "Unexpect empty operand list!");
3127  X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
3128  assert(Op.isToken() && "Leading operand should always be a mnemonic!");
3129  StringRef Mnemonic = Op.getToken();
3130  SMRange EmptyRange = None;
3131  StringRef Base = Op.getToken();
3132  unsigned Prefixes = getPrefixes(Operands);
3133 
3134  // First, handle aliases that expand to multiple instructions.
3135  MatchFPUWaitAlias(IDLoc, Op, Operands, Out, MatchingInlineAsm);
3136 
3137  MCInst Inst;
3138 
3139  if (Prefixes)
3140  Inst.setFlags(Prefixes);
3141 
3142  // Find one unsized memory operand, if present.
3143  X86Operand *UnsizedMemOp = nullptr;
3144  for (const auto &Op : Operands) {
3145  X86Operand *X86Op = static_cast<X86Operand *>(Op.get());
3146  if (X86Op->isMemUnsized()) {
3147  UnsizedMemOp = X86Op;
3148  // Have we found an unqualified memory operand,
3149  // break. IA allows only one memory operand.
3150  break;
3151  }
3152  }
3153 
3154  // Allow some instructions to have implicitly pointer-sized operands. This is
3155  // compatible with gas.
3156  if (UnsizedMemOp) {
3157  static const char *const PtrSizedInstrs[] = {"call", "jmp", "push"};
3158  for (const char *Instr : PtrSizedInstrs) {
3159  if (Mnemonic == Instr) {
3160  UnsizedMemOp->Mem.Size = getPointerWidth();
3161  break;
3162  }
3163  }
3164  }
3165 
3167  FeatureBitset ErrorInfoMissingFeatures;
3168  FeatureBitset MissingFeatures;
3169 
3170  // If unsized push has immediate operand we should default the default pointer
3171  // size for the size.
3172  if (Mnemonic == "push" && Operands.size() == 2) {
3173  auto *X86Op = static_cast<X86Operand *>(Operands[1].get());
3174  if (X86Op->isImm()) {
3175  // If it's not a constant fall through and let remainder take care of it.
3176  const auto *CE = dyn_cast<MCConstantExpr>(X86Op->getImm());
3177  unsigned Size = getPointerWidth();
3178  if (CE &&
3179  (isIntN(Size, CE->getValue()) || isUIntN(Size, CE->getValue()))) {
3180  SmallString<16> Tmp;
3181  Tmp += Base;
3182  Tmp += (is64BitMode())
3183  ? "q"
3184  : (is32BitMode()) ? "l" : (is16BitMode()) ? "w" : " ";
3185  Op.setTokenValue(Tmp);
3186  // Do match in ATT mode to allow explicit suffix usage.
3187  Match.push_back(MatchInstruction(Operands, Inst, ErrorInfo,
3188  MissingFeatures, MatchingInlineAsm,
3189  false /*isParsingIntelSyntax()*/));
3190  Op.setTokenValue(Base);
3191  }
3192  }
3193  }
3194 
3195  // If an unsized memory operand is present, try to match with each memory
3196  // operand size. In Intel assembly, the size is not part of the instruction
3197  // mnemonic.
3198  if (UnsizedMemOp && UnsizedMemOp->isMemUnsized()) {
3199  static const unsigned MopSizes[] = {8, 16, 32, 64, 80, 128, 256, 512};
3200  for (unsigned Size : MopSizes) {
3201  UnsizedMemOp->Mem.Size = Size;
3202  uint64_t ErrorInfoIgnore;
3203  unsigned LastOpcode = Inst.getOpcode();
3204  unsigned M = MatchInstruction(Operands, Inst, ErrorInfoIgnore,
3205  MissingFeatures, MatchingInlineAsm,
3206  isParsingIntelSyntax());
3207  if (Match.empty() || LastOpcode != Inst.getOpcode())
3208  Match.push_back(M);
3209 
3210  // If this returned as a missing feature failure, remember that.
3211  if (Match.back() == Match_MissingFeature)
3212  ErrorInfoMissingFeatures = MissingFeatures;
3213  }
3214 
3215  // Restore the size of the unsized memory operand if we modified it.
3216  UnsizedMemOp->Mem.Size = 0;
3217  }
3218 
3219  // If we haven't matched anything yet, this is not a basic integer or FPU
3220  // operation. There shouldn't be any ambiguity in our mnemonic table, so try
3221  // matching with the unsized operand.
3222  if (Match.empty()) {
3223  Match.push_back(MatchInstruction(
3224  Operands, Inst, ErrorInfo, MissingFeatures, MatchingInlineAsm,
3225  isParsingIntelSyntax()));
3226  // If this returned as a missing feature failure, remember that.
3227  if (Match.back() == Match_MissingFeature)
3228  ErrorInfoMissingFeatures = MissingFeatures;
3229  }
3230 
3231  // Restore the size of the unsized memory operand if we modified it.
3232  if (UnsizedMemOp)
3233  UnsizedMemOp->Mem.Size = 0;
3234 
3235  // If it's a bad mnemonic, all results will be the same.
3236  if (Match.back() == Match_MnemonicFail) {
3237  return Error(IDLoc, "invalid instruction mnemonic '" + Mnemonic + "'",
3238  Op.getLocRange(), MatchingInlineAsm);
3239  }
3240 
3241  unsigned NumSuccessfulMatches =
3242  std::count(std::begin(Match), std::end(Match), Match_Success);
3243 
3244  // If matching was ambiguous and we had size information from the frontend,
3245  // try again with that. This handles cases like "movxz eax, m8/m16".
3246  if (UnsizedMemOp && NumSuccessfulMatches > 1 &&
3247  UnsizedMemOp->getMemFrontendSize()) {
3248  UnsizedMemOp->Mem.Size = UnsizedMemOp->getMemFrontendSize();
3249  unsigned M = MatchInstruction(
3250  Operands, Inst, ErrorInfo, MissingFeatures, MatchingInlineAsm,
3251  isParsingIntelSyntax());
3252  if (M == Match_Success)
3253  NumSuccessfulMatches = 1;
3254 
3255  // Add a rewrite that encodes the size information we used from the
3256  // frontend.
3257  InstInfo->AsmRewrites->emplace_back(
3258  AOK_SizeDirective, UnsizedMemOp->getStartLoc(),
3259  /*Len=*/0, UnsizedMemOp->getMemFrontendSize());
3260  }
3261 
3262  // If exactly one matched, then we treat that as a successful match (and the
3263  // instruction will already have been filled in correctly, since the failing
3264  // matches won't have modified it).
3265  if (NumSuccessfulMatches == 1) {
3266  if (!MatchingInlineAsm && validateInstruction(Inst, Operands))
3267  return true;
3268  // Some instructions need post-processing to, for example, tweak which
3269  // encoding is selected. Loop on it while changes happen so the individual
3270  // transformations can chain off each other.
3271  if (!MatchingInlineAsm)
3272  while (processInstruction(Inst, Operands))
3273  ;
3274  Inst.setLoc(IDLoc);
3275  if (!MatchingInlineAsm)
3276  EmitInstruction(Inst, Operands, Out);
3277  Opcode = Inst.getOpcode();
3278  return false;
3279  } else if (NumSuccessfulMatches > 1) {
3280  assert(UnsizedMemOp &&
3281  "multiple matches only possible with unsized memory operands");
3282  return Error(UnsizedMemOp->getStartLoc(),
3283  "ambiguous operand size for instruction '" + Mnemonic + "\'",
3284  UnsizedMemOp->getLocRange());
3285  }
3286 
3287  // If one instruction matched with a missing feature, report this as a
3288  // missing feature.
3289  if (std::count(std::begin(Match), std::end(Match),
3290  Match_MissingFeature) == 1) {
3291  ErrorInfo = Match_MissingFeature;
3292  return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeatures,
3293  MatchingInlineAsm);
3294  }
3295 
3296  // If one instruction matched with an invalid operand, report this as an
3297  // operand failure.
3298  if (std::count(std::begin(Match), std::end(Match),
3299  Match_InvalidOperand) == 1) {
3300  return Error(IDLoc, "invalid operand for instruction", EmptyRange,
3301  MatchingInlineAsm);
3302  }
3303 
3304  // If all of these were an outright failure, report it in a useless way.
3305  return Error(IDLoc, "unknown instruction mnemonic", EmptyRange,
3306  MatchingInlineAsm);
3307 }
3308 
3309 bool X86AsmParser::OmitRegisterFromClobberLists(unsigned RegNo) {
3310  return X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo);
3311 }
3312 
3313 bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
3314  MCAsmParser &Parser = getParser();
3315  StringRef IDVal = DirectiveID.getIdentifier();
3316  if (IDVal.startswith(".code"))
3317  return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
3318  else if (IDVal.startswith(".att_syntax")) {
3319  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3320  if (Parser.getTok().getString() == "prefix")
3321  Parser.Lex();
3322  else if (Parser.getTok().getString() == "noprefix")
3323  return Error(DirectiveID.getLoc(), "'.att_syntax noprefix' is not "
3324  "supported: registers must have a "
3325  "'%' prefix in .att_syntax");
3326  }
3327  getParser().setAssemblerDialect(0);
3328  return false;
3329  } else if (IDVal.startswith(".intel_syntax")) {
3330  getParser().setAssemblerDialect(1);
3331  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3332  if (Parser.getTok().getString() == "noprefix")
3333  Parser.Lex();
3334  else if (Parser.getTok().getString() == "prefix")
3335  return Error(DirectiveID.getLoc(), "'.intel_syntax prefix' is not "
3336  "supported: registers must not have "
3337  "a '%' prefix in .intel_syntax");
3338  }
3339  return false;
3340  } else if (IDVal == ".even")
3341  return parseDirectiveEven(DirectiveID.getLoc());
3342  else if (IDVal == ".cv_fpo_proc")
3343  return parseDirectiveFPOProc(DirectiveID.getLoc());
3344  else if (IDVal == ".cv_fpo_setframe")
3345  return parseDirectiveFPOSetFrame(DirectiveID.getLoc());
3346  else if (IDVal == ".cv_fpo_pushreg")
3347  return parseDirectiveFPOPushReg(DirectiveID.getLoc());
3348  else if (IDVal == ".cv_fpo_stackalloc")
3349  return parseDirectiveFPOStackAlloc(DirectiveID.getLoc());
3350  else if (IDVal == ".cv_fpo_stackalign")
3351  return parseDirectiveFPOStackAlign(DirectiveID.getLoc());
3352  else if (IDVal == ".cv_fpo_endprologue")
3353  return parseDirectiveFPOEndPrologue(DirectiveID.getLoc());
3354  else if (IDVal == ".cv_fpo_endproc")
3355  return parseDirectiveFPOEndProc(DirectiveID.getLoc());
3356 
3357  return true;
3358 }
3359 
3360 /// parseDirectiveEven
3361 /// ::= .even
3362 bool X86AsmParser::parseDirectiveEven(SMLoc L) {
3363  if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
3364  return false;
3365 
3366  const MCSection *Section = getStreamer().getCurrentSectionOnly();
3367  if (!Section) {
3368  getStreamer().InitSections(false);
3369  Section = getStreamer().getCurrentSectionOnly();
3370  }
3371  if (Section->UseCodeAlign())
3372  getStreamer().EmitCodeAlignment(2, 0);
3373  else
3374  getStreamer().EmitValueToAlignment(2, 0, 1, 0);
3375  return false;
3376 }
3377 
3378 /// ParseDirectiveCode
3379 /// ::= .code16 | .code32 | .code64
3380 bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
3381  MCAsmParser &Parser = getParser();
3382  Code16GCC = false;
3383  if (IDVal == ".code16") {
3384  Parser.Lex();
3385  if (!is16BitMode()) {
3386  SwitchMode(X86::Mode16Bit);
3387  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3388  }
3389  } else if (IDVal == ".code16gcc") {
3390  // .code16gcc parses as if in 32-bit mode, but emits code in 16-bit mode.
3391  Parser.Lex();
3392  Code16GCC = true;
3393  if (!is16BitMode()) {
3394  SwitchMode(X86::Mode16Bit);
3395  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3396  }
3397  } else if (IDVal == ".code32") {
3398  Parser.Lex();
3399  if (!is32BitMode()) {
3400  SwitchMode(X86::Mode32Bit);
3401  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3402  }
3403  } else if (IDVal == ".code64") {
3404  Parser.Lex();
3405  if (!is64BitMode()) {
3406  SwitchMode(X86::Mode64Bit);
3407  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code64);
3408  }
3409  } else {
3410  Error(L, "unknown directive " + IDVal);
3411  return false;
3412  }
3413 
3414  return false;
3415 }
3416 
3417 // .cv_fpo_proc foo
3418 bool X86AsmParser::parseDirectiveFPOProc(SMLoc L) {
3419  MCAsmParser &Parser = getParser();
3420  StringRef ProcName;
3421  int64_t ParamsSize;
3422  if (Parser.parseIdentifier(ProcName))
3423  return Parser.TokError("expected symbol name");
3424  if (Parser.parseIntToken(ParamsSize, "expected parameter byte count"))
3425  return true;
3426  if (!isUIntN(32, ParamsSize))
3427  return Parser.TokError("parameters size out of range");
3428  if (Parser.parseEOL("unexpected tokens"))
3429  return addErrorSuffix(" in '.cv_fpo_proc' directive");
3430  MCSymbol *ProcSym = getContext().getOrCreateSymbol(ProcName);
3431  return getTargetStreamer().emitFPOProc(ProcSym, ParamsSize, L);
3432 }
3433 
3434 // .cv_fpo_setframe ebp
3435 bool X86AsmParser::parseDirectiveFPOSetFrame(SMLoc L) {
3436  MCAsmParser &Parser = getParser();
3437  unsigned Reg;
3438  SMLoc DummyLoc;
3439  if (ParseRegister(Reg, DummyLoc, DummyLoc) ||
3440  Parser.parseEOL("unexpected tokens"))
3441  return addErrorSuffix(" in '.cv_fpo_setframe' directive");
3442  return getTargetStreamer().emitFPOSetFrame(Reg, L);
3443 }
3444 
3445 // .cv_fpo_pushreg ebx
3446 bool X86AsmParser::parseDirectiveFPOPushReg(SMLoc L) {
3447  MCAsmParser &Parser = getParser();
3448  unsigned Reg;
3449  SMLoc DummyLoc;
3450  if (ParseRegister(Reg, DummyLoc, DummyLoc) ||
3451  Parser.parseEOL("unexpected tokens"))
3452  return addErrorSuffix(" in '.cv_fpo_pushreg' directive");
3453  return getTargetStreamer().emitFPOPushReg(Reg, L);
3454 }
3455 
3456 // .cv_fpo_stackalloc 20
3457 bool X86AsmParser::parseDirectiveFPOStackAlloc(SMLoc L) {
3458  MCAsmParser &Parser = getParser();
3459  int64_t Offset;
3460  if (Parser.parseIntToken(Offset, "expected offset") ||
3461  Parser.parseEOL("unexpected tokens"))
3462  return addErrorSuffix(" in '.cv_fpo_stackalloc' directive");
3463  return getTargetStreamer().emitFPOStackAlloc(Offset, L);
3464 }
3465 
3466 // .cv_fpo_stackalign 8
3467 bool X86AsmParser::parseDirectiveFPOStackAlign(SMLoc L) {
3468  MCAsmParser &Parser = getParser();
3469  int64_t Offset;
3470  if (Parser.parseIntToken(Offset, "expected offset") ||
3471  Parser.parseEOL("unexpected tokens"))
3472  return addErrorSuffix(" in '.cv_fpo_stackalign' directive");
3473  return getTargetStreamer().emitFPOStackAlign(Offset, L);
3474 }
3475 
3476 // .cv_fpo_endprologue
3477 bool X86AsmParser::parseDirectiveFPOEndPrologue(SMLoc L) {
3478  MCAsmParser &Parser = getParser();
3479  if (Parser.parseEOL("unexpected tokens"))
3480  return addErrorSuffix(" in '.cv_fpo_endprologue' directive");
3481  return getTargetStreamer().emitFPOEndPrologue(L);
3482 }
3483 
3484 // .cv_fpo_endproc
3485 bool X86AsmParser::parseDirectiveFPOEndProc(SMLoc L) {
3486  MCAsmParser &Parser = getParser();
3487  if (Parser.parseEOL("unexpected tokens"))
3488  return addErrorSuffix(" in '.cv_fpo_endproc' directive");
3489  return getTargetStreamer().emitFPOEndProc(L);
3490 }
3491 
3492 // Force static initialization.
3493 extern "C" void LLVMInitializeX86AsmParser() {
3496 }
3497 
3498 #define GET_REGISTER_MATCHER
3499 #define GET_MATCHER_IMPLEMENTATION
3500 #define GET_SUBTARGET_FEATURE_NAME
3501 #include "X86GenAsmMatcher.inc"
static const char * getSubtargetFeatureName(uint64_t Val)
Represents a range in source code.
Definition: SMLoc.h:48
Instances of this class represent a uniqued identifier for a section in the current translation unit...
Definition: MCSection.h:38
static bool checkScale(unsigned Scale, StringRef &ErrMsg)
LLVM_NODISCARD StringRef take_front(size_t N=1) const
Return a StringRef equal to &#39;this&#39; but with only the first N elements remaining.
Definition: StringRef.h:587
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:258
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
Definition: MCAsmMacro.h:110
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1562
unsigned getMemFrontendSize() const
Definition: X86Operand.h:197
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:249
bool isX86_64NonExtLowByteReg(unsigned reg)
Definition: X86BaseInfo.h:804
LLVM_NODISCARD bool endswith(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition: StringRef.h:267
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:319
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
SMRange getLocRange() const
getLocRange - Get the range between the first and last token of this operand.
Definition: X86Operand.h:93
bool isVariable() const
isVariable - Check if this is a variable symbol.
Definition: MCSymbol.h:293
SmallVectorImpl< AsmRewrite > * AsmRewrites
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
LLVM_NODISCARD bool equals_lower(StringRef RHS) const
equals_lower - Check for string equality, ignoring case.
Definition: StringRef.h:167
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:109
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
bool isKind(IdKind kind) const
Definition: MCAsmParser.h:65
MCTargetAsmParser - Generic interface to target specific assembly parsers.
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:256
LLVM_NODISCARD int compare(StringRef RHS) const
compare - Compare two strings; the result is -1, 0, or 1 if this string is lexicographically less tha...
Definition: StringRef.h:174
Target specific streamer interface.
Definition: MCStreamer.h:83
unsigned Reg
bool isNot(TokenKind K) const
Definition: MCAsmMacro.h:83
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:509
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Definition: MCAsmParser.cpp:33
static std::unique_ptr< X86Operand > CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc, unsigned Size=0, StringRef SymName=StringRef(), void *OpDecl=nullptr, unsigned FrontendSize=0)
Create an absolute memory operand.
Definition: X86Operand.h:566
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:955
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
bool parseIntToken(int64_t &V, const Twine &ErrMsg)
Definition: MCAsmParser.cpp:58
return AArch64::GPR64RegClass contains(Reg)
static ModuleSymbolTable::Symbol getSym(DataRefImpl &Symb)
StringRef getToken() const
Definition: X86Operand.h:148
amode Optimize addressing mode
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string...
Definition: MCAsmMacro.h:99
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
void LLVMInitializeX86AsmParser()
const FeatureBitset & getFeatureBits() const
unsigned getPrefix() const
Definition: X86Operand.h:163
bool isMemUnsized() const
Definition: X86Operand.h:281
SMLoc getEndLoc() const override
getEndLoc - Get the location of the last token of this operand.
Definition: X86Operand.h:89
LLVM_NODISCARD StringRef drop_front(size_t N=1) const
Return a StringRef equal to &#39;this&#39; but with the first N elements dropped.
Definition: StringRef.h:620
LLVM_NODISCARD size_t count(char C) const
Return the number of occurrences of C in the string.
Definition: StringRef.h:457
bool isImm() const override
isImm - Is this an immediate operand?
Definition: X86Operand.h:204
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
Target independent representation for an assembler token.
Definition: MCAsmMacro.h:21
LLVM_NODISCARD StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
Definition: StringRef.h:679
static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg, unsigned Scale, bool Is64BitMode, StringRef &ErrMsg)
}
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:578
bool isMem8() const
Definition: X86Operand.h:284
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
zlib-gnu style compression
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand...
static std::unique_ptr< X86Operand > CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc)
Definition: X86Operand.h:557
static bool startswith(StringRef Magic, const char(&S)[N])
Definition: Magic.cpp:29
virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse an arbitrary expression.
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
unsigned getReg() const override
Definition: X86Operand.h:158
RegisterMCAsmParser - Helper template for registering a target specific assembly parser, for use in the target machine initialization function.
.code16 (X86) / .code 16 (ARM)
Definition: MCDirectives.h:51
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:25
SMLoc getLoc() const
Definition: MCAsmLexer.cpp:27
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:457
LLVM_NODISCARD std::string upper() const
Convert the given ASCII string to uppercase.
Definition: StringRef.cpp:115
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
virtual void eatToEndOfStatement()=0
Skip to the end of the current statement, for error recovery.
auto count(R &&Range, const E &Element) -> typename std::iterator_traits< decltype(adl_begin(Range))>::difference_type
Wrapper function around std::count to count the number of times an element Element occurs in the give...
Definition: STLExtras.h:1251
static const X86MCExpr * create(int64_t RegNo, MCContext &Ctx)
Definition: X86MCExpr.h:36
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool isPrefix() const
Definition: X86Operand.h:444
bool isX86_64ExtendedReg(unsigned RegNo)
isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) register? e.g.
Definition: X86BaseInfo.h:770
virtual void addAliasForDirective(StringRef Directive, StringRef Alias)=0
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
const char * getPointer() const
Definition: SMLoc.h:34
virtual MCContext & getContext()=0
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
Streaming machine code generation interface.
Definition: MCStreamer.h:188
StringSwitch & Cases(StringLiteral S0, StringLiteral S1, T Value)
Definition: StringSwitch.h:88
unsigned const MachineRegisterInfo * MRI
X86Operand - Instances of this class represent a parsed X86 machine instruction.
Definition: X86Operand.h:31
MCTargetStreamer * getTargetStreamer()
Definition: MCStreamer.h:257
Container class for subtarget features.
SMLoc getEndLoc() const
Definition: MCAsmLexer.cpp:31
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
virtual bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse a primary expression.
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
const MCExpr * getImm() const
Definition: X86Operand.h:168
bool parseTokenLoc(SMLoc &Loc)
Definition: MCAsmParser.cpp:37
int64_t getIntVal() const
Definition: MCAsmMacro.h:115
unsigned getNumOperands() const
Definition: MCInst.h:181
static std::unique_ptr< X86Operand > CreateDXReg(SMLoc StartLoc, SMLoc EndLoc)
Definition: X86Operand.h:546
bool Error(SMLoc L, const Twine &Msg, SMRange Range=None)
Return an error at the location L, with the message Msg.
Definition: MCAsmParser.cpp:87
static const char * getRegisterName(unsigned RegNo)
virtual bool UseCodeAlign() const =0
Return true if a .align directive should use "optimized nops" to fill instead of 0s.
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:397
iterator erase(const_iterator CI)
Definition: SmallVector.h:438
size_t size() const
Definition: SmallVector.h:52
LLVM_NODISCARD char back() const
back - Get the last character in the string.
Definition: StringRef.h:141
void setLoc(SMLoc loc)
Definition: MCInst.h:176
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SMLoc getStartLoc() const override
getStartLoc - Get the location of the first token of this operand.
Definition: X86Operand.h:86
unsigned getX86SubSuperRegisterOrZero(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:478
void setFlags(unsigned F)
Definition: MCInst.h:173
MCStreamer & getStreamer()
Definition: MCStreamer.h:91
void setOpcode(unsigned Op)
Definition: MCInst.h:170
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
Definition: STLExtras.h:1166
bool isUndefined(bool SetUsed=true) const
isUndefined - Check if this symbol undefined (i.e., implicitly defined).
Definition: MCSymbol.h:256
static unsigned MatchRegisterName(StringRef Name)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:696
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1043
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:41
struct MemOp Mem
Definition: X86Operand.h:75
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:374
StringRef str()
Return a StringRef for the vector contents.
Definition: raw_ostream.h:534
X86 target streamer implementing x86-only assembly directives.
static bool isPrefix(const IndicesVector &Prefix, const IndicesVector &Longer)
Returns true if Prefix is a prefix of longer.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
bool is(TokenKind K) const
Definition: MCAsmMacro.h:82
Class for arbitrary precision integers.
Definition: APInt.h:69
bool isValid() const
Definition: SMLoc.h:29
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Base class for user error types.
Definition: Error.h:344
static std::unique_ptr< X86Operand > CreateToken(StringRef Str, SMLoc Loc)
Definition: X86Operand.h:524
VariableIdentifier Var
Definition: MCAsmParser.h:63
.code32 (X86) / .code 32 (ARM)
Definition: MCDirectives.h:52
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:36
static std::unique_ptr< X86Operand > CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc, bool AddressOf=false, SMLoc OffsetOfLoc=SMLoc(), StringRef SymName=StringRef(), void *OpDecl=nullptr)
Definition: X86Operand.h:533
.code64 (X86)
Definition: MCDirectives.h:53
LLVM_NODISCARD bool equals(StringRef RHS) const
equals - Check for string equality, this is more efficient than compare() when the relative ordering ...
Definition: StringRef.h:160
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
static unsigned getPrefixes(OperandVector &Operands)
Generic base class for all target subtargets.
virtual bool parseAbsoluteExpression(int64_t &Res)=0
Parse an expression which must evaluate to an absolute value.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:322
Target & getTheX86_32Target()
uint32_t Size
Definition: Profile.cpp:46
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:202
bool isDXReg() const
Definition: X86Operand.h:446
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:107
static std::unique_ptr< X86Operand > CreatePrefix(unsigned Prefixes, SMLoc StartLoc, SMLoc EndLoc)
Definition: X86Operand.h:551
LLVM_NODISCARD const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:122
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool TokError(const Twine &Msg, SMRange Range=None)
Report an error at the current lexer location.
Definition: MCAsmParser.cpp:83
const MCExpr * getVariableValue(bool SetUsed=true) const
getVariableValue - Get the value for variable symbols.
Definition: MCSymbol.h:298
LLVM_NODISCARD StringRef drop_back(size_t N=1) const
Return a StringRef equal to &#39;this&#39; but with the last N elements dropped.
Definition: StringRef.h:628
bool parseEOL(const Twine &ErrMsg)
Definition: MCAsmParser.cpp:42
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
bool parseOptionalToken(AsmToken::TokenKind T)
Attempt to parse and consume token, returning true on success.
Definition: MCAsmParser.cpp:66
bool isReg() const override
isReg - Is this a register operand?
Definition: X86Operand.h:445
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
virtual bool parseIdentifier(StringRef &Res)=0
Parse an identifier or string (as a quoted identifier) and set Res to the identifier contents...
Represents a location in source code.
Definition: SMLoc.h:23
unsigned getOpcode() const
Definition: MCInst.h:171
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:392
Target & getTheX86_64Target()
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:163
bool isMem() const override
isMem - Is this a memory operand?
Definition: X86Operand.h:280