LLVM  9.0.0svn
X86CallLowering.cpp
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1 //===- llvm/lib/Target/X86/X86CallLowering.cpp - Call lowering ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86CallLowering.h"
16 #include "X86CallingConv.h"
17 #include "X86ISelLowering.h"
18 #include "X86InstrInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/CodeGen/Analysis.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/Value.h"
42 #include "llvm/MC/MCRegisterInfo.h"
45 #include <cassert>
46 #include <cstdint>
47 
48 using namespace llvm;
49 
51  : CallLowering(&TLI) {}
52 
53 bool X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
54  SmallVectorImpl<ArgInfo> &SplitArgs,
55  const DataLayout &DL,
57  SplitArgTy PerformArgSplit) const {
58  const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
59  LLVMContext &Context = OrigArg.Ty->getContext();
60 
61  SmallVector<EVT, 4> SplitVTs;
63  ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
64 
65  if (OrigArg.Ty->isVoidTy())
66  return true;
67 
68  EVT VT = SplitVTs[0];
69  unsigned NumParts = TLI.getNumRegisters(Context, VT);
70 
71  if (NumParts == 1) {
72  // replace the original type ( pointer -> GPR ).
73  SplitArgs.emplace_back(OrigArg.Reg, VT.getTypeForEVT(Context),
74  OrigArg.Flags, OrigArg.IsFixed);
75  return true;
76  }
77 
78  SmallVector<unsigned, 8> SplitRegs;
79 
80  EVT PartVT = TLI.getRegisterType(Context, VT);
81  Type *PartTy = PartVT.getTypeForEVT(Context);
82 
83  for (unsigned i = 0; i < NumParts; ++i) {
84  ArgInfo Info =
86  PartTy, OrigArg.Flags};
87  SplitArgs.push_back(Info);
88  SplitRegs.push_back(Info.Reg);
89  }
90 
91  PerformArgSplit(SplitRegs);
92  return true;
93 }
94 
95 namespace {
96 
97 struct OutgoingValueHandler : public CallLowering::ValueHandler {
98  OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
99  MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
100  : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
101  DL(MIRBuilder.getMF().getDataLayout()),
102  STI(MIRBuilder.getMF().getSubtarget<X86Subtarget>()) {}
103 
104  unsigned getStackAddress(uint64_t Size, int64_t Offset,
105  MachinePointerInfo &MPO) override {
106  LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
107  LLT SType = LLT::scalar(DL.getPointerSizeInBits(0));
108  unsigned SPReg = MRI.createGenericVirtualRegister(p0);
109  MIRBuilder.buildCopy(SPReg, STI.getRegisterInfo()->getStackRegister());
110 
111  unsigned OffsetReg = MRI.createGenericVirtualRegister(SType);
112  MIRBuilder.buildConstant(OffsetReg, Offset);
113 
114  unsigned AddrReg = MRI.createGenericVirtualRegister(p0);
115  MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
116 
117  MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
118  return AddrReg;
119  }
120 
121  void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
122  CCValAssign &VA) override {
123  MIB.addUse(PhysReg, RegState::Implicit);
124 
125  unsigned ExtReg;
126  // If we are copying the value to a physical register with the
127  // size larger than the size of the value itself - build AnyExt
128  // to the size of the register first and only then do the copy.
129  // The example of that would be copying from s32 to xmm0, for which
130  // case ValVT == LocVT == MVT::f32. If LocSize and ValSize are not equal
131  // we expect normal extendRegister mechanism to work.
132  unsigned PhysRegSize =
133  MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
134  unsigned ValSize = VA.getValVT().getSizeInBits();
135  unsigned LocSize = VA.getLocVT().getSizeInBits();
136  if (PhysRegSize > ValSize && LocSize == ValSize) {
137  assert((PhysRegSize == 128 || PhysRegSize == 80) && "We expect that to be 128 bit");
138  auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg);
139  ExtReg = MIB->getOperand(0).getReg();
140  } else
141  ExtReg = extendRegister(ValVReg, VA);
142 
143  MIRBuilder.buildCopy(PhysReg, ExtReg);
144  }
145 
146  void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
147  MachinePointerInfo &MPO, CCValAssign &VA) override {
148  unsigned ExtReg = extendRegister(ValVReg, VA);
149  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
151  /* Alignment */ 1);
152  MIRBuilder.buildStore(ExtReg, Addr, *MMO);
153  }
154 
155  bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
156  CCValAssign::LocInfo LocInfo,
157  const CallLowering::ArgInfo &Info, CCState &State) override {
158  bool Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State);
159  StackSize = State.getNextStackOffset();
160 
161  static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2,
162  X86::XMM3, X86::XMM4, X86::XMM5,
163  X86::XMM6, X86::XMM7};
164  if (!Info.IsFixed)
165  NumXMMRegs = State.getFirstUnallocated(XMMArgRegs);
166 
167  return Res;
168  }
169 
170  uint64_t getStackSize() { return StackSize; }
171  uint64_t getNumXmmRegs() { return NumXMMRegs; }
172 
173 protected:
174  MachineInstrBuilder &MIB;
175  uint64_t StackSize = 0;
176  const DataLayout &DL;
177  const X86Subtarget &STI;
178  unsigned NumXMMRegs = 0;
179 };
180 
181 } // end anonymous namespace
182 
184  MachineIRBuilder &MIRBuilder, const Value *Val,
185  ArrayRef<unsigned> VRegs) const {
186  assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
187  "Return value without a vreg");
188  auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0);
189 
190  if (!VRegs.empty()) {
191  MachineFunction &MF = MIRBuilder.getMF();
192  const Function &F = MF.getFunction();
193  MachineRegisterInfo &MRI = MF.getRegInfo();
194  auto &DL = MF.getDataLayout();
195  LLVMContext &Ctx = Val->getType()->getContext();
196  const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
197 
198  SmallVector<EVT, 4> SplitEVTs;
199  ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
200  assert(VRegs.size() == SplitEVTs.size() &&
201  "For each split Type there should be exactly one VReg.");
202 
203  SmallVector<ArgInfo, 8> SplitArgs;
204  for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
205  ArgInfo CurArgInfo = ArgInfo{VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx)};
206  setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
207  if (!splitToValueTypes(CurArgInfo, SplitArgs, DL, MRI,
208  [&](ArrayRef<unsigned> Regs) {
209  MIRBuilder.buildUnmerge(Regs, VRegs[i]);
210  }))
211  return false;
212  }
213 
214  OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86);
215  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
216  return false;
217  }
218 
219  MIRBuilder.insertInstr(MIB);
220  return true;
221 }
222 
223 namespace {
224 
225 struct IncomingValueHandler : public CallLowering::ValueHandler {
226  IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
227  CCAssignFn *AssignFn)
228  : ValueHandler(MIRBuilder, MRI, AssignFn),
229  DL(MIRBuilder.getMF().getDataLayout()) {}
230 
231  bool isArgumentHandler() const override { return true; }
232 
233  unsigned getStackAddress(uint64_t Size, int64_t Offset,
234  MachinePointerInfo &MPO) override {
235  auto &MFI = MIRBuilder.getMF().getFrameInfo();
236  int FI = MFI.CreateFixedObject(Size, Offset, true);
237  MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
238 
239  unsigned AddrReg = MRI.createGenericVirtualRegister(
241  MIRBuilder.buildFrameIndex(AddrReg, FI);
242  return AddrReg;
243  }
244 
245  void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
246  MachinePointerInfo &MPO, CCValAssign &VA) override {
247  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
249  1);
250  MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
251  }
252 
253  void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
254  CCValAssign &VA) override {
255  markPhysRegUsed(PhysReg);
256 
257  switch (VA.getLocInfo()) {
258  default: {
259  // If we are copying the value from a physical register with the
260  // size larger than the size of the value itself - build the copy
261  // of the phys reg first and then build the truncation of that copy.
262  // The example of that would be copying from xmm0 to s32, for which
263  // case ValVT == LocVT == MVT::f32. If LocSize and ValSize are not equal
264  // we expect this to be handled in SExt/ZExt/AExt case.
265  unsigned PhysRegSize =
266  MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
267  unsigned ValSize = VA.getValVT().getSizeInBits();
268  unsigned LocSize = VA.getLocVT().getSizeInBits();
269  if (PhysRegSize > ValSize && LocSize == ValSize) {
270  auto Copy = MIRBuilder.buildCopy(LLT::scalar(PhysRegSize), PhysReg);
271  MIRBuilder.buildTrunc(ValVReg, Copy);
272  return;
273  }
274 
275  MIRBuilder.buildCopy(ValVReg, PhysReg);
276  break;
277  }
278  case CCValAssign::LocInfo::SExt:
279  case CCValAssign::LocInfo::ZExt:
280  case CCValAssign::LocInfo::AExt: {
281  auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
282  MIRBuilder.buildTrunc(ValVReg, Copy);
283  break;
284  }
285  }
286  }
287 
288  /// How the physical register gets marked varies between formal
289  /// parameters (it's a basic-block live-in), and a call instruction
290  /// (it's an implicit-def of the BL).
291  virtual void markPhysRegUsed(unsigned PhysReg) = 0;
292 
293 protected:
294  const DataLayout &DL;
295 };
296 
297 struct FormalArgHandler : public IncomingValueHandler {
298  FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
299  CCAssignFn *AssignFn)
300  : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
301 
302  void markPhysRegUsed(unsigned PhysReg) override {
303  MIRBuilder.getMBB().addLiveIn(PhysReg);
304  }
305 };
306 
307 struct CallReturnHandler : public IncomingValueHandler {
308  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
309  CCAssignFn *AssignFn, MachineInstrBuilder &MIB)
310  : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
311 
312  void markPhysRegUsed(unsigned PhysReg) override {
313  MIB.addDef(PhysReg, RegState::Implicit);
314  }
315 
316 protected:
317  MachineInstrBuilder &MIB;
318 };
319 
320 } // end anonymous namespace
321 
323  const Function &F,
324  ArrayRef<unsigned> VRegs) const {
325  if (F.arg_empty())
326  return true;
327 
328  // TODO: handle variadic function
329  if (F.isVarArg())
330  return false;
331 
332  MachineFunction &MF = MIRBuilder.getMF();
333  MachineRegisterInfo &MRI = MF.getRegInfo();
334  auto DL = MF.getDataLayout();
335 
336  SmallVector<ArgInfo, 8> SplitArgs;
337  unsigned Idx = 0;
338  for (auto &Arg : F.args()) {
339 
340  // TODO: handle not simple cases.
341  if (Arg.hasAttribute(Attribute::ByVal) ||
342  Arg.hasAttribute(Attribute::InReg) ||
343  Arg.hasAttribute(Attribute::StructRet) ||
344  Arg.hasAttribute(Attribute::SwiftSelf) ||
345  Arg.hasAttribute(Attribute::SwiftError) ||
346  Arg.hasAttribute(Attribute::Nest))
347  return false;
348 
349  ArgInfo OrigArg(VRegs[Idx], Arg.getType());
350  setArgFlags(OrigArg, Idx + AttributeList::FirstArgIndex, DL, F);
351  if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
352  [&](ArrayRef<unsigned> Regs) {
353  MIRBuilder.buildMerge(VRegs[Idx], Regs);
354  }))
355  return false;
356  Idx++;
357  }
358 
359  MachineBasicBlock &MBB = MIRBuilder.getMBB();
360  if (!MBB.empty())
361  MIRBuilder.setInstr(*MBB.begin());
362 
363  FormalArgHandler Handler(MIRBuilder, MRI, CC_X86);
364  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
365  return false;
366 
367  // Move back to the end of the basic block.
368  MIRBuilder.setMBB(MBB);
369 
370  return true;
371 }
372 
374  CallingConv::ID CallConv,
375  const MachineOperand &Callee,
376  const ArgInfo &OrigRet,
377  ArrayRef<ArgInfo> OrigArgs) const {
378  MachineFunction &MF = MIRBuilder.getMF();
379  const Function &F = MF.getFunction();
380  MachineRegisterInfo &MRI = MF.getRegInfo();
381  auto &DL = F.getParent()->getDataLayout();
382  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
383  const TargetInstrInfo &TII = *STI.getInstrInfo();
384  auto TRI = STI.getRegisterInfo();
385 
386  // Handle only Linux C, X86_64_SysV calling conventions for now.
387  if (!STI.isTargetLinux() ||
388  !(CallConv == CallingConv::C || CallConv == CallingConv::X86_64_SysV))
389  return false;
390 
391  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
392  auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown);
393 
394  // Create a temporarily-floating call instruction so we can add the implicit
395  // uses of arg registers.
396  bool Is64Bit = STI.is64Bit();
397  unsigned CallOpc = Callee.isReg()
398  ? (Is64Bit ? X86::CALL64r : X86::CALL32r)
399  : (Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32);
400 
401  auto MIB = MIRBuilder.buildInstrNoInsert(CallOpc).add(Callee).addRegMask(
402  TRI->getCallPreservedMask(MF, CallConv));
403 
404  SmallVector<ArgInfo, 8> SplitArgs;
405  for (const auto &OrigArg : OrigArgs) {
406 
407  // TODO: handle not simple cases.
408  if (OrigArg.Flags.isByVal())
409  return false;
410 
411  if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
412  [&](ArrayRef<unsigned> Regs) {
413  MIRBuilder.buildUnmerge(Regs, OrigArg.Reg);
414  }))
415  return false;
416  }
417  // Do the actual argument marshalling.
418  OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, CC_X86);
419  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
420  return false;
421 
422  bool IsFixed = OrigArgs.empty() ? true : OrigArgs.back().IsFixed;
423  if (STI.is64Bit() && !IsFixed && !STI.isCallingConvWin64(CallConv)) {
424  // From AMD64 ABI document:
425  // For calls that may call functions that use varargs or stdargs
426  // (prototype-less calls or calls to functions containing ellipsis (...) in
427  // the declaration) %al is used as hidden argument to specify the number
428  // of SSE registers used. The contents of %al do not need to match exactly
429  // the number of registers, but must be an ubound on the number of SSE
430  // registers used and is in the range 0 - 8 inclusive.
431 
432  MIRBuilder.buildInstr(X86::MOV8ri)
433  .addDef(X86::AL)
434  .addImm(Handler.getNumXmmRegs());
436  }
437 
438  // Now we can add the actual call instruction to the correct basic block.
439  MIRBuilder.insertInstr(MIB);
440 
441  // If Callee is a reg, since it is used by a target specific
442  // instruction, it must have a register class matching the
443  // constraint of that instruction.
444  if (Callee.isReg())
446  MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
447  *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Callee, 0));
448 
449  // Finally we can copy the returned value back into its virtual-register. In
450  // symmetry with the arguments, the physical register must be an
451  // implicit-define of the call instruction.
452 
453  if (OrigRet.Reg) {
454  SplitArgs.clear();
455  SmallVector<unsigned, 8> NewRegs;
456 
457  if (!splitToValueTypes(OrigRet, SplitArgs, DL, MRI,
458  [&](ArrayRef<unsigned> Regs) {
459  NewRegs.assign(Regs.begin(), Regs.end());
460  }))
461  return false;
462 
463  CallReturnHandler Handler(MIRBuilder, MRI, RetCC_X86, MIB);
464  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
465  return false;
466 
467  if (!NewRegs.empty())
468  MIRBuilder.buildMerge(OrigRet.Reg, NewRegs);
469  }
470 
471  CallSeqStart.addImm(Handler.getStackSize())
472  .addImm(0 /* see getFrameTotalSize */)
473  .addImm(0 /* see getFrameAdjustment */);
474 
475  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
476  MIRBuilder.buildInstr(AdjStackUp)
477  .addImm(Handler.getStackSize())
478  .addImm(0 /* NumBytesForCalleeToPop */);
479 
480  return true;
481 }
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:176
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set, or Regs.size() if they are all allocated.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:536
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:645
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ...
LLVMContext & Context
MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0, unsigned Op1)
Build and insert Res = G_GEP Op0, Op1.
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO, unsigned OpIdx)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:40
This class represents lattice values for constants.
Definition: AllocatorList.h:23
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
iterator begin() const
Definition: ArrayRef.h:136
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:495
unsigned getReg() const
getReg - Returns the register number.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1045
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< unsigned > VRegs) const override
This hook must be implemented to lower the incoming (formal) arguments, described by Args...
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:388
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
unsigned const TargetRegisterInfo * TRI
F(f)
block Block Frequency true
bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, const MachineOperand &Callee, const ArgInfo &OrigRet, ArrayRef< ArgInfo > OrigArgs) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
bool CC_X86(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:129
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
MachineInstrBuilder buildStore(unsigned Val, unsigned Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
bool handleAssignments(MachineIRBuilder &MIRBuilder, ArrayRef< ArgInfo > Args, ValueHandler &Handler) const
Invoke Handler::assignArg on each of the given Args and then use Callback to move them to the assigne...
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:369
const HexagonInstrInfo * TII
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:205
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
This file contains the simple types necessary to represent the attributes associated with functions a...
unsigned getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LocInfo getLocInfo() const
unsigned getSizeInBits() const
void assign(size_type NumElts, const T &Elt)
Definition: SmallVector.h:416
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
bool arg_empty() const
Definition: Function.h:704
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
virtual const TargetInstrInfo * getInstrInfo() const
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:119
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
TargetInstrInfo - Interface to description of machine instruction set.
bool isVoidTy() const
Return true if this is &#39;void&#39;.
Definition: Type.h:140
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const TargetRegisterInfo * getTargetRegisterInfo() const
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
Helper class to build MachineInstr.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
Extended Value Type.
Definition: ValueTypes.h:33
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
Argument handling is mostly uniform between the four places that make these decisions: function forma...
Definition: CallLowering.h:64
This class contains a discriminated union of information about pointers in memory operands...
MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
The memory access writes data.
const X86RegisterInfo * getRegisterInfo() const override
Definition: X86Subtarget.h:505
unsigned createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< unsigned > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
CCState - This class holds information needed while lowering arguments and return values...
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
CCValAssign - Represent assignment of one arg/retval to a location.
iterator end() const
Definition: ArrayRef.h:137
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
bool RetCC_X86(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
const Function & getFunction() const
Return the LLVM function that this machine code represents.
This file declares the MachineIRBuilder class.
This file describes how to lower LLVM calls to machine code calls.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:143
The memory access always returns the same value (or traps).
uint32_t Size
Definition: Profile.cpp:46
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< unsigned > VRegs) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
Return the number of registers that this ValueType will eventually require.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:565
LLVM Value Representation.
Definition: Value.h:72
bool isTargetLinux() const
Definition: X86Subtarget.h:752
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:803
MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
X86CallLowering(const X86TargetLowering &TLI)
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
iterator_range< arg_iterator > args()
Definition: Function.h:694
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143