LLVM  10.0.0svn
X86CallLowering.cpp
Go to the documentation of this file.
1 //===- llvm/lib/Target/X86/X86CallLowering.cpp - Call lowering ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86CallLowering.h"
16 #include "X86CallingConv.h"
17 #include "X86ISelLowering.h"
18 #include "X86InstrInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/CodeGen/Analysis.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/Value.h"
42 #include "llvm/MC/MCRegisterInfo.h"
45 #include <cassert>
46 #include <cstdint>
47 
48 using namespace llvm;
49 
51  : CallLowering(&TLI) {}
52 
53 bool X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
54  SmallVectorImpl<ArgInfo> &SplitArgs,
55  const DataLayout &DL,
57  SplitArgTy PerformArgSplit) const {
58  const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
59  LLVMContext &Context = OrigArg.Ty->getContext();
60 
61  SmallVector<EVT, 4> SplitVTs;
63  ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
64  assert(OrigArg.Regs.size() == 1 && "Can't handle multple regs yet");
65 
66  if (OrigArg.Ty->isVoidTy())
67  return true;
68 
69  EVT VT = SplitVTs[0];
70  unsigned NumParts = TLI.getNumRegisters(Context, VT);
71 
72  if (NumParts == 1) {
73  // replace the original type ( pointer -> GPR ).
74  SplitArgs.emplace_back(OrigArg.Regs[0], VT.getTypeForEVT(Context),
75  OrigArg.Flags, OrigArg.IsFixed);
76  return true;
77  }
78 
79  SmallVector<Register, 8> SplitRegs;
80 
81  EVT PartVT = TLI.getRegisterType(Context, VT);
82  Type *PartTy = PartVT.getTypeForEVT(Context);
83 
84  for (unsigned i = 0; i < NumParts; ++i) {
85  ArgInfo Info =
87  PartTy, OrigArg.Flags};
88  SplitArgs.push_back(Info);
89  SplitRegs.push_back(Info.Regs[0]);
90  }
91 
92  PerformArgSplit(SplitRegs);
93  return true;
94 }
95 
96 namespace {
97 
98 struct OutgoingValueHandler : public CallLowering::ValueHandler {
99  OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
100  MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
101  : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
102  DL(MIRBuilder.getMF().getDataLayout()),
103  STI(MIRBuilder.getMF().getSubtarget<X86Subtarget>()) {}
104 
105  bool isIncomingArgumentHandler() const override { return false; }
106 
107  Register getStackAddress(uint64_t Size, int64_t Offset,
108  MachinePointerInfo &MPO) override {
109  LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
110  LLT SType = LLT::scalar(DL.getPointerSizeInBits(0));
111  Register SPReg = MRI.createGenericVirtualRegister(p0);
112  MIRBuilder.buildCopy(SPReg, STI.getRegisterInfo()->getStackRegister());
113 
114  Register OffsetReg = MRI.createGenericVirtualRegister(SType);
115  MIRBuilder.buildConstant(OffsetReg, Offset);
116 
117  Register AddrReg = MRI.createGenericVirtualRegister(p0);
118  MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
119 
120  MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
121  return AddrReg;
122  }
123 
124  void assignValueToReg(Register ValVReg, Register PhysReg,
125  CCValAssign &VA) override {
126  MIB.addUse(PhysReg, RegState::Implicit);
127 
128  Register ExtReg;
129  // If we are copying the value to a physical register with the
130  // size larger than the size of the value itself - build AnyExt
131  // to the size of the register first and only then do the copy.
132  // The example of that would be copying from s32 to xmm0, for which
133  // case ValVT == LocVT == MVT::f32. If LocSize and ValSize are not equal
134  // we expect normal extendRegister mechanism to work.
135  unsigned PhysRegSize =
136  MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
137  unsigned ValSize = VA.getValVT().getSizeInBits();
138  unsigned LocSize = VA.getLocVT().getSizeInBits();
139  if (PhysRegSize > ValSize && LocSize == ValSize) {
140  assert((PhysRegSize == 128 || PhysRegSize == 80) && "We expect that to be 128 bit");
141  auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg);
142  ExtReg = MIB->getOperand(0).getReg();
143  } else
144  ExtReg = extendRegister(ValVReg, VA);
145 
146  MIRBuilder.buildCopy(PhysReg, ExtReg);
147  }
148 
149  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
150  MachinePointerInfo &MPO, CCValAssign &VA) override {
151  Register ExtReg = extendRegister(ValVReg, VA);
152  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
154  /* Alignment */ 1);
155  MIRBuilder.buildStore(ExtReg, Addr, *MMO);
156  }
157 
158  bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
159  CCValAssign::LocInfo LocInfo,
161  CCState &State) override {
162  bool Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
163  StackSize = State.getNextStackOffset();
164 
165  static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2,
166  X86::XMM3, X86::XMM4, X86::XMM5,
167  X86::XMM6, X86::XMM7};
168  if (!Info.IsFixed)
169  NumXMMRegs = State.getFirstUnallocated(XMMArgRegs);
170 
171  return Res;
172  }
173 
174  uint64_t getStackSize() { return StackSize; }
175  uint64_t getNumXmmRegs() { return NumXMMRegs; }
176 
177 protected:
178  MachineInstrBuilder &MIB;
179  uint64_t StackSize = 0;
180  const DataLayout &DL;
181  const X86Subtarget &STI;
182  unsigned NumXMMRegs = 0;
183 };
184 
185 } // end anonymous namespace
186 
188  MachineIRBuilder &MIRBuilder, const Value *Val,
189  ArrayRef<Register> VRegs) const {
190  assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
191  "Return value without a vreg");
192  auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0);
193 
194  if (!VRegs.empty()) {
195  MachineFunction &MF = MIRBuilder.getMF();
196  const Function &F = MF.getFunction();
197  MachineRegisterInfo &MRI = MF.getRegInfo();
198  auto &DL = MF.getDataLayout();
199  LLVMContext &Ctx = Val->getType()->getContext();
200  const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
201 
202  SmallVector<EVT, 4> SplitEVTs;
203  ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
204  assert(VRegs.size() == SplitEVTs.size() &&
205  "For each split Type there should be exactly one VReg.");
206 
207  SmallVector<ArgInfo, 8> SplitArgs;
208  for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
209  ArgInfo CurArgInfo = ArgInfo{VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx)};
210  setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
211  if (!splitToValueTypes(CurArgInfo, SplitArgs, DL, MRI,
212  [&](ArrayRef<Register> Regs) {
213  MIRBuilder.buildUnmerge(Regs, VRegs[i]);
214  }))
215  return false;
216  }
217 
218  OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86);
219  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
220  return false;
221  }
222 
223  MIRBuilder.insertInstr(MIB);
224  return true;
225 }
226 
227 namespace {
228 
229 struct IncomingValueHandler : public CallLowering::ValueHandler {
230  IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
231  CCAssignFn *AssignFn)
232  : ValueHandler(MIRBuilder, MRI, AssignFn),
233  DL(MIRBuilder.getMF().getDataLayout()) {}
234 
235  bool isIncomingArgumentHandler() const override { return true; }
236 
237  Register getStackAddress(uint64_t Size, int64_t Offset,
238  MachinePointerInfo &MPO) override {
239  auto &MFI = MIRBuilder.getMF().getFrameInfo();
240  int FI = MFI.CreateFixedObject(Size, Offset, true);
241  MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
242 
245  MIRBuilder.buildFrameIndex(AddrReg, FI);
246  return AddrReg;
247  }
248 
249  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
250  MachinePointerInfo &MPO, CCValAssign &VA) override {
251  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
253  1);
254  MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
255  }
256 
257  void assignValueToReg(Register ValVReg, Register PhysReg,
258  CCValAssign &VA) override {
259  markPhysRegUsed(PhysReg);
260 
261  switch (VA.getLocInfo()) {
262  default: {
263  // If we are copying the value from a physical register with the
264  // size larger than the size of the value itself - build the copy
265  // of the phys reg first and then build the truncation of that copy.
266  // The example of that would be copying from xmm0 to s32, for which
267  // case ValVT == LocVT == MVT::f32. If LocSize and ValSize are not equal
268  // we expect this to be handled in SExt/ZExt/AExt case.
269  unsigned PhysRegSize =
270  MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
271  unsigned ValSize = VA.getValVT().getSizeInBits();
272  unsigned LocSize = VA.getLocVT().getSizeInBits();
273  if (PhysRegSize > ValSize && LocSize == ValSize) {
274  auto Copy = MIRBuilder.buildCopy(LLT::scalar(PhysRegSize), PhysReg);
275  MIRBuilder.buildTrunc(ValVReg, Copy);
276  return;
277  }
278 
279  MIRBuilder.buildCopy(ValVReg, PhysReg);
280  break;
281  }
282  case CCValAssign::LocInfo::SExt:
283  case CCValAssign::LocInfo::ZExt:
284  case CCValAssign::LocInfo::AExt: {
285  auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
286  MIRBuilder.buildTrunc(ValVReg, Copy);
287  break;
288  }
289  }
290  }
291 
292  /// How the physical register gets marked varies between formal
293  /// parameters (it's a basic-block live-in), and a call instruction
294  /// (it's an implicit-def of the BL).
295  virtual void markPhysRegUsed(unsigned PhysReg) = 0;
296 
297 protected:
298  const DataLayout &DL;
299 };
300 
301 struct FormalArgHandler : public IncomingValueHandler {
302  FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
303  CCAssignFn *AssignFn)
304  : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
305 
306  void markPhysRegUsed(unsigned PhysReg) override {
307  MIRBuilder.getMRI()->addLiveIn(PhysReg);
308  MIRBuilder.getMBB().addLiveIn(PhysReg);
309  }
310 };
311 
312 struct CallReturnHandler : public IncomingValueHandler {
313  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
314  CCAssignFn *AssignFn, MachineInstrBuilder &MIB)
315  : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
316 
317  void markPhysRegUsed(unsigned PhysReg) override {
318  MIB.addDef(PhysReg, RegState::Implicit);
319  }
320 
321 protected:
322  MachineInstrBuilder &MIB;
323 };
324 
325 } // end anonymous namespace
326 
328  MachineIRBuilder &MIRBuilder, const Function &F,
329  ArrayRef<ArrayRef<Register>> VRegs) const {
330  if (F.arg_empty())
331  return true;
332 
333  // TODO: handle variadic function
334  if (F.isVarArg())
335  return false;
336 
337  MachineFunction &MF = MIRBuilder.getMF();
338  MachineRegisterInfo &MRI = MF.getRegInfo();
339  auto DL = MF.getDataLayout();
340 
341  SmallVector<ArgInfo, 8> SplitArgs;
342  unsigned Idx = 0;
343  for (auto &Arg : F.args()) {
344 
345  // TODO: handle not simple cases.
346  if (Arg.hasAttribute(Attribute::ByVal) ||
347  Arg.hasAttribute(Attribute::InReg) ||
348  Arg.hasAttribute(Attribute::StructRet) ||
349  Arg.hasAttribute(Attribute::SwiftSelf) ||
350  Arg.hasAttribute(Attribute::SwiftError) ||
351  Arg.hasAttribute(Attribute::Nest) || VRegs[Idx].size() > 1)
352  return false;
353 
354  ArgInfo OrigArg(VRegs[Idx], Arg.getType());
355  setArgFlags(OrigArg, Idx + AttributeList::FirstArgIndex, DL, F);
356  if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
357  [&](ArrayRef<Register> Regs) {
358  MIRBuilder.buildMerge(VRegs[Idx][0], Regs);
359  }))
360  return false;
361  Idx++;
362  }
363 
364  MachineBasicBlock &MBB = MIRBuilder.getMBB();
365  if (!MBB.empty())
366  MIRBuilder.setInstr(*MBB.begin());
367 
368  FormalArgHandler Handler(MIRBuilder, MRI, CC_X86);
369  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
370  return false;
371 
372  // Move back to the end of the basic block.
373  MIRBuilder.setMBB(MBB);
374 
375  return true;
376 }
377 
379  CallLoweringInfo &Info) const {
380  MachineFunction &MF = MIRBuilder.getMF();
381  const Function &F = MF.getFunction();
382  MachineRegisterInfo &MRI = MF.getRegInfo();
383  auto &DL = F.getParent()->getDataLayout();
384  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
385  const TargetInstrInfo &TII = *STI.getInstrInfo();
386  auto TRI = STI.getRegisterInfo();
387 
388  // Handle only Linux C, X86_64_SysV calling conventions for now.
389  if (!STI.isTargetLinux() || !(Info.CallConv == CallingConv::C ||
391  return false;
392 
393  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
394  auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown);
395 
396  // Create a temporarily-floating call instruction so we can add the implicit
397  // uses of arg registers.
398  bool Is64Bit = STI.is64Bit();
399  unsigned CallOpc = Info.Callee.isReg()
400  ? (Is64Bit ? X86::CALL64r : X86::CALL32r)
401  : (Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32);
402 
403  auto MIB = MIRBuilder.buildInstrNoInsert(CallOpc)
404  .add(Info.Callee)
405  .addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
406 
407  SmallVector<ArgInfo, 8> SplitArgs;
408  for (const auto &OrigArg : Info.OrigArgs) {
409 
410  // TODO: handle not simple cases.
411  if (OrigArg.Flags[0].isByVal())
412  return false;
413 
414  if (OrigArg.Regs.size() > 1)
415  return false;
416 
417  if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
418  [&](ArrayRef<Register> Regs) {
419  MIRBuilder.buildUnmerge(Regs, OrigArg.Regs[0]);
420  }))
421  return false;
422  }
423  // Do the actual argument marshalling.
424  OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, CC_X86);
425  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
426  return false;
427 
428  bool IsFixed = Info.OrigArgs.empty() ? true : Info.OrigArgs.back().IsFixed;
429  if (STI.is64Bit() && !IsFixed && !STI.isCallingConvWin64(Info.CallConv)) {
430  // From AMD64 ABI document:
431  // For calls that may call functions that use varargs or stdargs
432  // (prototype-less calls or calls to functions containing ellipsis (...) in
433  // the declaration) %al is used as hidden argument to specify the number
434  // of SSE registers used. The contents of %al do not need to match exactly
435  // the number of registers, but must be an ubound on the number of SSE
436  // registers used and is in the range 0 - 8 inclusive.
437 
438  MIRBuilder.buildInstr(X86::MOV8ri)
439  .addDef(X86::AL)
440  .addImm(Handler.getNumXmmRegs());
442  }
443 
444  // Now we can add the actual call instruction to the correct basic block.
445  MIRBuilder.insertInstr(MIB);
446 
447  // If Callee is a reg, since it is used by a target specific
448  // instruction, it must have a register class matching the
449  // constraint of that instruction.
450  if (Info.Callee.isReg())
452  MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
453  *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
454  0));
455 
456  // Finally we can copy the returned value back into its virtual-register. In
457  // symmetry with the arguments, the physical register must be an
458  // implicit-define of the call instruction.
459 
460  if (!Info.OrigRet.Ty->isVoidTy()) {
461  if (Info.OrigRet.Regs.size() > 1)
462  return false;
463 
464  SplitArgs.clear();
465  SmallVector<Register, 8> NewRegs;
466 
467  if (!splitToValueTypes(Info.OrigRet, SplitArgs, DL, MRI,
468  [&](ArrayRef<Register> Regs) {
469  NewRegs.assign(Regs.begin(), Regs.end());
470  }))
471  return false;
472 
473  CallReturnHandler Handler(MIRBuilder, MRI, RetCC_X86, MIB);
474  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
475  return false;
476 
477  if (!NewRegs.empty())
478  MIRBuilder.buildMerge(Info.OrigRet.Regs[0], NewRegs);
479  }
480 
481  CallSeqStart.addImm(Handler.getStackSize())
482  .addImm(0 /* see getFrameTotalSize */)
483  .addImm(0 /* see getFrameAdjustment */);
484 
485  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
486  MIRBuilder.buildInstr(AdjStackUp)
487  .addImm(Handler.getStackSize())
488  .addImm(0 /* NumBytesForCalleeToPop */);
489 
490  return true;
491 }
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:176
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set, or Regs.size() if they are all allocated.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:548
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:641
MachineOperand Callee
Destination of the call.
Definition: CallLowering.h:77
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ...
LLVMContext & Context
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO, unsigned OpIdx)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:40
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:507
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
bool handleAssignments(MachineIRBuilder &MIRBuilder, SmallVectorImpl< ArgInfo > &Args, ValueHandler &Handler) const
Invoke Handler::assignArg on each of the given Args and then use Callback to move them to the assigne...
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1136
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:392
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
unsigned const TargetRegisterInfo * TRI
F(f)
block Block Frequency true
bool CC_X86(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
SmallVector< ISD::ArgFlagsTy, 4 > Flags
Definition: CallLowering.h:53
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:130
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:369
const HexagonInstrInfo * TII
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:264
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
This file contains the simple types necessary to represent the attributes associated with functions a...
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:148
unsigned getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LocInfo getLocInfo() const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
unsigned getSizeInBits() const
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:246
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs) const override
This hook behaves as the extended lowerReturn function, but for targets that do not support swifterro...
bool arg_empty() const
Definition: Function.h:734
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
void setReg(Register Reg)
Change the register this operand corresponds to.
virtual const TargetInstrInfo * getInstrInfo() const
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:119
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
TargetInstrInfo - Interface to description of machine instruction set.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
bool isVoidTy() const
Return true if this is &#39;void&#39;.
Definition: Type.h:141
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineRegisterInfo * getMRI()
Getter for MRI.
const TargetRegisterInfo * getTargetRegisterInfo() const
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
Helper class to build MachineInstr.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
MachineInstrBuilder buildGEP(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_GEP Op0, Op1.
Extended Value Type.
Definition: ValueTypes.h:33
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
Argument handling is mostly uniform between the four places that make these decisions: function forma...
Definition: CallLowering.h:112
This class contains a discriminated union of information about pointers in memory operands...
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
The memory access writes data.
SmallVector< ArgInfo, 8 > OrigArgs
List of descriptors of the arguments passed to the function.
Definition: CallLowering.h:83
const X86RegisterInfo * getRegisterInfo() const override
Definition: X86Subtarget.h:517
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
CCState - This class holds information needed while lowering arguments and return values...
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
CCValAssign - Represent assignment of one arg/retval to a location.
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
bool RetCC_X86(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
const Function & getFunction() const
Return the LLVM function that this machine code represents.
This file declares the MachineIRBuilder class.
This file describes how to lower LLVM calls to machine code calls.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
CallingConv::ID CallConv
Calling convention to be used for the call.
Definition: CallLowering.h:73
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
The memory access always returns the same value (or traps).
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
uint32_t Size
Definition: Profile.cpp:46
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
Return the number of registers that this ValueType will eventually require.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:575
LLVM Value Representation.
Definition: Value.h:74
bool isTargetLinux() const
Definition: X86Subtarget.h:766
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:813
X86CallLowering(const X86TargetLowering &TLI)
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
SmallVector< Register, 4 > Regs
Definition: CallLowering.h:47
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs...
Register getReg() const
getReg - Returns the register number.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
ArgInfo OrigRet
Descriptor for the return type of the function.
Definition: CallLowering.h:80
iterator_range< arg_iterator > args()
Definition: Function.h:724
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143