LLVM  10.0.0svn
X86CallLowering.cpp
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1 //===- llvm/lib/Target/X86/X86CallLowering.cpp - Call lowering ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86CallLowering.h"
16 #include "X86CallingConv.h"
17 #include "X86ISelLowering.h"
18 #include "X86InstrInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/CodeGen/Analysis.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/Value.h"
42 #include "llvm/MC/MCRegisterInfo.h"
45 #include <cassert>
46 #include <cstdint>
47 
48 using namespace llvm;
49 
51  : CallLowering(&TLI) {}
52 
53 bool X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
54  SmallVectorImpl<ArgInfo> &SplitArgs,
55  const DataLayout &DL,
57  SplitArgTy PerformArgSplit) const {
58  const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
59  LLVMContext &Context = OrigArg.Ty->getContext();
60 
61  SmallVector<EVT, 4> SplitVTs;
63  ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
64  assert(OrigArg.Regs.size() == 1 && "Can't handle multple regs yet");
65 
66  if (OrigArg.Ty->isVoidTy())
67  return true;
68 
69  EVT VT = SplitVTs[0];
70  unsigned NumParts = TLI.getNumRegisters(Context, VT);
71 
72  if (NumParts == 1) {
73  // replace the original type ( pointer -> GPR ).
74  SplitArgs.emplace_back(OrigArg.Regs[0], VT.getTypeForEVT(Context),
75  OrigArg.Flags, OrigArg.IsFixed);
76  return true;
77  }
78 
79  SmallVector<Register, 8> SplitRegs;
80 
81  EVT PartVT = TLI.getRegisterType(Context, VT);
82  Type *PartTy = PartVT.getTypeForEVT(Context);
83 
84  for (unsigned i = 0; i < NumParts; ++i) {
85  ArgInfo Info =
87  PartTy, OrigArg.Flags};
88  SplitArgs.push_back(Info);
89  SplitRegs.push_back(Info.Regs[0]);
90  }
91 
92  PerformArgSplit(SplitRegs);
93  return true;
94 }
95 
96 namespace {
97 
98 struct OutgoingValueHandler : public CallLowering::ValueHandler {
99  OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
100  MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
101  : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
102  DL(MIRBuilder.getMF().getDataLayout()),
103  STI(MIRBuilder.getMF().getSubtarget<X86Subtarget>()) {}
104 
105  Register getStackAddress(uint64_t Size, int64_t Offset,
106  MachinePointerInfo &MPO) override {
107  LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
108  LLT SType = LLT::scalar(DL.getPointerSizeInBits(0));
109  Register SPReg = MRI.createGenericVirtualRegister(p0);
110  MIRBuilder.buildCopy(SPReg, STI.getRegisterInfo()->getStackRegister());
111 
112  Register OffsetReg = MRI.createGenericVirtualRegister(SType);
113  MIRBuilder.buildConstant(OffsetReg, Offset);
114 
115  Register AddrReg = MRI.createGenericVirtualRegister(p0);
116  MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
117 
118  MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
119  return AddrReg;
120  }
121 
122  void assignValueToReg(Register ValVReg, Register PhysReg,
123  CCValAssign &VA) override {
124  MIB.addUse(PhysReg, RegState::Implicit);
125 
126  Register ExtReg;
127  // If we are copying the value to a physical register with the
128  // size larger than the size of the value itself - build AnyExt
129  // to the size of the register first and only then do the copy.
130  // The example of that would be copying from s32 to xmm0, for which
131  // case ValVT == LocVT == MVT::f32. If LocSize and ValSize are not equal
132  // we expect normal extendRegister mechanism to work.
133  unsigned PhysRegSize =
134  MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
135  unsigned ValSize = VA.getValVT().getSizeInBits();
136  unsigned LocSize = VA.getLocVT().getSizeInBits();
137  if (PhysRegSize > ValSize && LocSize == ValSize) {
138  assert((PhysRegSize == 128 || PhysRegSize == 80) && "We expect that to be 128 bit");
139  auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg);
140  ExtReg = MIB->getOperand(0).getReg();
141  } else
142  ExtReg = extendRegister(ValVReg, VA);
143 
144  MIRBuilder.buildCopy(PhysReg, ExtReg);
145  }
146 
147  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
148  MachinePointerInfo &MPO, CCValAssign &VA) override {
149  Register ExtReg = extendRegister(ValVReg, VA);
150  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
152  /* Alignment */ 1);
153  MIRBuilder.buildStore(ExtReg, Addr, *MMO);
154  }
155 
156  bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
157  CCValAssign::LocInfo LocInfo,
158  const CallLowering::ArgInfo &Info, CCState &State) override {
159  bool Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State);
160  StackSize = State.getNextStackOffset();
161 
162  static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2,
163  X86::XMM3, X86::XMM4, X86::XMM5,
164  X86::XMM6, X86::XMM7};
165  if (!Info.IsFixed)
166  NumXMMRegs = State.getFirstUnallocated(XMMArgRegs);
167 
168  return Res;
169  }
170 
171  uint64_t getStackSize() { return StackSize; }
172  uint64_t getNumXmmRegs() { return NumXMMRegs; }
173 
174 protected:
175  MachineInstrBuilder &MIB;
176  uint64_t StackSize = 0;
177  const DataLayout &DL;
178  const X86Subtarget &STI;
179  unsigned NumXMMRegs = 0;
180 };
181 
182 } // end anonymous namespace
183 
185  MachineIRBuilder &MIRBuilder, const Value *Val,
186  ArrayRef<Register> VRegs) const {
187  assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
188  "Return value without a vreg");
189  auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0);
190 
191  if (!VRegs.empty()) {
192  MachineFunction &MF = MIRBuilder.getMF();
193  const Function &F = MF.getFunction();
194  MachineRegisterInfo &MRI = MF.getRegInfo();
195  auto &DL = MF.getDataLayout();
196  LLVMContext &Ctx = Val->getType()->getContext();
197  const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
198 
199  SmallVector<EVT, 4> SplitEVTs;
200  ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
201  assert(VRegs.size() == SplitEVTs.size() &&
202  "For each split Type there should be exactly one VReg.");
203 
204  SmallVector<ArgInfo, 8> SplitArgs;
205  for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
206  ArgInfo CurArgInfo = ArgInfo{VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx)};
207  setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
208  if (!splitToValueTypes(CurArgInfo, SplitArgs, DL, MRI,
209  [&](ArrayRef<Register> Regs) {
210  MIRBuilder.buildUnmerge(Regs, VRegs[i]);
211  }))
212  return false;
213  }
214 
215  OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86);
216  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
217  return false;
218  }
219 
220  MIRBuilder.insertInstr(MIB);
221  return true;
222 }
223 
224 namespace {
225 
226 struct IncomingValueHandler : public CallLowering::ValueHandler {
227  IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
228  CCAssignFn *AssignFn)
229  : ValueHandler(MIRBuilder, MRI, AssignFn),
230  DL(MIRBuilder.getMF().getDataLayout()) {}
231 
232  bool isArgumentHandler() const override { return true; }
233 
234  Register getStackAddress(uint64_t Size, int64_t Offset,
235  MachinePointerInfo &MPO) override {
236  auto &MFI = MIRBuilder.getMF().getFrameInfo();
237  int FI = MFI.CreateFixedObject(Size, Offset, true);
238  MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
239 
240  unsigned AddrReg = MRI.createGenericVirtualRegister(
242  MIRBuilder.buildFrameIndex(AddrReg, FI);
243  return AddrReg;
244  }
245 
246  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
247  MachinePointerInfo &MPO, CCValAssign &VA) override {
248  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
250  1);
251  MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
252  }
253 
254  void assignValueToReg(Register ValVReg, Register PhysReg,
255  CCValAssign &VA) override {
256  markPhysRegUsed(PhysReg);
257 
258  switch (VA.getLocInfo()) {
259  default: {
260  // If we are copying the value from a physical register with the
261  // size larger than the size of the value itself - build the copy
262  // of the phys reg first and then build the truncation of that copy.
263  // The example of that would be copying from xmm0 to s32, for which
264  // case ValVT == LocVT == MVT::f32. If LocSize and ValSize are not equal
265  // we expect this to be handled in SExt/ZExt/AExt case.
266  unsigned PhysRegSize =
267  MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
268  unsigned ValSize = VA.getValVT().getSizeInBits();
269  unsigned LocSize = VA.getLocVT().getSizeInBits();
270  if (PhysRegSize > ValSize && LocSize == ValSize) {
271  auto Copy = MIRBuilder.buildCopy(LLT::scalar(PhysRegSize), PhysReg);
272  MIRBuilder.buildTrunc(ValVReg, Copy);
273  return;
274  }
275 
276  MIRBuilder.buildCopy(ValVReg, PhysReg);
277  break;
278  }
279  case CCValAssign::LocInfo::SExt:
280  case CCValAssign::LocInfo::ZExt:
281  case CCValAssign::LocInfo::AExt: {
282  auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
283  MIRBuilder.buildTrunc(ValVReg, Copy);
284  break;
285  }
286  }
287  }
288 
289  /// How the physical register gets marked varies between formal
290  /// parameters (it's a basic-block live-in), and a call instruction
291  /// (it's an implicit-def of the BL).
292  virtual void markPhysRegUsed(unsigned PhysReg) = 0;
293 
294 protected:
295  const DataLayout &DL;
296 };
297 
298 struct FormalArgHandler : public IncomingValueHandler {
299  FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
300  CCAssignFn *AssignFn)
301  : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
302 
303  void markPhysRegUsed(unsigned PhysReg) override {
304  MIRBuilder.getMBB().addLiveIn(PhysReg);
305  }
306 };
307 
308 struct CallReturnHandler : public IncomingValueHandler {
309  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
310  CCAssignFn *AssignFn, MachineInstrBuilder &MIB)
311  : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
312 
313  void markPhysRegUsed(unsigned PhysReg) override {
314  MIB.addDef(PhysReg, RegState::Implicit);
315  }
316 
317 protected:
318  MachineInstrBuilder &MIB;
319 };
320 
321 } // end anonymous namespace
322 
324  MachineIRBuilder &MIRBuilder, const Function &F,
325  ArrayRef<ArrayRef<Register>> VRegs) const {
326  if (F.arg_empty())
327  return true;
328 
329  // TODO: handle variadic function
330  if (F.isVarArg())
331  return false;
332 
333  MachineFunction &MF = MIRBuilder.getMF();
334  MachineRegisterInfo &MRI = MF.getRegInfo();
335  auto DL = MF.getDataLayout();
336 
337  SmallVector<ArgInfo, 8> SplitArgs;
338  unsigned Idx = 0;
339  for (auto &Arg : F.args()) {
340 
341  // TODO: handle not simple cases.
342  if (Arg.hasAttribute(Attribute::ByVal) ||
343  Arg.hasAttribute(Attribute::InReg) ||
344  Arg.hasAttribute(Attribute::StructRet) ||
345  Arg.hasAttribute(Attribute::SwiftSelf) ||
346  Arg.hasAttribute(Attribute::SwiftError) ||
347  Arg.hasAttribute(Attribute::Nest) || VRegs[Idx].size() > 1)
348  return false;
349 
350  ArgInfo OrigArg(VRegs[Idx], Arg.getType());
351  setArgFlags(OrigArg, Idx + AttributeList::FirstArgIndex, DL, F);
352  if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
353  [&](ArrayRef<Register> Regs) {
354  MIRBuilder.buildMerge(VRegs[Idx][0], Regs);
355  }))
356  return false;
357  Idx++;
358  }
359 
360  MachineBasicBlock &MBB = MIRBuilder.getMBB();
361  if (!MBB.empty())
362  MIRBuilder.setInstr(*MBB.begin());
363 
364  FormalArgHandler Handler(MIRBuilder, MRI, CC_X86);
365  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
366  return false;
367 
368  // Move back to the end of the basic block.
369  MIRBuilder.setMBB(MBB);
370 
371  return true;
372 }
373 
375  CallingConv::ID CallConv,
376  const MachineOperand &Callee,
377  const ArgInfo &OrigRet,
378  ArrayRef<ArgInfo> OrigArgs) const {
379  MachineFunction &MF = MIRBuilder.getMF();
380  const Function &F = MF.getFunction();
381  MachineRegisterInfo &MRI = MF.getRegInfo();
382  auto &DL = F.getParent()->getDataLayout();
383  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
384  const TargetInstrInfo &TII = *STI.getInstrInfo();
385  auto TRI = STI.getRegisterInfo();
386 
387  // Handle only Linux C, X86_64_SysV calling conventions for now.
388  if (!STI.isTargetLinux() ||
389  !(CallConv == CallingConv::C || CallConv == CallingConv::X86_64_SysV))
390  return false;
391 
392  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
393  auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown);
394 
395  // Create a temporarily-floating call instruction so we can add the implicit
396  // uses of arg registers.
397  bool Is64Bit = STI.is64Bit();
398  unsigned CallOpc = Callee.isReg()
399  ? (Is64Bit ? X86::CALL64r : X86::CALL32r)
400  : (Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32);
401 
402  auto MIB = MIRBuilder.buildInstrNoInsert(CallOpc).add(Callee).addRegMask(
403  TRI->getCallPreservedMask(MF, CallConv));
404 
405  SmallVector<ArgInfo, 8> SplitArgs;
406  for (const auto &OrigArg : OrigArgs) {
407 
408  // TODO: handle not simple cases.
409  if (OrigArg.Flags.isByVal())
410  return false;
411 
412  if (OrigArg.Regs.size() > 1)
413  return false;
414 
415  if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
416  [&](ArrayRef<Register> Regs) {
417  MIRBuilder.buildUnmerge(Regs, OrigArg.Regs[0]);
418  }))
419  return false;
420  }
421  // Do the actual argument marshalling.
422  OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, CC_X86);
423  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
424  return false;
425 
426  bool IsFixed = OrigArgs.empty() ? true : OrigArgs.back().IsFixed;
427  if (STI.is64Bit() && !IsFixed && !STI.isCallingConvWin64(CallConv)) {
428  // From AMD64 ABI document:
429  // For calls that may call functions that use varargs or stdargs
430  // (prototype-less calls or calls to functions containing ellipsis (...) in
431  // the declaration) %al is used as hidden argument to specify the number
432  // of SSE registers used. The contents of %al do not need to match exactly
433  // the number of registers, but must be an ubound on the number of SSE
434  // registers used and is in the range 0 - 8 inclusive.
435 
436  MIRBuilder.buildInstr(X86::MOV8ri)
437  .addDef(X86::AL)
438  .addImm(Handler.getNumXmmRegs());
440  }
441 
442  // Now we can add the actual call instruction to the correct basic block.
443  MIRBuilder.insertInstr(MIB);
444 
445  // If Callee is a reg, since it is used by a target specific
446  // instruction, it must have a register class matching the
447  // constraint of that instruction.
448  if (Callee.isReg())
450  MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
451  *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Callee, 0));
452 
453  // Finally we can copy the returned value back into its virtual-register. In
454  // symmetry with the arguments, the physical register must be an
455  // implicit-define of the call instruction.
456 
457  if (!OrigRet.Ty->isVoidTy()) {
458  if (OrigRet.Regs.size() > 1)
459  return false;
460 
461  SplitArgs.clear();
462  SmallVector<Register, 8> NewRegs;
463 
464  if (!splitToValueTypes(OrigRet, SplitArgs, DL, MRI,
465  [&](ArrayRef<Register> Regs) {
466  NewRegs.assign(Regs.begin(), Regs.end());
467  }))
468  return false;
469 
470  CallReturnHandler Handler(MIRBuilder, MRI, RetCC_X86, MIB);
471  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
472  return false;
473 
474  if (!NewRegs.empty())
475  MIRBuilder.buildMerge(OrigRet.Regs[0], NewRegs);
476  }
477 
478  CallSeqStart.addImm(Handler.getStackSize())
479  .addImm(0 /* see getFrameTotalSize */)
480  .addImm(0 /* see getFrameAdjustment */);
481 
482  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
483  MIRBuilder.buildInstr(AdjStackUp)
484  .addImm(Handler.getStackSize())
485  .addImm(0 /* NumBytesForCalleeToPop */);
486 
487  return true;
488 }
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:176
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set, or Regs.size() if they are all allocated.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:542
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:641
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ...
LLVMContext & Context
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO, unsigned OpIdx)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:40
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:143
This class represents lattice values for constants.
Definition: AllocatorList.h:23
iterator begin() const
Definition: ArrayRef.h:136
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:501
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1100
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:388
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
unsigned const TargetRegisterInfo * TRI
F(f)
block Block Frequency true
bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, const MachineOperand &Callee, const ArgInfo &OrigRet, ArrayRef< ArgInfo > OrigArgs) const override
This hook behaves as the extended lowerCall function, but for targets that do not support swifterror ...
bool CC_X86(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:129
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
bool handleAssignments(MachineIRBuilder &MIRBuilder, ArrayRef< ArgInfo > Args, ValueHandler &Handler) const
Invoke Handler::assignArg on each of the given Args and then use Callback to move them to the assigne...
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:369
const HexagonInstrInfo * TII
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:217
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
This file contains the simple types necessary to represent the attributes associated with functions a...
unsigned getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LocInfo getLocInfo() const
unsigned getSizeInBits() const
void assign(size_type NumElts, const T &Elt)
Definition: SmallVector.h:412
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs) const override
This hook behaves as the extended lowerReturn function, but for targets that do not support swifterro...
bool arg_empty() const
Definition: Function.h:723
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
virtual const TargetInstrInfo * getInstrInfo() const
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:119
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
TargetInstrInfo - Interface to description of machine instruction set.
bool isVoidTy() const
Return true if this is &#39;void&#39;.
Definition: Type.h:140
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const TargetRegisterInfo * getTargetRegisterInfo() const
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
Helper class to build MachineInstr.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
MachineInstrBuilder buildGEP(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_GEP Op0, Op1.
Extended Value Type.
Definition: ValueTypes.h:33
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
Argument handling is mostly uniform between the four places that make these decisions: function forma...
Definition: CallLowering.h:68
This class contains a discriminated union of information about pointers in memory operands...
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
The memory access writes data.
const X86RegisterInfo * getRegisterInfo() const override
Definition: X86Subtarget.h:511
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
CCState - This class holds information needed while lowering arguments and return values...
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
CCValAssign - Represent assignment of one arg/retval to a location.
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
iterator end() const
Definition: ArrayRef.h:137
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
bool RetCC_X86(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
const Function & getFunction() const
Return the LLVM function that this machine code represents.
This file declares the MachineIRBuilder class.
This file describes how to lower LLVM calls to machine code calls.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
The memory access always returns the same value (or traps).
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
uint32_t Size
Definition: Profile.cpp:46
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
Return the number of registers that this ValueType will eventually require.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:575
LLVM Value Representation.
Definition: Value.h:72
bool isTargetLinux() const
Definition: X86Subtarget.h:760
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:807
X86CallLowering(const X86TargetLowering &TLI)
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
SmallVector< Register, 4 > Regs
Definition: CallLowering.h:47
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs...
Register getReg() const
getReg - Returns the register number.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
iterator_range< arg_iterator > args()
Definition: Function.h:713
Wrapper class representing virtual and physical registers.
Definition: Register.h:18
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143