LLVM  9.0.0svn
X86FrameLowering.cpp
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1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86FrameLowering.h"
14 #include "X86InstrBuilder.h"
15 #include "X86InstrInfo.h"
16 #include "X86MachineFunctionInfo.h"
17 #include "X86Subtarget.h"
18 #include "X86TargetMachine.h"
19 #include "llvm/ADT/SmallSet.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCSymbol.h"
31 #include "llvm/Support/Debug.h"
33 #include <cstdlib>
34 
35 using namespace llvm;
36 
38  unsigned StackAlignOverride)
39  : TargetFrameLowering(StackGrowsDown, StackAlignOverride,
40  STI.is64Bit() ? -8 : -4),
41  STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
42  // Cache a bunch of frame-related predicates for this subtarget.
44  Is64Bit = STI.is64Bit();
45  IsLP64 = STI.isTarget64BitLP64();
46  // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
49 }
50 
52  return !MF.getFrameInfo().hasVarSizedObjects() &&
53  !MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
54 }
55 
56 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
57 /// call frame pseudos can be simplified. Having a FP, as in the default
58 /// implementation, is not sufficient here since we can't always use it.
59 /// Use a more nuanced condition.
60 bool
62  return hasReservedCallFrame(MF) ||
63  (hasFP(MF) && !TRI->needsStackRealignment(MF)) ||
64  TRI->hasBasePointer(MF);
65 }
66 
67 // needsFrameIndexResolution - Do we need to perform FI resolution for
68 // this function. Normally, this is required only when the function
69 // has any stack objects. However, FI resolution actually has another job,
70 // not apparent from the title - it resolves callframesetup/destroy
71 // that were not simplified earlier.
72 // So, this is required for x86 functions that have push sequences even
73 // when there are no stack objects.
74 bool
76  return MF.getFrameInfo().hasStackObjects() ||
77  MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
78 }
79 
80 /// hasFP - Return true if the specified function should have a dedicated frame
81 /// pointer register. This is true if the function has variable sized allocas
82 /// or if frame pointer elimination is disabled.
84  const MachineFrameInfo &MFI = MF.getFrameInfo();
85  return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
86  TRI->needsStackRealignment(MF) ||
87  MFI.hasVarSizedObjects() ||
89  MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
90  MF.callsUnwindInit() || MF.hasEHFunclets() || MF.callsEHReturn() ||
91  MFI.hasStackMap() || MFI.hasPatchPoint() ||
93 }
94 
95 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
96  if (IsLP64) {
97  if (isInt<8>(Imm))
98  return X86::SUB64ri8;
99  return X86::SUB64ri32;
100  } else {
101  if (isInt<8>(Imm))
102  return X86::SUB32ri8;
103  return X86::SUB32ri;
104  }
105 }
106 
107 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
108  if (IsLP64) {
109  if (isInt<8>(Imm))
110  return X86::ADD64ri8;
111  return X86::ADD64ri32;
112  } else {
113  if (isInt<8>(Imm))
114  return X86::ADD32ri8;
115  return X86::ADD32ri;
116  }
117 }
118 
119 static unsigned getSUBrrOpcode(unsigned isLP64) {
120  return isLP64 ? X86::SUB64rr : X86::SUB32rr;
121 }
122 
123 static unsigned getADDrrOpcode(unsigned isLP64) {
124  return isLP64 ? X86::ADD64rr : X86::ADD32rr;
125 }
126 
127 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
128  if (IsLP64) {
129  if (isInt<8>(Imm))
130  return X86::AND64ri8;
131  return X86::AND64ri32;
132  }
133  if (isInt<8>(Imm))
134  return X86::AND32ri8;
135  return X86::AND32ri;
136 }
137 
138 static unsigned getLEArOpcode(unsigned IsLP64) {
139  return IsLP64 ? X86::LEA64r : X86::LEA32r;
140 }
141 
142 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
143 /// when it reaches the "return" instruction. We can then pop a stack object
144 /// to this register without worry about clobbering it.
147  const X86RegisterInfo *TRI,
148  bool Is64Bit) {
149  const MachineFunction *MF = MBB.getParent();
150  if (MF->callsEHReturn())
151  return 0;
152 
153  const TargetRegisterClass &AvailableRegs = *TRI->getGPRsForTailCall(*MF);
154 
155  if (MBBI == MBB.end())
156  return 0;
157 
158  switch (MBBI->getOpcode()) {
159  default: return 0;
160  case TargetOpcode::PATCHABLE_RET:
161  case X86::RET:
162  case X86::RETL:
163  case X86::RETQ:
164  case X86::RETIL:
165  case X86::RETIQ:
166  case X86::TCRETURNdi:
167  case X86::TCRETURNri:
168  case X86::TCRETURNmi:
169  case X86::TCRETURNdi64:
170  case X86::TCRETURNri64:
171  case X86::TCRETURNmi64:
172  case X86::EH_RETURN:
173  case X86::EH_RETURN64: {
175  for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
176  MachineOperand &MO = MBBI->getOperand(i);
177  if (!MO.isReg() || MO.isDef())
178  continue;
179  unsigned Reg = MO.getReg();
180  if (!Reg)
181  continue;
182  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
183  Uses.insert(*AI);
184  }
185 
186  for (auto CS : AvailableRegs)
187  if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP &&
188  CS != X86::ESP)
189  return CS;
190  }
191  }
192 
193  return 0;
194 }
195 
196 static bool isEAXLiveIn(MachineBasicBlock &MBB) {
197  for (MachineBasicBlock::RegisterMaskPair RegMask : MBB.liveins()) {
198  unsigned Reg = RegMask.PhysReg;
199 
200  if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
201  Reg == X86::AH || Reg == X86::AL)
202  return true;
203  }
204 
205  return false;
206 }
207 
208 /// Check if the flags need to be preserved before the terminators.
209 /// This would be the case, if the eflags is live-in of the region
210 /// composed by the terminators or live-out of that region, without
211 /// being defined by a terminator.
212 static bool
214  for (const MachineInstr &MI : MBB.terminators()) {
215  bool BreakNext = false;
216  for (const MachineOperand &MO : MI.operands()) {
217  if (!MO.isReg())
218  continue;
219  unsigned Reg = MO.getReg();
220  if (Reg != X86::EFLAGS)
221  continue;
222 
223  // This terminator needs an eflags that is not defined
224  // by a previous another terminator:
225  // EFLAGS is live-in of the region composed by the terminators.
226  if (!MO.isDef())
227  return true;
228  // This terminator defines the eflags, i.e., we don't need to preserve it.
229  // However, we still need to check this specific terminator does not
230  // read a live-in value.
231  BreakNext = true;
232  }
233  // We found a definition of the eflags, no need to preserve them.
234  if (BreakNext)
235  return false;
236  }
237 
238  // None of the terminators use or define the eflags.
239  // Check if they are live-out, that would imply we need to preserve them.
240  for (const MachineBasicBlock *Succ : MBB.successors())
241  if (Succ->isLiveIn(X86::EFLAGS))
242  return true;
243 
244  return false;
245 }
246 
247 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
248 /// stack pointer by a constant value.
251  const DebugLoc &DL,
252  int64_t NumBytes, bool InEpilogue) const {
253  bool isSub = NumBytes < 0;
254  uint64_t Offset = isSub ? -NumBytes : NumBytes;
257 
258  uint64_t Chunk = (1LL << 31) - 1;
259 
260  if (Offset > Chunk) {
261  // Rather than emit a long series of instructions for large offsets,
262  // load the offset into a register and do one sub/add
263  unsigned Reg = 0;
264  unsigned Rax = (unsigned)(Is64Bit ? X86::RAX : X86::EAX);
265 
266  if (isSub && !isEAXLiveIn(MBB))
267  Reg = Rax;
268  else
269  Reg = findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
270 
271  unsigned MovRIOpc = Is64Bit ? X86::MOV64ri : X86::MOV32ri;
272  unsigned AddSubRROpc =
274  if (Reg) {
275  BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Reg)
276  .addImm(Offset)
277  .setMIFlag(Flag);
278  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AddSubRROpc), StackPtr)
279  .addReg(StackPtr)
280  .addReg(Reg);
281  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
282  return;
283  } else if (Offset > 8 * Chunk) {
284  // If we would need more than 8 add or sub instructions (a >16GB stack
285  // frame), it's worth spilling RAX to materialize this immediate.
286  // pushq %rax
287  // movabsq +-$Offset+-SlotSize, %rax
288  // addq %rsp, %rax
289  // xchg %rax, (%rsp)
290  // movq (%rsp), %rsp
291  assert(Is64Bit && "can't have 32-bit 16GB stack frame");
292  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
293  .addReg(Rax, RegState::Kill)
294  .setMIFlag(Flag);
295  // Subtract is not commutative, so negate the offset and always use add.
296  // Subtract 8 less and add 8 more to account for the PUSH we just did.
297  if (isSub)
298  Offset = -(Offset - SlotSize);
299  else
300  Offset = Offset + SlotSize;
301  BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Rax)
302  .addImm(Offset)
303  .setMIFlag(Flag);
304  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(X86::ADD64rr), Rax)
305  .addReg(Rax)
306  .addReg(StackPtr);
307  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
308  // Exchange the new SP in RAX with the top of the stack.
309  addRegOffset(
310  BuildMI(MBB, MBBI, DL, TII.get(X86::XCHG64rm), Rax).addReg(Rax),
311  StackPtr, false, 0);
312  // Load new SP from the top of the stack into RSP.
313  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), StackPtr),
314  StackPtr, false, 0);
315  return;
316  }
317  }
318 
319  while (Offset) {
320  uint64_t ThisVal = std::min(Offset, Chunk);
321  if (ThisVal == SlotSize) {
322  // Use push / pop for slot sized adjustments as a size optimization. We
323  // need to find a dead register when using pop.
324  unsigned Reg = isSub
325  ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
326  : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
327  if (Reg) {
328  unsigned Opc = isSub
329  ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
330  : (Is64Bit ? X86::POP64r : X86::POP32r);
331  BuildMI(MBB, MBBI, DL, TII.get(Opc))
332  .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub))
333  .setMIFlag(Flag);
334  Offset -= ThisVal;
335  continue;
336  }
337  }
338 
339  BuildStackAdjustment(MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue)
340  .setMIFlag(Flag);
341 
342  Offset -= ThisVal;
343  }
344 }
345 
346 MachineInstrBuilder X86FrameLowering::BuildStackAdjustment(
348  const DebugLoc &DL, int64_t Offset, bool InEpilogue) const {
349  assert(Offset != 0 && "zero offset stack adjustment requested");
350 
351  // On Atom, using LEA to adjust SP is preferred, but using it in the epilogue
352  // is tricky.
353  bool UseLEA;
354  if (!InEpilogue) {
355  // Check if inserting the prologue at the beginning
356  // of MBB would require to use LEA operations.
357  // We need to use LEA operations if EFLAGS is live in, because
358  // it means an instruction will read it before it gets defined.
359  UseLEA = STI.useLeaForSP() || MBB.isLiveIn(X86::EFLAGS);
360  } else {
361  // If we can use LEA for SP but we shouldn't, check that none
362  // of the terminators uses the eflags. Otherwise we will insert
363  // a ADD that will redefine the eflags and break the condition.
364  // Alternatively, we could move the ADD, but this may not be possible
365  // and is an optimization anyway.
366  UseLEA = canUseLEAForSPInEpilogue(*MBB.getParent());
367  if (UseLEA && !STI.useLeaForSP())
369  // If that assert breaks, that means we do not do the right thing
370  // in canUseAsEpilogue.
372  "We shouldn't have allowed this insertion point");
373  }
374 
376  if (UseLEA) {
377  MI = addRegOffset(BuildMI(MBB, MBBI, DL,
379  StackPtr),
380  StackPtr, false, Offset);
381  } else {
382  bool IsSub = Offset < 0;
383  uint64_t AbsOffset = IsSub ? -Offset : Offset;
384  unsigned Opc = IsSub ? getSUBriOpcode(Uses64BitFramePtr, AbsOffset)
385  : getADDriOpcode(Uses64BitFramePtr, AbsOffset);
386  MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
387  .addReg(StackPtr)
388  .addImm(AbsOffset);
389  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
390  }
391  return MI;
392 }
393 
396  bool doMergeWithPrevious) const {
397  if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
398  (!doMergeWithPrevious && MBBI == MBB.end()))
399  return 0;
400 
401  MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
402 
403  PI = skipDebugInstructionsBackward(PI, MBB.begin());
404  // It is assumed that ADD/SUB/LEA instruction is succeded by one CFI
405  // instruction, and that there are no DBG_VALUE or other instructions between
406  // ADD/SUB/LEA and its corresponding CFI instruction.
407  /* TODO: Add support for the case where there are multiple CFI instructions
408  below the ADD/SUB/LEA, e.g.:
409  ...
410  add
411  cfi_def_cfa_offset
412  cfi_offset
413  ...
414  */
415  if (doMergeWithPrevious && PI != MBB.begin() && PI->isCFIInstruction())
416  PI = std::prev(PI);
417 
418  unsigned Opc = PI->getOpcode();
419  int Offset = 0;
420 
421  if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
422  Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
423  PI->getOperand(0).getReg() == StackPtr){
424  assert(PI->getOperand(1).getReg() == StackPtr);
425  Offset = PI->getOperand(2).getImm();
426  } else if ((Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
427  PI->getOperand(0).getReg() == StackPtr &&
428  PI->getOperand(1).getReg() == StackPtr &&
429  PI->getOperand(2).getImm() == 1 &&
430  PI->getOperand(3).getReg() == X86::NoRegister &&
431  PI->getOperand(5).getReg() == X86::NoRegister) {
432  // For LEAs we have: def = lea SP, FI, noreg, Offset, noreg.
433  Offset = PI->getOperand(4).getImm();
434  } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
435  Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
436  PI->getOperand(0).getReg() == StackPtr) {
437  assert(PI->getOperand(1).getReg() == StackPtr);
438  Offset = -PI->getOperand(2).getImm();
439  } else
440  return 0;
441 
442  PI = MBB.erase(PI);
443  if (PI != MBB.end() && PI->isCFIInstruction()) PI = MBB.erase(PI);
444  if (!doMergeWithPrevious)
445  MBBI = skipDebugInstructionsForward(PI, MBB.end());
446 
447  return Offset;
448 }
449 
452  const DebugLoc &DL,
453  const MCCFIInstruction &CFIInst) const {
454  MachineFunction &MF = *MBB.getParent();
455  unsigned CFIIndex = MF.addFrameInst(CFIInst);
456  BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
457  .addCFIIndex(CFIIndex);
458 }
459 
462  const DebugLoc &DL) const {
463  MachineFunction &MF = *MBB.getParent();
464  MachineFrameInfo &MFI = MF.getFrameInfo();
465  MachineModuleInfo &MMI = MF.getMMI();
466  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
467 
468  // Add callee saved registers to move list.
469  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
470  if (CSI.empty()) return;
471 
472  // Calculate offsets.
473  for (std::vector<CalleeSavedInfo>::const_iterator
474  I = CSI.begin(), E = CSI.end(); I != E; ++I) {
475  int64_t Offset = MFI.getObjectOffset(I->getFrameIdx());
476  unsigned Reg = I->getReg();
477 
478  unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
479  BuildCFI(MBB, MBBI, DL,
480  MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
481  }
482 }
483 
485  MachineBasicBlock &MBB,
487  const DebugLoc &DL, bool InProlog) const {
488  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
489  if (STI.isTargetWindowsCoreCLR()) {
490  if (InProlog) {
491  emitStackProbeInlineStub(MF, MBB, MBBI, DL, true);
492  } else {
493  emitStackProbeInline(MF, MBB, MBBI, DL, false);
494  }
495  } else {
496  emitStackProbeCall(MF, MBB, MBBI, DL, InProlog);
497  }
498 }
499 
501  MachineBasicBlock &PrologMBB) const {
502  const StringRef ChkStkStubSymbol = "__chkstk_stub";
503  MachineInstr *ChkStkStub = nullptr;
504 
505  for (MachineInstr &MI : PrologMBB) {
506  if (MI.isCall() && MI.getOperand(0).isSymbol() &&
507  ChkStkStubSymbol == MI.getOperand(0).getSymbolName()) {
508  ChkStkStub = &MI;
509  break;
510  }
511  }
512 
513  if (ChkStkStub != nullptr) {
514  assert(!ChkStkStub->isBundled() &&
515  "Not expecting bundled instructions here");
516  MachineBasicBlock::iterator MBBI = std::next(ChkStkStub->getIterator());
517  assert(std::prev(MBBI) == ChkStkStub &&
518  "MBBI expected after __chkstk_stub.");
519  DebugLoc DL = PrologMBB.findDebugLoc(MBBI);
520  emitStackProbeInline(MF, PrologMBB, MBBI, DL, true);
521  ChkStkStub->eraseFromParent();
522  }
523 }
524 
525 void X86FrameLowering::emitStackProbeInline(MachineFunction &MF,
526  MachineBasicBlock &MBB,
528  const DebugLoc &DL,
529  bool InProlog) const {
530  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
531  assert(STI.is64Bit() && "different expansion needed for 32 bit");
532  assert(STI.isTargetWindowsCoreCLR() && "custom expansion expects CoreCLR");
533  const TargetInstrInfo &TII = *STI.getInstrInfo();
534  const BasicBlock *LLVM_BB = MBB.getBasicBlock();
535 
536  // RAX contains the number of bytes of desired stack adjustment.
537  // The handling here assumes this value has already been updated so as to
538  // maintain stack alignment.
539  //
540  // We need to exit with RSP modified by this amount and execute suitable
541  // page touches to notify the OS that we're growing the stack responsibly.
542  // All stack probing must be done without modifying RSP.
543  //
544  // MBB:
545  // SizeReg = RAX;
546  // ZeroReg = 0
547  // CopyReg = RSP
548  // Flags, TestReg = CopyReg - SizeReg
549  // FinalReg = !Flags.Ovf ? TestReg : ZeroReg
550  // LimitReg = gs magic thread env access
551  // if FinalReg >= LimitReg goto ContinueMBB
552  // RoundBB:
553  // RoundReg = page address of FinalReg
554  // LoopMBB:
555  // LoopReg = PHI(LimitReg,ProbeReg)
556  // ProbeReg = LoopReg - PageSize
557  // [ProbeReg] = 0
558  // if (ProbeReg > RoundReg) goto LoopMBB
559  // ContinueMBB:
560  // RSP = RSP - RAX
561  // [rest of original MBB]
562 
563  // Set up the new basic blocks
564  MachineBasicBlock *RoundMBB = MF.CreateMachineBasicBlock(LLVM_BB);
565  MachineBasicBlock *LoopMBB = MF.CreateMachineBasicBlock(LLVM_BB);
566  MachineBasicBlock *ContinueMBB = MF.CreateMachineBasicBlock(LLVM_BB);
567 
568  MachineFunction::iterator MBBIter = std::next(MBB.getIterator());
569  MF.insert(MBBIter, RoundMBB);
570  MF.insert(MBBIter, LoopMBB);
571  MF.insert(MBBIter, ContinueMBB);
572 
573  // Split MBB and move the tail portion down to ContinueMBB.
574  MachineBasicBlock::iterator BeforeMBBI = std::prev(MBBI);
575  ContinueMBB->splice(ContinueMBB->begin(), &MBB, MBBI, MBB.end());
576  ContinueMBB->transferSuccessorsAndUpdatePHIs(&MBB);
577 
578  // Some useful constants
579  const int64_t ThreadEnvironmentStackLimit = 0x10;
580  const int64_t PageSize = 0x1000;
581  const int64_t PageMask = ~(PageSize - 1);
582 
583  // Registers we need. For the normal case we use virtual
584  // registers. For the prolog expansion we use RAX, RCX and RDX.
586  const TargetRegisterClass *RegClass = &X86::GR64RegClass;
587  const unsigned SizeReg = InProlog ? (unsigned)X86::RAX
588  : MRI.createVirtualRegister(RegClass),
589  ZeroReg = InProlog ? (unsigned)X86::RCX
590  : MRI.createVirtualRegister(RegClass),
591  CopyReg = InProlog ? (unsigned)X86::RDX
592  : MRI.createVirtualRegister(RegClass),
593  TestReg = InProlog ? (unsigned)X86::RDX
594  : MRI.createVirtualRegister(RegClass),
595  FinalReg = InProlog ? (unsigned)X86::RDX
596  : MRI.createVirtualRegister(RegClass),
597  RoundedReg = InProlog ? (unsigned)X86::RDX
598  : MRI.createVirtualRegister(RegClass),
599  LimitReg = InProlog ? (unsigned)X86::RCX
600  : MRI.createVirtualRegister(RegClass),
601  JoinReg = InProlog ? (unsigned)X86::RCX
602  : MRI.createVirtualRegister(RegClass),
603  ProbeReg = InProlog ? (unsigned)X86::RCX
604  : MRI.createVirtualRegister(RegClass);
605 
606  // SP-relative offsets where we can save RCX and RDX.
607  int64_t RCXShadowSlot = 0;
608  int64_t RDXShadowSlot = 0;
609 
610  // If inlining in the prolog, save RCX and RDX.
611  if (InProlog) {
612  // Compute the offsets. We need to account for things already
613  // pushed onto the stack at this point: return address, frame
614  // pointer (if used), and callee saves.
616  const int64_t CalleeSaveSize = X86FI->getCalleeSavedFrameSize();
617  const bool HasFP = hasFP(MF);
618 
619  // Check if we need to spill RCX and/or RDX.
620  // Here we assume that no earlier prologue instruction changes RCX and/or
621  // RDX, so checking the block live-ins is enough.
622  const bool IsRCXLiveIn = MBB.isLiveIn(X86::RCX);
623  const bool IsRDXLiveIn = MBB.isLiveIn(X86::RDX);
624  int64_t InitSlot = 8 + CalleeSaveSize + (HasFP ? 8 : 0);
625  // Assign the initial slot to both registers, then change RDX's slot if both
626  // need to be spilled.
627  if (IsRCXLiveIn)
628  RCXShadowSlot = InitSlot;
629  if (IsRDXLiveIn)
630  RDXShadowSlot = InitSlot;
631  if (IsRDXLiveIn && IsRCXLiveIn)
632  RDXShadowSlot += 8;
633  // Emit the saves if needed.
634  if (IsRCXLiveIn)
635  addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
636  RCXShadowSlot)
637  .addReg(X86::RCX);
638  if (IsRDXLiveIn)
639  addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
640  RDXShadowSlot)
641  .addReg(X86::RDX);
642  } else {
643  // Not in the prolog. Copy RAX to a virtual reg.
644  BuildMI(&MBB, DL, TII.get(X86::MOV64rr), SizeReg).addReg(X86::RAX);
645  }
646 
647  // Add code to MBB to check for overflow and set the new target stack pointer
648  // to zero if so.
649  BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg)
650  .addReg(ZeroReg, RegState::Undef)
651  .addReg(ZeroReg, RegState::Undef);
652  BuildMI(&MBB, DL, TII.get(X86::MOV64rr), CopyReg).addReg(X86::RSP);
653  BuildMI(&MBB, DL, TII.get(X86::SUB64rr), TestReg)
654  .addReg(CopyReg)
655  .addReg(SizeReg);
656  BuildMI(&MBB, DL, TII.get(X86::CMOV64rr), FinalReg)
657  .addReg(TestReg)
658  .addReg(ZeroReg)
660 
661  // FinalReg now holds final stack pointer value, or zero if
662  // allocation would overflow. Compare against the current stack
663  // limit from the thread environment block. Note this limit is the
664  // lowest touched page on the stack, not the point at which the OS
665  // will cause an overflow exception, so this is just an optimization
666  // to avoid unnecessarily touching pages that are below the current
667  // SP but already committed to the stack by the OS.
668  BuildMI(&MBB, DL, TII.get(X86::MOV64rm), LimitReg)
669  .addReg(0)
670  .addImm(1)
671  .addReg(0)
672  .addImm(ThreadEnvironmentStackLimit)
673  .addReg(X86::GS);
674  BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg);
675  // Jump if the desired stack pointer is at or above the stack limit.
676  BuildMI(&MBB, DL, TII.get(X86::JCC_1)).addMBB(ContinueMBB).addImm(X86::COND_AE);
677 
678  // Add code to roundMBB to round the final stack pointer to a page boundary.
679  RoundMBB->addLiveIn(FinalReg);
680  BuildMI(RoundMBB, DL, TII.get(X86::AND64ri32), RoundedReg)
681  .addReg(FinalReg)
682  .addImm(PageMask);
683  BuildMI(RoundMBB, DL, TII.get(X86::JMP_1)).addMBB(LoopMBB);
684 
685  // LimitReg now holds the current stack limit, RoundedReg page-rounded
686  // final RSP value. Add code to loopMBB to decrement LimitReg page-by-page
687  // and probe until we reach RoundedReg.
688  if (!InProlog) {
689  BuildMI(LoopMBB, DL, TII.get(X86::PHI), JoinReg)
690  .addReg(LimitReg)
691  .addMBB(RoundMBB)
692  .addReg(ProbeReg)
693  .addMBB(LoopMBB);
694  }
695 
696  LoopMBB->addLiveIn(JoinReg);
697  addRegOffset(BuildMI(LoopMBB, DL, TII.get(X86::LEA64r), ProbeReg), JoinReg,
698  false, -PageSize);
699 
700  // Probe by storing a byte onto the stack.
701  BuildMI(LoopMBB, DL, TII.get(X86::MOV8mi))
702  .addReg(ProbeReg)
703  .addImm(1)
704  .addReg(0)
705  .addImm(0)
706  .addReg(0)
707  .addImm(0);
708 
709  LoopMBB->addLiveIn(RoundedReg);
710  BuildMI(LoopMBB, DL, TII.get(X86::CMP64rr))
711  .addReg(RoundedReg)
712  .addReg(ProbeReg);
713  BuildMI(LoopMBB, DL, TII.get(X86::JCC_1)).addMBB(LoopMBB).addImm(X86::COND_NE);
714 
715  MachineBasicBlock::iterator ContinueMBBI = ContinueMBB->getFirstNonPHI();
716 
717  // If in prolog, restore RDX and RCX.
718  if (InProlog) {
719  if (RCXShadowSlot) // It means we spilled RCX in the prologue.
720  addRegOffset(BuildMI(*ContinueMBB, ContinueMBBI, DL,
721  TII.get(X86::MOV64rm), X86::RCX),
722  X86::RSP, false, RCXShadowSlot);
723  if (RDXShadowSlot) // It means we spilled RDX in the prologue.
724  addRegOffset(BuildMI(*ContinueMBB, ContinueMBBI, DL,
725  TII.get(X86::MOV64rm), X86::RDX),
726  X86::RSP, false, RDXShadowSlot);
727  }
728 
729  // Now that the probing is done, add code to continueMBB to update
730  // the stack pointer for real.
731  ContinueMBB->addLiveIn(SizeReg);
732  BuildMI(*ContinueMBB, ContinueMBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
733  .addReg(X86::RSP)
734  .addReg(SizeReg);
735 
736  // Add the control flow edges we need.
737  MBB.addSuccessor(ContinueMBB);
738  MBB.addSuccessor(RoundMBB);
739  RoundMBB->addSuccessor(LoopMBB);
740  LoopMBB->addSuccessor(ContinueMBB);
741  LoopMBB->addSuccessor(LoopMBB);
742 
743  // Mark all the instructions added to the prolog as frame setup.
744  if (InProlog) {
745  for (++BeforeMBBI; BeforeMBBI != MBB.end(); ++BeforeMBBI) {
746  BeforeMBBI->setFlag(MachineInstr::FrameSetup);
747  }
748  for (MachineInstr &MI : *RoundMBB) {
749  MI.setFlag(MachineInstr::FrameSetup);
750  }
751  for (MachineInstr &MI : *LoopMBB) {
752  MI.setFlag(MachineInstr::FrameSetup);
753  }
754  for (MachineBasicBlock::iterator CMBBI = ContinueMBB->begin();
755  CMBBI != ContinueMBBI; ++CMBBI) {
756  CMBBI->setFlag(MachineInstr::FrameSetup);
757  }
758  }
759 }
760 
761 void X86FrameLowering::emitStackProbeCall(MachineFunction &MF,
762  MachineBasicBlock &MBB,
764  const DebugLoc &DL,
765  bool InProlog) const {
766  bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large;
767 
768  // FIXME: Add retpoline support and remove this.
769  if (Is64Bit && IsLargeCodeModel && STI.useRetpolineIndirectCalls())
770  report_fatal_error("Emitting stack probe calls on 64-bit with the large "
771  "code model and retpoline not yet implemented.");
772 
773  unsigned CallOp;
774  if (Is64Bit)
775  CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32;
776  else
777  CallOp = X86::CALLpcrel32;
778 
780 
782  MachineBasicBlock::iterator ExpansionMBBI = std::prev(MBBI);
783 
784  // All current stack probes take AX and SP as input, clobber flags, and
785  // preserve all registers. x86_64 probes leave RSP unmodified.
786  if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
787  // For the large code model, we have to call through a register. Use R11,
788  // as it is scratch in all supported calling conventions.
789  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
790  .addExternalSymbol(MF.createExternalSymbolName(Symbol));
791  CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
792  } else {
793  CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp))
794  .addExternalSymbol(MF.createExternalSymbolName(Symbol));
795  }
796 
797  unsigned AX = Uses64BitFramePtr ? X86::RAX : X86::EAX;
798  unsigned SP = Uses64BitFramePtr ? X86::RSP : X86::ESP;
799  CI.addReg(AX, RegState::Implicit)
803  .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
804 
805  if (STI.isTargetWin64() || !STI.isOSWindows()) {
806  // MSVC x32's _chkstk and cygwin/mingw's _alloca adjust %esp themselves.
807  // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
808  // themselves. They also does not clobber %rax so we can reuse it when
809  // adjusting %rsp.
810  // All other platforms do not specify a particular ABI for the stack probe
811  // function, so we arbitrarily define it to not adjust %esp/%rsp itself.
812  BuildMI(MBB, MBBI, DL, TII.get(getSUBrrOpcode(Uses64BitFramePtr)), SP)
813  .addReg(SP)
814  .addReg(AX);
815  }
816 
817  if (InProlog) {
818  // Apply the frame setup flag to all inserted instrs.
819  for (++ExpansionMBBI; ExpansionMBBI != MBBI; ++ExpansionMBBI)
820  ExpansionMBBI->setFlag(MachineInstr::FrameSetup);
821  }
822 }
823 
824 void X86FrameLowering::emitStackProbeInlineStub(
826  MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog) const {
827 
828  assert(InProlog && "ChkStkStub called outside prolog!");
829 
830  BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
831  .addExternalSymbol("__chkstk_stub");
832 }
833 
834 static unsigned calculateSetFPREG(uint64_t SPAdjust) {
835  // Win64 ABI has a less restrictive limitation of 240; 128 works equally well
836  // and might require smaller successive adjustments.
837  const uint64_t Win64MaxSEHOffset = 128;
838  uint64_t SEHFrameOffset = std::min(SPAdjust, Win64MaxSEHOffset);
839  // Win64 ABI requires 16-byte alignment for the UWOP_SET_FPREG opcode.
840  return SEHFrameOffset & -16;
841 }
842 
843 // If we're forcing a stack realignment we can't rely on just the frame
844 // info, we need to know the ABI stack alignment as well in case we
845 // have a call out. Otherwise just make sure we have some alignment - we'll
846 // go with the minimum SlotSize.
847 uint64_t X86FrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {
848  const MachineFrameInfo &MFI = MF.getFrameInfo();
849  uint64_t MaxAlign = MFI.getMaxAlignment(); // Desired stack alignment.
850  unsigned StackAlign = getStackAlignment();
851  if (MF.getFunction().hasFnAttribute("stackrealign")) {
852  if (MFI.hasCalls())
853  MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
854  else if (MaxAlign < SlotSize)
855  MaxAlign = SlotSize;
856  }
857  return MaxAlign;
858 }
859 
860 void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
862  const DebugLoc &DL, unsigned Reg,
863  uint64_t MaxAlign) const {
864  uint64_t Val = -MaxAlign;
865  unsigned AndOp = getANDriOpcode(Uses64BitFramePtr, Val);
866  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AndOp), Reg)
867  .addReg(Reg)
868  .addImm(Val)
870 
871  // The EFLAGS implicit def is dead.
872  MI->getOperand(3).setIsDead();
873 }
874 
876  // x86-64 (non Win64) has a 128 byte red zone which is guaranteed not to be
877  // clobbered by any interrupt handler.
878  assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
879  "MF used frame lowering for wrong subtarget");
880  const Function &Fn = MF.getFunction();
881  const bool IsWin64CC = STI.isCallingConvWin64(Fn.getCallingConv());
882  return Is64Bit && !IsWin64CC && !Fn.hasFnAttribute(Attribute::NoRedZone);
883 }
884 
885 
886 /// emitPrologue - Push callee-saved registers onto the stack, which
887 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
888 /// space for local variables. Also emit labels used by the exception handler to
889 /// generate the exception handling frames.
890 
891 /*
892  Here's a gist of what gets emitted:
893 
894  ; Establish frame pointer, if needed
895  [if needs FP]
896  push %rbp
897  .cfi_def_cfa_offset 16
898  .cfi_offset %rbp, -16
899  .seh_pushreg %rpb
900  mov %rsp, %rbp
901  .cfi_def_cfa_register %rbp
902 
903  ; Spill general-purpose registers
904  [for all callee-saved GPRs]
905  pushq %<reg>
906  [if not needs FP]
907  .cfi_def_cfa_offset (offset from RETADDR)
908  .seh_pushreg %<reg>
909 
910  ; If the required stack alignment > default stack alignment
911  ; rsp needs to be re-aligned. This creates a "re-alignment gap"
912  ; of unknown size in the stack frame.
913  [if stack needs re-alignment]
914  and $MASK, %rsp
915 
916  ; Allocate space for locals
917  [if target is Windows and allocated space > 4096 bytes]
918  ; Windows needs special care for allocations larger
919  ; than one page.
920  mov $NNN, %rax
921  call ___chkstk_ms/___chkstk
922  sub %rax, %rsp
923  [else]
924  sub $NNN, %rsp
925 
926  [if needs FP]
927  .seh_stackalloc (size of XMM spill slots)
928  .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
929  [else]
930  .seh_stackalloc NNN
931 
932  ; Spill XMMs
933  ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
934  ; they may get spilled on any platform, if the current function
935  ; calls @llvm.eh.unwind.init
936  [if needs FP]
937  [for all callee-saved XMM registers]
938  movaps %<xmm reg>, -MMM(%rbp)
939  [for all callee-saved XMM registers]
940  .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
941  ; i.e. the offset relative to (%rbp - SEHFrameOffset)
942  [else]
943  [for all callee-saved XMM registers]
944  movaps %<xmm reg>, KKK(%rsp)
945  [for all callee-saved XMM registers]
946  .seh_savexmm %<xmm reg>, KKK
947 
948  .seh_endprologue
949 
950  [if needs base pointer]
951  mov %rsp, %rbx
952  [if needs to restore base pointer]
953  mov %rsp, -MMM(%rbp)
954 
955  ; Emit CFI info
956  [if needs FP]
957  [for all callee-saved registers]
958  .cfi_offset %<reg>, (offset from %rbp)
959  [else]
960  .cfi_def_cfa_offset (offset from RETADDR)
961  [for all callee-saved registers]
962  .cfi_offset %<reg>, (offset from %rsp)
963 
964  Notes:
965  - .seh directives are emitted only for Windows 64 ABI
966  - .cv_fpo directives are emitted on win32 when emitting CodeView
967  - .cfi directives are emitted for all other ABIs
968  - for 32-bit code, substitute %e?? registers for %r??
969 */
970 
972  MachineBasicBlock &MBB) const {
973  assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
974  "MF used frame lowering for wrong subtarget");
975  MachineBasicBlock::iterator MBBI = MBB.begin();
976  MachineFrameInfo &MFI = MF.getFrameInfo();
977  const Function &Fn = MF.getFunction();
978  MachineModuleInfo &MMI = MF.getMMI();
980  uint64_t MaxAlign = calculateMaxStackAlign(MF); // Desired stack alignment.
981  uint64_t StackSize = MFI.getStackSize(); // Number of bytes to allocate.
982  bool IsFunclet = MBB.isEHFuncletEntry();
984  if (Fn.hasPersonalityFn())
985  Personality = classifyEHPersonality(Fn.getPersonalityFn());
986  bool FnHasClrFunclet =
987  MF.hasEHFunclets() && Personality == EHPersonality::CoreCLR;
988  bool IsClrFunclet = IsFunclet && FnHasClrFunclet;
989  bool HasFP = hasFP(MF);
990  bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
991  bool NeedsWin64CFI = IsWin64Prologue && Fn.needsUnwindTableEntry();
992  // FIXME: Emit FPO data for EH funclets.
993  bool NeedsWinFPO =
994  !IsFunclet && STI.isTargetWin32() && MMI.getModule()->getCodeViewFlag();
995  bool NeedsWinCFI = NeedsWin64CFI || NeedsWinFPO;
996  bool NeedsDwarfCFI =
997  !IsWin64Prologue && (MMI.hasDebugInfo() || Fn.needsUnwindTableEntry());
998  unsigned FramePtr = TRI->getFrameRegister(MF);
999  const unsigned MachineFramePtr =
1001  ? getX86SubSuperRegister(FramePtr, 64) : FramePtr;
1002  unsigned BasePtr = TRI->getBaseRegister();
1003  bool HasWinCFI = false;
1004 
1005  // Debug location must be unknown since the first debug location is used
1006  // to determine the end of the prologue.
1007  DebugLoc DL;
1008 
1009  // Add RETADDR move area to callee saved frame size.
1010  int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1011  if (TailCallReturnAddrDelta && IsWin64Prologue)
1012  report_fatal_error("Can't handle guaranteed tail call under win64 yet");
1013 
1014  if (TailCallReturnAddrDelta < 0)
1015  X86FI->setCalleeSavedFrameSize(
1016  X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
1017 
1018  bool UseStackProbe = !STI.getTargetLowering()->getStackProbeSymbolName(MF).empty();
1019 
1020  // The default stack probe size is 4096 if the function has no stackprobesize
1021  // attribute.
1022  unsigned StackProbeSize = 4096;
1023  if (Fn.hasFnAttribute("stack-probe-size"))
1024  Fn.getFnAttribute("stack-probe-size")
1025  .getValueAsString()
1026  .getAsInteger(0, StackProbeSize);
1027 
1028  // Re-align the stack on 64-bit if the x86-interrupt calling convention is
1029  // used and an error code was pushed, since the x86-64 ABI requires a 16-byte
1030  // stack alignment.
1031  if (Fn.getCallingConv() == CallingConv::X86_INTR && Is64Bit &&
1032  Fn.arg_size() == 2) {
1033  StackSize += 8;
1034  MFI.setStackSize(StackSize);
1035  emitSPUpdate(MBB, MBBI, DL, -8, /*InEpilogue=*/false);
1036  }
1037 
1038  // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
1039  // function, and use up to 128 bytes of stack space, don't have a frame
1040  // pointer, calls, or dynamic alloca then we do not need to adjust the
1041  // stack pointer (we fit in the Red Zone). We also check that we don't
1042  // push and pop from the stack.
1043  if (has128ByteRedZone(MF) &&
1044  !TRI->needsStackRealignment(MF) &&
1045  !MFI.hasVarSizedObjects() && // No dynamic alloca.
1046  !MFI.adjustsStack() && // No calls.
1047  !UseStackProbe && // No stack probes.
1048  !MFI.hasCopyImplyingStackAdjustment() && // Don't push and pop.
1049  !MF.shouldSplitStack()) { // Regular stack
1050  uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
1051  if (HasFP) MinSize += SlotSize;
1052  X86FI->setUsesRedZone(MinSize > 0 || StackSize > 0);
1053  StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
1054  MFI.setStackSize(StackSize);
1055  }
1056 
1057  // Insert stack pointer adjustment for later moving of return addr. Only
1058  // applies to tail call optimized functions where the callee argument stack
1059  // size is bigger than the callers.
1060  if (TailCallReturnAddrDelta < 0) {
1061  BuildStackAdjustment(MBB, MBBI, DL, TailCallReturnAddrDelta,
1062  /*InEpilogue=*/false)
1064  }
1065 
1066  // Mapping for machine moves:
1067  //
1068  // DST: VirtualFP AND
1069  // SRC: VirtualFP => DW_CFA_def_cfa_offset
1070  // ELSE => DW_CFA_def_cfa
1071  //
1072  // SRC: VirtualFP AND
1073  // DST: Register => DW_CFA_def_cfa_register
1074  //
1075  // ELSE
1076  // OFFSET < 0 => DW_CFA_offset_extended_sf
1077  // REG < 64 => DW_CFA_offset + Reg
1078  // ELSE => DW_CFA_offset_extended
1079 
1080  uint64_t NumBytes = 0;
1081  int stackGrowth = -SlotSize;
1082 
1083  // Find the funclet establisher parameter
1084  unsigned Establisher = X86::NoRegister;
1085  if (IsClrFunclet)
1086  Establisher = Uses64BitFramePtr ? X86::RCX : X86::ECX;
1087  else if (IsFunclet)
1088  Establisher = Uses64BitFramePtr ? X86::RDX : X86::EDX;
1089 
1090  if (IsWin64Prologue && IsFunclet && !IsClrFunclet) {
1091  // Immediately spill establisher into the home slot.
1092  // The runtime cares about this.
1093  // MOV64mr %rdx, 16(%rsp)
1094  unsigned MOVmr = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1095  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MOVmr)), StackPtr, true, 16)
1096  .addReg(Establisher)
1098  MBB.addLiveIn(Establisher);
1099  }
1100 
1101  if (HasFP) {
1102  assert(MF.getRegInfo().isReserved(MachineFramePtr) && "FP reserved");
1103 
1104  // Calculate required stack adjustment.
1105  uint64_t FrameSize = StackSize - SlotSize;
1106  // If required, include space for extra hidden slot for stashing base pointer.
1107  if (X86FI->getRestoreBasePointer())
1108  FrameSize += SlotSize;
1109 
1110  NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
1111 
1112  // Callee-saved registers are pushed on stack before the stack is realigned.
1113  if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
1114  NumBytes = alignTo(NumBytes, MaxAlign);
1115 
1116  // Save EBP/RBP into the appropriate stack slot.
1117  BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
1118  .addReg(MachineFramePtr, RegState::Kill)
1120 
1121  if (NeedsDwarfCFI) {
1122  // Mark the place where EBP/RBP was saved.
1123  // Define the current CFA rule to use the provided offset.
1124  assert(StackSize);
1125  BuildCFI(MBB, MBBI, DL,
1126  MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
1127 
1128  // Change the rule for the FramePtr to be an "offset" rule.
1129  unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
1131  nullptr, DwarfFramePtr, 2 * stackGrowth));
1132  }
1133 
1134  if (NeedsWinCFI) {
1135  HasWinCFI = true;
1136  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1137  .addImm(FramePtr)
1139  }
1140 
1141  if (!IsWin64Prologue && !IsFunclet) {
1142  // Update EBP with the new base value.
1143  BuildMI(MBB, MBBI, DL,
1144  TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
1145  FramePtr)
1146  .addReg(StackPtr)
1148 
1149  if (NeedsDwarfCFI) {
1150  // Mark effective beginning of when frame pointer becomes valid.
1151  // Define the current CFA to use the EBP/RBP register.
1152  unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
1154  nullptr, DwarfFramePtr));
1155  }
1156 
1157  if (NeedsWinFPO) {
1158  // .cv_fpo_setframe $FramePtr
1159  HasWinCFI = true;
1160  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1161  .addImm(FramePtr)
1162  .addImm(0)
1164  }
1165  }
1166  } else {
1167  assert(!IsFunclet && "funclets without FPs not yet implemented");
1168  NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1169  }
1170 
1171  // Update the offset adjustment, which is mainly used by codeview to translate
1172  // from ESP to VFRAME relative local variable offsets.
1173  if (!IsFunclet) {
1174  if (HasFP && TRI->needsStackRealignment(MF))
1175  MFI.setOffsetAdjustment(-NumBytes);
1176  else
1177  MFI.setOffsetAdjustment(-StackSize);
1178  }
1179 
1180  // For EH funclets, only allocate enough space for outgoing calls. Save the
1181  // NumBytes value that we would've used for the parent frame.
1182  unsigned ParentFrameNumBytes = NumBytes;
1183  if (IsFunclet)
1184  NumBytes = getWinEHFuncletFrameSize(MF);
1185 
1186  // Skip the callee-saved push instructions.
1187  bool PushedRegs = false;
1188  int StackOffset = 2 * stackGrowth;
1189 
1190  while (MBBI != MBB.end() &&
1191  MBBI->getFlag(MachineInstr::FrameSetup) &&
1192  (MBBI->getOpcode() == X86::PUSH32r ||
1193  MBBI->getOpcode() == X86::PUSH64r)) {
1194  PushedRegs = true;
1195  unsigned Reg = MBBI->getOperand(0).getReg();
1196  ++MBBI;
1197 
1198  if (!HasFP && NeedsDwarfCFI) {
1199  // Mark callee-saved push instruction.
1200  // Define the current CFA rule to use the provided offset.
1201  assert(StackSize);
1202  BuildCFI(MBB, MBBI, DL,
1203  MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
1204  StackOffset += stackGrowth;
1205  }
1206 
1207  if (NeedsWinCFI) {
1208  HasWinCFI = true;
1209  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1210  .addImm(Reg)
1212  }
1213  }
1214 
1215  // Realign stack after we pushed callee-saved registers (so that we'll be
1216  // able to calculate their offsets from the frame pointer).
1217  // Don't do this for Win64, it needs to realign the stack after the prologue.
1218  if (!IsWin64Prologue && !IsFunclet && TRI->needsStackRealignment(MF)) {
1219  assert(HasFP && "There should be a frame pointer if stack is realigned.");
1220  BuildStackAlignAND(MBB, MBBI, DL, StackPtr, MaxAlign);
1221 
1222  if (NeedsWinCFI) {
1223  HasWinCFI = true;
1224  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlign))
1225  .addImm(MaxAlign)
1227  }
1228  }
1229 
1230  // If there is an SUB32ri of ESP immediately before this instruction, merge
1231  // the two. This can be the case when tail call elimination is enabled and
1232  // the callee has more arguments then the caller.
1233  NumBytes -= mergeSPUpdates(MBB, MBBI, true);
1234 
1235  // Adjust stack pointer: ESP -= numbytes.
1236 
1237  // Windows and cygwin/mingw require a prologue helper routine when allocating
1238  // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
1239  // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
1240  // stack and adjust the stack pointer in one go. The 64-bit version of
1241  // __chkstk is only responsible for probing the stack. The 64-bit prologue is
1242  // responsible for adjusting the stack pointer. Touching the stack at 4K
1243  // increments is necessary to ensure that the guard pages used by the OS
1244  // virtual memory manager are allocated in correct sequence.
1245  uint64_t AlignedNumBytes = NumBytes;
1246  if (IsWin64Prologue && !IsFunclet && TRI->needsStackRealignment(MF))
1247  AlignedNumBytes = alignTo(AlignedNumBytes, MaxAlign);
1248  if (AlignedNumBytes >= StackProbeSize && UseStackProbe) {
1249  assert(!X86FI->getUsesRedZone() &&
1250  "The Red Zone is not accounted for in stack probes");
1251 
1252  // Check whether EAX is livein for this block.
1253  bool isEAXAlive = isEAXLiveIn(MBB);
1254 
1255  if (isEAXAlive) {
1256  if (Is64Bit) {
1257  // Save RAX
1258  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
1259  .addReg(X86::RAX, RegState::Kill)
1261  } else {
1262  // Save EAX
1263  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1264  .addReg(X86::EAX, RegState::Kill)
1266  }
1267  }
1268 
1269  if (Is64Bit) {
1270  // Handle the 64-bit Windows ABI case where we need to call __chkstk.
1271  // Function prologue is responsible for adjusting the stack pointer.
1272  int Alloc = isEAXAlive ? NumBytes - 8 : NumBytes;
1273  if (isUInt<32>(Alloc)) {
1274  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1275  .addImm(Alloc)
1277  } else if (isInt<32>(Alloc)) {
1278  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri32), X86::RAX)
1279  .addImm(Alloc)
1281  } else {
1282  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
1283  .addImm(Alloc)
1285  }
1286  } else {
1287  // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
1288  // We'll also use 4 already allocated bytes for EAX.
1289  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1290  .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
1292  }
1293 
1294  // Call __chkstk, __chkstk_ms, or __alloca.
1295  emitStackProbe(MF, MBB, MBBI, DL, true);
1296 
1297  if (isEAXAlive) {
1298  // Restore RAX/EAX
1299  MachineInstr *MI;
1300  if (Is64Bit)
1301  MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV64rm), X86::RAX),
1302  StackPtr, false, NumBytes - 8);
1303  else
1304  MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm), X86::EAX),
1305  StackPtr, false, NumBytes - 4);
1307  MBB.insert(MBBI, MI);
1308  }
1309  } else if (NumBytes) {
1310  emitSPUpdate(MBB, MBBI, DL, -(int64_t)NumBytes, /*InEpilogue=*/false);
1311  }
1312 
1313  if (NeedsWinCFI && NumBytes) {
1314  HasWinCFI = true;
1315  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
1316  .addImm(NumBytes)
1318  }
1319 
1320  int SEHFrameOffset = 0;
1321  unsigned SPOrEstablisher;
1322  if (IsFunclet) {
1323  if (IsClrFunclet) {
1324  // The establisher parameter passed to a CLR funclet is actually a pointer
1325  // to the (mostly empty) frame of its nearest enclosing funclet; we have
1326  // to find the root function establisher frame by loading the PSPSym from
1327  // the intermediate frame.
1328  unsigned PSPSlotOffset = getPSPSlotOffsetFromSP(MF);
1329  MachinePointerInfo NoInfo;
1330  MBB.addLiveIn(Establisher);
1331  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), Establisher),
1332  Establisher, false, PSPSlotOffset)
1335  ;
1336  // Save the root establisher back into the current funclet's (mostly
1337  // empty) frame, in case a sub-funclet or the GC needs it.
1338  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr,
1339  false, PSPSlotOffset)
1340  .addReg(Establisher)
1341  .addMemOperand(
1344  SlotSize, SlotSize));
1345  }
1346  SPOrEstablisher = Establisher;
1347  } else {
1348  SPOrEstablisher = StackPtr;
1349  }
1350 
1351  if (IsWin64Prologue && HasFP) {
1352  // Set RBP to a small fixed offset from RSP. In the funclet case, we base
1353  // this calculation on the incoming establisher, which holds the value of
1354  // RSP from the parent frame at the end of the prologue.
1355  SEHFrameOffset = calculateSetFPREG(ParentFrameNumBytes);
1356  if (SEHFrameOffset)
1357  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
1358  SPOrEstablisher, false, SEHFrameOffset);
1359  else
1360  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FramePtr)
1361  .addReg(SPOrEstablisher);
1362 
1363  // If this is not a funclet, emit the CFI describing our frame pointer.
1364  if (NeedsWinCFI && !IsFunclet) {
1365  assert(!NeedsWinFPO && "this setframe incompatible with FPO data");
1366  HasWinCFI = true;
1367  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1368  .addImm(FramePtr)
1369  .addImm(SEHFrameOffset)
1371  if (isAsynchronousEHPersonality(Personality))
1372  MF.getWinEHFuncInfo()->SEHSetFrameOffset = SEHFrameOffset;
1373  }
1374  } else if (IsFunclet && STI.is32Bit()) {
1375  // Reset EBP / ESI to something good for funclets.
1376  MBBI = restoreWin32EHStackPointers(MBB, MBBI, DL);
1377  // If we're a catch funclet, we can be returned to via catchret. Save ESP
1378  // into the registration node so that the runtime will restore it for us.
1379  if (!MBB.isCleanupFuncletEntry()) {
1380  assert(Personality == EHPersonality::MSVC_CXX);
1381  unsigned FrameReg;
1382  int FI = MF.getWinEHFuncInfo()->EHRegNodeFrameIndex;
1383  int64_t EHRegOffset = getFrameIndexReference(MF, FI, FrameReg);
1384  // ESP is the first field, so no extra displacement is needed.
1385  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32mr)), FrameReg,
1386  false, EHRegOffset)
1387  .addReg(X86::ESP);
1388  }
1389  }
1390 
1391  while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) {
1392  const MachineInstr &FrameInstr = *MBBI;
1393  ++MBBI;
1394 
1395  if (NeedsWinCFI) {
1396  int FI;
1397  if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
1398  if (X86::FR64RegClass.contains(Reg)) {
1399  unsigned IgnoredFrameReg;
1400  int Offset = getFrameIndexReference(MF, FI, IgnoredFrameReg);
1401  Offset += SEHFrameOffset;
1402 
1403  HasWinCFI = true;
1404  assert(!NeedsWinFPO && "SEH_SaveXMM incompatible with FPO data");
1405  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
1406  .addImm(Reg)
1407  .addImm(Offset)
1409  }
1410  }
1411  }
1412  }
1413 
1414  if (NeedsWinCFI && HasWinCFI)
1415  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
1416  .setMIFlag(MachineInstr::FrameSetup);
1417 
1418  if (FnHasClrFunclet && !IsFunclet) {
1419  // Save the so-called Initial-SP (i.e. the value of the stack pointer
1420  // immediately after the prolog) into the PSPSlot so that funclets
1421  // and the GC can recover it.
1422  unsigned PSPSlotOffset = getPSPSlotOffsetFromSP(MF);
1423  auto PSPInfo = MachinePointerInfo::getFixedStack(
1424  MF, MF.getWinEHFuncInfo()->PSPSymFrameIdx);
1425  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr, false,
1426  PSPSlotOffset)
1427  .addReg(StackPtr)
1430  SlotSize, SlotSize));
1431  }
1432 
1433  // Realign stack after we spilled callee-saved registers (so that we'll be
1434  // able to calculate their offsets from the frame pointer).
1435  // Win64 requires aligning the stack after the prologue.
1436  if (IsWin64Prologue && TRI->needsStackRealignment(MF)) {
1437  assert(HasFP && "There should be a frame pointer if stack is realigned.");
1438  BuildStackAlignAND(MBB, MBBI, DL, SPOrEstablisher, MaxAlign);
1439  }
1440 
1441  // We already dealt with stack realignment and funclets above.
1442  if (IsFunclet && STI.is32Bit())
1443  return;
1444 
1445  // If we need a base pointer, set it up here. It's whatever the value
1446  // of the stack pointer is at this point. Any variable size objects
1447  // will be allocated after this, so we can still use the base pointer
1448  // to reference locals.
1449  if (TRI->hasBasePointer(MF)) {
1450  // Update the base pointer with the current stack pointer.
1451  unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
1452  BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
1453  .addReg(SPOrEstablisher)
1455  if (X86FI->getRestoreBasePointer()) {
1456  // Stash value of base pointer. Saving RSP instead of EBP shortens
1457  // dependence chain. Used by SjLj EH.
1458  unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1459  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
1460  FramePtr, true, X86FI->getRestoreBasePointerOffset())
1461  .addReg(SPOrEstablisher)
1463  }
1464 
1465  if (X86FI->getHasSEHFramePtrSave() && !IsFunclet) {
1466  // Stash the value of the frame pointer relative to the base pointer for
1467  // Win32 EH. This supports Win32 EH, which does the inverse of the above:
1468  // it recovers the frame pointer from the base pointer rather than the
1469  // other way around.
1470  unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1471  unsigned UsedReg;
1472  int Offset =
1473  getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg);
1474  assert(UsedReg == BasePtr);
1475  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), UsedReg, true, Offset)
1476  .addReg(FramePtr)
1478  }
1479  }
1480 
1481  if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
1482  // Mark end of stack pointer adjustment.
1483  if (!HasFP && NumBytes) {
1484  // Define the current CFA rule to use the provided offset.
1485  assert(StackSize);
1487  nullptr, -StackSize + stackGrowth));
1488  }
1489 
1490  // Emit DWARF info specifying the offsets of the callee-saved registers.
1491  emitCalleeSavedFrameMoves(MBB, MBBI, DL);
1492  }
1493 
1494  // X86 Interrupt handling function cannot assume anything about the direction
1495  // flag (DF in EFLAGS register). Clear this flag by creating "cld" instruction
1496  // in each prologue of interrupt handler function.
1497  //
1498  // FIXME: Create "cld" instruction only in these cases:
1499  // 1. The interrupt handling function uses any of the "rep" instructions.
1500  // 2. Interrupt handling function calls another function.
1501  //
1503  BuildMI(MBB, MBBI, DL, TII.get(X86::CLD))
1504  .setMIFlag(MachineInstr::FrameSetup);
1505 
1506  // At this point we know if the function has WinCFI or not.
1507  MF.setHasWinCFI(HasWinCFI);
1508 }
1509 
1511  const MachineFunction &MF) const {
1512  // We can't use LEA instructions for adjusting the stack pointer if we don't
1513  // have a frame pointer in the Win64 ABI. Only ADD instructions may be used
1514  // to deallocate the stack.
1515  // This means that we can use LEA for SP in two situations:
1516  // 1. We *aren't* using the Win64 ABI which means we are free to use LEA.
1517  // 2. We *have* a frame pointer which means we are permitted to use LEA.
1518  return !MF.getTarget().getMCAsmInfo()->usesWindowsCFI() || hasFP(MF);
1519 }
1520 
1522  switch (MI.getOpcode()) {
1523  case X86::CATCHRET:
1524  case X86::CLEANUPRET:
1525  return true;
1526  default:
1527  return false;
1528  }
1529  llvm_unreachable("impossible");
1530 }
1531 
1532 // CLR funclets use a special "Previous Stack Pointer Symbol" slot on the
1533 // stack. It holds a pointer to the bottom of the root function frame. The
1534 // establisher frame pointer passed to a nested funclet may point to the
1535 // (mostly empty) frame of its parent funclet, but it will need to find
1536 // the frame of the root function to access locals. To facilitate this,
1537 // every funclet copies the pointer to the bottom of the root function
1538 // frame into a PSPSym slot in its own (mostly empty) stack frame. Using the
1539 // same offset for the PSPSym in the root function frame that's used in the
1540 // funclets' frames allows each funclet to dynamically accept any ancestor
1541 // frame as its establisher argument (the runtime doesn't guarantee the
1542 // immediate parent for some reason lost to history), and also allows the GC,
1543 // which uses the PSPSym for some bookkeeping, to find it in any funclet's
1544 // frame with only a single offset reported for the entire method.
1545 unsigned
1546 X86FrameLowering::getPSPSlotOffsetFromSP(const MachineFunction &MF) const {
1547  const WinEHFuncInfo &Info = *MF.getWinEHFuncInfo();
1548  unsigned SPReg;
1550  /*IgnoreSPUpdates*/ true);
1551  assert(Offset >= 0 && SPReg == TRI->getStackRegister());
1552  return static_cast<unsigned>(Offset);
1553 }
1554 
1555 unsigned
1556 X86FrameLowering::getWinEHFuncletFrameSize(const MachineFunction &MF) const {
1557  // This is the size of the pushed CSRs.
1558  unsigned CSSize =
1559  MF.getInfo<X86MachineFunctionInfo>()->getCalleeSavedFrameSize();
1560  // This is the amount of stack a funclet needs to allocate.
1561  unsigned UsedSize;
1562  EHPersonality Personality =
1564  if (Personality == EHPersonality::CoreCLR) {
1565  // CLR funclets need to hold enough space to include the PSPSym, at the
1566  // same offset from the stack pointer (immediately after the prolog) as it
1567  // resides at in the main function.
1568  UsedSize = getPSPSlotOffsetFromSP(MF) + SlotSize;
1569  } else {
1570  // Other funclets just need enough stack for outgoing call arguments.
1571  UsedSize = MF.getFrameInfo().getMaxCallFrameSize();
1572  }
1573  // RBP is not included in the callee saved register block. After pushing RBP,
1574  // everything is 16 byte aligned. Everything we allocate before an outgoing
1575  // call must also be 16 byte aligned.
1576  unsigned FrameSizeMinusRBP = alignTo(CSSize + UsedSize, getStackAlignment());
1577  // Subtract out the size of the callee saved registers. This is how much stack
1578  // each funclet will allocate.
1579  return FrameSizeMinusRBP - CSSize;
1580 }
1581 
1582 static bool isTailCallOpcode(unsigned Opc) {
1583  return Opc == X86::TCRETURNri || Opc == X86::TCRETURNdi ||
1584  Opc == X86::TCRETURNmi ||
1585  Opc == X86::TCRETURNri64 || Opc == X86::TCRETURNdi64 ||
1586  Opc == X86::TCRETURNmi64;
1587 }
1588 
1590  MachineBasicBlock &MBB) const {
1591  const MachineFrameInfo &MFI = MF.getFrameInfo();
1595  DebugLoc DL;
1596  if (MBBI != MBB.end())
1597  DL = MBBI->getDebugLoc();
1598  // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
1599  const bool Is64BitILP32 = STI.isTarget64BitILP32();
1600  unsigned FramePtr = TRI->getFrameRegister(MF);
1601  unsigned MachineFramePtr =
1602  Is64BitILP32 ? getX86SubSuperRegister(FramePtr, 64) : FramePtr;
1603 
1604  bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1605  bool NeedsWin64CFI =
1606  IsWin64Prologue && MF.getFunction().needsUnwindTableEntry();
1607  bool IsFunclet = MBBI == MBB.end() ? false : isFuncletReturnInstr(*MBBI);
1608 
1609  // Get the number of bytes to allocate from the FrameInfo.
1610  uint64_t StackSize = MFI.getStackSize();
1611  uint64_t MaxAlign = calculateMaxStackAlign(MF);
1612  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1613  bool HasFP = hasFP(MF);
1614  uint64_t NumBytes = 0;
1615 
1616  bool NeedsDwarfCFI =
1617  (!MF.getTarget().getTargetTriple().isOSDarwin() &&
1618  !MF.getTarget().getTargetTriple().isOSWindows()) &&
1620 
1621  if (IsFunclet) {
1622  assert(HasFP && "EH funclets without FP not yet implemented");
1623  NumBytes = getWinEHFuncletFrameSize(MF);
1624  } else if (HasFP) {
1625  // Calculate required stack adjustment.
1626  uint64_t FrameSize = StackSize - SlotSize;
1627  NumBytes = FrameSize - CSSize;
1628 
1629  // Callee-saved registers were pushed on stack before the stack was
1630  // realigned.
1631  if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
1632  NumBytes = alignTo(FrameSize, MaxAlign);
1633  } else {
1634  NumBytes = StackSize - CSSize;
1635  }
1636  uint64_t SEHStackAllocAmt = NumBytes;
1637 
1638  if (HasFP) {
1639  // Pop EBP.
1640  BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::POP64r : X86::POP32r),
1641  MachineFramePtr)
1642  .setMIFlag(MachineInstr::FrameDestroy);
1643  if (NeedsDwarfCFI) {
1644  unsigned DwarfStackPtr =
1645  TRI->getDwarfRegNum(Is64Bit ? X86::RSP : X86::ESP, true);
1647  nullptr, DwarfStackPtr, -SlotSize));
1648  --MBBI;
1649  }
1650  }
1651 
1652  MachineBasicBlock::iterator FirstCSPop = MBBI;
1653  // Skip the callee-saved pop instructions.
1654  while (MBBI != MBB.begin()) {
1655  MachineBasicBlock::iterator PI = std::prev(MBBI);
1656  unsigned Opc = PI->getOpcode();
1657 
1658  if (Opc != X86::DBG_VALUE && !PI->isTerminator()) {
1659  if ((Opc != X86::POP32r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
1660  (Opc != X86::POP64r || !PI->getFlag(MachineInstr::FrameDestroy)))
1661  break;
1662  FirstCSPop = PI;
1663  }
1664 
1665  --MBBI;
1666  }
1667  MBBI = FirstCSPop;
1668 
1669  if (IsFunclet && Terminator->getOpcode() == X86::CATCHRET)
1670  emitCatchRetReturnValue(MBB, FirstCSPop, &*Terminator);
1671 
1672  if (MBBI != MBB.end())
1673  DL = MBBI->getDebugLoc();
1674 
1675  // If there is an ADD32ri or SUB32ri of ESP immediately before this
1676  // instruction, merge the two instructions.
1677  if (NumBytes || MFI.hasVarSizedObjects())
1678  NumBytes += mergeSPUpdates(MBB, MBBI, true);
1679 
1680  // If dynamic alloca is used, then reset esp to point to the last callee-saved
1681  // slot before popping them off! Same applies for the case, when stack was
1682  // realigned. Don't do this if this was a funclet epilogue, since the funclets
1683  // will not do realignment or dynamic stack allocation.
1684  if ((TRI->needsStackRealignment(MF) || MFI.hasVarSizedObjects()) &&
1685  !IsFunclet) {
1686  if (TRI->needsStackRealignment(MF))
1687  MBBI = FirstCSPop;
1688  unsigned SEHFrameOffset = calculateSetFPREG(SEHStackAllocAmt);
1689  uint64_t LEAAmount =
1690  IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : -CSSize;
1691 
1692  // There are only two legal forms of epilogue:
1693  // - add SEHAllocationSize, %rsp
1694  // - lea SEHAllocationSize(%FramePtr), %rsp
1695  //
1696  // 'mov %FramePtr, %rsp' will not be recognized as an epilogue sequence.
1697  // However, we may use this sequence if we have a frame pointer because the
1698  // effects of the prologue can safely be undone.
1699  if (LEAAmount != 0) {
1700  unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
1701  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1702  FramePtr, false, LEAAmount);
1703  --MBBI;
1704  } else {
1705  unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
1706  BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1707  .addReg(FramePtr);
1708  --MBBI;
1709  }
1710  } else if (NumBytes) {
1711  // Adjust stack pointer back: ESP += numbytes.
1712  emitSPUpdate(MBB, MBBI, DL, NumBytes, /*InEpilogue=*/true);
1713  if (!hasFP(MF) && NeedsDwarfCFI) {
1714  // Define the current CFA rule to use the provided offset.
1716  nullptr, -CSSize - SlotSize));
1717  }
1718  --MBBI;
1719  }
1720 
1721  // Windows unwinder will not invoke function's exception handler if IP is
1722  // either in prologue or in epilogue. This behavior causes a problem when a
1723  // call immediately precedes an epilogue, because the return address points
1724  // into the epilogue. To cope with that, we insert an epilogue marker here,
1725  // then replace it with a 'nop' if it ends up immediately after a CALL in the
1726  // final emitted code.
1727  if (NeedsWin64CFI && MF.hasWinCFI())
1728  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
1729 
1730  if (!hasFP(MF) && NeedsDwarfCFI) {
1731  MBBI = FirstCSPop;
1732  int64_t Offset = -CSSize - SlotSize;
1733  // Mark callee-saved pop instruction.
1734  // Define the current CFA rule to use the provided offset.
1735  while (MBBI != MBB.end()) {
1736  MachineBasicBlock::iterator PI = MBBI;
1737  unsigned Opc = PI->getOpcode();
1738  ++MBBI;
1739  if (Opc == X86::POP32r || Opc == X86::POP64r) {
1740  Offset += SlotSize;
1741  BuildCFI(MBB, MBBI, DL,
1742  MCCFIInstruction::createDefCfaOffset(nullptr, Offset));
1743  }
1744  }
1745  }
1746 
1747  if (Terminator == MBB.end() || !isTailCallOpcode(Terminator->getOpcode())) {
1748  // Add the return addr area delta back since we are not tail calling.
1749  int Offset = -1 * X86FI->getTCReturnAddrDelta();
1750  assert(Offset >= 0 && "TCDelta should never be positive");
1751  if (Offset) {
1752  // Check for possible merge with preceding ADD instruction.
1753  Offset += mergeSPUpdates(MBB, Terminator, true);
1754  emitSPUpdate(MBB, Terminator, DL, Offset, /*InEpilogue=*/true);
1755  }
1756  }
1757 }
1758 
1760  unsigned &FrameReg) const {
1761  const MachineFrameInfo &MFI = MF.getFrameInfo();
1762 
1763  bool IsFixed = MFI.isFixedObjectIndex(FI);
1764  // We can't calculate offset from frame pointer if the stack is realigned,
1765  // so enforce usage of stack/base pointer. The base pointer is used when we
1766  // have dynamic allocas in addition to dynamic realignment.
1767  if (TRI->hasBasePointer(MF))
1768  FrameReg = IsFixed ? TRI->getFramePtr() : TRI->getBaseRegister();
1769  else if (TRI->needsStackRealignment(MF))
1770  FrameReg = IsFixed ? TRI->getFramePtr() : TRI->getStackRegister();
1771  else
1772  FrameReg = TRI->getFrameRegister(MF);
1773 
1774  // Offset will hold the offset from the stack pointer at function entry to the
1775  // object.
1776  // We need to factor in additional offsets applied during the prologue to the
1777  // frame, base, and stack pointer depending on which is used.
1778  int Offset = MFI.getObjectOffset(FI) - getOffsetOfLocalArea();
1780  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1781  uint64_t StackSize = MFI.getStackSize();
1782  bool HasFP = hasFP(MF);
1783  bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1784  int64_t FPDelta = 0;
1785 
1786  // In an x86 interrupt, remove the offset we added to account for the return
1787  // address from any stack object allocated in the caller's frame. Interrupts
1788  // do not have a standard return address. Fixed objects in the current frame,
1789  // such as SSE register spills, should not get this treatment.
1791  Offset >= 0) {
1792  Offset += getOffsetOfLocalArea();
1793  }
1794 
1795  if (IsWin64Prologue) {
1796  assert(!MFI.hasCalls() || (StackSize % 16) == 8);
1797 
1798  // Calculate required stack adjustment.
1799  uint64_t FrameSize = StackSize - SlotSize;
1800  // If required, include space for extra hidden slot for stashing base pointer.
1801  if (X86FI->getRestoreBasePointer())
1802  FrameSize += SlotSize;
1803  uint64_t NumBytes = FrameSize - CSSize;
1804 
1805  uint64_t SEHFrameOffset = calculateSetFPREG(NumBytes);
1806  if (FI && FI == X86FI->getFAIndex())
1807  return -SEHFrameOffset;
1808 
1809  // FPDelta is the offset from the "traditional" FP location of the old base
1810  // pointer followed by return address and the location required by the
1811  // restricted Win64 prologue.
1812  // Add FPDelta to all offsets below that go through the frame pointer.
1813  FPDelta = FrameSize - SEHFrameOffset;
1814  assert((!MFI.hasCalls() || (FPDelta % 16) == 0) &&
1815  "FPDelta isn't aligned per the Win64 ABI!");
1816  }
1817 
1818 
1819  if (TRI->hasBasePointer(MF)) {
1820  assert(HasFP && "VLAs and dynamic stack realign, but no FP?!");
1821  if (FI < 0) {
1822  // Skip the saved EBP.
1823  return Offset + SlotSize + FPDelta;
1824  } else {
1825  assert((-(Offset + StackSize)) % MFI.getObjectAlignment(FI) == 0);
1826  return Offset + StackSize;
1827  }
1828  } else if (TRI->needsStackRealignment(MF)) {
1829  if (FI < 0) {
1830  // Skip the saved EBP.
1831  return Offset + SlotSize + FPDelta;
1832  } else {
1833  assert((-(Offset + StackSize)) % MFI.getObjectAlignment(FI) == 0);
1834  return Offset + StackSize;
1835  }
1836  // FIXME: Support tail calls
1837  } else {
1838  if (!HasFP)
1839  return Offset + StackSize;
1840 
1841  // Skip the saved EBP.
1842  Offset += SlotSize;
1843 
1844  // Skip the RETADDR move area
1845  int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1846  if (TailCallReturnAddrDelta < 0)
1847  Offset -= TailCallReturnAddrDelta;
1848  }
1849 
1850  return Offset + FPDelta;
1851 }
1852 
1854  int FI, unsigned &FrameReg,
1855  int Adjustment) const {
1856  const MachineFrameInfo &MFI = MF.getFrameInfo();
1857  FrameReg = TRI->getStackRegister();
1858  return MFI.getObjectOffset(FI) - getOffsetOfLocalArea() + Adjustment;
1859 }
1860 
1861 int
1863  int FI, unsigned &FrameReg,
1864  bool IgnoreSPUpdates) const {
1865 
1866  const MachineFrameInfo &MFI = MF.getFrameInfo();
1867  // Does not include any dynamic realign.
1868  const uint64_t StackSize = MFI.getStackSize();
1869  // LLVM arranges the stack as follows:
1870  // ...
1871  // ARG2
1872  // ARG1
1873  // RETADDR
1874  // PUSH RBP <-- RBP points here
1875  // PUSH CSRs
1876  // ~~~~~~~ <-- possible stack realignment (non-win64)
1877  // ...
1878  // STACK OBJECTS
1879  // ... <-- RSP after prologue points here
1880  // ~~~~~~~ <-- possible stack realignment (win64)
1881  //
1882  // if (hasVarSizedObjects()):
1883  // ... <-- "base pointer" (ESI/RBX) points here
1884  // DYNAMIC ALLOCAS
1885  // ... <-- RSP points here
1886  //
1887  // Case 1: In the simple case of no stack realignment and no dynamic
1888  // allocas, both "fixed" stack objects (arguments and CSRs) are addressable
1889  // with fixed offsets from RSP.
1890  //
1891  // Case 2: In the case of stack realignment with no dynamic allocas, fixed
1892  // stack objects are addressed with RBP and regular stack objects with RSP.
1893  //
1894  // Case 3: In the case of dynamic allocas and stack realignment, RSP is used
1895  // to address stack arguments for outgoing calls and nothing else. The "base
1896  // pointer" points to local variables, and RBP points to fixed objects.
1897  //
1898  // In cases 2 and 3, we can only answer for non-fixed stack objects, and the
1899  // answer we give is relative to the SP after the prologue, and not the
1900  // SP in the middle of the function.
1901 
1902  if (MFI.isFixedObjectIndex(FI) && TRI->needsStackRealignment(MF) &&
1903  !STI.isTargetWin64())
1904  return getFrameIndexReference(MF, FI, FrameReg);
1905 
1906  // If !hasReservedCallFrame the function might have SP adjustement in the
1907  // body. So, even though the offset is statically known, it depends on where
1908  // we are in the function.
1910  if (!IgnoreSPUpdates && !TFI->hasReservedCallFrame(MF))
1911  return getFrameIndexReference(MF, FI, FrameReg);
1912 
1913  // We don't handle tail calls, and shouldn't be seeing them either.
1915  "we don't handle this case!");
1916 
1917  // This is how the math works out:
1918  //
1919  // %rsp grows (i.e. gets lower) left to right. Each box below is
1920  // one word (eight bytes). Obj0 is the stack slot we're trying to
1921  // get to.
1922  //
1923  // ----------------------------------
1924  // | BP | Obj0 | Obj1 | ... | ObjN |
1925  // ----------------------------------
1926  // ^ ^ ^ ^
1927  // A B C E
1928  //
1929  // A is the incoming stack pointer.
1930  // (B - A) is the local area offset (-8 for x86-64) [1]
1931  // (C - A) is the Offset returned by MFI.getObjectOffset for Obj0 [2]
1932  //
1933  // |(E - B)| is the StackSize (absolute value, positive). For a
1934  // stack that grown down, this works out to be (B - E). [3]
1935  //
1936  // E is also the value of %rsp after stack has been set up, and we
1937  // want (C - E) -- the value we can add to %rsp to get to Obj0. Now
1938  // (C - E) == (C - A) - (B - A) + (B - E)
1939  // { Using [1], [2] and [3] above }
1940  // == getObjectOffset - LocalAreaOffset + StackSize
1941 
1942  return getFrameIndexReferenceSP(MF, FI, FrameReg, StackSize);
1943 }
1944 
1947  std::vector<CalleeSavedInfo> &CSI) const {
1948  MachineFrameInfo &MFI = MF.getFrameInfo();
1950 
1951  unsigned CalleeSavedFrameSize = 0;
1952  int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
1953 
1954  int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1955 
1956  if (TailCallReturnAddrDelta < 0) {
1957  // create RETURNADDR area
1958  // arg
1959  // arg
1960  // RETADDR
1961  // { ...
1962  // RETADDR area
1963  // ...
1964  // }
1965  // [EBP]
1966  MFI.CreateFixedObject(-TailCallReturnAddrDelta,
1967  TailCallReturnAddrDelta - SlotSize, true);
1968  }
1969 
1970  // Spill the BasePtr if it's used.
1971  if (this->TRI->hasBasePointer(MF)) {
1972  // Allocate a spill slot for EBP if we have a base pointer and EH funclets.
1973  if (MF.hasEHFunclets()) {
1974  int FI = MFI.CreateSpillStackObject(SlotSize, SlotSize);
1975  X86FI->setHasSEHFramePtrSave(true);
1976  X86FI->setSEHFramePtrSaveIndex(FI);
1977  }
1978  }
1979 
1980  if (hasFP(MF)) {
1981  // emitPrologue always spills frame register the first thing.
1982  SpillSlotOffset -= SlotSize;
1983  MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1984 
1985  // Since emitPrologue and emitEpilogue will handle spilling and restoring of
1986  // the frame register, we can delete it from CSI list and not have to worry
1987  // about avoiding it later.
1988  unsigned FPReg = TRI->getFrameRegister(MF);
1989  for (unsigned i = 0; i < CSI.size(); ++i) {
1990  if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
1991  CSI.erase(CSI.begin() + i);
1992  break;
1993  }
1994  }
1995  }
1996 
1997  // Assign slots for GPRs. It increases frame size.
1998  for (unsigned i = CSI.size(); i != 0; --i) {
1999  unsigned Reg = CSI[i - 1].getReg();
2000 
2001  if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
2002  continue;
2003 
2004  SpillSlotOffset -= SlotSize;
2005  CalleeSavedFrameSize += SlotSize;
2006 
2007  int SlotIndex = MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
2008  CSI[i - 1].setFrameIdx(SlotIndex);
2009  }
2010 
2011  X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
2012  MFI.setCVBytesOfCalleeSavedRegisters(CalleeSavedFrameSize);
2013 
2014  // Assign slots for XMMs.
2015  for (unsigned i = CSI.size(); i != 0; --i) {
2016  unsigned Reg = CSI[i - 1].getReg();
2017  if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2018  continue;
2019 
2020  // If this is k-register make sure we lookup via the largest legal type.
2021  MVT VT = MVT::Other;
2022  if (X86::VK16RegClass.contains(Reg))
2023  VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2024 
2025  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2026  unsigned Size = TRI->getSpillSize(*RC);
2027  unsigned Align = TRI->getSpillAlignment(*RC);
2028  // ensure alignment
2029  SpillSlotOffset -= std::abs(SpillSlotOffset) % Align;
2030  // spill into slot
2031  SpillSlotOffset -= Size;
2032  int SlotIndex = MFI.CreateFixedSpillStackObject(Size, SpillSlotOffset);
2033  CSI[i - 1].setFrameIdx(SlotIndex);
2034  MFI.ensureMaxAlignment(Align);
2035  }
2036 
2037  return true;
2038 }
2039 
2042  const std::vector<CalleeSavedInfo> &CSI,
2043  const TargetRegisterInfo *TRI) const {
2044  DebugLoc DL = MBB.findDebugLoc(MI);
2045 
2046  // Don't save CSRs in 32-bit EH funclets. The caller saves EBX, EBP, ESI, EDI
2047  // for us, and there are no XMM CSRs on Win32.
2048  if (MBB.isEHFuncletEntry() && STI.is32Bit() && STI.isOSWindows())
2049  return true;
2050 
2051  // Push GPRs. It increases frame size.
2052  const MachineFunction &MF = *MBB.getParent();
2053  unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
2054  for (unsigned i = CSI.size(); i != 0; --i) {
2055  unsigned Reg = CSI[i - 1].getReg();
2056 
2057  if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
2058  continue;
2059 
2060  const MachineRegisterInfo &MRI = MF.getRegInfo();
2061  bool isLiveIn = MRI.isLiveIn(Reg);
2062  if (!isLiveIn)
2063  MBB.addLiveIn(Reg);
2064 
2065  // Decide whether we can add a kill flag to the use.
2066  bool CanKill = !isLiveIn;
2067  // Check if any subregister is live-in
2068  if (CanKill) {
2069  for (MCRegAliasIterator AReg(Reg, TRI, false); AReg.isValid(); ++AReg) {
2070  if (MRI.isLiveIn(*AReg)) {
2071  CanKill = false;
2072  break;
2073  }
2074  }
2075  }
2076 
2077  // Do not set a kill flag on values that are also marked as live-in. This
2078  // happens with the @llvm-returnaddress intrinsic and with arguments
2079  // passed in callee saved registers.
2080  // Omitting the kill flags is conservatively correct even if the live-in
2081  // is not used after all.
2082  BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, getKillRegState(CanKill))
2083  .setMIFlag(MachineInstr::FrameSetup);
2084  }
2085 
2086  // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
2087  // It can be done by spilling XMMs to stack frame.
2088  for (unsigned i = CSI.size(); i != 0; --i) {
2089  unsigned Reg = CSI[i-1].getReg();
2090  if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2091  continue;
2092 
2093  // If this is k-register make sure we lookup via the largest legal type.
2094  MVT VT = MVT::Other;
2095  if (X86::VK16RegClass.contains(Reg))
2096  VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2097 
2098  // Add the callee-saved register as live-in. It's killed at the spill.
2099  MBB.addLiveIn(Reg);
2100  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2101 
2102  TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
2103  TRI);
2104  --MI;
2105  MI->setFlag(MachineInstr::FrameSetup);
2106  ++MI;
2107  }
2108 
2109  return true;
2110 }
2111 
2112 void X86FrameLowering::emitCatchRetReturnValue(MachineBasicBlock &MBB,
2114  MachineInstr *CatchRet) const {
2115  // SEH shouldn't use catchret.
2117  MBB.getParent()->getFunction().getPersonalityFn())) &&
2118  "SEH should not use CATCHRET");
2119  DebugLoc DL = CatchRet->getDebugLoc();
2120  MachineBasicBlock *CatchRetTarget = CatchRet->getOperand(0).getMBB();
2121 
2122  // Fill EAX/RAX with the address of the target block.
2123  if (STI.is64Bit()) {
2124  // LEA64r CatchRetTarget(%rip), %rax
2125  BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), X86::RAX)
2126  .addReg(X86::RIP)
2127  .addImm(0)
2128  .addReg(0)
2129  .addMBB(CatchRetTarget)
2130  .addReg(0);
2131  } else {
2132  // MOV32ri $CatchRetTarget, %eax
2133  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
2134  .addMBB(CatchRetTarget);
2135  }
2136 
2137  // Record that we've taken the address of CatchRetTarget and no longer just
2138  // reference it in a terminator.
2139  CatchRetTarget->setHasAddressTaken();
2140 }
2141 
2144  std::vector<CalleeSavedInfo> &CSI,
2145  const TargetRegisterInfo *TRI) const {
2146  if (CSI.empty())
2147  return false;
2148 
2149  if (MI != MBB.end() && isFuncletReturnInstr(*MI) && STI.isOSWindows()) {
2150  // Don't restore CSRs in 32-bit EH funclets. Matches
2151  // spillCalleeSavedRegisters.
2152  if (STI.is32Bit())
2153  return true;
2154  // Don't restore CSRs before an SEH catchret. SEH except blocks do not form
2155  // funclets. emitEpilogue transforms these to normal jumps.
2156  if (MI->getOpcode() == X86::CATCHRET) {
2157  const Function &F = MBB.getParent()->getFunction();
2158  bool IsSEH = isAsynchronousEHPersonality(
2160  if (IsSEH)
2161  return true;
2162  }
2163  }
2164 
2165  DebugLoc DL = MBB.findDebugLoc(MI);
2166 
2167  // Reload XMMs from stack frame.
2168  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2169  unsigned Reg = CSI[i].getReg();
2170  if (X86::GR64RegClass.contains(Reg) ||
2171  X86::GR32RegClass.contains(Reg))
2172  continue;
2173 
2174  // If this is k-register make sure we lookup via the largest legal type.
2175  MVT VT = MVT::Other;
2176  if (X86::VK16RegClass.contains(Reg))
2177  VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2178 
2179  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2180  TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
2181  }
2182 
2183  // POP GPRs.
2184  unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
2185  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2186  unsigned Reg = CSI[i].getReg();
2187  if (!X86::GR64RegClass.contains(Reg) &&
2188  !X86::GR32RegClass.contains(Reg))
2189  continue;
2190 
2191  BuildMI(MBB, MI, DL, TII.get(Opc), Reg)
2192  .setMIFlag(MachineInstr::FrameDestroy);
2193  }
2194  return true;
2195 }
2196 
2198  BitVector &SavedRegs,
2199  RegScavenger *RS) const {
2200  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
2201 
2202  // Spill the BasePtr if it's used.
2203  if (TRI->hasBasePointer(MF)){
2204  unsigned BasePtr = TRI->getBaseRegister();
2205  if (STI.isTarget64BitILP32())
2206  BasePtr = getX86SubSuperRegister(BasePtr, 64);
2207  SavedRegs.set(BasePtr);
2208  }
2209 }
2210 
2211 static bool
2213  const Function &F = MF->getFunction();
2214  for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
2215  I != E; I++) {
2216  if (I->hasNestAttr())
2217  return true;
2218  }
2219  return false;
2220 }
2221 
2222 /// GetScratchRegister - Get a temp register for performing work in the
2223 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
2224 /// and the properties of the function either one or two registers will be
2225 /// needed. Set primary to true for the first register, false for the second.
2226 static unsigned
2227 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
2229 
2230  // Erlang stuff.
2231  if (CallingConvention == CallingConv::HiPE) {
2232  if (Is64Bit)
2233  return Primary ? X86::R14 : X86::R13;
2234  else
2235  return Primary ? X86::EBX : X86::EDI;
2236  }
2237 
2238  if (Is64Bit) {
2239  if (IsLP64)
2240  return Primary ? X86::R11 : X86::R12;
2241  else
2242  return Primary ? X86::R11D : X86::R12D;
2243  }
2244 
2245  bool IsNested = HasNestArgument(&MF);
2246 
2247  if (CallingConvention == CallingConv::X86_FastCall ||
2248  CallingConvention == CallingConv::Fast) {
2249  if (IsNested)
2250  report_fatal_error("Segmented stacks does not support fastcall with "
2251  "nested function.");
2252  return Primary ? X86::EAX : X86::ECX;
2253  }
2254  if (IsNested)
2255  return Primary ? X86::EDX : X86::EAX;
2256  return Primary ? X86::ECX : X86::EAX;
2257 }
2258 
2259 // The stack limit in the TCB is set to this many bytes above the actual stack
2260 // limit.
2261 static const uint64_t kSplitStackAvailable = 256;
2262 
2264  MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
2265  MachineFrameInfo &MFI = MF.getFrameInfo();
2266  uint64_t StackSize;
2267  unsigned TlsReg, TlsOffset;
2268  DebugLoc DL;
2269 
2270  // To support shrink-wrapping we would need to insert the new blocks
2271  // at the right place and update the branches to PrologueMBB.
2272  assert(&(*MF.begin()) == &PrologueMBB && "Shrink-wrapping not supported yet");
2273 
2274  unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2275  assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
2276  "Scratch register is live-in");
2277 
2278  if (MF.getFunction().isVarArg())
2279  report_fatal_error("Segmented stacks do not support vararg functions.");
2280  if (!STI.isTargetLinux() && !STI.isTargetDarwin() && !STI.isTargetWin32() &&
2281  !STI.isTargetWin64() && !STI.isTargetFreeBSD() &&
2283  report_fatal_error("Segmented stacks not supported on this platform.");
2284 
2285  // Eventually StackSize will be calculated by a link-time pass; which will
2286  // also decide whether checking code needs to be injected into this particular
2287  // prologue.
2288  StackSize = MFI.getStackSize();
2289 
2290  // Do not generate a prologue for leaf functions with a stack of size zero.
2291  // For non-leaf functions we have to allow for the possibility that the
2292  // callis to a non-split function, as in PR37807. This function could also
2293  // take the address of a non-split function. When the linker tries to adjust
2294  // its non-existent prologue, it would fail with an error. Mark the object
2295  // file so that such failures are not errors. See this Go language bug-report
2296  // https://go-review.googlesource.com/c/go/+/148819/
2297  if (StackSize == 0 && !MFI.hasTailCall()) {
2298  MF.getMMI().setHasNosplitStack(true);
2299  return;
2300  }
2301 
2302  MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
2303  MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
2305  bool IsNested = false;
2306 
2307  // We need to know if the function has a nest argument only in 64 bit mode.
2308  if (Is64Bit)
2309  IsNested = HasNestArgument(&MF);
2310 
2311  // The MOV R10, RAX needs to be in a different block, since the RET we emit in
2312  // allocMBB needs to be last (terminating) instruction.
2313 
2314  for (const auto &LI : PrologueMBB.liveins()) {
2315  allocMBB->addLiveIn(LI);
2316  checkMBB->addLiveIn(LI);
2317  }
2318 
2319  if (IsNested)
2320  allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
2321 
2322  MF.push_front(allocMBB);
2323  MF.push_front(checkMBB);
2324 
2325  // When the frame size is less than 256 we just compare the stack
2326  // boundary directly to the value of the stack pointer, per gcc.
2327  bool CompareStackPointer = StackSize < kSplitStackAvailable;
2328 
2329  // Read the limit off the current stacklet off the stack_guard location.
2330  if (Is64Bit) {
2331  if (STI.isTargetLinux()) {
2332  TlsReg = X86::FS;
2333  TlsOffset = IsLP64 ? 0x70 : 0x40;
2334  } else if (STI.isTargetDarwin()) {
2335  TlsReg = X86::GS;
2336  TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
2337  } else if (STI.isTargetWin64()) {
2338  TlsReg = X86::GS;
2339  TlsOffset = 0x28; // pvArbitrary, reserved for application use
2340  } else if (STI.isTargetFreeBSD()) {
2341  TlsReg = X86::FS;
2342  TlsOffset = 0x18;
2343  } else if (STI.isTargetDragonFly()) {
2344  TlsReg = X86::FS;
2345  TlsOffset = 0x20; // use tls_tcb.tcb_segstack
2346  } else {
2347  report_fatal_error("Segmented stacks not supported on this platform.");
2348  }
2349 
2350  if (CompareStackPointer)
2351  ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
2352  else
2353  BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
2354  .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2355 
2356  BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
2357  .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2358  } else {
2359  if (STI.isTargetLinux()) {
2360  TlsReg = X86::GS;
2361  TlsOffset = 0x30;
2362  } else if (STI.isTargetDarwin()) {
2363  TlsReg = X86::GS;
2364  TlsOffset = 0x48 + 90*4;
2365  } else if (STI.isTargetWin32()) {
2366  TlsReg = X86::FS;
2367  TlsOffset = 0x14; // pvArbitrary, reserved for application use
2368  } else if (STI.isTargetDragonFly()) {
2369  TlsReg = X86::FS;
2370  TlsOffset = 0x10; // use tls_tcb.tcb_segstack
2371  } else if (STI.isTargetFreeBSD()) {
2372  report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
2373  } else {
2374  report_fatal_error("Segmented stacks not supported on this platform.");
2375  }
2376 
2377  if (CompareStackPointer)
2378  ScratchReg = X86::ESP;
2379  else
2380  BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
2381  .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2382 
2383  if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64() ||
2384  STI.isTargetDragonFly()) {
2385  BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
2386  .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2387  } else if (STI.isTargetDarwin()) {
2388 
2389  // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
2390  unsigned ScratchReg2;
2391  bool SaveScratch2;
2392  if (CompareStackPointer) {
2393  // The primary scratch register is available for holding the TLS offset.
2394  ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2395  SaveScratch2 = false;
2396  } else {
2397  // Need to use a second register to hold the TLS offset
2398  ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
2399 
2400  // Unfortunately, with fastcc the second scratch register may hold an
2401  // argument.
2402  SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
2403  }
2404 
2405  // If Scratch2 is live-in then it needs to be saved.
2406  assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
2407  "Scratch register is live-in and not saved");
2408 
2409  if (SaveScratch2)
2410  BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
2411  .addReg(ScratchReg2, RegState::Kill);
2412 
2413  BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
2414  .addImm(TlsOffset);
2415  BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
2416  .addReg(ScratchReg)
2417  .addReg(ScratchReg2).addImm(1).addReg(0)
2418  .addImm(0)
2419  .addReg(TlsReg);
2420 
2421  if (SaveScratch2)
2422  BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
2423  }
2424  }
2425 
2426  // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
2427  // It jumps to normal execution of the function body.
2428  BuildMI(checkMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_A);
2429 
2430  // On 32 bit we first push the arguments size and then the frame size. On 64
2431  // bit, we pass the stack frame size in r10 and the argument size in r11.
2432  if (Is64Bit) {
2433  // Functions with nested arguments use R10, so it needs to be saved across
2434  // the call to _morestack
2435 
2436  const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
2437  const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
2438  const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
2439  const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
2440  const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
2441 
2442  if (IsNested)
2443  BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
2444 
2445  BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
2446  .addImm(StackSize);
2447  BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
2448  .addImm(X86FI->getArgumentStackSize());
2449  } else {
2450  BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
2451  .addImm(X86FI->getArgumentStackSize());
2452  BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
2453  .addImm(StackSize);
2454  }
2455 
2456  // __morestack is in libgcc
2457  if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
2458  // Under the large code model, we cannot assume that __morestack lives
2459  // within 2^31 bytes of the call site, so we cannot use pc-relative
2460  // addressing. We cannot perform the call via a temporary register,
2461  // as the rax register may be used to store the static chain, and all
2462  // other suitable registers may be either callee-save or used for
2463  // parameter passing. We cannot use the stack at this point either
2464  // because __morestack manipulates the stack directly.
2465  //
2466  // To avoid these issues, perform an indirect call via a read-only memory
2467  // location containing the address.
2468  //
2469  // This solution is not perfect, as it assumes that the .rodata section
2470  // is laid out within 2^31 bytes of each function body, but this seems
2471  // to be sufficient for JIT.
2472  // FIXME: Add retpoline support and remove the error here..
2474  report_fatal_error("Emitting morestack calls on 64-bit with the large "
2475  "code model and retpoline not yet implemented.");
2476  BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
2477  .addReg(X86::RIP)
2478  .addImm(0)
2479  .addReg(0)
2480  .addExternalSymbol("__morestack_addr")
2481  .addReg(0);
2482  MF.getMMI().setUsesMorestackAddr(true);
2483  } else {
2484  if (Is64Bit)
2485  BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
2486  .addExternalSymbol("__morestack");
2487  else
2488  BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
2489  .addExternalSymbol("__morestack");
2490  }
2491 
2492  if (IsNested)
2493  BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
2494  else
2495  BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
2496 
2497  allocMBB->addSuccessor(&PrologueMBB);
2498 
2499  checkMBB->addSuccessor(allocMBB, BranchProbability::getZero());
2500  checkMBB->addSuccessor(&PrologueMBB, BranchProbability::getOne());
2501 
2502 #ifdef EXPENSIVE_CHECKS
2503  MF.verify();
2504 #endif
2505 }
2506 
2507 /// Lookup an ERTS parameter in the !hipe.literals named metadata node.
2508 /// HiPE provides Erlang Runtime System-internal parameters, such as PCB offsets
2509 /// to fields it needs, through a named metadata node "hipe.literals" containing
2510 /// name-value pairs.
2511 static unsigned getHiPELiteral(
2512  NamedMDNode *HiPELiteralsMD, const StringRef LiteralName) {
2513  for (int i = 0, e = HiPELiteralsMD->getNumOperands(); i != e; ++i) {
2514  MDNode *Node = HiPELiteralsMD->getOperand(i);
2515  if (Node->getNumOperands() != 2) continue;
2516  MDString *NodeName = dyn_cast<MDString>(Node->getOperand(0));
2517  ValueAsMetadata *NodeVal = dyn_cast<ValueAsMetadata>(Node->getOperand(1));
2518  if (!NodeName || !NodeVal) continue;
2519  ConstantInt *ValConst = dyn_cast_or_null<ConstantInt>(NodeVal->getValue());
2520  if (ValConst && NodeName->getString() == LiteralName) {
2521  return ValConst->getZExtValue();
2522  }
2523  }
2524 
2525  report_fatal_error("HiPE literal " + LiteralName
2526  + " required but not provided");
2527 }
2528 
2529 /// Erlang programs may need a special prologue to handle the stack size they
2530 /// might need at runtime. That is because Erlang/OTP does not implement a C
2531 /// stack but uses a custom implementation of hybrid stack/heap architecture.
2532 /// (for more information see Eric Stenman's Ph.D. thesis:
2533 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
2534 ///
2535 /// CheckStack:
2536 /// temp0 = sp - MaxStack
2537 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
2538 /// OldStart:
2539 /// ...
2540 /// IncStack:
2541 /// call inc_stack # doubles the stack space
2542 /// temp0 = sp - MaxStack
2543 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
2545  MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
2546  MachineFrameInfo &MFI = MF.getFrameInfo();
2547  DebugLoc DL;
2548 
2549  // To support shrink-wrapping we would need to insert the new blocks
2550  // at the right place and update the branches to PrologueMBB.
2551  assert(&(*MF.begin()) == &PrologueMBB && "Shrink-wrapping not supported yet");
2552 
2553  // HiPE-specific values
2554  NamedMDNode *HiPELiteralsMD = MF.getMMI().getModule()
2555  ->getNamedMetadata("hipe.literals");
2556  if (!HiPELiteralsMD)
2558  "Can't generate HiPE prologue without runtime parameters");
2559  const unsigned HipeLeafWords
2560  = getHiPELiteral(HiPELiteralsMD,
2561  Is64Bit ? "AMD64_LEAF_WORDS" : "X86_LEAF_WORDS");
2562  const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
2563  const unsigned Guaranteed = HipeLeafWords * SlotSize;
2564  unsigned CallerStkArity = MF.getFunction().arg_size() > CCRegisteredArgs ?
2565  MF.getFunction().arg_size() - CCRegisteredArgs : 0;
2566  unsigned MaxStack = MFI.getStackSize() + CallerStkArity*SlotSize + SlotSize;
2567 
2568  assert(STI.isTargetLinux() &&
2569  "HiPE prologue is only supported on Linux operating systems.");
2570 
2571  // Compute the largest caller's frame that is needed to fit the callees'
2572  // frames. This 'MaxStack' is computed from:
2573  //
2574  // a) the fixed frame size, which is the space needed for all spilled temps,
2575  // b) outgoing on-stack parameter areas, and
2576  // c) the minimum stack space this function needs to make available for the
2577  // functions it calls (a tunable ABI property).
2578  if (MFI.hasCalls()) {
2579  unsigned MoreStackForCalls = 0;
2580 
2581  for (auto &MBB : MF) {
2582  for (auto &MI : MBB) {
2583  if (!MI.isCall())
2584  continue;
2585 
2586  // Get callee operand.
2587  const MachineOperand &MO = MI.getOperand(0);
2588 
2589  // Only take account of global function calls (no closures etc.).
2590  if (!MO.isGlobal())
2591  continue;
2592 
2593  const Function *F = dyn_cast<Function>(MO.getGlobal());
2594  if (!F)
2595  continue;
2596 
2597  // Do not update 'MaxStack' for primitive and built-in functions
2598  // (encoded with names either starting with "erlang."/"bif_" or not
2599  // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
2600  // "_", such as the BIF "suspend_0") as they are executed on another
2601  // stack.
2602  if (F->getName().find("erlang.") != StringRef::npos ||
2603  F->getName().find("bif_") != StringRef::npos ||
2604  F->getName().find_first_of("._") == StringRef::npos)
2605  continue;
2606 
2607  unsigned CalleeStkArity =
2608  F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
2609  if (HipeLeafWords - 1 > CalleeStkArity)
2610  MoreStackForCalls = std::max(MoreStackForCalls,
2611  (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
2612  }
2613  }
2614  MaxStack += MoreStackForCalls;
2615  }
2616 
2617  // If the stack frame needed is larger than the guaranteed then runtime checks
2618  // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
2619  if (MaxStack > Guaranteed) {
2620  MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
2621  MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
2622 
2623  for (const auto &LI : PrologueMBB.liveins()) {
2624  stackCheckMBB->addLiveIn(LI);
2625  incStackMBB->addLiveIn(LI);
2626  }
2627 
2628  MF.push_front(incStackMBB);
2629  MF.push_front(stackCheckMBB);
2630 
2631  unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
2632  unsigned LEAop, CMPop, CALLop;
2633  SPLimitOffset = getHiPELiteral(HiPELiteralsMD, "P_NSP_LIMIT");
2634  if (Is64Bit) {
2635  SPReg = X86::RSP;
2636  PReg = X86::RBP;
2637  LEAop = X86::LEA64r;
2638  CMPop = X86::CMP64rm;
2639  CALLop = X86::CALL64pcrel32;
2640  } else {
2641  SPReg = X86::ESP;
2642  PReg = X86::EBP;
2643  LEAop = X86::LEA32r;
2644  CMPop = X86::CMP32rm;
2645  CALLop = X86::CALLpcrel32;
2646  }
2647 
2648  ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2649  assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
2650  "HiPE prologue scratch register is live-in");
2651 
2652  // Create new MBB for StackCheck:
2653  addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
2654  SPReg, false, -MaxStack);
2655  // SPLimitOffset is in a fixed heap location (pointed by BP).
2656  addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
2657  .addReg(ScratchReg), PReg, false, SPLimitOffset);
2658  BuildMI(stackCheckMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_AE);
2659 
2660  // Create new MBB for IncStack:
2661  BuildMI(incStackMBB, DL, TII.get(CALLop)).
2662  addExternalSymbol("inc_stack_0");
2663  addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
2664  SPReg, false, -MaxStack);
2665  addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
2666  .addReg(ScratchReg), PReg, false, SPLimitOffset);
2667  BuildMI(incStackMBB, DL, TII.get(X86::JCC_1)).addMBB(incStackMBB).addImm(X86::COND_LE);
2668 
2669  stackCheckMBB->addSuccessor(&PrologueMBB, {99, 100});
2670  stackCheckMBB->addSuccessor(incStackMBB, {1, 100});
2671  incStackMBB->addSuccessor(&PrologueMBB, {99, 100});
2672  incStackMBB->addSuccessor(incStackMBB, {1, 100});
2673  }
2674 #ifdef EXPENSIVE_CHECKS
2675  MF.verify();
2676 #endif
2677 }
2678 
2679 bool X86FrameLowering::adjustStackWithPops(MachineBasicBlock &MBB,
2681  const DebugLoc &DL,
2682  int Offset) const {
2683 
2684  if (Offset <= 0)
2685  return false;
2686 
2687  if (Offset % SlotSize)
2688  return false;
2689 
2690  int NumPops = Offset / SlotSize;
2691  // This is only worth it if we have at most 2 pops.
2692  if (NumPops != 1 && NumPops != 2)
2693  return false;
2694 
2695  // Handle only the trivial case where the adjustment directly follows
2696  // a call. This is the most common one, anyway.
2697  if (MBBI == MBB.begin())
2698  return false;
2699  MachineBasicBlock::iterator Prev = std::prev(MBBI);
2700  if (!Prev->isCall() || !Prev->getOperand(1).isRegMask())
2701  return false;
2702 
2703  unsigned Regs[2];
2704  unsigned FoundRegs = 0;
2705 
2706  auto &MRI = MBB.getParent()->getRegInfo();
2707  auto RegMask = Prev->getOperand(1);
2708 
2709  auto &RegClass =
2710  Is64Bit ? X86::GR64_NOREX_NOSPRegClass : X86::GR32_NOREX_NOSPRegClass;
2711  // Try to find up to NumPops free registers.
2712  for (auto Candidate : RegClass) {
2713 
2714  // Poor man's liveness:
2715  // Since we're immediately after a call, any register that is clobbered
2716  // by the call and not defined by it can be considered dead.
2717  if (!RegMask.clobbersPhysReg(Candidate))
2718  continue;
2719 
2720  // Don't clobber reserved registers
2721  if (MRI.isReserved(Candidate))
2722  continue;
2723 
2724  bool IsDef = false;
2725  for (const MachineOperand &MO : Prev->implicit_operands()) {
2726  if (MO.isReg() && MO.isDef() &&
2727  TRI->isSuperOrSubRegisterEq(MO.getReg(), Candidate)) {
2728  IsDef = true;
2729  break;
2730  }
2731  }
2732 
2733  if (IsDef)
2734  continue;
2735 
2736  Regs[FoundRegs++] = Candidate;
2737  if (FoundRegs == (unsigned)NumPops)
2738  break;
2739  }
2740 
2741  if (FoundRegs == 0)
2742  return false;
2743 
2744  // If we found only one free register, but need two, reuse the same one twice.
2745  while (FoundRegs < (unsigned)NumPops)
2746  Regs[FoundRegs++] = Regs[0];
2747 
2748  for (int i = 0; i < NumPops; ++i)
2749  BuildMI(MBB, MBBI, DL,
2750  TII.get(STI.is64Bit() ? X86::POP64r : X86::POP32r), Regs[i]);
2751 
2752  return true;
2753 }
2754 
2758  bool reserveCallFrame = hasReservedCallFrame(MF);
2759  unsigned Opcode = I->getOpcode();
2760  bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
2761  DebugLoc DL = I->getDebugLoc();
2762  uint64_t Amount = !reserveCallFrame ? TII.getFrameSize(*I) : 0;
2763  uint64_t InternalAmt = (isDestroy || Amount) ? TII.getFrameAdjustment(*I) : 0;
2764  I = MBB.erase(I);
2765  auto InsertPos = skipDebugInstructionsForward(I, MBB.end());
2766 
2767  if (!reserveCallFrame) {
2768  // If the stack pointer can be changed after prologue, turn the
2769  // adjcallstackup instruction into a 'sub ESP, <amt>' and the
2770  // adjcallstackdown instruction into 'add ESP, <amt>'
2771 
2772  // We need to keep the stack aligned properly. To do this, we round the
2773  // amount of space needed for the outgoing arguments up to the next
2774  // alignment boundary.
2775  unsigned StackAlign = getStackAlignment();
2776  Amount = alignTo(Amount, StackAlign);
2777 
2778  MachineModuleInfo &MMI = MF.getMMI();
2779  const Function &F = MF.getFunction();
2780  bool WindowsCFI = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
2781  bool DwarfCFI = !WindowsCFI &&
2782  (MMI.hasDebugInfo() || F.needsUnwindTableEntry());
2783 
2784  // If we have any exception handlers in this function, and we adjust
2785  // the SP before calls, we may need to indicate this to the unwinder
2786  // using GNU_ARGS_SIZE. Note that this may be necessary even when
2787  // Amount == 0, because the preceding function may have set a non-0
2788  // GNU_ARGS_SIZE.
2789  // TODO: We don't need to reset this between subsequent functions,
2790  // if it didn't change.
2791  bool HasDwarfEHHandlers = !WindowsCFI && !MF.getLandingPads().empty();
2792 
2793  if (HasDwarfEHHandlers && !isDestroy &&
2795  BuildCFI(MBB, InsertPos, DL,
2796  MCCFIInstruction::createGnuArgsSize(nullptr, Amount));
2797 
2798  if (Amount == 0)
2799  return I;
2800 
2801  // Factor out the amount that gets handled inside the sequence
2802  // (Pushes of argument for frame setup, callee pops for frame destroy)
2803  Amount -= InternalAmt;
2804 
2805  // TODO: This is needed only if we require precise CFA.
2806  // If this is a callee-pop calling convention, emit a CFA adjust for
2807  // the amount the callee popped.
2808  if (isDestroy && InternalAmt && DwarfCFI && !hasFP(MF))
2809  BuildCFI(MBB, InsertPos, DL,
2810  MCCFIInstruction::createAdjustCfaOffset(nullptr, -InternalAmt));
2811 
2812  // Add Amount to SP to destroy a frame, or subtract to setup.
2813  int64_t StackAdjustment = isDestroy ? Amount : -Amount;
2814 
2815  if (StackAdjustment) {
2816  // Merge with any previous or following adjustment instruction. Note: the
2817  // instructions merged with here do not have CFI, so their stack
2818  // adjustments do not feed into CfaAdjustment.
2819  StackAdjustment += mergeSPUpdates(MBB, InsertPos, true);
2820  StackAdjustment += mergeSPUpdates(MBB, InsertPos, false);
2821 
2822  if (StackAdjustment) {
2823  if (!(F.hasMinSize() &&
2824  adjustStackWithPops(MBB, InsertPos, DL, StackAdjustment)))
2825  BuildStackAdjustment(MBB, InsertPos, DL, StackAdjustment,
2826  /*InEpilogue=*/false);
2827  }
2828  }
2829 
2830  if (DwarfCFI && !hasFP(MF)) {
2831  // If we don't have FP, but need to generate unwind information,
2832  // we need to set the correct CFA offset after the stack adjustment.
2833  // How much we adjust the CFA offset depends on whether we're emitting
2834  // CFI only for EH purposes or for debugging. EH only requires the CFA
2835  // offset to be correct at each call site, while for debugging we want
2836  // it to be more precise.
2837 
2838  int64_t CfaAdjustment = -StackAdjustment;
2839  // TODO: When not using precise CFA, we also need to adjust for the
2840  // InternalAmt here.
2841  if (CfaAdjustment) {
2842  BuildCFI(MBB, InsertPos, DL,
2844  CfaAdjustment));
2845  }
2846  }
2847 
2848  return I;
2849  }
2850 
2851  if (isDestroy && InternalAmt) {
2852  // If we are performing frame pointer elimination and if the callee pops
2853  // something off the stack pointer, add it back. We do this until we have
2854  // more advanced stack pointer tracking ability.
2855  // We are not tracking the stack pointer adjustment by the callee, so make
2856  // sure we restore the stack pointer immediately after the call, there may
2857  // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
2860  while (CI != B && !std::prev(CI)->isCall())
2861  --CI;
2862  BuildStackAdjustment(MBB, CI, DL, -InternalAmt, /*InEpilogue=*/false);
2863  }
2864 
2865  return I;
2866 }
2867 
2869  assert(MBB.getParent() && "Block is not attached to a function!");
2870  const MachineFunction &MF = *MBB.getParent();
2871  return !TRI->needsStackRealignment(MF) || !MBB.isLiveIn(X86::EFLAGS);
2872 }
2873 
2875  assert(MBB.getParent() && "Block is not attached to a function!");
2876 
2877  // Win64 has strict requirements in terms of epilogue and we are
2878  // not taking a chance at messing with them.
2879  // I.e., unless this block is already an exit block, we can't use
2880  // it as an epilogue.
2881  if (STI.isTargetWin64() && !MBB.succ_empty() && !MBB.isReturnBlock())
2882  return false;
2883 
2884  if (canUseLEAForSPInEpilogue(*MBB.getParent()))
2885  return true;
2886 
2887  // If we cannot use LEA to adjust SP, we may need to use ADD, which
2888  // clobbers the EFLAGS. Check that we do not need to preserve it,
2889  // otherwise, conservatively assume this is not
2890  // safe to insert the epilogue here.
2892 }
2893 
2895  // If we may need to emit frameless compact unwind information, give
2896  // up as this is currently broken: PR25614.
2897  return (MF.getFunction().hasFnAttribute(Attribute::NoUnwind) || hasFP(MF)) &&
2898  // The lowering of segmented stack and HiPE only support entry blocks
2899  // as prologue blocks: PR26107.
2900  // This limitation may be lifted if we fix:
2901  // - adjustForSegmentedStacks
2902  // - adjustForHiPEPrologue
2904  !MF.shouldSplitStack();
2905 }
2906 
2909  const DebugLoc &DL, bool RestoreSP) const {
2910  assert(STI.isTargetWindowsMSVC() && "funclets only supported in MSVC env");
2911  assert(STI.isTargetWin32() && "EBP/ESI restoration only required on win32");
2913  "restoring EBP/ESI on non-32-bit target");
2914 
2915  MachineFunction &MF = *MBB.getParent();
2916  unsigned FramePtr = TRI->getFrameRegister(MF);
2917  unsigned BasePtr = TRI->getBaseRegister();
2918  WinEHFuncInfo &FuncInfo = *MF.getWinEHFuncInfo();
2919  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2920  MachineFrameInfo &MFI = MF.getFrameInfo();
2921 
2922  // FIXME: Don't set FrameSetup flag in catchret case.
2923 
2924  int FI = FuncInfo.EHRegNodeFrameIndex;
2925  int EHRegSize = MFI.getObjectSize(FI);
2926 
2927  if (RestoreSP) {
2928  // MOV32rm -EHRegSize(%ebp), %esp
2929  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), X86::ESP),
2930  X86::EBP, true, -EHRegSize)
2932  }
2933 
2934  unsigned UsedReg;
2935  int EHRegOffset = getFrameIndexReference(MF, FI, UsedReg);
2936  int EndOffset = -EHRegOffset - EHRegSize;
2937  FuncInfo.EHRegNodeEndOffset = EndOffset;
2938 
2939  if (UsedReg == FramePtr) {
2940  // ADD $offset, %ebp
2941  unsigned ADDri = getADDriOpcode(false, EndOffset);
2942  BuildMI(MBB, MBBI, DL, TII.get(ADDri), FramePtr)
2943  .addReg(FramePtr)
2944  .addImm(EndOffset)
2946  ->getOperand(3)
2947  .setIsDead();
2948  assert(EndOffset >= 0 &&
2949  "end of registration object above normal EBP position!");
2950  } else if (UsedReg == BasePtr) {
2951  // LEA offset(%ebp), %esi
2952  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA32r), BasePtr),
2953  FramePtr, false, EndOffset)
2955  // MOV32rm SavedEBPOffset(%esi), %ebp
2956  assert(X86FI->getHasSEHFramePtrSave());
2957  int Offset =
2958  getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg);
2959  assert(UsedReg == BasePtr);
2960  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), FramePtr),
2961  UsedReg, true, Offset)
2963  } else {
2964  llvm_unreachable("32-bit frames with WinEH must use FramePtr or BasePtr");
2965  }
2966  return MBBI;
2967 }
2968 
2970  return TRI->getSlotSize();
2971 }
2972 
2974  const {
2975  return TRI->getDwarfRegNum(StackPtr, true);
2976 }
2977 
2978 namespace {
2979 // Struct used by orderFrameObjects to help sort the stack objects.
2980 struct X86FrameSortingObject {
2981  bool IsValid = false; // true if we care about this Object.
2982  unsigned ObjectIndex = 0; // Index of Object into MFI list.
2983  unsigned ObjectSize = 0; // Size of Object in bytes.
2984  unsigned ObjectAlignment = 1; // Alignment of Object in bytes.
2985  unsigned ObjectNumUses = 0; // Object static number of uses.
2986 };
2987 
2988 // The comparison function we use for std::sort to order our local
2989 // stack symbols. The current algorithm is to use an estimated
2990 // "density". This takes into consideration the size and number of
2991 // uses each object has in order to roughly minimize code size.
2992 // So, for example, an object of size 16B that is referenced 5 times
2993 // will get higher priority than 4 4B objects referenced 1 time each.
2994 // It's not perfect and we may be able to squeeze a few more bytes out of
2995 // it (for example : 0(esp) requires fewer bytes, symbols allocated at the
2996 // fringe end can have special consideration, given their size is less
2997 // important, etc.), but the algorithmic complexity grows too much to be
2998 // worth the extra gains we get. This gets us pretty close.
2999 // The final order leaves us with objects with highest priority going
3000 // at the end of our list.
3001 struct X86FrameSortingComparator {
3002  inline bool operator()(const X86FrameSortingObject &A,
3003  const X86FrameSortingObject &B) {
3004  uint64_t DensityAScaled, DensityBScaled;
3005 
3006  // For consistency in our comparison, all invalid objects are placed
3007  // at the end. This also allows us to stop walking when we hit the
3008  // first invalid item after it's all sorted.
3009  if (!A.IsValid)
3010  return false;
3011  if (!B.IsValid)
3012  return true;
3013 
3014  // The density is calculated by doing :
3015  // (double)DensityA = A.ObjectNumUses / A.ObjectSize
3016  // (double)DensityB = B.ObjectNumUses / B.ObjectSize
3017  // Since this approach may cause inconsistencies in
3018  // the floating point <, >, == comparisons, depending on the floating
3019  // point model with which the compiler was built, we're going
3020  // to scale both sides by multiplying with
3021  // A.ObjectSize * B.ObjectSize. This ends up factoring away
3022  // the division and, with it, the need for any floating point
3023  // arithmetic.
3024  DensityAScaled = static_cast<uint64_t>(A.ObjectNumUses) *
3025  static_cast<uint64_t>(B.ObjectSize);
3026  DensityBScaled = static_cast<uint64_t>(B.ObjectNumUses) *
3027  static_cast<uint64_t>(A.ObjectSize);
3028 
3029  // If the two densities are equal, prioritize highest alignment
3030  // objects. This allows for similar alignment objects
3031  // to be packed together (given the same density).
3032  // There's room for improvement here, also, since we can pack
3033  // similar alignment (different density) objects next to each
3034  // other to save padding. This will also require further
3035  // complexity/iterations, and the overall gain isn't worth it,
3036  // in general. Something to keep in mind, though.
3037  if (DensityAScaled == DensityBScaled)
3038  return A.ObjectAlignment < B.ObjectAlignment;
3039 
3040  return DensityAScaled < DensityBScaled;
3041  }
3042 };
3043 } // namespace
3044 
3045 // Order the symbols in the local stack.
3046 // We want to place the local stack objects in some sort of sensible order.
3047 // The heuristic we use is to try and pack them according to static number
3048 // of uses and size of object in order to minimize code size.
3050  const MachineFunction &MF, SmallVectorImpl<int> &ObjectsToAllocate) const {
3051  const MachineFrameInfo &MFI = MF.getFrameInfo();
3052 
3053  // Don't waste time if there's nothing to do.
3054  if (ObjectsToAllocate.empty())
3055  return;
3056 
3057  // Create an array of all MFI objects. We won't need all of these
3058  // objects, but we're going to create a full array of them to make
3059  // it easier to index into when we're counting "uses" down below.
3060  // We want to be able to easily/cheaply access an object by simply
3061  // indexing into it, instead of having to search for it every time.
3062  std::vector<X86FrameSortingObject> SortingObjects(MFI.getObjectIndexEnd());
3063 
3064  // Walk the objects we care about and mark them as such in our working
3065  // struct.
3066  for (auto &Obj : ObjectsToAllocate) {
3067  SortingObjects[Obj].IsValid = true;
3068  SortingObjects[Obj].ObjectIndex = Obj;
3069  SortingObjects[Obj].ObjectAlignment = MFI.getObjectAlignment(Obj);
3070  // Set the size.
3071  int ObjectSize = MFI.getObjectSize(Obj);
3072  if (ObjectSize == 0)
3073  // Variable size. Just use 4.
3074  SortingObjects[Obj].ObjectSize = 4;
3075  else
3076  SortingObjects[Obj].ObjectSize = ObjectSize;
3077  }
3078 
3079  // Count the number of uses for each object.
3080  for (auto &MBB : MF) {
3081  for (auto &MI : MBB) {
3082  if (MI.isDebugInstr())
3083  continue;
3084  for (const MachineOperand &MO : MI.operands()) {
3085  // Check to see if it's a local stack symbol.
3086  if (!MO.isFI())
3087  continue;
3088  int Index = MO.getIndex();
3089  // Check to see if it falls within our range, and is tagged
3090  // to require ordering.
3091  if (Index >= 0 && Index < MFI.getObjectIndexEnd() &&
3092  SortingObjects[Index].IsValid)
3093  SortingObjects[Index].ObjectNumUses++;
3094  }
3095  }
3096  }
3097 
3098  // Sort the objects using X86FrameSortingAlgorithm (see its comment for
3099  // info).
3100  llvm::stable_sort(SortingObjects, X86FrameSortingComparator());
3101 
3102  // Now modify the original list to represent the final order that
3103  // we want. The order will depend on whether we're going to access them
3104  // from the stack pointer or the frame pointer. For SP, the list should
3105  // end up with the END containing objects that we want with smaller offsets.
3106  // For FP, it should be flipped.
3107  int i = 0;
3108  for (auto &Obj : SortingObjects) {
3109  // All invalid items are sorted at the end, so it's safe to stop.
3110  if (!Obj.IsValid)
3111  break;
3112  ObjectsToAllocate[i++] = Obj.ObjectIndex;
3113  }
3114 
3115  // Flip it if we're accessing off of the FP.
3116  if (!TRI->needsStackRealignment(MF) && hasFP(MF))
3117  std::reverse(ObjectsToAllocate.begin(), ObjectsToAllocate.end());
3118 }
3119 
3120 
3122  // RDX, the parent frame pointer, is homed into 16(%rsp) in the prologue.
3123  unsigned Offset = 16;
3124  // RBP is immediately pushed.
3125  Offset += SlotSize;
3126  // All callee-saved registers are then pushed.
3127  Offset += MF.getInfo<X86MachineFunctionInfo>()->getCalleeSavedFrameSize();
3128  // Every funclet allocates enough stack space for the largest outgoing call.
3129  Offset += getWinEHFuncletFrameSize(MF);
3130  return Offset;
3131 }
3132 
3134  MachineFunction &MF, RegScavenger *RS) const {
3135  // Mark the function as not having WinCFI. We will set it back to true in
3136  // emitPrologue if it gets called and emits CFI.
3137  MF.setHasWinCFI(false);
3138 
3139  // If this function isn't doing Win64-style C++ EH, we don't need to do
3140  // anything.
3141  const Function &F = MF.getFunction();
3142  if (!STI.is64Bit() || !MF.hasEHFunclets() ||
3144  return;
3145 
3146  // Win64 C++ EH needs to allocate the UnwindHelp object at some fixed offset
3147  // relative to RSP after the prologue. Find the offset of the last fixed
3148  // object, so that we can allocate a slot immediately following it. If there
3149  // were no fixed objects, use offset -SlotSize, which is immediately after the
3150  // return address. Fixed objects have negative frame indices.
3151  MachineFrameInfo &MFI = MF.getFrameInfo();
3152  WinEHFuncInfo &EHInfo = *MF.getWinEHFuncInfo();
3153  int64_t MinFixedObjOffset = -SlotSize;
3154  for (int I = MFI.getObjectIndexBegin(); I < 0; ++I)
3155  MinFixedObjOffset = std::min(MinFixedObjOffset, MFI.getObjectOffset(I));
3156 
3157  for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
3158  for (WinEHHandlerType &H : TBME.HandlerArray) {
3159  int FrameIndex = H.CatchObj.FrameIndex;
3160  if (FrameIndex != INT_MAX) {
3161  // Ensure alignment.
3162  unsigned Align = MFI.getObjectAlignment(FrameIndex);
3163  MinFixedObjOffset -= std::abs(MinFixedObjOffset) % Align;
3164  MinFixedObjOffset -= MFI.getObjectSize(FrameIndex);
3165  MFI.setObjectOffset(FrameIndex, MinFixedObjOffset);
3166  }
3167  }
3168  }
3169 
3170  // Ensure alignment.
3171  MinFixedObjOffset -= std::abs(MinFixedObjOffset) % 8;
3172  int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize;
3173  int UnwindHelpFI =
3174  MFI.CreateFixedObject(SlotSize, UnwindHelpOffset, /*Immutable=*/false);
3175  EHInfo.UnwindHelpFrameIdx = UnwindHelpFI;
3176 
3177  // Store -2 into UnwindHelp on function entry. We have to scan forwards past
3178  // other frame setup instructions.
3179  MachineBasicBlock &MBB = MF.front();
3180  auto MBBI = MBB.begin();
3181  while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
3182  ++MBBI;
3183 
3184  DebugLoc DL = MBB.findDebugLoc(MBBI);
3185  addFrameReference(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mi32)),
3186  UnwindHelpFI)
3187  .addImm(-2);
3188 }
void push_front(MachineBasicBlock *MBB)
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:176
constexpr bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:348
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:479
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:536
static bool flagsNeedToBePreservedBeforeTheTerminators(const MachineBasicBlock &MBB)
Check if the flags need to be preserved before the terminators.
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
bool usesWindowsCFI() const
Definition: MCAsmInfo.h:583
bool hasBasePointer(const MachineFunction &MF) const
BitVector & set()
Definition: BitVector.h:397
bool hasStackMap() const
This method may be called any time after instruction selection is complete to determine if there is a...
SmallVector< WinEHHandlerType, 1 > HandlerArray
Definition: WinEHFuncInfo.h:76
DILocation * get() const
Get the underlying DILocation.
Definition: DebugLoc.cpp:21
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
MachineBasicBlock * getMBB() const
bool hasDebugInfo() const
Returns true if valid debug info is present.
MDNode * getOperand(unsigned i) const
Definition: Metadata.cpp:1080
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isOSWindows() const
Definition: X86Subtarget.h:788
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:495
bool hasStackObjects() const
Return true if there are any stack objects in this function.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
bool isCleanupFuncletEntry() const
Returns true if this is the entry block of a cleanup funclet.
unsigned getReg() const
getReg - Returns the register number.
const TargetRegisterClass * getGPRsForTailCall(const MachineFunction &MF) const
getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls...
static unsigned getLEArOpcode(unsigned IsLP64)
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:504
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
unsigned Reg
MachineBasicBlock::iterator restoreWin32EHStackPointers(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool RestoreSP=false) const
Sets up EBP and optionally ESI based on the incoming EBP value.
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:302
void setCalleeSavedFrameSize(unsigned bytes)
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:323
arg_iterator arg_end()
Definition: Function.h:685
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
Metadata node.
Definition: Metadata.h:863
void setIsDead(bool Val=true)
F(f)
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
MachineModuleInfo & getMMI() const
const MDOperand & getOperand(unsigned I) const
Definition: Metadata.h:1068
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:684
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
static BranchProbability getOne()
bool isTargetNaCl64() const
Definition: X86Subtarget.h:758
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:491
unsigned getSlotSize() const
static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int Adjustment)
.cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but Offset is a relative value that is added/subt...
Definition: MCDwarf.h:498
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
bool isTargetWindowsMSVC() const
Definition: X86Subtarget.h:762
X86FrameLowering(const X86Subtarget &STI, unsigned StackAlignOverride)
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
return AArch64::GPR64RegClass contains(Reg)
iterator_range< succ_iterator > successors()
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
bool Uses64BitFramePtr
True if the 64-bit frame or stack pointer should be used.
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
CLEANUPRET - Represents a return from a cleanup block funclet.
Definition: ISDOpcodes.h:721
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
A tuple of MDNodes.
Definition: Metadata.h:1325
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction. ...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
const HexagonInstrInfo * TII
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:555
MachineBasicBlock iterator that automatically skips over MIs that are inside bundles (i...
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool is32Bit() const
Definition: X86Subtarget.h:540
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
iterator_range< iterator > terminators()
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
void adjustForHiPEPrologue(MachineFunction &MF, MachineBasicBlock &PrologueMBB) const override
Erlang programs may need a special prologue to handle the stack size they might need at runtime...
unsigned getNumOperands() const
Definition: Metadata.cpp:1076
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
static const uint64_t kSplitStackAvailable
virtual unsigned getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
unsigned getBaseRegister() const
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Definition: STLExtras.h:266
unsigned getWinEHParentFrameOffset(const MachineFunction &MF) const override
uint16_t StackAdjustment(const RuntimeFunction &RF)
StackAdjustment - calculated stack adjustment in words.
Definition: ARMWinEH.h:196
bool canUseLEAForSPInEpilogue(const MachineFunction &MF) const
Check that LEA can be used on SP in an epilogue sequence for MF.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
bool needsFrameIndexResolution(const MachineFunction &MF) const override
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
void inlineStackProbe(MachineFunction &MF, MachineBasicBlock &PrologMBB) const override
Replace a StackProbe inline-stub with the actual probe code inline.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
static unsigned getANDriOpcode(bool IsLP64, int64_t Imm)
const MCContext & getContext() const
int getObjectIndexBegin() const
Return the minimum frame object index.
NamedMDNode * getNamedMetadata(const Twine &Name) const
Return the first NamedMDNode in the module with the specified name.
Definition: Module.cpp:250
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
static unsigned getHiPELiteral(NamedMDNode *HiPELiteralsMD, const StringRef LiteralName)
Lookup an ERTS parameter in the !hipe.literals named metadata node.
int getObjectIndexEnd() const
Return one past the maximum frame object index.
bool hasPersonalityFn() const
Check whether this function has a personality function.
Definition: Function.h:707
bool hasCopyImplyingStackAdjustment() const
Returns true if the function contains operations which will lower down to instructions which manipula...
StringRef getStackProbeSymbolName(MachineFunction &MF) const override
Returns the name of the symbol used to emit stack probes or the empty string if not applicable...
Value wrapper in the Metadata hierarchy.
Definition: Metadata.h:338
static unsigned calculateSetFPREG(uint64_t SPAdjust)
bool Is64Bit
Is64Bit implies that x86_64 instructions are available.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getUndefRegState(bool B)
void BuildCFI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, const MCCFIInstruction &CFIInst) const
Wraps up getting a CFI index and building a MachineInstr for it.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
unsigned getKillRegState(bool B)
unsigned getCodeViewFlag() const
Returns the CodeView Version by checking module flags.
Definition: Module.cpp:468
unsigned getStackRegister() const
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getInitialCFARegister(const MachineFunction &MF) const override
Return initial CFA register value i.e.
StringRef getString() const
Definition: Metadata.cpp:463
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:532
unsigned getDefRegState(bool B)
The memory access is volatile.
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:491
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a prologue for the target.
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:148
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:477
Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:484
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:355
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool hasEHFunclets() const
void setStackSize(uint64_t Size)
Set the size of the stack.
static bool is64Bit(const char *name)
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions...
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
const GlobalValue * getGlobal() const
const X86InstrInfo & TII
#define H(x, y, z)
Definition: MD5.cpp:57
static MCCFIInstruction createGnuArgsSize(MCSymbol *L, int Size)
A special wrapper for .cfi_escape that indicates GNU_ARGS_SIZE.
Definition: MCDwarf.h:570
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
LLVM_NODISCARD size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:285
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
union llvm::WinEHHandlerType::@194 CatchObj
The CatchObj starts out life as an LLVM alloca and is eventually turned frame index.
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:299
MCRegAliasIterator enumerates all registers aliasing Reg.
static const MachineInstrBuilder & addRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, bool isKill, int Offset)
addRegOffset - This function is used to add a memory reference of the form [Reg + Offset]...
bool useLeaForSP() const
Definition: X86Subtarget.h:640
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
unsigned getFramePtr() const
Returns physical register used as frame pointer.
bool isTargetFreeBSD() const
Definition: X86Subtarget.h:743
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const Triple & getTargetTriple() const
size_t arg_size() const
Definition: Function.h:703
arg_iterator arg_begin()
Definition: Function.h:676
self_iterator getIterator()
Definition: ilist_node.h:81
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:180
bool isTargetDarwin() const
Definition: X86Subtarget.h:742
int CreateSpillStackObject(uint64_t Size, unsigned Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
bool useRetpolineIndirectCalls() const
Definition: X86Subtarget.h:691
bool isTargetWin64() const
Definition: X86Subtarget.h:790
This class contains a discriminated union of information about pointers in memory operands...
const char * createExternalSymbolName(StringRef Name)
Allocate a string and populate it with the given external symbol name.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
virtual bool hasReservedCallFrame(const MachineFunction &MF) const
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm)
static bool isFuncletReturnInstr(MachineInstr &MI)
static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
void emitStackProbe(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog) const
Emit target stack probe code.
The memory access writes data.
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:478
const std::vector< LandingPadInfo > & getLandingPads() const
Return a reference to the landing pad info for the current function.
const X86Subtarget & STI
Iterator for intrusive lists based on ilist_node.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:308
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
bool regsOverlap(unsigned regA, unsigned regB) const
Returns true if the two registers are equal or alias each other.
bool shouldSplitStack() const
Should we be emitting segmented stack stuff for the function.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &DL, int64_t NumBytes, bool InEpilogue) const
Emit a series of instructions to increment / decrement the stack pointer by a constant value...
MachineOperand class - Representation of each machine instruction operand.
Information about stack frame layout on the target.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
int CreateFixedSpillStackObject(uint64_t Size, int64_t SPOffset, bool IsImmutable=false)
Create a spill slot at a fixed location on the stack.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
bool isTargetWin32() const
Definition: X86Subtarget.h:792
int getFrameIndexReferencePreferSP(const MachineFunction &MF, int FI, unsigned &FrameReg, bool IgnoreSPUpdates) const override
Same as getFrameIndexReference, except that the stack pointer (as opposed to the frame pointer) will ...
const WinEHFuncInfo * getWinEHFuncInfo() const
getWinEHFuncInfo - Return information about how the current function uses Windows exception handling...
int64_t getFrameAdjustment(const MachineInstr &I) const
Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e...
Definition: X86InstrInfo.h:152
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
void setOffsetAdjustment(int Adj)
Set the correction for frame offsets.
bool callsUnwindInit() const
bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override
canSimplifyCallFramePseudos - If there is a reserved call frame, the call frame pseudos can be simpli...
IterT skipDebugInstructionsBackward(IterT It, IterT Begin)
Decrement It until it points to a non-debug instruction or to Begin and return the resulting iterator...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:549
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
Definition: Function.h:575
bool callsEHReturn() const
unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
static bool isTailCallOpcode(unsigned Opc)
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
SmallVector< WinEHTryBlockMapEntry, 4 > TryBlockMap
Definition: WinEHFuncInfo.h:96
CodeModel::Model getCodeModel() const
Returns the code model.
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
void setHasAddressTaken()
Set this block to reflect that it potentially is the target of an indirect branch.
IterT skipDebugInstructionsForward(IterT It, IterT End)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator...
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:717
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
int getFrameIndexReferenceSP(const MachineFunction &MF, int FI, unsigned &SPReg, int Adjustment) const
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
assignCalleeSavedSpillSlots - Allows target to override spill slot assignment logic.
void adjustForSegmentedStacks(MachineFunction &MF, MachineBasicBlock &PrologueMBB) const override
Adjust the prologue to have the function use segmented stacks.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void ensureMaxAlignment(unsigned Align)
Make sure the function is at least Align bytes aligned.
static const size_t npos
Definition: StringRef.h:50
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isTargetDragonFly() const
Definition: X86Subtarget.h:744
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use...
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:194
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:214
TargetOptions Options
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
LLVM_NODISCARD size_t find_first_of(char C, size_t From=0) const
Find the first character in the string that is C, or npos if not found.
Definition: StringRef.h:380
#define I(x, y, z)
Definition: MD5.cpp:58
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1212
Pair of physical register and lane mask.
virtual const TargetFrameLowering * getFrameLowering() const
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:600
bool has128ByteRedZone(const MachineFunction &MF) const
Return true if the function has a redzone (accessible bytes past the frame of the top of stack functi...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
void setCVBytesOfCalleeSavedRegisters(unsigned S)
uint32_t Size
Definition: Profile.cpp:46
static unsigned getSUBrrOpcode(unsigned isLP64)
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const X86RegisterInfo * TRI
const Module * getModule() const
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
static cl::opt< int > PageSize("imp-null-check-page-size", cl::desc("The page size of the target in bytes"), cl::init(4096), cl::Hidden)
iterator_range< livein_iterator > liveins() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents &#39;eh_return&#39; gcc dwarf builtin...
Definition: ISDOpcodes.h:101
CallingConvention
Definition: Dwarf.h:202
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isEAXLiveIn(MachineBasicBlock &MBB)
static unsigned getADDrrOpcode(unsigned isLP64)
void insert(iterator MBBI, MachineBasicBlock *MBB)
bool isAsynchronousEHPersonality(EHPersonality Pers)
Returns true if this personality function catches asynchronous exceptions.
void stable_sort(R &&Range)
Definition: STLExtras.h:1309
static unsigned GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary)
GetScratchRegister - Get a temp register for performing work in the segmented stack and the Erlang/Hi...
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:294
Constant * getPersonalityFn() const
Get the personality function associated with this function.
Definition: Function.cpp:1306
bool isTargetLinux() const
Definition: X86Subtarget.h:752
static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const X86RegisterInfo *TRI, bool Is64Bit)
findDeadCallerSavedReg - Return a caller-saved register that isn&#39;t live when it reaches the "return" ...
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:803
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:333
X86_FastCall - &#39;fast&#39; analog of X86_StdCall.
Definition: CallingConv.h:91
int getInitialCFAOffset(const MachineFunction &MF) const override
Return initial CFA offset value i.e.
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
IRTranslator LLVM IR MI
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool hasBWI() const
Definition: X86Subtarget.h:674
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
A single uniqued string.
Definition: Metadata.h:603
void emitCalleeSavedFrameMoves(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL) const
unsigned getFrameRegister(const MachineFunction &MF) const override
static BranchProbability getZero()
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
DWARF-like instruction based exceptions.
void orderFrameObjects(const MachineFunction &MF, SmallVectorImpl< int > &ObjectsToAllocate) const override
Order the symbols in the local stack.
int mergeSPUpdates(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, bool doMergeWithPrevious) const
Check the instruction before/after the passed instruction.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getNumOperands() const
Return number of MDNode operands.
Definition: Metadata.h:1074
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
static bool HasNestArgument(const MachineFunction *MF)
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
bool hasTailCall() const
Returns true if the function contains a tail call.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
Function Alias Analysis false
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
X86_INTR - x86 hardware interrupt context.
Definition: CallingConv.h:173
This class contains meta information specific to a module.
bool hasCalls() const
Return true if the current function has any function calls.
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164
bool isTargetWindowsCoreCLR() const
Definition: X86Subtarget.h:770