LLVM  9.0.0svn
X86InstrInfo.cpp
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1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86InstrInfo.h"
14 #include "X86.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrFoldTables.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Sequence.h"
30 #include "llvm/CodeGen/StackMaps.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/LLVMContext.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCExpr.h"
36 #include "llvm/MC/MCInst.h"
38 #include "llvm/Support/Debug.h"
42 
43 using namespace llvm;
44 
45 #define DEBUG_TYPE "x86-instr-info"
46 
47 #define GET_INSTRINFO_CTOR_DTOR
48 #include "X86GenInstrInfo.inc"
49 
50 static cl::opt<bool>
51  NoFusing("disable-spill-fusing",
52  cl::desc("Disable fusing of spill code into instructions"),
53  cl::Hidden);
54 static cl::opt<bool>
55 PrintFailedFusing("print-failed-fuse-candidates",
56  cl::desc("Print instructions that the allocator wants to"
57  " fuse, but the X86 backend currently can't"),
58  cl::Hidden);
59 static cl::opt<bool>
60 ReMatPICStubLoad("remat-pic-stub-load",
61  cl::desc("Re-materialize load from stub in PIC mode"),
62  cl::init(false), cl::Hidden);
63 static cl::opt<unsigned>
64 PartialRegUpdateClearance("partial-reg-update-clearance",
65  cl::desc("Clearance between two register writes "
66  "for inserting XOR to avoid partial "
67  "register update"),
68  cl::init(64), cl::Hidden);
69 static cl::opt<unsigned>
70 UndefRegClearance("undef-reg-clearance",
71  cl::desc("How many idle instructions we would like before "
72  "certain undef register reads"),
73  cl::init(128), cl::Hidden);
74 
75 
76 // Pin the vtable to this file.
77 void X86InstrInfo::anchor() {}
78 
80  : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
81  : X86::ADJCALLSTACKDOWN32),
82  (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
83  : X86::ADJCALLSTACKUP32),
84  X86::CATCHRET,
85  (STI.is64Bit() ? X86::RETQ : X86::RETL)),
86  Subtarget(STI), RI(STI.getTargetTriple()) {
87 }
88 
89 bool
91  unsigned &SrcReg, unsigned &DstReg,
92  unsigned &SubIdx) const {
93  switch (MI.getOpcode()) {
94  default: break;
95  case X86::MOVSX16rr8:
96  case X86::MOVZX16rr8:
97  case X86::MOVSX32rr8:
98  case X86::MOVZX32rr8:
99  case X86::MOVSX64rr8:
100  if (!Subtarget.is64Bit())
101  // It's not always legal to reference the low 8-bit of the larger
102  // register in 32-bit mode.
103  return false;
105  case X86::MOVSX32rr16:
106  case X86::MOVZX32rr16:
107  case X86::MOVSX64rr16:
108  case X86::MOVSX64rr32: {
109  if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
110  // Be conservative.
111  return false;
112  SrcReg = MI.getOperand(1).getReg();
113  DstReg = MI.getOperand(0).getReg();
114  switch (MI.getOpcode()) {
115  default: llvm_unreachable("Unreachable!");
116  case X86::MOVSX16rr8:
117  case X86::MOVZX16rr8:
118  case X86::MOVSX32rr8:
119  case X86::MOVZX32rr8:
120  case X86::MOVSX64rr8:
121  SubIdx = X86::sub_8bit;
122  break;
123  case X86::MOVSX32rr16:
124  case X86::MOVZX32rr16:
125  case X86::MOVSX64rr16:
126  SubIdx = X86::sub_16bit;
127  break;
128  case X86::MOVSX64rr32:
129  SubIdx = X86::sub_32bit;
130  break;
131  }
132  return true;
133  }
134  }
135  return false;
136 }
137 
139  const MachineFunction *MF = MI.getParent()->getParent();
141 
142  if (isFrameInstr(MI)) {
143  unsigned StackAlign = TFI->getStackAlignment();
144  int SPAdj = alignTo(getFrameSize(MI), StackAlign);
145  SPAdj -= getFrameAdjustment(MI);
146  if (!isFrameSetup(MI))
147  SPAdj = -SPAdj;
148  return SPAdj;
149  }
150 
151  // To know whether a call adjusts the stack, we need information
152  // that is bound to the following ADJCALLSTACKUP pseudo.
153  // Look for the next ADJCALLSTACKUP that follows the call.
154  if (MI.isCall()) {
155  const MachineBasicBlock *MBB = MI.getParent();
157  for (auto E = MBB->end(); I != E; ++I) {
158  if (I->getOpcode() == getCallFrameDestroyOpcode() ||
159  I->isCall())
160  break;
161  }
162 
163  // If we could not find a frame destroy opcode, then it has already
164  // been simplified, so we don't care.
165  if (I->getOpcode() != getCallFrameDestroyOpcode())
166  return 0;
167 
168  return -(I->getOperand(1).getImm());
169  }
170 
171  // Currently handle only PUSHes we can reasonably expect to see
172  // in call sequences
173  switch (MI.getOpcode()) {
174  default:
175  return 0;
176  case X86::PUSH32i8:
177  case X86::PUSH32r:
178  case X86::PUSH32rmm:
179  case X86::PUSH32rmr:
180  case X86::PUSHi32:
181  return 4;
182  case X86::PUSH64i8:
183  case X86::PUSH64r:
184  case X86::PUSH64rmm:
185  case X86::PUSH64rmr:
186  case X86::PUSH64i32:
187  return 8;
188  }
189 }
190 
191 /// Return true and the FrameIndex if the specified
192 /// operand and follow operands form a reference to the stack frame.
193 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
194  int &FrameIndex) const {
195  if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
196  MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
197  MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
198  MI.getOperand(Op + X86::AddrDisp).isImm() &&
199  MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
200  MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
201  MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
202  FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
203  return true;
204  }
205  return false;
206 }
207 
208 static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
209  switch (Opcode) {
210  default:
211  return false;
212  case X86::MOV8rm:
213  case X86::KMOVBkm:
214  MemBytes = 1;
215  return true;
216  case X86::MOV16rm:
217  case X86::KMOVWkm:
218  MemBytes = 2;
219  return true;
220  case X86::MOV32rm:
221  case X86::MOVSSrm:
222  case X86::VMOVSSZrm:
223  case X86::VMOVSSrm:
224  case X86::KMOVDkm:
225  MemBytes = 4;
226  return true;
227  case X86::MOV64rm:
228  case X86::LD_Fp64m:
229  case X86::MOVSDrm:
230  case X86::VMOVSDrm:
231  case X86::VMOVSDZrm:
232  case X86::MMX_MOVD64rm:
233  case X86::MMX_MOVQ64rm:
234  case X86::KMOVQkm:
235  MemBytes = 8;
236  return true;
237  case X86::MOVAPSrm:
238  case X86::MOVUPSrm:
239  case X86::MOVAPDrm:
240  case X86::MOVUPDrm:
241  case X86::MOVDQArm:
242  case X86::MOVDQUrm:
243  case X86::VMOVAPSrm:
244  case X86::VMOVUPSrm:
245  case X86::VMOVAPDrm:
246  case X86::VMOVUPDrm:
247  case X86::VMOVDQArm:
248  case X86::VMOVDQUrm:
249  case X86::VMOVAPSZ128rm:
250  case X86::VMOVUPSZ128rm:
251  case X86::VMOVAPSZ128rm_NOVLX:
252  case X86::VMOVUPSZ128rm_NOVLX:
253  case X86::VMOVAPDZ128rm:
254  case X86::VMOVUPDZ128rm:
255  case X86::VMOVDQU8Z128rm:
256  case X86::VMOVDQU16Z128rm:
257  case X86::VMOVDQA32Z128rm:
258  case X86::VMOVDQU32Z128rm:
259  case X86::VMOVDQA64Z128rm:
260  case X86::VMOVDQU64Z128rm:
261  MemBytes = 16;
262  return true;
263  case X86::VMOVAPSYrm:
264  case X86::VMOVUPSYrm:
265  case X86::VMOVAPDYrm:
266  case X86::VMOVUPDYrm:
267  case X86::VMOVDQAYrm:
268  case X86::VMOVDQUYrm:
269  case X86::VMOVAPSZ256rm:
270  case X86::VMOVUPSZ256rm:
271  case X86::VMOVAPSZ256rm_NOVLX:
272  case X86::VMOVUPSZ256rm_NOVLX:
273  case X86::VMOVAPDZ256rm:
274  case X86::VMOVUPDZ256rm:
275  case X86::VMOVDQU8Z256rm:
276  case X86::VMOVDQU16Z256rm:
277  case X86::VMOVDQA32Z256rm:
278  case X86::VMOVDQU32Z256rm:
279  case X86::VMOVDQA64Z256rm:
280  case X86::VMOVDQU64Z256rm:
281  MemBytes = 32;
282  return true;
283  case X86::VMOVAPSZrm:
284  case X86::VMOVUPSZrm:
285  case X86::VMOVAPDZrm:
286  case X86::VMOVUPDZrm:
287  case X86::VMOVDQU8Zrm:
288  case X86::VMOVDQU16Zrm:
289  case X86::VMOVDQA32Zrm:
290  case X86::VMOVDQU32Zrm:
291  case X86::VMOVDQA64Zrm:
292  case X86::VMOVDQU64Zrm:
293  MemBytes = 64;
294  return true;
295  }
296 }
297 
298 static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
299  switch (Opcode) {
300  default:
301  return false;
302  case X86::MOV8mr:
303  case X86::KMOVBmk:
304  MemBytes = 1;
305  return true;
306  case X86::MOV16mr:
307  case X86::KMOVWmk:
308  MemBytes = 2;
309  return true;
310  case X86::MOV32mr:
311  case X86::MOVSSmr:
312  case X86::VMOVSSmr:
313  case X86::VMOVSSZmr:
314  case X86::KMOVDmk:
315  MemBytes = 4;
316  return true;
317  case X86::MOV64mr:
318  case X86::ST_FpP64m:
319  case X86::MOVSDmr:
320  case X86::VMOVSDmr:
321  case X86::VMOVSDZmr:
322  case X86::MMX_MOVD64mr:
323  case X86::MMX_MOVQ64mr:
324  case X86::MMX_MOVNTQmr:
325  case X86::KMOVQmk:
326  MemBytes = 8;
327  return true;
328  case X86::MOVAPSmr:
329  case X86::MOVUPSmr:
330  case X86::MOVAPDmr:
331  case X86::MOVUPDmr:
332  case X86::MOVDQAmr:
333  case X86::MOVDQUmr:
334  case X86::VMOVAPSmr:
335  case X86::VMOVUPSmr:
336  case X86::VMOVAPDmr:
337  case X86::VMOVUPDmr:
338  case X86::VMOVDQAmr:
339  case X86::VMOVDQUmr:
340  case X86::VMOVUPSZ128mr:
341  case X86::VMOVAPSZ128mr:
342  case X86::VMOVUPSZ128mr_NOVLX:
343  case X86::VMOVAPSZ128mr_NOVLX:
344  case X86::VMOVUPDZ128mr:
345  case X86::VMOVAPDZ128mr:
346  case X86::VMOVDQA32Z128mr:
347  case X86::VMOVDQU32Z128mr:
348  case X86::VMOVDQA64Z128mr:
349  case X86::VMOVDQU64Z128mr:
350  case X86::VMOVDQU8Z128mr:
351  case X86::VMOVDQU16Z128mr:
352  MemBytes = 16;
353  return true;
354  case X86::VMOVUPSYmr:
355  case X86::VMOVAPSYmr:
356  case X86::VMOVUPDYmr:
357  case X86::VMOVAPDYmr:
358  case X86::VMOVDQUYmr:
359  case X86::VMOVDQAYmr:
360  case X86::VMOVUPSZ256mr:
361  case X86::VMOVAPSZ256mr:
362  case X86::VMOVUPSZ256mr_NOVLX:
363  case X86::VMOVAPSZ256mr_NOVLX:
364  case X86::VMOVUPDZ256mr:
365  case X86::VMOVAPDZ256mr:
366  case X86::VMOVDQU8Z256mr:
367  case X86::VMOVDQU16Z256mr:
368  case X86::VMOVDQA32Z256mr:
369  case X86::VMOVDQU32Z256mr:
370  case X86::VMOVDQA64Z256mr:
371  case X86::VMOVDQU64Z256mr:
372  MemBytes = 32;
373  return true;
374  case X86::VMOVUPSZmr:
375  case X86::VMOVAPSZmr:
376  case X86::VMOVUPDZmr:
377  case X86::VMOVAPDZmr:
378  case X86::VMOVDQU8Zmr:
379  case X86::VMOVDQU16Zmr:
380  case X86::VMOVDQA32Zmr:
381  case X86::VMOVDQU32Zmr:
382  case X86::VMOVDQA64Zmr:
383  case X86::VMOVDQU64Zmr:
384  MemBytes = 64;
385  return true;
386  }
387  return false;
388 }
389 
391  int &FrameIndex) const {
392  unsigned Dummy;
393  return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
394 }
395 
397  int &FrameIndex,
398  unsigned &MemBytes) const {
399  if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
400  if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
401  return MI.getOperand(0).getReg();
402  return 0;
403 }
404 
406  int &FrameIndex) const {
407  unsigned Dummy;
408  if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
409  unsigned Reg;
410  if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
411  return Reg;
412  // Check for post-frame index elimination operations
414  if (hasLoadFromStackSlot(MI, Accesses)) {
415  FrameIndex =
416  cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
417  ->getFrameIndex();
418  return 1;
419  }
420  }
421  return 0;
422 }
423 
425  int &FrameIndex) const {
426  unsigned Dummy;
427  return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
428 }
429 
431  int &FrameIndex,
432  unsigned &MemBytes) const {
433  if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
434  if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
435  isFrameOperand(MI, 0, FrameIndex))
437  return 0;
438 }
439 
441  int &FrameIndex) const {
442  unsigned Dummy;
443  if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
444  unsigned Reg;
445  if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
446  return Reg;
447  // Check for post-frame index elimination operations
449  if (hasStoreToStackSlot(MI, Accesses)) {
450  FrameIndex =
451  cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
452  ->getFrameIndex();
453  return 1;
454  }
455  }
456  return 0;
457 }
458 
459 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
460 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
461  // Don't waste compile time scanning use-def chains of physregs.
463  return false;
464  bool isPICBase = false;
466  E = MRI.def_instr_end(); I != E; ++I) {
467  MachineInstr *DefMI = &*I;
468  if (DefMI->getOpcode() != X86::MOVPC32r)
469  return false;
470  assert(!isPICBase && "More than one PIC base?");
471  isPICBase = true;
472  }
473  return isPICBase;
474 }
475 
477  AliasAnalysis *AA) const {
478  switch (MI.getOpcode()) {
479  default: break;
480  case X86::MOV8rm:
481  case X86::MOV8rm_NOREX:
482  case X86::MOV16rm:
483  case X86::MOV32rm:
484  case X86::MOV64rm:
485  case X86::MOVSSrm:
486  case X86::MOVSDrm:
487  case X86::MOVAPSrm:
488  case X86::MOVUPSrm:
489  case X86::MOVAPDrm:
490  case X86::MOVUPDrm:
491  case X86::MOVDQArm:
492  case X86::MOVDQUrm:
493  case X86::VMOVSSrm:
494  case X86::VMOVSDrm:
495  case X86::VMOVAPSrm:
496  case X86::VMOVUPSrm:
497  case X86::VMOVAPDrm:
498  case X86::VMOVUPDrm:
499  case X86::VMOVDQArm:
500  case X86::VMOVDQUrm:
501  case X86::VMOVAPSYrm:
502  case X86::VMOVUPSYrm:
503  case X86::VMOVAPDYrm:
504  case X86::VMOVUPDYrm:
505  case X86::VMOVDQAYrm:
506  case X86::VMOVDQUYrm:
507  case X86::MMX_MOVD64rm:
508  case X86::MMX_MOVQ64rm:
509  // AVX-512
510  case X86::VMOVSSZrm:
511  case X86::VMOVSDZrm:
512  case X86::VMOVAPDZ128rm:
513  case X86::VMOVAPDZ256rm:
514  case X86::VMOVAPDZrm:
515  case X86::VMOVAPSZ128rm:
516  case X86::VMOVAPSZ256rm:
517  case X86::VMOVAPSZ128rm_NOVLX:
518  case X86::VMOVAPSZ256rm_NOVLX:
519  case X86::VMOVAPSZrm:
520  case X86::VMOVDQA32Z128rm:
521  case X86::VMOVDQA32Z256rm:
522  case X86::VMOVDQA32Zrm:
523  case X86::VMOVDQA64Z128rm:
524  case X86::VMOVDQA64Z256rm:
525  case X86::VMOVDQA64Zrm:
526  case X86::VMOVDQU16Z128rm:
527  case X86::VMOVDQU16Z256rm:
528  case X86::VMOVDQU16Zrm:
529  case X86::VMOVDQU32Z128rm:
530  case X86::VMOVDQU32Z256rm:
531  case X86::VMOVDQU32Zrm:
532  case X86::VMOVDQU64Z128rm:
533  case X86::VMOVDQU64Z256rm:
534  case X86::VMOVDQU64Zrm:
535  case X86::VMOVDQU8Z128rm:
536  case X86::VMOVDQU8Z256rm:
537  case X86::VMOVDQU8Zrm:
538  case X86::VMOVUPDZ128rm:
539  case X86::VMOVUPDZ256rm:
540  case X86::VMOVUPDZrm:
541  case X86::VMOVUPSZ128rm:
542  case X86::VMOVUPSZ256rm:
543  case X86::VMOVUPSZ128rm_NOVLX:
544  case X86::VMOVUPSZ256rm_NOVLX:
545  case X86::VMOVUPSZrm: {
546  // Loads from constant pools are trivially rematerializable.
547  if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
548  MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
549  MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
550  MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
552  unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
553  if (BaseReg == 0 || BaseReg == X86::RIP)
554  return true;
555  // Allow re-materialization of PIC load.
557  return false;
558  const MachineFunction &MF = *MI.getParent()->getParent();
559  const MachineRegisterInfo &MRI = MF.getRegInfo();
560  return regIsPICBase(BaseReg, MRI);
561  }
562  return false;
563  }
564 
565  case X86::LEA32r:
566  case X86::LEA64r: {
567  if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
568  MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
569  MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
570  !MI.getOperand(1 + X86::AddrDisp).isReg()) {
571  // lea fi#, lea GV, etc. are all rematerializable.
572  if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
573  return true;
574  unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
575  if (BaseReg == 0)
576  return true;
577  // Allow re-materialization of lea PICBase + x.
578  const MachineFunction &MF = *MI.getParent()->getParent();
579  const MachineRegisterInfo &MRI = MF.getRegInfo();
580  return regIsPICBase(BaseReg, MRI);
581  }
582  return false;
583  }
584  }
585 
586  // All other instructions marked M_REMATERIALIZABLE are always trivially
587  // rematerializable.
588  return true;
589 }
590 
593  unsigned DestReg, unsigned SubIdx,
594  const MachineInstr &Orig,
595  const TargetRegisterInfo &TRI) const {
596  bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
597  if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
598  // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
599  // effects.
600  int Value;
601  switch (Orig.getOpcode()) {
602  case X86::MOV32r0: Value = 0; break;
603  case X86::MOV32r1: Value = 1; break;
604  case X86::MOV32r_1: Value = -1; break;
605  default:
606  llvm_unreachable("Unexpected instruction!");
607  }
608 
609  const DebugLoc &DL = Orig.getDebugLoc();
610  BuildMI(MBB, I, DL, get(X86::MOV32ri))
611  .add(Orig.getOperand(0))
612  .addImm(Value);
613  } else {
614  MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
615  MBB.insert(I, MI);
616  }
617 
618  MachineInstr &NewMI = *std::prev(I);
619  NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
620 }
621 
622 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
624  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
625  MachineOperand &MO = MI.getOperand(i);
626  if (MO.isReg() && MO.isDef() &&
627  MO.getReg() == X86::EFLAGS && !MO.isDead()) {
628  return true;
629  }
630  }
631  return false;
632 }
633 
634 /// Check whether the shift count for a machine operand is non-zero.
635 inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
636  unsigned ShiftAmtOperandIdx) {
637  // The shift count is six bits with the REX.W prefix and five bits without.
638  unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
639  unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
640  return Imm & ShiftCountMask;
641 }
642 
643 /// Check whether the given shift count is appropriate
644 /// can be represented by a LEA instruction.
645 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
646  // Left shift instructions can be transformed into load-effective-address
647  // instructions if we can encode them appropriately.
648  // A LEA instruction utilizes a SIB byte to encode its scale factor.
649  // The SIB.scale field is two bits wide which means that we can encode any
650  // shift amount less than 4.
651  return ShAmt < 4 && ShAmt > 0;
652 }
653 
655  unsigned Opc, bool AllowSP, unsigned &NewSrc,
656  bool &isKill, MachineOperand &ImplicitOp,
657  LiveVariables *LV) const {
658  MachineFunction &MF = *MI.getParent()->getParent();
659  const TargetRegisterClass *RC;
660  if (AllowSP) {
661  RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
662  } else {
663  RC = Opc != X86::LEA32r ?
664  &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
665  }
666  unsigned SrcReg = Src.getReg();
667 
668  // For both LEA64 and LEA32 the register already has essentially the right
669  // type (32-bit or 64-bit) we may just need to forbid SP.
670  if (Opc != X86::LEA64_32r) {
671  NewSrc = SrcReg;
672  isKill = Src.isKill();
673  assert(!Src.isUndef() && "Undef op doesn't need optimization");
674 
676  !MF.getRegInfo().constrainRegClass(NewSrc, RC))
677  return false;
678 
679  return true;
680  }
681 
682  // This is for an LEA64_32r and incoming registers are 32-bit. One way or
683  // another we need to add 64-bit registers to the final MI.
685  ImplicitOp = Src;
686  ImplicitOp.setImplicit();
687 
688  NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
689  isKill = Src.isKill();
690  assert(!Src.isUndef() && "Undef op doesn't need optimization");
691  } else {
692  // Virtual register of the wrong class, we have to create a temporary 64-bit
693  // vreg to feed into the LEA.
694  NewSrc = MF.getRegInfo().createVirtualRegister(RC);
695  MachineInstr *Copy =
696  BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
697  .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
698  .add(Src);
699 
700  // Which is obviously going to be dead after we're done with it.
701  isKill = true;
702 
703  if (LV)
704  LV->replaceKillInstruction(SrcReg, MI, *Copy);
705  }
706 
707  // We've set all the parameters without issue.
708  return true;
709 }
710 
711 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
712  unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
713  LiveVariables *LV, bool Is8BitOp) const {
714  // We handle 8-bit adds and various 16-bit opcodes in the switch below.
715  MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
716  assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
717  *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
718  "Unexpected type for LEA transform");
719 
720  // TODO: For a 32-bit target, we need to adjust the LEA variables with
721  // something like this:
722  // Opcode = X86::LEA32r;
723  // InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
724  // OutRegLEA =
725  // Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
726  // : RegInfo.createVirtualRegister(&X86::GR32RegClass);
727  if (!Subtarget.is64Bit())
728  return nullptr;
729 
730  unsigned Opcode = X86::LEA64_32r;
731  unsigned InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
732  unsigned OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
733 
734  // Build and insert into an implicit UNDEF value. This is OK because
735  // we will be shifting and then extracting the lower 8/16-bits.
736  // This has the potential to cause partial register stall. e.g.
737  // movw (%rbp,%rcx,2), %dx
738  // leal -65(%rdx), %esi
739  // But testing has shown this *does* help performance in 64-bit mode (at
740  // least on modern x86 machines).
742  unsigned Dest = MI.getOperand(0).getReg();
743  unsigned Src = MI.getOperand(1).getReg();
744  bool IsDead = MI.getOperand(0).isDead();
745  bool IsKill = MI.getOperand(1).isKill();
746  unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
747  assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
748  BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
749  MachineInstr *InsMI =
750  BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
751  .addReg(InRegLEA, RegState::Define, SubReg)
752  .addReg(Src, getKillRegState(IsKill));
753 
754  MachineInstrBuilder MIB =
755  BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
756  switch (MIOpc) {
757  default: llvm_unreachable("Unreachable!");
758  case X86::SHL8ri:
759  case X86::SHL16ri: {
760  unsigned ShAmt = MI.getOperand(2).getImm();
761  MIB.addReg(0).addImm(1ULL << ShAmt)
762  .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
763  break;
764  }
765  case X86::INC8r:
766  case X86::INC16r:
767  addRegOffset(MIB, InRegLEA, true, 1);
768  break;
769  case X86::DEC8r:
770  case X86::DEC16r:
771  addRegOffset(MIB, InRegLEA, true, -1);
772  break;
773  case X86::ADD8ri:
774  case X86::ADD8ri_DB:
775  case X86::ADD16ri:
776  case X86::ADD16ri8:
777  case X86::ADD16ri_DB:
778  case X86::ADD16ri8_DB:
779  addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
780  break;
781  case X86::ADD8rr:
782  case X86::ADD8rr_DB:
783  case X86::ADD16rr:
784  case X86::ADD16rr_DB: {
785  unsigned Src2 = MI.getOperand(2).getReg();
786  bool IsKill2 = MI.getOperand(2).isKill();
787  assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
788  unsigned InRegLEA2 = 0;
789  MachineInstr *InsMI2 = nullptr;
790  if (Src == Src2) {
791  // ADD8rr/ADD16rr killed %reg1028, %reg1028
792  // just a single insert_subreg.
793  addRegReg(MIB, InRegLEA, true, InRegLEA, false);
794  } else {
795  if (Subtarget.is64Bit())
796  InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
797  else
798  InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
799  // Build and insert into an implicit UNDEF value. This is OK because
800  // we will be shifting and then extracting the lower 8/16-bits.
801  BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2);
802  InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
803  .addReg(InRegLEA2, RegState::Define, SubReg)
804  .addReg(Src2, getKillRegState(IsKill2));
805  addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
806  }
807  if (LV && IsKill2 && InsMI2)
808  LV->replaceKillInstruction(Src2, MI, *InsMI2);
809  break;
810  }
811  }
812 
813  MachineInstr *NewMI = MIB;
814  MachineInstr *ExtMI =
815  BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
816  .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
817  .addReg(OutRegLEA, RegState::Kill, SubReg);
818 
819  if (LV) {
820  // Update live variables.
821  LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
822  LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
823  if (IsKill)
824  LV->replaceKillInstruction(Src, MI, *InsMI);
825  if (IsDead)
826  LV->replaceKillInstruction(Dest, MI, *ExtMI);
827  }
828 
829  return ExtMI;
830 }
831 
832 /// This method must be implemented by targets that
833 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
834 /// may be able to convert a two-address instruction into a true
835 /// three-address instruction on demand. This allows the X86 target (for
836 /// example) to convert ADD and SHL instructions into LEA instructions if they
837 /// would require register copies due to two-addressness.
838 ///
839 /// This method returns a null pointer if the transformation cannot be
840 /// performed, otherwise it returns the new instruction.
841 ///
842 MachineInstr *
844  MachineInstr &MI, LiveVariables *LV) const {
845  // The following opcodes also sets the condition code register(s). Only
846  // convert them to equivalent lea if the condition code register def's
847  // are dead!
848  if (hasLiveCondCodeDef(MI))
849  return nullptr;
850 
851  MachineFunction &MF = *MI.getParent()->getParent();
852  // All instructions input are two-addr instructions. Get the known operands.
853  const MachineOperand &Dest = MI.getOperand(0);
854  const MachineOperand &Src = MI.getOperand(1);
855 
856  // Ideally, operations with undef should be folded before we get here, but we
857  // can't guarantee it. Bail out because optimizing undefs is a waste of time.
858  // Without this, we have to forward undef state to new register operands to
859  // avoid machine verifier errors.
860  if (Src.isUndef())
861  return nullptr;
862  if (MI.getNumOperands() > 2)
863  if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
864  return nullptr;
865 
866  MachineInstr *NewMI = nullptr;
867  bool Is64Bit = Subtarget.is64Bit();
868 
869  bool Is8BitOp = false;
870  unsigned MIOpc = MI.getOpcode();
871  switch (MIOpc) {
872  default: return nullptr;
873  case X86::SHL64ri: {
874  assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
875  unsigned ShAmt = getTruncatedShiftCount(MI, 2);
876  if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
877 
878  // LEA can't handle RSP.
880  !MF.getRegInfo().constrainRegClass(Src.getReg(),
881  &X86::GR64_NOSPRegClass))
882  return nullptr;
883 
884  NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
885  .add(Dest)
886  .addReg(0)
887  .addImm(1ULL << ShAmt)
888  .add(Src)
889  .addImm(0)
890  .addReg(0);
891  break;
892  }
893  case X86::SHL32ri: {
894  assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
895  unsigned ShAmt = getTruncatedShiftCount(MI, 2);
896  if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
897 
898  unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
899 
900  // LEA can't handle ESP.
901  bool isKill;
902  unsigned SrcReg;
903  MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
904  if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
905  SrcReg, isKill, ImplicitOp, LV))
906  return nullptr;
907 
908  MachineInstrBuilder MIB =
909  BuildMI(MF, MI.getDebugLoc(), get(Opc))
910  .add(Dest)
911  .addReg(0)
912  .addImm(1ULL << ShAmt)
913  .addReg(SrcReg, getKillRegState(isKill))
914  .addImm(0)
915  .addReg(0);
916  if (ImplicitOp.getReg() != 0)
917  MIB.add(ImplicitOp);
918  NewMI = MIB;
919 
920  break;
921  }
922  case X86::SHL8ri:
923  Is8BitOp = true;
925  case X86::SHL16ri: {
926  assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
927  unsigned ShAmt = getTruncatedShiftCount(MI, 2);
928  if (!isTruncatedShiftCountForLEA(ShAmt))
929  return nullptr;
930  return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
931  }
932  case X86::INC64r:
933  case X86::INC32r: {
934  assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
935  unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
936  (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
937  bool isKill;
938  unsigned SrcReg;
939  MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
940  if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
941  ImplicitOp, LV))
942  return nullptr;
943 
944  MachineInstrBuilder MIB =
945  BuildMI(MF, MI.getDebugLoc(), get(Opc))
946  .add(Dest)
947  .addReg(SrcReg, getKillRegState(isKill));
948  if (ImplicitOp.getReg() != 0)
949  MIB.add(ImplicitOp);
950 
951  NewMI = addOffset(MIB, 1);
952  break;
953  }
954  case X86::DEC64r:
955  case X86::DEC32r: {
956  assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
957  unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
958  : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
959 
960  bool isKill;
961  unsigned SrcReg;
962  MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
963  if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
964  ImplicitOp, LV))
965  return nullptr;
966 
967  MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
968  .add(Dest)
969  .addReg(SrcReg, getKillRegState(isKill));
970  if (ImplicitOp.getReg() != 0)
971  MIB.add(ImplicitOp);
972 
973  NewMI = addOffset(MIB, -1);
974 
975  break;
976  }
977  case X86::DEC8r:
978  case X86::INC8r:
979  Is8BitOp = true;
981  case X86::DEC16r:
982  case X86::INC16r:
983  return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
984  case X86::ADD64rr:
985  case X86::ADD64rr_DB:
986  case X86::ADD32rr:
987  case X86::ADD32rr_DB: {
988  assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
989  unsigned Opc;
990  if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
991  Opc = X86::LEA64r;
992  else
993  Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
994 
995  bool isKill;
996  unsigned SrcReg;
997  MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
998  if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
999  SrcReg, isKill, ImplicitOp, LV))
1000  return nullptr;
1001 
1002  const MachineOperand &Src2 = MI.getOperand(2);
1003  bool isKill2;
1004  unsigned SrcReg2;
1005  MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1006  if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
1007  SrcReg2, isKill2, ImplicitOp2, LV))
1008  return nullptr;
1009 
1010  MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1011  if (ImplicitOp.getReg() != 0)
1012  MIB.add(ImplicitOp);
1013  if (ImplicitOp2.getReg() != 0)
1014  MIB.add(ImplicitOp2);
1015 
1016  NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1017  if (LV && Src2.isKill())
1018  LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
1019  break;
1020  }
1021  case X86::ADD8rr:
1022  case X86::ADD8rr_DB:
1023  Is8BitOp = true;
1025  case X86::ADD16rr:
1026  case X86::ADD16rr_DB:
1027  return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1028  case X86::ADD64ri32:
1029  case X86::ADD64ri8:
1030  case X86::ADD64ri32_DB:
1031  case X86::ADD64ri8_DB:
1032  assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1033  NewMI = addOffset(
1034  BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
1035  MI.getOperand(2));
1036  break;
1037  case X86::ADD32ri:
1038  case X86::ADD32ri8:
1039  case X86::ADD32ri_DB:
1040  case X86::ADD32ri8_DB: {
1041  assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1042  unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1043 
1044  bool isKill;
1045  unsigned SrcReg;
1046  MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1047  if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1048  SrcReg, isKill, ImplicitOp, LV))
1049  return nullptr;
1050 
1051  MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1052  .add(Dest)
1053  .addReg(SrcReg, getKillRegState(isKill));
1054  if (ImplicitOp.getReg() != 0)
1055  MIB.add(ImplicitOp);
1056 
1057  NewMI = addOffset(MIB, MI.getOperand(2));
1058  break;
1059  }
1060  case X86::ADD8ri:
1061  case X86::ADD8ri_DB:
1062  Is8BitOp = true;
1064  case X86::ADD16ri:
1065  case X86::ADD16ri8:
1066  case X86::ADD16ri_DB:
1067  case X86::ADD16ri8_DB:
1068  return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1069  case X86::VMOVDQU8Z128rmk:
1070  case X86::VMOVDQU8Z256rmk:
1071  case X86::VMOVDQU8Zrmk:
1072  case X86::VMOVDQU16Z128rmk:
1073  case X86::VMOVDQU16Z256rmk:
1074  case X86::VMOVDQU16Zrmk:
1075  case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
1076  case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
1077  case X86::VMOVDQU32Zrmk: case X86::VMOVDQA32Zrmk:
1078  case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
1079  case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
1080  case X86::VMOVDQU64Zrmk: case X86::VMOVDQA64Zrmk:
1081  case X86::VMOVUPDZ128rmk: case X86::VMOVAPDZ128rmk:
1082  case X86::VMOVUPDZ256rmk: case X86::VMOVAPDZ256rmk:
1083  case X86::VMOVUPDZrmk: case X86::VMOVAPDZrmk:
1084  case X86::VMOVUPSZ128rmk: case X86::VMOVAPSZ128rmk:
1085  case X86::VMOVUPSZ256rmk: case X86::VMOVAPSZ256rmk:
1086  case X86::VMOVUPSZrmk: case X86::VMOVAPSZrmk: {
1087  unsigned Opc;
1088  switch (MIOpc) {
1089  default: llvm_unreachable("Unreachable!");
1090  case X86::VMOVDQU8Z128rmk: Opc = X86::VPBLENDMBZ128rmk; break;
1091  case X86::VMOVDQU8Z256rmk: Opc = X86::VPBLENDMBZ256rmk; break;
1092  case X86::VMOVDQU8Zrmk: Opc = X86::VPBLENDMBZrmk; break;
1093  case X86::VMOVDQU16Z128rmk: Opc = X86::VPBLENDMWZ128rmk; break;
1094  case X86::VMOVDQU16Z256rmk: Opc = X86::VPBLENDMWZ256rmk; break;
1095  case X86::VMOVDQU16Zrmk: Opc = X86::VPBLENDMWZrmk; break;
1096  case X86::VMOVDQU32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
1097  case X86::VMOVDQU32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
1098  case X86::VMOVDQU32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
1099  case X86::VMOVDQU64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
1100  case X86::VMOVDQU64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
1101  case X86::VMOVDQU64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
1102  case X86::VMOVUPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
1103  case X86::VMOVUPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
1104  case X86::VMOVUPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
1105  case X86::VMOVUPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
1106  case X86::VMOVUPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
1107  case X86::VMOVUPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
1108  case X86::VMOVDQA32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
1109  case X86::VMOVDQA32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
1110  case X86::VMOVDQA32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
1111  case X86::VMOVDQA64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
1112  case X86::VMOVDQA64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
1113  case X86::VMOVDQA64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
1114  case X86::VMOVAPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
1115  case X86::VMOVAPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
1116  case X86::VMOVAPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
1117  case X86::VMOVAPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
1118  case X86::VMOVAPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
1119  case X86::VMOVAPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
1120  }
1121 
1122  NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1123  .add(Dest)
1124  .add(MI.getOperand(2))
1125  .add(Src)
1126  .add(MI.getOperand(3))
1127  .add(MI.getOperand(4))
1128  .add(MI.getOperand(5))
1129  .add(MI.getOperand(6))
1130  .add(MI.getOperand(7));
1131  break;
1132  }
1133  case X86::VMOVDQU8Z128rrk:
1134  case X86::VMOVDQU8Z256rrk:
1135  case X86::VMOVDQU8Zrrk:
1136  case X86::VMOVDQU16Z128rrk:
1137  case X86::VMOVDQU16Z256rrk:
1138  case X86::VMOVDQU16Zrrk:
1139  case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
1140  case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
1141  case X86::VMOVDQU32Zrrk: case X86::VMOVDQA32Zrrk:
1142  case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
1143  case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
1144  case X86::VMOVDQU64Zrrk: case X86::VMOVDQA64Zrrk:
1145  case X86::VMOVUPDZ128rrk: case X86::VMOVAPDZ128rrk:
1146  case X86::VMOVUPDZ256rrk: case X86::VMOVAPDZ256rrk:
1147  case X86::VMOVUPDZrrk: case X86::VMOVAPDZrrk:
1148  case X86::VMOVUPSZ128rrk: case X86::VMOVAPSZ128rrk:
1149  case X86::VMOVUPSZ256rrk: case X86::VMOVAPSZ256rrk:
1150  case X86::VMOVUPSZrrk: case X86::VMOVAPSZrrk: {
1151  unsigned Opc;
1152  switch (MIOpc) {
1153  default: llvm_unreachable("Unreachable!");
1154  case X86::VMOVDQU8Z128rrk: Opc = X86::VPBLENDMBZ128rrk; break;
1155  case X86::VMOVDQU8Z256rrk: Opc = X86::VPBLENDMBZ256rrk; break;
1156  case X86::VMOVDQU8Zrrk: Opc = X86::VPBLENDMBZrrk; break;
1157  case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
1158  case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
1159  case X86::VMOVDQU16Zrrk: Opc = X86::VPBLENDMWZrrk; break;
1160  case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1161  case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1162  case X86::VMOVDQU32Zrrk: Opc = X86::VPBLENDMDZrrk; break;
1163  case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1164  case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1165  case X86::VMOVDQU64Zrrk: Opc = X86::VPBLENDMQZrrk; break;
1166  case X86::VMOVUPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break;
1167  case X86::VMOVUPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break;
1168  case X86::VMOVUPDZrrk: Opc = X86::VBLENDMPDZrrk; break;
1169  case X86::VMOVUPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break;
1170  case X86::VMOVUPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break;
1171  case X86::VMOVUPSZrrk: Opc = X86::VBLENDMPSZrrk; break;
1172  case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1173  case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1174  case X86::VMOVDQA32Zrrk: Opc = X86::VPBLENDMDZrrk; break;
1175  case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1176  case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1177  case X86::VMOVDQA64Zrrk: Opc = X86::VPBLENDMQZrrk; break;
1178  case X86::VMOVAPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break;
1179  case X86::VMOVAPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break;
1180  case X86::VMOVAPDZrrk: Opc = X86::VBLENDMPDZrrk; break;
1181  case X86::VMOVAPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break;
1182  case X86::VMOVAPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break;
1183  case X86::VMOVAPSZrrk: Opc = X86::VBLENDMPSZrrk; break;
1184  }
1185 
1186  NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1187  .add(Dest)
1188  .add(MI.getOperand(2))
1189  .add(Src)
1190  .add(MI.getOperand(3));
1191  break;
1192  }
1193  }
1194 
1195  if (!NewMI) return nullptr;
1196 
1197  if (LV) { // Update live variables
1198  if (Src.isKill())
1199  LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
1200  if (Dest.isDead())
1201  LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
1202  }
1203 
1204  MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
1205  return NewMI;
1206 }
1207 
1208 /// This determines which of three possible cases of a three source commute
1209 /// the source indexes correspond to taking into account any mask operands.
1210 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
1211 /// possible.
1212 /// Case 0 - Possible to commute the first and second operands.
1213 /// Case 1 - Possible to commute the first and third operands.
1214 /// Case 2 - Possible to commute the second and third operands.
1215 static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
1216  unsigned SrcOpIdx2) {
1217  // Put the lowest index to SrcOpIdx1 to simplify the checks below.
1218  if (SrcOpIdx1 > SrcOpIdx2)
1219  std::swap(SrcOpIdx1, SrcOpIdx2);
1220 
1221  unsigned Op1 = 1, Op2 = 2, Op3 = 3;
1222  if (X86II::isKMasked(TSFlags)) {
1223  Op2++;
1224  Op3++;
1225  }
1226 
1227  if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
1228  return 0;
1229  if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
1230  return 1;
1231  if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
1232  return 2;
1233  llvm_unreachable("Unknown three src commute case.");
1234 }
1235 
1237  const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
1238  const X86InstrFMA3Group &FMA3Group) const {
1239 
1240  unsigned Opc = MI.getOpcode();
1241 
1242  // TODO: Commuting the 1st operand of FMA*_Int requires some additional
1243  // analysis. The commute optimization is legal only if all users of FMA*_Int
1244  // use only the lowest element of the FMA*_Int instruction. Such analysis are
1245  // not implemented yet. So, just return 0 in that case.
1246  // When such analysis are available this place will be the right place for
1247  // calling it.
1248  assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&
1249  "Intrinsic instructions can't commute operand 1");
1250 
1251  // Determine which case this commute is or if it can't be done.
1252  unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1253  SrcOpIdx2);
1254  assert(Case < 3 && "Unexpected case number!");
1255 
1256  // Define the FMA forms mapping array that helps to map input FMA form
1257  // to output FMA form to preserve the operation semantics after
1258  // commuting the operands.
1259  const unsigned Form132Index = 0;
1260  const unsigned Form213Index = 1;
1261  const unsigned Form231Index = 2;
1262  static const unsigned FormMapping[][3] = {
1263  // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
1264  // FMA132 A, C, b; ==> FMA231 C, A, b;
1265  // FMA213 B, A, c; ==> FMA213 A, B, c;
1266  // FMA231 C, A, b; ==> FMA132 A, C, b;
1267  { Form231Index, Form213Index, Form132Index },
1268  // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
1269  // FMA132 A, c, B; ==> FMA132 B, c, A;
1270  // FMA213 B, a, C; ==> FMA231 C, a, B;
1271  // FMA231 C, a, B; ==> FMA213 B, a, C;
1272  { Form132Index, Form231Index, Form213Index },
1273  // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
1274  // FMA132 a, C, B; ==> FMA213 a, B, C;
1275  // FMA213 b, A, C; ==> FMA132 b, C, A;
1276  // FMA231 c, A, B; ==> FMA231 c, B, A;
1277  { Form213Index, Form132Index, Form231Index }
1278  };
1279 
1280  unsigned FMAForms[3];
1281  FMAForms[0] = FMA3Group.get132Opcode();
1282  FMAForms[1] = FMA3Group.get213Opcode();
1283  FMAForms[2] = FMA3Group.get231Opcode();
1284  unsigned FormIndex;
1285  for (FormIndex = 0; FormIndex < 3; FormIndex++)
1286  if (Opc == FMAForms[FormIndex])
1287  break;
1288 
1289  // Everything is ready, just adjust the FMA opcode and return it.
1290  FormIndex = FormMapping[Case][FormIndex];
1291  return FMAForms[FormIndex];
1292 }
1293 
1294 static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
1295  unsigned SrcOpIdx2) {
1296  // Determine which case this commute is or if it can't be done.
1297  unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1298  SrcOpIdx2);
1299  assert(Case < 3 && "Unexpected case value!");
1300 
1301  // For each case we need to swap two pairs of bits in the final immediate.
1302  static const uint8_t SwapMasks[3][4] = {
1303  { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
1304  { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
1305  { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
1306  };
1307 
1308  uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
1309  // Clear out the bits we are swapping.
1310  uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
1311  SwapMasks[Case][2] | SwapMasks[Case][3]);
1312  // If the immediate had a bit of the pair set, then set the opposite bit.
1313  if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
1314  if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
1315  if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
1316  if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
1317  MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
1318 }
1319 
1320 // Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
1321 // commuted.
1322 static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
1323 #define VPERM_CASES(Suffix) \
1324  case X86::VPERMI2##Suffix##128rr: case X86::VPERMT2##Suffix##128rr: \
1325  case X86::VPERMI2##Suffix##256rr: case X86::VPERMT2##Suffix##256rr: \
1326  case X86::VPERMI2##Suffix##rr: case X86::VPERMT2##Suffix##rr: \
1327  case X86::VPERMI2##Suffix##128rm: case X86::VPERMT2##Suffix##128rm: \
1328  case X86::VPERMI2##Suffix##256rm: case X86::VPERMT2##Suffix##256rm: \
1329  case X86::VPERMI2##Suffix##rm: case X86::VPERMT2##Suffix##rm: \
1330  case X86::VPERMI2##Suffix##128rrkz: case X86::VPERMT2##Suffix##128rrkz: \
1331  case X86::VPERMI2##Suffix##256rrkz: case X86::VPERMT2##Suffix##256rrkz: \
1332  case X86::VPERMI2##Suffix##rrkz: case X86::VPERMT2##Suffix##rrkz: \
1333  case X86::VPERMI2##Suffix##128rmkz: case X86::VPERMT2##Suffix##128rmkz: \
1334  case X86::VPERMI2##Suffix##256rmkz: case X86::VPERMT2##Suffix##256rmkz: \
1335  case X86::VPERMI2##Suffix##rmkz: case X86::VPERMT2##Suffix##rmkz:
1336 
1337 #define VPERM_CASES_BROADCAST(Suffix) \
1338  VPERM_CASES(Suffix) \
1339  case X86::VPERMI2##Suffix##128rmb: case X86::VPERMT2##Suffix##128rmb: \
1340  case X86::VPERMI2##Suffix##256rmb: case X86::VPERMT2##Suffix##256rmb: \
1341  case X86::VPERMI2##Suffix##rmb: case X86::VPERMT2##Suffix##rmb: \
1342  case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
1343  case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
1344  case X86::VPERMI2##Suffix##rmbkz: case X86::VPERMT2##Suffix##rmbkz:
1345 
1346  switch (Opcode) {
1347  default: return false;
1348  VPERM_CASES(B)
1353  VPERM_CASES(W)
1354  return true;
1355  }
1356 #undef VPERM_CASES_BROADCAST
1357 #undef VPERM_CASES
1358 }
1359 
1360 // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
1361 // from the I opcode to the T opcode and vice versa.
1362 static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
1363 #define VPERM_CASES(Orig, New) \
1364  case X86::Orig##128rr: return X86::New##128rr; \
1365  case X86::Orig##128rrkz: return X86::New##128rrkz; \
1366  case X86::Orig##128rm: return X86::New##128rm; \
1367  case X86::Orig##128rmkz: return X86::New##128rmkz; \
1368  case X86::Orig##256rr: return X86::New##256rr; \
1369  case X86::Orig##256rrkz: return X86::New##256rrkz; \
1370  case X86::Orig##256rm: return X86::New##256rm; \
1371  case X86::Orig##256rmkz: return X86::New##256rmkz; \
1372  case X86::Orig##rr: return X86::New##rr; \
1373  case X86::Orig##rrkz: return X86::New##rrkz; \
1374  case X86::Orig##rm: return X86::New##rm; \
1375  case X86::Orig##rmkz: return X86::New##rmkz;
1376 
1377 #define VPERM_CASES_BROADCAST(Orig, New) \
1378  VPERM_CASES(Orig, New) \
1379  case X86::Orig##128rmb: return X86::New##128rmb; \
1380  case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
1381  case X86::Orig##256rmb: return X86::New##256rmb; \
1382  case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
1383  case X86::Orig##rmb: return X86::New##rmb; \
1384  case X86::Orig##rmbkz: return X86::New##rmbkz;
1385 
1386  switch (Opcode) {
1387  VPERM_CASES(VPERMI2B, VPERMT2B)
1388  VPERM_CASES_BROADCAST(VPERMI2D, VPERMT2D)
1389  VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
1390  VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
1391  VPERM_CASES_BROADCAST(VPERMI2Q, VPERMT2Q)
1392  VPERM_CASES(VPERMI2W, VPERMT2W)
1393  VPERM_CASES(VPERMT2B, VPERMI2B)
1394  VPERM_CASES_BROADCAST(VPERMT2D, VPERMI2D)
1395  VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
1396  VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
1397  VPERM_CASES_BROADCAST(VPERMT2Q, VPERMI2Q)
1398  VPERM_CASES(VPERMT2W, VPERMI2W)
1399  }
1400 
1401  llvm_unreachable("Unreachable!");
1402 #undef VPERM_CASES_BROADCAST
1403 #undef VPERM_CASES
1404 }
1405 
1407  unsigned OpIdx1,
1408  unsigned OpIdx2) const {
1409  auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
1410  if (NewMI)
1411  return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
1412  return MI;
1413  };
1414 
1415  switch (MI.getOpcode()) {
1416  case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1417  case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1418  case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1419  case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1420  case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1421  case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1422  unsigned Opc;
1423  unsigned Size;
1424  switch (MI.getOpcode()) {
1425  default: llvm_unreachable("Unreachable!");
1426  case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1427  case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1428  case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1429  case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1430  case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1431  case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1432  }
1433  unsigned Amt = MI.getOperand(3).getImm();
1434  auto &WorkingMI = cloneIfNew(MI);
1435  WorkingMI.setDesc(get(Opc));
1436  WorkingMI.getOperand(3).setImm(Size - Amt);
1437  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1438  OpIdx1, OpIdx2);
1439  }
1440  case X86::PFSUBrr:
1441  case X86::PFSUBRrr: {
1442  // PFSUB x, y: x = x - y
1443  // PFSUBR x, y: x = y - x
1444  unsigned Opc =
1445  (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
1446  auto &WorkingMI = cloneIfNew(MI);
1447  WorkingMI.setDesc(get(Opc));
1448  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1449  OpIdx1, OpIdx2);
1450  }
1451  case X86::BLENDPDrri:
1452  case X86::BLENDPSrri:
1453  case X86::VBLENDPDrri:
1454  case X86::VBLENDPSrri:
1455  // If we're optimizing for size, try to use MOVSD/MOVSS.
1456  if (MI.getParent()->getParent()->getFunction().optForSize()) {
1457  unsigned Mask, Opc;
1458  switch (MI.getOpcode()) {
1459  default: llvm_unreachable("Unreachable!");
1460  case X86::BLENDPDrri: Opc = X86::MOVSDrr; Mask = 0x03; break;
1461  case X86::BLENDPSrri: Opc = X86::MOVSSrr; Mask = 0x0F; break;
1462  case X86::VBLENDPDrri: Opc = X86::VMOVSDrr; Mask = 0x03; break;
1463  case X86::VBLENDPSrri: Opc = X86::VMOVSSrr; Mask = 0x0F; break;
1464  }
1465  if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
1466  auto &WorkingMI = cloneIfNew(MI);
1467  WorkingMI.setDesc(get(Opc));
1468  WorkingMI.RemoveOperand(3);
1469  return TargetInstrInfo::commuteInstructionImpl(WorkingMI,
1470  /*NewMI=*/false,
1471  OpIdx1, OpIdx2);
1472  }
1473  }
1475  case X86::PBLENDWrri:
1476  case X86::VBLENDPDYrri:
1477  case X86::VBLENDPSYrri:
1478  case X86::VPBLENDDrri:
1479  case X86::VPBLENDWrri:
1480  case X86::VPBLENDDYrri:
1481  case X86::VPBLENDWYrri:{
1482  int8_t Mask;
1483  switch (MI.getOpcode()) {
1484  default: llvm_unreachable("Unreachable!");
1485  case X86::BLENDPDrri: Mask = (int8_t)0x03; break;
1486  case X86::BLENDPSrri: Mask = (int8_t)0x0F; break;
1487  case X86::PBLENDWrri: Mask = (int8_t)0xFF; break;
1488  case X86::VBLENDPDrri: Mask = (int8_t)0x03; break;
1489  case X86::VBLENDPSrri: Mask = (int8_t)0x0F; break;
1490  case X86::VBLENDPDYrri: Mask = (int8_t)0x0F; break;
1491  case X86::VBLENDPSYrri: Mask = (int8_t)0xFF; break;
1492  case X86::VPBLENDDrri: Mask = (int8_t)0x0F; break;
1493  case X86::VPBLENDWrri: Mask = (int8_t)0xFF; break;
1494  case X86::VPBLENDDYrri: Mask = (int8_t)0xFF; break;
1495  case X86::VPBLENDWYrri: Mask = (int8_t)0xFF; break;
1496  }
1497  // Only the least significant bits of Imm are used.
1498  // Using int8_t to ensure it will be sign extended to the int64_t that
1499  // setImm takes in order to match isel behavior.
1500  int8_t Imm = MI.getOperand(3).getImm() & Mask;
1501  auto &WorkingMI = cloneIfNew(MI);
1502  WorkingMI.getOperand(3).setImm(Mask ^ Imm);
1503  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1504  OpIdx1, OpIdx2);
1505  }
1506  case X86::INSERTPSrr:
1507  case X86::VINSERTPSrr:
1508  case X86::VINSERTPSZrr: {
1509  unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
1510  unsigned ZMask = Imm & 15;
1511  unsigned DstIdx = (Imm >> 4) & 3;
1512  unsigned SrcIdx = (Imm >> 6) & 3;
1513 
1514  // We can commute insertps if we zero 2 of the elements, the insertion is
1515  // "inline" and we don't override the insertion with a zero.
1516  if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
1517  countPopulation(ZMask) == 2) {
1518  unsigned AltIdx = findFirstSet((ZMask | (1 << DstIdx)) ^ 15);
1519  assert(AltIdx < 4 && "Illegal insertion index");
1520  unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
1521  auto &WorkingMI = cloneIfNew(MI);
1522  WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(AltImm);
1523  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1524  OpIdx1, OpIdx2);
1525  }
1526  return nullptr;
1527  }
1528  case X86::MOVSDrr:
1529  case X86::MOVSSrr:
1530  case X86::VMOVSDrr:
1531  case X86::VMOVSSrr:{
1532  // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
1533  assert(Subtarget.hasSSE41() && "Commuting MOVSD/MOVSS requires SSE41!");
1534 
1535  unsigned Mask, Opc;
1536  switch (MI.getOpcode()) {
1537  default: llvm_unreachable("Unreachable!");
1538  case X86::MOVSDrr: Opc = X86::BLENDPDrri; Mask = 0x02; break;
1539  case X86::MOVSSrr: Opc = X86::BLENDPSrri; Mask = 0x0E; break;
1540  case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
1541  case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
1542  }
1543 
1544  auto &WorkingMI = cloneIfNew(MI);
1545  WorkingMI.setDesc(get(Opc));
1546  WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
1547  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1548  OpIdx1, OpIdx2);
1549  }
1550  case X86::PCLMULQDQrr:
1551  case X86::VPCLMULQDQrr:
1552  case X86::VPCLMULQDQYrr:
1553  case X86::VPCLMULQDQZrr:
1554  case X86::VPCLMULQDQZ128rr:
1555  case X86::VPCLMULQDQZ256rr: {
1556  // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
1557  // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
1558  unsigned Imm = MI.getOperand(3).getImm();
1559  unsigned Src1Hi = Imm & 0x01;
1560  unsigned Src2Hi = Imm & 0x10;
1561  auto &WorkingMI = cloneIfNew(MI);
1562  WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
1563  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1564  OpIdx1, OpIdx2);
1565  }
1566  case X86::VPCMPBZ128rri: case X86::VPCMPUBZ128rri:
1567  case X86::VPCMPBZ256rri: case X86::VPCMPUBZ256rri:
1568  case X86::VPCMPBZrri: case X86::VPCMPUBZrri:
1569  case X86::VPCMPDZ128rri: case X86::VPCMPUDZ128rri:
1570  case X86::VPCMPDZ256rri: case X86::VPCMPUDZ256rri:
1571  case X86::VPCMPDZrri: case X86::VPCMPUDZrri:
1572  case X86::VPCMPQZ128rri: case X86::VPCMPUQZ128rri:
1573  case X86::VPCMPQZ256rri: case X86::VPCMPUQZ256rri:
1574  case X86::VPCMPQZrri: case X86::VPCMPUQZrri:
1575  case X86::VPCMPWZ128rri: case X86::VPCMPUWZ128rri:
1576  case X86::VPCMPWZ256rri: case X86::VPCMPUWZ256rri:
1577  case X86::VPCMPWZrri: case X86::VPCMPUWZrri:
1578  case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
1579  case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
1580  case X86::VPCMPBZrrik: case X86::VPCMPUBZrrik:
1581  case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
1582  case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
1583  case X86::VPCMPDZrrik: case X86::VPCMPUDZrrik:
1584  case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
1585  case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
1586  case X86::VPCMPQZrrik: case X86::VPCMPUQZrrik:
1587  case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
1588  case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
1589  case X86::VPCMPWZrrik: case X86::VPCMPUWZrrik: {
1590  // Flip comparison mode immediate (if necessary).
1591  unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
1592  Imm = X86::getSwappedVPCMPImm(Imm);
1593  auto &WorkingMI = cloneIfNew(MI);
1594  WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
1595  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1596  OpIdx1, OpIdx2);
1597  }
1598  case X86::VPCOMBri: case X86::VPCOMUBri:
1599  case X86::VPCOMDri: case X86::VPCOMUDri:
1600  case X86::VPCOMQri: case X86::VPCOMUQri:
1601  case X86::VPCOMWri: case X86::VPCOMUWri: {
1602  // Flip comparison mode immediate (if necessary).
1603  unsigned Imm = MI.getOperand(3).getImm() & 0x7;
1604  Imm = X86::getSwappedVPCOMImm(Imm);
1605  auto &WorkingMI = cloneIfNew(MI);
1606  WorkingMI.getOperand(3).setImm(Imm);
1607  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1608  OpIdx1, OpIdx2);
1609  }
1610  case X86::VPERM2F128rr:
1611  case X86::VPERM2I128rr: {
1612  // Flip permute source immediate.
1613  // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
1614  // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
1615  int8_t Imm = MI.getOperand(3).getImm() & 0xFF;
1616  auto &WorkingMI = cloneIfNew(MI);
1617  WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
1618  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1619  OpIdx1, OpIdx2);
1620  }
1621  case X86::MOVHLPSrr:
1622  case X86::UNPCKHPDrr:
1623  case X86::VMOVHLPSrr:
1624  case X86::VUNPCKHPDrr:
1625  case X86::VMOVHLPSZrr:
1626  case X86::VUNPCKHPDZ128rr: {
1627  assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!");
1628 
1629  unsigned Opc = MI.getOpcode();
1630  switch (Opc) {
1631  default: llvm_unreachable("Unreachable!");
1632  case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr; break;
1633  case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr; break;
1634  case X86::VMOVHLPSrr: Opc = X86::VUNPCKHPDrr; break;
1635  case X86::VUNPCKHPDrr: Opc = X86::VMOVHLPSrr; break;
1636  case X86::VMOVHLPSZrr: Opc = X86::VUNPCKHPDZ128rr; break;
1637  case X86::VUNPCKHPDZ128rr: Opc = X86::VMOVHLPSZrr; break;
1638  }
1639  auto &WorkingMI = cloneIfNew(MI);
1640  WorkingMI.setDesc(get(Opc));
1641  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1642  OpIdx1, OpIdx2);
1643  }
1644  case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
1645  case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
1646  case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
1647  case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
1648  case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
1649  case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
1650  case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
1651  case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
1652  case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
1653  case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
1654  case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
1655  case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
1656  case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
1657  case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
1658  case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
1659  case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
1660  unsigned Opc;
1661  switch (MI.getOpcode()) {
1662  default: llvm_unreachable("Unreachable!");
1663  case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1664  case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1665  case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1666  case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1667  case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1668  case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1669  case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1670  case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1671  case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1672  case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1673  case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1674  case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1675  case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1676  case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1677  case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1678  case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1679  case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1680  case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1681  case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1682  case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1683  case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1684  case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1685  case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1686  case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1687  case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1688  case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1689  case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1690  case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1691  case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1692  case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1693  case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1694  case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1695  case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1696  case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1697  case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1698  case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1699  case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1700  case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1701  case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1702  case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1703  case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1704  case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1705  case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1706  case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1707  case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1708  case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1709  case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1710  case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1711  }
1712  auto &WorkingMI = cloneIfNew(MI);
1713  WorkingMI.setDesc(get(Opc));
1714  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1715  OpIdx1, OpIdx2);
1716  }
1717  case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi:
1718  case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi:
1719  case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi:
1720  case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi:
1721  case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi:
1722  case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi:
1723  case X86::VPTERNLOGDZrrik:
1724  case X86::VPTERNLOGDZ128rrik:
1725  case X86::VPTERNLOGDZ256rrik:
1726  case X86::VPTERNLOGQZrrik:
1727  case X86::VPTERNLOGQZ128rrik:
1728  case X86::VPTERNLOGQZ256rrik:
1729  case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz:
1730  case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
1731  case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
1732  case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz:
1733  case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
1734  case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
1735  case X86::VPTERNLOGDZ128rmbi:
1736  case X86::VPTERNLOGDZ256rmbi:
1737  case X86::VPTERNLOGDZrmbi:
1738  case X86::VPTERNLOGQZ128rmbi:
1739  case X86::VPTERNLOGQZ256rmbi:
1740  case X86::VPTERNLOGQZrmbi:
1741  case X86::VPTERNLOGDZ128rmbikz:
1742  case X86::VPTERNLOGDZ256rmbikz:
1743  case X86::VPTERNLOGDZrmbikz:
1744  case X86::VPTERNLOGQZ128rmbikz:
1745  case X86::VPTERNLOGQZ256rmbikz:
1746  case X86::VPTERNLOGQZrmbikz: {
1747  auto &WorkingMI = cloneIfNew(MI);
1748  commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2);
1749  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1750  OpIdx1, OpIdx2);
1751  }
1752  default: {
1754  unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
1755  auto &WorkingMI = cloneIfNew(MI);
1756  WorkingMI.setDesc(get(Opc));
1757  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1758  OpIdx1, OpIdx2);
1759  }
1760 
1761  const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
1762  MI.getDesc().TSFlags);
1763  if (FMA3Group) {
1764  unsigned Opc =
1765  getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
1766  auto &WorkingMI = cloneIfNew(MI);
1767  WorkingMI.setDesc(get(Opc));
1768  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1769  OpIdx1, OpIdx2);
1770  }
1771 
1772  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1773  }
1774  }
1775 }
1776 
1777 bool
1778 X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
1779  unsigned &SrcOpIdx1,
1780  unsigned &SrcOpIdx2,
1781  bool IsIntrinsic) const {
1782  uint64_t TSFlags = MI.getDesc().TSFlags;
1783 
1784  unsigned FirstCommutableVecOp = 1;
1785  unsigned LastCommutableVecOp = 3;
1786  unsigned KMaskOp = -1U;
1787  if (X86II::isKMasked(TSFlags)) {
1788  // For k-zero-masked operations it is Ok to commute the first vector
1789  // operand.
1790  // For regular k-masked operations a conservative choice is done as the
1791  // elements of the first vector operand, for which the corresponding bit
1792  // in the k-mask operand is set to 0, are copied to the result of the
1793  // instruction.
1794  // TODO/FIXME: The commute still may be legal if it is known that the
1795  // k-mask operand is set to either all ones or all zeroes.
1796  // It is also Ok to commute the 1st operand if all users of MI use only
1797  // the elements enabled by the k-mask operand. For example,
1798  // v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
1799  // : v1[i];
1800  // VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
1801  // // Ok, to commute v1 in FMADD213PSZrk.
1802 
1803  // The k-mask operand has index = 2 for masked and zero-masked operations.
1804  KMaskOp = 2;
1805 
1806  // The operand with index = 1 is used as a source for those elements for
1807  // which the corresponding bit in the k-mask is set to 0.
1808  if (X86II::isKMergeMasked(TSFlags))
1809  FirstCommutableVecOp = 3;
1810 
1811  LastCommutableVecOp++;
1812  } else if (IsIntrinsic) {
1813  // Commuting the first operand of an intrinsic instruction isn't possible
1814  // unless we can prove that only the lowest element of the result is used.
1815  FirstCommutableVecOp = 2;
1816  }
1817 
1818  if (isMem(MI, LastCommutableVecOp))
1819  LastCommutableVecOp--;
1820 
1821  // Only the first RegOpsNum operands are commutable.
1822  // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
1823  // that the operand is not specified/fixed.
1824  if (SrcOpIdx1 != CommuteAnyOperandIndex &&
1825  (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
1826  SrcOpIdx1 == KMaskOp))
1827  return false;
1828  if (SrcOpIdx2 != CommuteAnyOperandIndex &&
1829  (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
1830  SrcOpIdx2 == KMaskOp))
1831  return false;
1832 
1833  // Look for two different register operands assumed to be commutable
1834  // regardless of the FMA opcode. The FMA opcode is adjusted later.
1835  if (SrcOpIdx1 == CommuteAnyOperandIndex ||
1836  SrcOpIdx2 == CommuteAnyOperandIndex) {
1837  unsigned CommutableOpIdx1 = SrcOpIdx1;
1838  unsigned CommutableOpIdx2 = SrcOpIdx2;
1839 
1840  // At least one of operands to be commuted is not specified and
1841  // this method is free to choose appropriate commutable operands.
1842  if (SrcOpIdx1 == SrcOpIdx2)
1843  // Both of operands are not fixed. By default set one of commutable
1844  // operands to the last register operand of the instruction.
1845  CommutableOpIdx2 = LastCommutableVecOp;
1846  else if (SrcOpIdx2 == CommuteAnyOperandIndex)
1847  // Only one of operands is not fixed.
1848  CommutableOpIdx2 = SrcOpIdx1;
1849 
1850  // CommutableOpIdx2 is well defined now. Let's choose another commutable
1851  // operand and assign its index to CommutableOpIdx1.
1852  unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
1853  for (CommutableOpIdx1 = LastCommutableVecOp;
1854  CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
1855  // Just ignore and skip the k-mask operand.
1856  if (CommutableOpIdx1 == KMaskOp)
1857  continue;
1858 
1859  // The commuted operands must have different registers.
1860  // Otherwise, the commute transformation does not change anything and
1861  // is useless then.
1862  if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
1863  break;
1864  }
1865 
1866  // No appropriate commutable operands were found.
1867  if (CommutableOpIdx1 < FirstCommutableVecOp)
1868  return false;
1869 
1870  // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
1871  // to return those values.
1872  if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
1873  CommutableOpIdx1, CommutableOpIdx2))
1874  return false;
1875  }
1876 
1877  return true;
1878 }
1879 
1881  unsigned &SrcOpIdx2) const {
1882  const MCInstrDesc &Desc = MI.getDesc();
1883  if (!Desc.isCommutable())
1884  return false;
1885 
1886  switch (MI.getOpcode()) {
1887  case X86::CMPSDrr:
1888  case X86::CMPSSrr:
1889  case X86::CMPPDrri:
1890  case X86::CMPPSrri:
1891  case X86::VCMPSDrr:
1892  case X86::VCMPSSrr:
1893  case X86::VCMPPDrri:
1894  case X86::VCMPPSrri:
1895  case X86::VCMPPDYrri:
1896  case X86::VCMPPSYrri:
1897  case X86::VCMPSDZrr:
1898  case X86::VCMPSSZrr:
1899  case X86::VCMPPDZrri:
1900  case X86::VCMPPSZrri:
1901  case X86::VCMPPDZ128rri:
1902  case X86::VCMPPSZ128rri:
1903  case X86::VCMPPDZ256rri:
1904  case X86::VCMPPSZ256rri: {
1905  // Float comparison can be safely commuted for
1906  // Ordered/Unordered/Equal/NotEqual tests
1907  unsigned Imm = MI.getOperand(3).getImm() & 0x7;
1908  switch (Imm) {
1909  case 0x00: // EQUAL
1910  case 0x03: // UNORDERED
1911  case 0x04: // NOT EQUAL
1912  case 0x07: // ORDERED
1913  // The indices of the commutable operands are 1 and 2.
1914  // Assign them to the returned operand indices here.
1915  return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
1916  }
1917  return false;
1918  }
1919  case X86::MOVSDrr:
1920  case X86::MOVSSrr:
1921  case X86::VMOVSDrr:
1922  case X86::VMOVSSrr:
1923  if (Subtarget.hasSSE41())
1924  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1925  return false;
1926  case X86::MOVHLPSrr:
1927  case X86::UNPCKHPDrr:
1928  case X86::VMOVHLPSrr:
1929  case X86::VUNPCKHPDrr:
1930  case X86::VMOVHLPSZrr:
1931  case X86::VUNPCKHPDZ128rr:
1932  if (Subtarget.hasSSE2())
1933  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1934  return false;
1935  case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi:
1936  case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi:
1937  case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi:
1938  case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi:
1939  case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi:
1940  case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi:
1941  case X86::VPTERNLOGDZrrik:
1942  case X86::VPTERNLOGDZ128rrik:
1943  case X86::VPTERNLOGDZ256rrik:
1944  case X86::VPTERNLOGQZrrik:
1945  case X86::VPTERNLOGQZ128rrik:
1946  case X86::VPTERNLOGQZ256rrik:
1947  case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz:
1948  case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
1949  case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
1950  case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz:
1951  case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
1952  case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
1953  case X86::VPTERNLOGDZ128rmbi:
1954  case X86::VPTERNLOGDZ256rmbi:
1955  case X86::VPTERNLOGDZrmbi:
1956  case X86::VPTERNLOGQZ128rmbi:
1957  case X86::VPTERNLOGQZ256rmbi:
1958  case X86::VPTERNLOGQZrmbi:
1959  case X86::VPTERNLOGDZ128rmbikz:
1960  case X86::VPTERNLOGDZ256rmbikz:
1961  case X86::VPTERNLOGDZrmbikz:
1962  case X86::VPTERNLOGQZ128rmbikz:
1963  case X86::VPTERNLOGQZ256rmbikz:
1964  case X86::VPTERNLOGQZrmbikz:
1965  return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1966  case X86::VPMADD52HUQZ128r:
1967  case X86::VPMADD52HUQZ128rk:
1968  case X86::VPMADD52HUQZ128rkz:
1969  case X86::VPMADD52HUQZ256r:
1970  case X86::VPMADD52HUQZ256rk:
1971  case X86::VPMADD52HUQZ256rkz:
1972  case X86::VPMADD52HUQZr:
1973  case X86::VPMADD52HUQZrk:
1974  case X86::VPMADD52HUQZrkz:
1975  case X86::VPMADD52LUQZ128r:
1976  case X86::VPMADD52LUQZ128rk:
1977  case X86::VPMADD52LUQZ128rkz:
1978  case X86::VPMADD52LUQZ256r:
1979  case X86::VPMADD52LUQZ256rk:
1980  case X86::VPMADD52LUQZ256rkz:
1981  case X86::VPMADD52LUQZr:
1982  case X86::VPMADD52LUQZrk:
1983  case X86::VPMADD52LUQZrkz: {
1984  unsigned CommutableOpIdx1 = 2;
1985  unsigned CommutableOpIdx2 = 3;
1986  if (X86II::isKMasked(Desc.TSFlags)) {
1987  // Skip the mask register.
1988  ++CommutableOpIdx1;
1989  ++CommutableOpIdx2;
1990  }
1991  if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
1992  CommutableOpIdx1, CommutableOpIdx2))
1993  return false;
1994  if (!MI.getOperand(SrcOpIdx1).isReg() ||
1995  !MI.getOperand(SrcOpIdx2).isReg())
1996  // No idea.
1997  return false;
1998  return true;
1999  }
2000 
2001  default:
2002  const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2003  MI.getDesc().TSFlags);
2004  if (FMA3Group)
2005  return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
2006  FMA3Group->isIntrinsic());
2007 
2008  // Handled masked instructions since we need to skip over the mask input
2009  // and the preserved input.
2010  if (X86II::isKMasked(Desc.TSFlags)) {
2011  // First assume that the first input is the mask operand and skip past it.
2012  unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
2013  unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
2014  // Check if the first input is tied. If there isn't one then we only
2015  // need to skip the mask operand which we did above.
2016  if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
2017  MCOI::TIED_TO) != -1)) {
2018  // If this is zero masking instruction with a tied operand, we need to
2019  // move the first index back to the first input since this must
2020  // be a 3 input instruction and we want the first two non-mask inputs.
2021  // Otherwise this is a 2 input instruction with a preserved input and
2022  // mask, so we need to move the indices to skip one more input.
2023  if (X86II::isKMergeMasked(Desc.TSFlags)) {
2024  ++CommutableOpIdx1;
2025  ++CommutableOpIdx2;
2026  } else {
2027  --CommutableOpIdx1;
2028  }
2029  }
2030 
2031  if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2032  CommutableOpIdx1, CommutableOpIdx2))
2033  return false;
2034 
2035  if (!MI.getOperand(SrcOpIdx1).isReg() ||
2036  !MI.getOperand(SrcOpIdx2).isReg())
2037  // No idea.
2038  return false;
2039  return true;
2040  }
2041 
2042  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2043  }
2044  return false;
2045 }
2046 
2048  switch (BrOpc) {
2049  default: return X86::COND_INVALID;
2050  case X86::JE_1: return X86::COND_E;
2051  case X86::JNE_1: return X86::COND_NE;
2052  case X86::JL_1: return X86::COND_L;
2053  case X86::JLE_1: return X86::COND_LE;
2054  case X86::JG_1: return X86::COND_G;
2055  case X86::JGE_1: return X86::COND_GE;
2056  case X86::JB_1: return X86::COND_B;
2057  case X86::JBE_1: return X86::COND_BE;
2058  case X86::JA_1: return X86::COND_A;
2059  case X86::JAE_1: return X86::COND_AE;
2060  case X86::JS_1: return X86::COND_S;
2061  case X86::JNS_1: return X86::COND_NS;
2062  case X86::JP_1: return X86::COND_P;
2063  case X86::JNP_1: return X86::COND_NP;
2064  case X86::JO_1: return X86::COND_O;
2065  case X86::JNO_1: return X86::COND_NO;
2066  }
2067 }
2068 
2069 /// Return condition code of a SET opcode.
2071  switch (Opc) {
2072  default: return X86::COND_INVALID;
2073  case X86::SETAr: case X86::SETAm: return X86::COND_A;
2074  case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2075  case X86::SETBr: case X86::SETBm: return X86::COND_B;
2076  case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2077  case X86::SETEr: case X86::SETEm: return X86::COND_E;
2078  case X86::SETGr: case X86::SETGm: return X86::COND_G;
2079  case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2080  case X86::SETLr: case X86::SETLm: return X86::COND_L;
2081  case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2082  case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2083  case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2084  case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2085  case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2086  case X86::SETOr: case X86::SETOm: return X86::COND_O;
2087  case X86::SETPr: case X86::SETPm: return X86::COND_P;
2088  case X86::SETSr: case X86::SETSm: return X86::COND_S;
2089  }
2090 }
2091 
2092 /// Return condition code of a CMov opcode.
2094  switch (Opc) {
2095  default: return X86::COND_INVALID;
2096  case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
2097  case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
2098  return X86::COND_A;
2099  case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2100  case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2101  return X86::COND_AE;
2102  case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
2103  case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
2104  return X86::COND_B;
2105  case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2106  case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2107  return X86::COND_BE;
2108  case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
2109  case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
2110  return X86::COND_E;
2111  case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
2112  case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
2113  return X86::COND_G;
2114  case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2115  case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2116  return X86::COND_GE;
2117  case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
2118  case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
2119  return X86::COND_L;
2120  case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2121  case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2122  return X86::COND_LE;
2123  case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2124  case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2125  return X86::COND_NE;
2126  case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2127  case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2128  return X86::COND_NO;
2129  case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
2130  case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
2131  return X86::COND_NP;
2132  case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
2133  case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
2134  return X86::COND_NS;
2135  case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
2136  case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
2137  return X86::COND_O;
2138  case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
2139  case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
2140  return X86::COND_P;
2141  case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
2142  case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
2143  return X86::COND_S;
2144  }
2145 }
2146 
2148  switch (CC) {
2149  default: llvm_unreachable("Illegal condition code!");
2150  case X86::COND_E: return X86::JE_1;
2151  case X86::COND_NE: return X86::JNE_1;
2152  case X86::COND_L: return X86::JL_1;
2153  case X86::COND_LE: return X86::JLE_1;
2154  case X86::COND_G: return X86::JG_1;
2155  case X86::COND_GE: return X86::JGE_1;
2156  case X86::COND_B: return X86::JB_1;
2157  case X86::COND_BE: return X86::JBE_1;
2158  case X86::COND_A: return X86::JA_1;
2159  case X86::COND_AE: return X86::JAE_1;
2160  case X86::COND_S: return X86::JS_1;
2161  case X86::COND_NS: return X86::JNS_1;
2162  case X86::COND_P: return X86::JP_1;
2163  case X86::COND_NP: return X86::JNP_1;
2164  case X86::COND_O: return X86::JO_1;
2165  case X86::COND_NO: return X86::JNO_1;
2166  }
2167 }
2168 
2169 /// Return the inverse of the specified condition,
2170 /// e.g. turning COND_E to COND_NE.
2172  switch (CC) {
2173  default: llvm_unreachable("Illegal condition code!");
2174  case X86::COND_E: return X86::COND_NE;
2175  case X86::COND_NE: return X86::COND_E;
2176  case X86::COND_L: return X86::COND_GE;
2177  case X86::COND_LE: return X86::COND_G;
2178  case X86::COND_G: return X86::COND_LE;
2179  case X86::COND_GE: return X86::COND_L;
2180  case X86::COND_B: return X86::COND_AE;
2181  case X86::COND_BE: return X86::COND_A;
2182  case X86::COND_A: return X86::COND_BE;
2183  case X86::COND_AE: return X86::COND_B;
2184  case X86::COND_S: return X86::COND_NS;
2185  case X86::COND_NS: return X86::COND_S;
2186  case X86::COND_P: return X86::COND_NP;
2187  case X86::COND_NP: return X86::COND_P;
2188  case X86::COND_O: return X86::COND_NO;
2189  case X86::COND_NO: return X86::COND_O;
2192  }
2193 }
2194 
2195 /// Assuming the flags are set by MI(a,b), return the condition code if we
2196 /// modify the instructions such that flags are set by MI(b,a).
2198  switch (CC) {
2199  default: return X86::COND_INVALID;
2200  case X86::COND_E: return X86::COND_E;
2201  case X86::COND_NE: return X86::COND_NE;
2202  case X86::COND_L: return X86::COND_G;
2203  case X86::COND_LE: return X86::COND_GE;
2204  case X86::COND_G: return X86::COND_L;
2205  case X86::COND_GE: return X86::COND_LE;
2206  case X86::COND_B: return X86::COND_A;
2207  case X86::COND_BE: return X86::COND_AE;
2208  case X86::COND_A: return X86::COND_B;
2209  case X86::COND_AE: return X86::COND_BE;
2210  }
2211 }
2212 
2213 std::pair<X86::CondCode, bool>
2216  bool NeedSwap = false;
2217  switch (Predicate) {
2218  default: break;
2219  // Floating-point Predicates
2220  case CmpInst::FCMP_UEQ: CC = X86::COND_E; break;
2221  case CmpInst::FCMP_OLT: NeedSwap = true; LLVM_FALLTHROUGH;
2222  case CmpInst::FCMP_OGT: CC = X86::COND_A; break;
2223  case CmpInst::FCMP_OLE: NeedSwap = true; LLVM_FALLTHROUGH;
2224  case CmpInst::FCMP_OGE: CC = X86::COND_AE; break;
2225  case CmpInst::FCMP_UGT: NeedSwap = true; LLVM_FALLTHROUGH;
2226  case CmpInst::FCMP_ULT: CC = X86::COND_B; break;
2227  case CmpInst::FCMP_UGE: NeedSwap = true; LLVM_FALLTHROUGH;
2228  case CmpInst::FCMP_ULE: CC = X86::COND_BE; break;
2229  case CmpInst::FCMP_ONE: CC = X86::COND_NE; break;
2230  case CmpInst::FCMP_UNO: CC = X86::COND_P; break;
2231  case CmpInst::FCMP_ORD: CC = X86::COND_NP; break;
2233  case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
2234 
2235  // Integer Predicates
2236  case CmpInst::ICMP_EQ: CC = X86::COND_E; break;
2237  case CmpInst::ICMP_NE: CC = X86::COND_NE; break;
2238  case CmpInst::ICMP_UGT: CC = X86::COND_A; break;
2239  case CmpInst::ICMP_UGE: CC = X86::COND_AE; break;
2240  case CmpInst::ICMP_ULT: CC = X86::COND_B; break;
2241  case CmpInst::ICMP_ULE: CC = X86::COND_BE; break;
2242  case CmpInst::ICMP_SGT: CC = X86::COND_G; break;
2243  case CmpInst::ICMP_SGE: CC = X86::COND_GE; break;
2244  case CmpInst::ICMP_SLT: CC = X86::COND_L; break;
2245  case CmpInst::ICMP_SLE: CC = X86::COND_LE; break;
2246  }
2247 
2248  return std::make_pair(CC, NeedSwap);
2249 }
2250 
2251 /// Return a set opcode for the given condition and
2252 /// whether it has memory operand.
2253 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
2254  static const uint16_t Opc[16][2] = {
2255  { X86::SETAr, X86::SETAm },
2256  { X86::SETAEr, X86::SETAEm },
2257  { X86::SETBr, X86::SETBm },
2258  { X86::SETBEr, X86::SETBEm },
2259  { X86::SETEr, X86::SETEm },
2260  { X86::SETGr, X86::SETGm },
2261  { X86::SETGEr, X86::SETGEm },
2262  { X86::SETLr, X86::SETLm },
2263  { X86::SETLEr, X86::SETLEm },
2264  { X86::SETNEr, X86::SETNEm },
2265  { X86::SETNOr, X86::SETNOm },
2266  { X86::SETNPr, X86::SETNPm },
2267  { X86::SETNSr, X86::SETNSm },
2268  { X86::SETOr, X86::SETOm },
2269  { X86::SETPr, X86::SETPm },
2270  { X86::SETSr, X86::SETSm }
2271  };
2272 
2273  assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
2274  return Opc[CC][HasMemoryOperand ? 1 : 0];
2275 }
2276 
2277 /// Return a cmov opcode for the given condition,
2278 /// register size in bytes, and operand type.
2279 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
2280  bool HasMemoryOperand) {
2281  static const uint16_t Opc[32][3] = {
2282  { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
2283  { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
2284  { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
2285  { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
2286  { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
2287  { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
2288  { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
2289  { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
2290  { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
2291  { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
2292  { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
2293  { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
2294  { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
2295  { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
2296  { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
2297  { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
2298  { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
2299  { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
2300  { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
2301  { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
2302  { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
2303  { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
2304  { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
2305  { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
2306  { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
2307  { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
2308  { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
2309  { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
2310  { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
2311  { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
2312  { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
2313  { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
2314  };
2315 
2316  assert(CC < 16 && "Can only handle standard cond codes");
2317  unsigned Idx = HasMemoryOperand ? 16+CC : CC;
2318  switch(RegBytes) {
2319  default: llvm_unreachable("Illegal register size!");
2320  case 2: return Opc[Idx][0];
2321  case 4: return Opc[Idx][1];
2322  case 8: return Opc[Idx][2];
2323  }
2324 }
2325 
2326 /// Get the VPCMP immediate for the given condition.
2328  switch (CC) {
2329  default: llvm_unreachable("Unexpected SETCC condition");
2330  case ISD::SETNE: return 4;
2331  case ISD::SETEQ: return 0;
2332  case ISD::SETULT:
2333  case ISD::SETLT: return 1;
2334  case ISD::SETUGT:
2335  case ISD::SETGT: return 6;
2336  case ISD::SETUGE:
2337  case ISD::SETGE: return 5;
2338  case ISD::SETULE:
2339  case ISD::SETLE: return 2;
2340  }
2341 }
2342 
2343 /// Get the VPCMP immediate if the opcodes are swapped.
2344 unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
2345  switch (Imm) {
2346  default: llvm_unreachable("Unreachable!");
2347  case 0x01: Imm = 0x06; break; // LT -> NLE
2348  case 0x02: Imm = 0x05; break; // LE -> NLT
2349  case 0x05: Imm = 0x02; break; // NLT -> LE
2350  case 0x06: Imm = 0x01; break; // NLE -> LT
2351  case 0x00: // EQ
2352  case 0x03: // FALSE
2353  case 0x04: // NE
2354  case 0x07: // TRUE
2355  break;
2356  }
2357 
2358  return Imm;
2359 }
2360 
2361 /// Get the VPCOM immediate if the opcodes are swapped.
2362 unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
2363  switch (Imm) {
2364  default: llvm_unreachable("Unreachable!");
2365  case 0x00: Imm = 0x02; break; // LT -> GT
2366  case 0x01: Imm = 0x03; break; // LE -> GE
2367  case 0x02: Imm = 0x00; break; // GT -> LT
2368  case 0x03: Imm = 0x01; break; // GE -> LE
2369  case 0x04: // EQ
2370  case 0x05: // NE
2371  case 0x06: // FALSE
2372  case 0x07: // TRUE
2373  break;
2374  }
2375 
2376  return Imm;
2377 }
2378 
2380  if (!MI.isTerminator()) return false;
2381 
2382  // Conditional branch is a special case.
2383  if (MI.isBranch() && !MI.isBarrier())
2384  return true;
2385  if (!MI.isPredicable())
2386  return true;
2387  return !isPredicated(MI);
2388 }
2389 
2391  switch (MI.getOpcode()) {
2392  case X86::TCRETURNdi:
2393  case X86::TCRETURNri:
2394  case X86::TCRETURNmi:
2395  case X86::TCRETURNdi64:
2396  case X86::TCRETURNri64:
2397  case X86::TCRETURNmi64:
2398  return true;
2399  default:
2400  return false;
2401  }
2402 }
2403 
2405  SmallVectorImpl<MachineOperand> &BranchCond,
2406  const MachineInstr &TailCall) const {
2407  if (TailCall.getOpcode() != X86::TCRETURNdi &&
2408  TailCall.getOpcode() != X86::TCRETURNdi64) {
2409  // Only direct calls can be done with a conditional branch.
2410  return false;
2411  }
2412 
2413  const MachineFunction *MF = TailCall.getParent()->getParent();
2414  if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
2415  // Conditional tail calls confuse the Win64 unwinder.
2416  return false;
2417  }
2418 
2419  assert(BranchCond.size() == 1);
2420  if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
2421  // Can't make a conditional tail call with this condition.
2422  return false;
2423  }
2424 
2426  if (X86FI->getTCReturnAddrDelta() != 0 ||
2427  TailCall.getOperand(1).getImm() != 0) {
2428  // A conditional tail call cannot do any stack adjustment.
2429  return false;
2430  }
2431 
2432  return true;
2433 }
2434 
2437  const MachineInstr &TailCall) const {
2438  assert(canMakeTailCallConditional(BranchCond, TailCall));
2439 
2441  while (I != MBB.begin()) {
2442  --I;
2443  if (I->isDebugInstr())
2444  continue;
2445  if (!I->isBranch())
2446  assert(0 && "Can't find the branch to replace!");
2447 
2448  X86::CondCode CC = X86::getCondFromBranchOpc(I->getOpcode());
2449  assert(BranchCond.size() == 1);
2450  if (CC != BranchCond[0].getImm())
2451  continue;
2452 
2453  break;
2454  }
2455 
2456  unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
2457  : X86::TCRETURNdi64cc;
2458 
2459  auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
2460  MIB->addOperand(TailCall.getOperand(0)); // Destination.
2461  MIB.addImm(0); // Stack offset (not used).
2462  MIB->addOperand(BranchCond[0]); // Condition.
2463  MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
2464 
2465  // Add implicit uses and defs of all live regs potentially clobbered by the
2466  // call. This way they still appear live across the call.
2467  LivePhysRegs LiveRegs(getRegisterInfo());
2468  LiveRegs.addLiveOuts(MBB);
2470  LiveRegs.stepForward(*MIB, Clobbers);
2471  for (const auto &C : Clobbers) {
2472  MIB.addReg(C.first, RegState::Implicit);
2473  MIB.addReg(C.first, RegState::Implicit | RegState::Define);
2474  }
2475 
2476  I->eraseFromParent();
2477 }
2478 
2479 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
2480 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
2481 // fallthrough MBB cannot be identified.
2483  MachineBasicBlock *TBB) {
2484  // Look for non-EHPad successors other than TBB. If we find exactly one, it
2485  // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
2486  // and fallthrough MBB. If we find more than one, we cannot identify the
2487  // fallthrough MBB and should return nullptr.
2488  MachineBasicBlock *FallthroughBB = nullptr;
2489  for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
2490  if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
2491  continue;
2492  // Return a nullptr if we found more than one fallthrough successor.
2493  if (FallthroughBB && FallthroughBB != TBB)
2494  return nullptr;
2495  FallthroughBB = *SI;
2496  }
2497  return FallthroughBB;
2498 }
2499 
2500 bool X86InstrInfo::AnalyzeBranchImpl(
2503  SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
2504 
2505  // Start from the bottom of the block and work up, examining the
2506  // terminator instructions.
2508  MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2509  while (I != MBB.begin()) {
2510  --I;
2511  if (I->isDebugInstr())
2512  continue;
2513 
2514  // Working from the bottom, when we see a non-terminator instruction, we're
2515  // done.
2516  if (!isUnpredicatedTerminator(*I))
2517  break;
2518 
2519  // A terminator that isn't a branch can't easily be handled by this
2520  // analysis.
2521  if (!I->isBranch())
2522  return true;
2523 
2524  // Handle unconditional branches.
2525  if (I->getOpcode() == X86::JMP_1) {
2526  UnCondBrIter = I;
2527 
2528  if (!AllowModify) {
2529  TBB = I->getOperand(0).getMBB();
2530  continue;
2531  }
2532 
2533  // If the block has any instructions after a JMP, delete them.
2534  while (std::next(I) != MBB.end())
2535  std::next(I)->eraseFromParent();
2536 
2537  Cond.clear();
2538  FBB = nullptr;
2539 
2540  // Delete the JMP if it's equivalent to a fall-through.
2541  if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2542  TBB = nullptr;
2543  I->eraseFromParent();
2544  I = MBB.end();
2545  UnCondBrIter = MBB.end();
2546  continue;
2547  }
2548 
2549  // TBB is used to indicate the unconditional destination.
2550  TBB = I->getOperand(0).getMBB();
2551  continue;
2552  }
2553 
2554  // Handle conditional branches.
2555  X86::CondCode BranchCode = X86::getCondFromBranchOpc(I->getOpcode());
2556  if (BranchCode == X86::COND_INVALID)
2557  return true; // Can't handle indirect branch.
2558 
2559  // In practice we should never have an undef eflags operand, if we do
2560  // abort here as we are not prepared to preserve the flag.
2561  if (I->getOperand(1).isUndef())
2562  return true;
2563 
2564  // Working from the bottom, handle the first conditional branch.
2565  if (Cond.empty()) {
2566  MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2567  if (AllowModify && UnCondBrIter != MBB.end() &&
2568  MBB.isLayoutSuccessor(TargetBB)) {
2569  // If we can modify the code and it ends in something like:
2570  //
2571  // jCC L1
2572  // jmp L2
2573  // L1:
2574  // ...
2575  // L2:
2576  //
2577  // Then we can change this to:
2578  //
2579  // jnCC L2
2580  // L1:
2581  // ...
2582  // L2:
2583  //
2584  // Which is a bit more efficient.
2585  // We conditionally jump to the fall-through block.
2586  BranchCode = GetOppositeBranchCondition(BranchCode);
2587  unsigned JNCC = GetCondBranchFromCond(BranchCode);
2588  MachineBasicBlock::iterator OldInst = I;
2589 
2590  BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2591  .addMBB(UnCondBrIter->getOperand(0).getMBB());
2592  BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
2593  .addMBB(TargetBB);
2594 
2595  OldInst->eraseFromParent();
2596  UnCondBrIter->eraseFromParent();
2597 
2598  // Restart the analysis.
2599  UnCondBrIter = MBB.end();
2600  I = MBB.end();
2601  continue;
2602  }
2603 
2604  FBB = TBB;
2605  TBB = I->getOperand(0).getMBB();
2606  Cond.push_back(MachineOperand::CreateImm(BranchCode));
2607  CondBranches.push_back(&*I);
2608  continue;
2609  }
2610 
2611  // Handle subsequent conditional branches. Only handle the case where all
2612  // conditional branches branch to the same destination and their condition
2613  // opcodes fit one of the special multi-branch idioms.
2614  assert(Cond.size() == 1);
2615  assert(TBB);
2616 
2617  // If the conditions are the same, we can leave them alone.
2618  X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2619  auto NewTBB = I->getOperand(0).getMBB();
2620  if (OldBranchCode == BranchCode && TBB == NewTBB)
2621  continue;
2622 
2623  // If they differ, see if they fit one of the known patterns. Theoretically,
2624  // we could handle more patterns here, but we shouldn't expect to see them
2625  // if instruction selection has done a reasonable job.
2626  if (TBB == NewTBB &&
2627  ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
2628  (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
2629  BranchCode = X86::COND_NE_OR_P;
2630  } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
2631  (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
2632  if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
2633  return true;
2634 
2635  // X86::COND_E_AND_NP usually has two different branch destinations.
2636  //
2637  // JP B1
2638  // JE B2
2639  // JMP B1
2640  // B1:
2641  // B2:
2642  //
2643  // Here this condition branches to B2 only if NP && E. It has another
2644  // equivalent form:
2645  //
2646  // JNE B1
2647  // JNP B2
2648  // JMP B1
2649  // B1:
2650  // B2:
2651  //
2652  // Similarly it branches to B2 only if E && NP. That is why this condition
2653  // is named with COND_E_AND_NP.
2654  BranchCode = X86::COND_E_AND_NP;
2655  } else
2656  return true;
2657 
2658  // Update the MachineOperand.
2659  Cond[0].setImm(BranchCode);
2660  CondBranches.push_back(&*I);
2661  }
2662 
2663  return false;
2664 }
2665 
2667  MachineBasicBlock *&TBB,
2668  MachineBasicBlock *&FBB,
2670  bool AllowModify) const {
2671  SmallVector<MachineInstr *, 4> CondBranches;
2672  return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
2673 }
2674 
2676  MachineBranchPredicate &MBP,
2677  bool AllowModify) const {
2678  using namespace std::placeholders;
2679 
2681  SmallVector<MachineInstr *, 4> CondBranches;
2682  if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
2683  AllowModify))
2684  return true;
2685 
2686  if (Cond.size() != 1)
2687  return true;
2688 
2689  assert(MBP.TrueDest && "expected!");
2690 
2691  if (!MBP.FalseDest)
2692  MBP.FalseDest = MBB.getNextNode();
2693 
2695 
2696  MachineInstr *ConditionDef = nullptr;
2697  bool SingleUseCondition = true;
2698 
2699  for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
2700  if (I->modifiesRegister(X86::EFLAGS, TRI)) {
2701  ConditionDef = &*I;
2702  break;
2703  }
2704 
2705  if (I->readsRegister(X86::EFLAGS, TRI))
2706  SingleUseCondition = false;
2707  }
2708 
2709  if (!ConditionDef)
2710  return true;
2711 
2712  if (SingleUseCondition) {
2713  for (auto *Succ : MBB.successors())
2714  if (Succ->isLiveIn(X86::EFLAGS))
2715  SingleUseCondition = false;
2716  }
2717 
2718  MBP.ConditionDef = ConditionDef;
2719  MBP.SingleUseCondition = SingleUseCondition;
2720 
2721  // Currently we only recognize the simple pattern:
2722  //
2723  // test %reg, %reg
2724  // je %label
2725  //
2726  const unsigned TestOpcode =
2727  Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
2728 
2729  if (ConditionDef->getOpcode() == TestOpcode &&
2730  ConditionDef->getNumOperands() == 3 &&
2731  ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
2732  (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
2733  MBP.LHS = ConditionDef->getOperand(0);
2734  MBP.RHS = MachineOperand::CreateImm(0);
2735  MBP.Predicate = Cond[0].getImm() == X86::COND_NE
2738  return false;
2739  }
2740 
2741  return true;
2742 }
2743 
2745  int *BytesRemoved) const {
2746  assert(!BytesRemoved && "code size not handled");
2747 
2749  unsigned Count = 0;
2750 
2751  while (I != MBB.begin()) {
2752  --I;
2753  if (I->isDebugInstr())
2754  continue;
2755  if (I->getOpcode() != X86::JMP_1 &&
2756  X86::getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2757  break;
2758  // Remove the branch.
2759  I->eraseFromParent();
2760  I = MBB.end();
2761  ++Count;
2762  }
2763 
2764  return Count;
2765 }
2766 
2768  MachineBasicBlock *TBB,
2769  MachineBasicBlock *FBB,
2771  const DebugLoc &DL,
2772  int *BytesAdded) const {
2773  // Shouldn't be a fall through.
2774  assert(TBB && "insertBranch must not be told to insert a fallthrough");
2775  assert((Cond.size() == 1 || Cond.size() == 0) &&
2776  "X86 branch conditions have one component!");
2777  assert(!BytesAdded && "code size not handled");
2778 
2779  if (Cond.empty()) {
2780  // Unconditional branch?
2781  assert(!FBB && "Unconditional branch with multiple successors!");
2782  BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
2783  return 1;
2784  }
2785 
2786  // If FBB is null, it is implied to be a fall-through block.
2787  bool FallThru = FBB == nullptr;
2788 
2789  // Conditional branch.
2790  unsigned Count = 0;
2791  X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2792  switch (CC) {
2793  case X86::COND_NE_OR_P:
2794  // Synthesize NE_OR_P with two branches.
2795  BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
2796  ++Count;
2797  BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
2798  ++Count;
2799  break;
2800  case X86::COND_E_AND_NP:
2801  // Use the next block of MBB as FBB if it is null.
2802  if (FBB == nullptr) {
2803  FBB = getFallThroughMBB(&MBB, TBB);
2804  assert(FBB && "MBB cannot be the last block in function when the false "
2805  "body is a fall-through.");
2806  }
2807  // Synthesize COND_E_AND_NP with two branches.
2808  BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
2809  ++Count;
2810  BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
2811  ++Count;
2812  break;
2813  default: {
2814  unsigned Opc = GetCondBranchFromCond(CC);
2815  BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
2816  ++Count;
2817  }
2818  }
2819  if (!FallThru) {
2820  // Two-way Conditional branch. Insert the second branch.
2821  BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
2822  ++Count;
2823  }
2824  return Count;
2825 }
2826 
2827 bool X86InstrInfo::
2830  unsigned TrueReg, unsigned FalseReg,
2831  int &CondCycles, int &TrueCycles, int &FalseCycles) const {
2832  // Not all subtargets have cmov instructions.
2833  if (!Subtarget.hasCMov())
2834  return false;
2835  if (Cond.size() != 1)
2836  return false;
2837  // We cannot do the composite conditions, at least not in SSA form.
2838  if ((X86::CondCode)Cond[0].getImm() > X86::LAST_VALID_COND)
2839  return false;
2840 
2841  // Check register classes.
2842  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2843  const TargetRegisterClass *RC =
2844  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2845  if (!RC)
2846  return false;
2847 
2848  // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
2849  if (X86::GR16RegClass.hasSubClassEq(RC) ||
2850  X86::GR32RegClass.hasSubClassEq(RC) ||
2851  X86::GR64RegClass.hasSubClassEq(RC)) {
2852  // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
2853  // Bridge. Probably Ivy Bridge as well.
2854  CondCycles = 2;
2855  TrueCycles = 2;
2856  FalseCycles = 2;
2857  return true;
2858  }
2859 
2860  // Can't do vectors.
2861  return false;
2862 }
2863 
2866  const DebugLoc &DL, unsigned DstReg,
2867  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
2868  unsigned FalseReg) const {
2871  const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
2872  assert(Cond.size() == 1 && "Invalid Cond array");
2873  unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
2874  TRI.getRegSizeInBits(RC) / 8,
2875  false /*HasMemoryOperand*/);
2876  BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
2877 }
2878 
2879 /// Test if the given register is a physical h register.
2880 static bool isHReg(unsigned Reg) {
2881  return X86::GR8_ABCD_HRegClass.contains(Reg);
2882 }
2883 
2884 // Try and copy between VR128/VR64 and GR64 registers.
2885 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2886  const X86Subtarget &Subtarget) {
2887  bool HasAVX = Subtarget.hasAVX();
2888  bool HasAVX512 = Subtarget.hasAVX512();
2889 
2890  // SrcReg(MaskReg) -> DestReg(GR64)
2891  // SrcReg(MaskReg) -> DestReg(GR32)
2892 
2893  // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2894  if (X86::VK16RegClass.contains(SrcReg)) {
2895  if (X86::GR64RegClass.contains(DestReg)) {
2896  assert(Subtarget.hasBWI());
2897  return X86::KMOVQrk;
2898  }
2899  if (X86::GR32RegClass.contains(DestReg))
2900  return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
2901  }
2902 
2903  // SrcReg(GR64) -> DestReg(MaskReg)
2904  // SrcReg(GR32) -> DestReg(MaskReg)
2905 
2906  // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2907  if (X86::VK16RegClass.contains(DestReg)) {
2908  if (X86::GR64RegClass.contains(SrcReg)) {
2909  assert(Subtarget.hasBWI());
2910  return X86::KMOVQkr;
2911  }
2912  if (X86::GR32RegClass.contains(SrcReg))
2913  return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
2914  }
2915 
2916 
2917  // SrcReg(VR128) -> DestReg(GR64)
2918  // SrcReg(VR64) -> DestReg(GR64)
2919  // SrcReg(GR64) -> DestReg(VR128)
2920  // SrcReg(GR64) -> DestReg(VR64)
2921 
2922  if (X86::GR64RegClass.contains(DestReg)) {
2923  if (X86::VR128XRegClass.contains(SrcReg))
2924  // Copy from a VR128 register to a GR64 register.
2925  return HasAVX512 ? X86::VMOVPQIto64Zrr :
2926  HasAVX ? X86::VMOVPQIto64rr :
2927  X86::MOVPQIto64rr;
2928  if (X86::VR64RegClass.contains(SrcReg))
2929  // Copy from a VR64 register to a GR64 register.
2930  return X86::MMX_MOVD64from64rr;
2931  } else if (X86::GR64RegClass.contains(SrcReg)) {
2932  // Copy from a GR64 register to a VR128 register.
2933  if (X86::VR128XRegClass.contains(DestReg))
2934  return HasAVX512 ? X86::VMOV64toPQIZrr :
2935  HasAVX ? X86::VMOV64toPQIrr :
2936  X86::MOV64toPQIrr;
2937  // Copy from a GR64 register to a VR64 register.
2938  if (X86::VR64RegClass.contains(DestReg))
2939  return X86::MMX_MOVD64to64rr;
2940  }
2941 
2942  // SrcReg(FR32) -> DestReg(GR32)
2943  // SrcReg(GR32) -> DestReg(FR32)
2944 
2945  if (X86::GR32RegClass.contains(DestReg) &&
2946  X86::FR32XRegClass.contains(SrcReg))
2947  // Copy from a FR32 register to a GR32 register.
2948  return HasAVX512 ? X86::VMOVSS2DIZrr :
2949  HasAVX ? X86::VMOVSS2DIrr :
2950  X86::MOVSS2DIrr;
2951 
2952  if (X86::FR32XRegClass.contains(DestReg) &&
2953  X86::GR32RegClass.contains(SrcReg))
2954  // Copy from a GR32 register to a FR32 register.
2955  return HasAVX512 ? X86::VMOVDI2SSZrr :
2956  HasAVX ? X86::VMOVDI2SSrr :
2957  X86::MOVDI2SSrr;
2958  return 0;
2959 }
2960 
2963  const DebugLoc &DL, unsigned DestReg,
2964  unsigned SrcReg, bool KillSrc) const {
2965  // First deal with the normal symmetric copies.
2966  bool HasAVX = Subtarget.hasAVX();
2967  bool HasVLX = Subtarget.hasVLX();
2968  unsigned Opc = 0;
2969  if (X86::GR64RegClass.contains(DestReg, SrcReg))
2970  Opc = X86::MOV64rr;
2971  else if (X86::GR32RegClass.contains(DestReg, SrcReg))
2972  Opc = X86::MOV32rr;
2973  else if (X86::GR16RegClass.contains(DestReg, SrcReg))
2974  Opc = X86::MOV16rr;
2975  else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
2976  // Copying to or from a physical H register on x86-64 requires a NOREX
2977  // move. Otherwise use a normal move.
2978  if ((isHReg(DestReg) || isHReg(SrcReg)) &&
2979  Subtarget.is64Bit()) {
2980  Opc = X86::MOV8rr_NOREX;
2981  // Both operands must be encodable without an REX prefix.
2982  assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
2983  "8-bit H register can not be copied outside GR8_NOREX");
2984  } else
2985  Opc = X86::MOV8rr;
2986  }
2987  else if (X86::VR64RegClass.contains(DestReg, SrcReg))
2988  Opc = X86::MMX_MOVQ64rr;
2989  else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
2990  if (HasVLX)
2991  Opc = X86::VMOVAPSZ128rr;
2992  else if (X86::VR128RegClass.contains(DestReg, SrcReg))
2993  Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
2994  else {
2995  // If this an extended register and we don't have VLX we need to use a
2996  // 512-bit move.
2997  Opc = X86::VMOVAPSZrr;
2999  DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
3000  &X86::VR512RegClass);
3001  SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
3002  &X86::VR512RegClass);
3003  }
3004  } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
3005  if (HasVLX)
3006  Opc = X86::VMOVAPSZ256rr;
3007  else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3008  Opc = X86::VMOVAPSYrr;
3009  else {
3010  // If this an extended register and we don't have VLX we need to use a
3011  // 512-bit move.
3012  Opc = X86::VMOVAPSZrr;
3014  DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
3015  &X86::VR512RegClass);
3016  SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
3017  &X86::VR512RegClass);
3018  }
3019  } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
3020  Opc = X86::VMOVAPSZrr;
3021  // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3022  else if (X86::VK16RegClass.contains(DestReg, SrcReg))
3023  Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
3024  if (!Opc)
3025  Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3026 
3027  if (Opc) {
3028  BuildMI(MBB, MI, DL, get(Opc), DestReg)
3029  .addReg(SrcReg, getKillRegState(KillSrc));
3030  return;
3031  }
3032 
3033  if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
3034  // FIXME: We use a fatal error here because historically LLVM has tried
3035  // lower some of these physreg copies and we want to ensure we get
3036  // reasonable bug reports if someone encounters a case no other testing
3037  // found. This path should be removed after the LLVM 7 release.
3038  report_fatal_error("Unable to copy EFLAGS physical register!");
3039  }
3040 
3041  LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
3042  << RI.getName(DestReg) << '\n');
3043  report_fatal_error("Cannot emit physreg copy instruction");
3044 }
3045 
3047  const MachineOperand *&Src,
3048  const MachineOperand *&Dest) const {
3049  if (MI.isMoveReg()) {
3050  Dest = &MI.getOperand(0);
3051  Src = &MI.getOperand(1);
3052  return true;
3053  }
3054  return false;
3055 }
3056 
3057 static unsigned getLoadStoreRegOpcode(unsigned Reg,
3058  const TargetRegisterClass *RC,
3059  bool isStackAligned,
3060  const X86Subtarget &STI,
3061  bool load) {
3062  bool HasAVX = STI.hasAVX();
3063  bool HasAVX512 = STI.hasAVX512();
3064  bool HasVLX = STI.hasVLX();
3065 
3066  switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
3067  default:
3068  llvm_unreachable("Unknown spill size");
3069  case 1:
3070  assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3071  if (STI.is64Bit())
3072  // Copying to or from a physical H register on x86-64 requires a NOREX
3073  // move. Otherwise use a normal move.
3074  if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3075  return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3076  return load ? X86::MOV8rm : X86::MOV8mr;
3077  case 2:
3078  if (X86::VK16RegClass.hasSubClassEq(RC))
3079  return load ? X86::KMOVWkm : X86::KMOVWmk;
3080  assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3081  return load ? X86::MOV16rm : X86::MOV16mr;
3082  case 4:
3083  if (X86::GR32RegClass.hasSubClassEq(RC))
3084  return load ? X86::MOV32rm : X86::MOV32mr;
3085  if (X86::FR32XRegClass.hasSubClassEq(RC))
3086  return load ?
3087  (HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3088  (HasAVX512 ? X86::VMOVSSZmr : HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
3089  if (X86::RFP32RegClass.hasSubClassEq(RC))
3090  return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3091  if (X86::VK32RegClass.hasSubClassEq(RC)) {
3092  assert(STI.hasBWI() && "KMOVD requires BWI");
3093  return load ? X86::KMOVDkm : X86::KMOVDmk;
3094  }
3095  llvm_unreachable("Unknown 4-byte regclass");
3096  case 8:
3097  if (X86::GR64RegClass.hasSubClassEq(RC))
3098  return load ? X86::MOV64rm : X86::MOV64mr;
3099  if (X86::FR64XRegClass.hasSubClassEq(RC))
3100  return load ?
3101  (HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3102  (HasAVX512 ? X86::VMOVSDZmr : HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
3103  if (X86::VR64RegClass.hasSubClassEq(RC))
3104  return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3105  if (X86::RFP64RegClass.hasSubClassEq(RC))
3106  return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3107  if (X86::VK64RegClass.hasSubClassEq(RC)) {
3108  assert(STI.hasBWI() && "KMOVQ requires BWI");
3109  return load ? X86::KMOVQkm : X86::KMOVQmk;
3110  }
3111  llvm_unreachable("Unknown 8-byte regclass");
3112  case 10:
3113  assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3114  return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3115  case 16: {
3116  if (X86::VR128XRegClass.hasSubClassEq(RC)) {
3117  // If stack is realigned we can use aligned stores.
3118  if (isStackAligned)
3119  return load ?
3120  (HasVLX ? X86::VMOVAPSZ128rm :
3121  HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
3122  HasAVX ? X86::VMOVAPSrm :
3123  X86::MOVAPSrm):
3124  (HasVLX ? X86::VMOVAPSZ128mr :
3125  HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
3126  HasAVX ? X86::VMOVAPSmr :
3127  X86::MOVAPSmr);
3128  else
3129  return load ?
3130  (HasVLX ? X86::VMOVUPSZ128rm :
3131  HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
3132  HasAVX ? X86::VMOVUPSrm :
3133  X86::MOVUPSrm):
3134  (HasVLX ? X86::VMOVUPSZ128mr :
3135  HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
3136  HasAVX ? X86::VMOVUPSmr :
3137  X86::MOVUPSmr);
3138  }
3139  if (X86::BNDRRegClass.hasSubClassEq(RC)) {
3140  if (STI.is64Bit())
3141  return load ? X86::BNDMOV64rm : X86::BNDMOV64mr;
3142  else
3143  return load ? X86::BNDMOV32rm : X86::BNDMOV32mr;
3144  }
3145  llvm_unreachable("Unknown 16-byte regclass");
3146  }
3147  case 32:
3148  assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
3149  // If stack is realigned we can use aligned stores.
3150  if (isStackAligned)
3151  return load ?
3152  (HasVLX ? X86::VMOVAPSZ256rm :
3153  HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
3154  X86::VMOVAPSYrm) :
3155  (HasVLX ? X86::VMOVAPSZ256mr :
3156  HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
3157  X86::VMOVAPSYmr);
3158  else
3159  return load ?
3160  (HasVLX ? X86::VMOVUPSZ256rm :
3161  HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
3162  X86::VMOVUPSYrm) :
3163  (HasVLX ? X86::VMOVUPSZ256mr :
3164  HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
3165  X86::VMOVUPSYmr);
3166  case 64:
3167  assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3168  assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
3169  if (isStackAligned)
3170  return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3171  else
3172  return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3173  }
3174 }
3175 
3177  MachineInstr &MemOp, MachineOperand *&BaseOp, int64_t &Offset,
3178  const TargetRegisterInfo *TRI) const {
3179  const MCInstrDesc &Desc = MemOp.getDesc();
3180  int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3181  if (MemRefBegin < 0)
3182  return false;
3183 
3184  MemRefBegin += X86II::getOperandBias(Desc);
3185 
3186  BaseOp = &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
3187  if (!BaseOp->isReg()) // Can be an MO_FrameIndex
3188  return false;
3189 
3190  if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
3191  return false;
3192 
3193  if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3194  X86::NoRegister)
3195  return false;
3196 
3197  const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
3198 
3199  // Displacement can be symbolic
3200  if (!DispMO.isImm())
3201  return false;
3202 
3203  Offset = DispMO.getImm();
3204 
3205  assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
3206  "operands of type register.");
3207  return true;
3208 }
3209 
3210 static unsigned getStoreRegOpcode(unsigned SrcReg,
3211  const TargetRegisterClass *RC,
3212  bool isStackAligned,
3213  const X86Subtarget &STI) {
3214  return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
3215 }
3216 
3217 
3218 static unsigned getLoadRegOpcode(unsigned DestReg,
3219  const TargetRegisterClass *RC,
3220  bool isStackAligned,
3221  const X86Subtarget &STI) {
3222  return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
3223 }
3224 
3227  unsigned SrcReg, bool isKill, int FrameIdx,
3228  const TargetRegisterClass *RC,
3229  const TargetRegisterInfo *TRI) const {
3230  const MachineFunction &MF = *MBB.getParent();
3231  assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&
3232  "Stack slot too small for store");
3233  unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3234  bool isAligned =
3235  (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3236  RI.canRealignStack(MF);
3237  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3238  addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3239  .addReg(SrcReg, getKillRegState(isKill));
3240 }
3241 
3243  MachineFunction &MF, unsigned SrcReg, bool isKill,
3246  SmallVectorImpl<MachineInstr *> &NewMIs) const {
3248  unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
3249  bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
3250  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3251  DebugLoc DL;
3252  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
3253  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3254  MIB.add(Addr[i]);
3255  MIB.addReg(SrcReg, getKillRegState(isKill));
3256  MIB.setMemRefs(MMOs);
3257  NewMIs.push_back(MIB);
3258 }
3259 
3260 
3263  unsigned DestReg, int FrameIdx,
3264  const TargetRegisterClass *RC,
3265  const TargetRegisterInfo *TRI) const {
3266  const MachineFunction &MF = *MBB.getParent();
3267  unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3268  bool isAligned =
3269  (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3270  RI.canRealignStack(MF);
3271  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3272  addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg), FrameIdx);
3273 }
3274 
3276  MachineFunction &MF, unsigned DestReg,
3279  SmallVectorImpl<MachineInstr *> &NewMIs) const {
3281  unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
3282  bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
3283  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3284  DebugLoc DL;
3285  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
3286  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3287  MIB.add(Addr[i]);
3288  MIB.setMemRefs(MMOs);
3289  NewMIs.push_back(MIB);
3290 }
3291 
3292 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
3293  unsigned &SrcReg2, int &CmpMask,
3294  int &CmpValue) const {
3295  switch (MI.getOpcode()) {
3296  default: break;
3297  case X86::CMP64ri32:
3298  case X86::CMP64ri8:
3299  case X86::CMP32ri:
3300  case X86::CMP32ri8:
3301  case X86::CMP16ri:
3302  case X86::CMP16ri8:
3303  case X86::CMP8ri:
3304  SrcReg = MI.getOperand(0).getReg();
3305  SrcReg2 = 0;
3306  if (MI.getOperand(1).isImm()) {
3307  CmpMask = ~0;
3308  CmpValue = MI.getOperand(1).getImm();
3309  } else {
3310  CmpMask = CmpValue = 0;
3311  }
3312  return true;
3313  // A SUB can be used to perform comparison.
3314  case X86::SUB64rm:
3315  case X86::SUB32rm:
3316  case X86::SUB16rm:
3317  case X86::SUB8rm:
3318  SrcReg = MI.getOperand(1).getReg();
3319  SrcReg2 = 0;
3320  CmpMask = 0;
3321  CmpValue = 0;
3322  return true;
3323  case X86::SUB64rr:
3324  case X86::SUB32rr:
3325  case X86::SUB16rr:
3326  case X86::SUB8rr:
3327  SrcReg = MI.getOperand(1).getReg();
3328  SrcReg2 = MI.getOperand(2).getReg();
3329  CmpMask = 0;
3330  CmpValue = 0;
3331  return true;
3332  case X86::SUB64ri32:
3333  case X86::SUB64ri8:
3334  case X86::SUB32ri:
3335  case X86::SUB32ri8:
3336  case X86::SUB16ri:
3337  case X86::SUB16ri8:
3338  case X86::SUB8ri:
3339  SrcReg = MI.getOperand(1).getReg();
3340  SrcReg2 = 0;
3341  if (MI.getOperand(2).isImm()) {
3342  CmpMask = ~0;
3343  CmpValue = MI.getOperand(2).getImm();
3344  } else {
3345  CmpMask = CmpValue = 0;
3346  }
3347  return true;
3348  case X86::CMP64rr:
3349  case X86::CMP32rr:
3350  case X86::CMP16rr:
3351  case X86::CMP8rr:
3352  SrcReg = MI.getOperand(0).getReg();
3353  SrcReg2 = MI.getOperand(1).getReg();
3354  CmpMask = 0;
3355  CmpValue = 0;
3356  return true;
3357  case X86::TEST8rr:
3358  case X86::TEST16rr:
3359  case X86::TEST32rr:
3360  case X86::TEST64rr:
3361  SrcReg = MI.getOperand(0).getReg();
3362  if (MI.getOperand(1).getReg() != SrcReg)
3363  return false;
3364  // Compare against zero.
3365  SrcReg2 = 0;
3366  CmpMask = ~0;
3367  CmpValue = 0;
3368  return true;
3369  }
3370  return false;
3371 }
3372 
3373 /// Check whether the first instruction, whose only
3374 /// purpose is to update flags, can be made redundant.
3375 /// CMPrr can be made redundant by SUBrr if the operands are the same.
3376 /// This function can be extended later on.
3377 /// SrcReg, SrcRegs: register operands for FlagI.
3378 /// ImmValue: immediate for FlagI if it takes an immediate.
3379 inline static bool isRedundantFlagInstr(const MachineInstr &FlagI,
3380  unsigned SrcReg, unsigned SrcReg2,
3381  int ImmMask, int ImmValue,
3382  const MachineInstr &OI) {
3383  if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
3384  (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
3385  (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
3386  (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
3387  ((OI.getOperand(1).getReg() == SrcReg &&
3388  OI.getOperand(2).getReg() == SrcReg2) ||
3389  (OI.getOperand(1).getReg() == SrcReg2 &&
3390  OI.getOperand(2).getReg() == SrcReg)))
3391  return true;
3392 
3393  if (ImmMask != 0 &&
3394  ((FlagI.getOpcode() == X86::CMP64ri32 &&
3395  OI.getOpcode() == X86::SUB64ri32) ||
3396  (FlagI.getOpcode() == X86::CMP64ri8 &&
3397  OI.getOpcode() == X86::SUB64ri8) ||
3398  (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
3399  (FlagI.getOpcode() == X86::CMP32ri8 &&
3400  OI.getOpcode() == X86::SUB32ri8) ||
3401  (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
3402  (FlagI.getOpcode() == X86::CMP16ri8 &&
3403  OI.getOpcode() == X86::SUB16ri8) ||
3404  (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
3405  OI.getOperand(1).getReg() == SrcReg &&
3406  OI.getOperand(2).getImm() == ImmValue)
3407  return true;
3408  return false;
3409 }
3410 
3411 /// Check whether the definition can be converted
3412 /// to remove a comparison against zero.
3413 inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag) {
3414  NoSignFlag = false;
3415 
3416  switch (MI.getOpcode()) {
3417  default: return false;
3418 
3419  // The shift instructions only modify ZF if their shift count is non-zero.
3420  // N.B.: The processor truncates the shift count depending on the encoding.
3421  case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
3422  case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
3423  return getTruncatedShiftCount(MI, 2) != 0;
3424 
3425  // Some left shift instructions can be turned into LEA instructions but only
3426  // if their flags aren't used. Avoid transforming such instructions.
3427  case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
3428  unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3429  if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3430  return ShAmt != 0;
3431  }
3432 
3433  case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3434  case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3435  return getTruncatedShiftCount(MI, 3) != 0;
3436 
3437  case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3438  case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
3439  case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
3440  case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
3441  case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
3442  case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
3443  case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3444  case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
3445  case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
3446  case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
3447  case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
3448  case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
3449  case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3450  case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
3451  case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
3452  case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
3453  case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
3454  case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3455  case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
3456  case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
3457  case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
3458  case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
3459  case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
3460  case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
3461  case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
3462  case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
3463  case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
3464  case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
3465  case X86::ADC32ri8: case X86::ADC16ri: case X86::ADC16ri8:
3466  case X86::ADC8ri: case X86::ADC64rr: case X86::ADC32rr:
3467  case X86::ADC16rr: case X86::ADC8rr: case X86::ADC64rm:
3468  case X86::ADC32rm: case X86::ADC16rm: case X86::ADC8rm:
3469  case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
3470  case X86::SBB32ri8: case X86::SBB16ri: case X86::SBB16ri8:
3471  case X86::SBB8ri: case X86::SBB64rr: case X86::SBB32rr:
3472  case X86::SBB16rr: case X86::SBB8rr: case X86::SBB64rm:
3473  case X86::SBB32rm: case X86::SBB16rm: case X86::SBB8rm:
3474  case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
3475  case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
3476  case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
3477  case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
3478  case X86::ANDN32rr: case X86::ANDN32rm:
3479  case X86::ANDN64rr: case X86::ANDN64rm:
3480  case X86::BLSI32rr: case X86::BLSI32rm:
3481  case X86::BLSI64rr: case X86::BLSI64rm:
3482  case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3483  case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3484  case X86::BLSR32rr: case X86::BLSR32rm:
3485  case X86::BLSR64rr: case X86::BLSR64rm:
3486  case X86::BZHI32rr: case X86::BZHI32rm:
3487  case X86::BZHI64rr: case X86::BZHI64rm:
3488  case X86::LZCNT16rr: case X86::LZCNT16rm:
3489  case X86::LZCNT32rr: case X86::LZCNT32rm:
3490  case X86::LZCNT64rr: case X86::LZCNT64rm:
3491  case X86::POPCNT16rr:case X86::POPCNT16rm:
3492  case X86::POPCNT32rr:case X86::POPCNT32rm:
3493  case X86::POPCNT64rr:case X86::POPCNT64rm:
3494  case X86::TZCNT16rr: case X86::TZCNT16rm:
3495  case X86::TZCNT32rr: case X86::TZCNT32rm:
3496  case X86::TZCNT64rr: case X86::TZCNT64rm:
3497  case X86::BLCFILL32rr: case X86::BLCFILL32rm:
3498  case X86::BLCFILL64rr: case X86::BLCFILL64rm:
3499  case X86::BLCI32rr: case X86::BLCI32rm:
3500  case X86::BLCI64rr: case X86::BLCI64rm:
3501  case X86::BLCIC32rr: case X86::BLCIC32rm:
3502  case X86::BLCIC64rr: case X86::BLCIC64rm:
3503  case X86::BLCMSK32rr: case X86::BLCMSK32rm:
3504  case X86::BLCMSK64rr: case X86::BLCMSK64rm:
3505  case X86::BLCS32rr: case X86::BLCS32rm:
3506  case X86::BLCS64rr: case X86::BLCS64rm:
3507  case X86::BLSFILL32rr: case X86::BLSFILL32rm:
3508  case X86::BLSFILL64rr: case X86::BLSFILL64rm:
3509  case X86::BLSIC32rr: case X86::BLSIC32rm:
3510  case X86::BLSIC64rr: case X86::BLSIC64rm:
3511  case X86::T1MSKC32rr: case X86::T1MSKC32rm:
3512  case X86::T1MSKC64rr: case X86::T1MSKC64rm:
3513  case X86::TZMSK32rr: case X86::TZMSK32rm:
3514  case X86::TZMSK64rr: case X86::TZMSK64rm:
3515  return true;
3516  case X86::BEXTR32rr: case X86::BEXTR64rr:
3517  case X86::BEXTR32rm: case X86::BEXTR64rm:
3518  case X86::BEXTRI32ri: case X86::BEXTRI32mi:
3519  case X86::BEXTRI64ri: case X86::BEXTRI64mi:
3520  // BEXTR doesn't update the sign flag so we can't use it.
3521  NoSignFlag = true;
3522  return true;
3523  }
3524 }
3525 
3526 /// Check whether the use can be converted to remove a comparison against zero.
3528  switch (MI.getOpcode()) {
3529  default: return X86::COND_INVALID;
3530  case X86::LZCNT16rr: case X86::LZCNT16rm:
3531  case X86::LZCNT32rr: case X86::LZCNT32rm:
3532  case X86::LZCNT64rr: case X86::LZCNT64rm:
3533  return X86::COND_B;
3534  case X86::POPCNT16rr:case X86::POPCNT16rm:
3535  case X86::POPCNT32rr:case X86::POPCNT32rm:
3536  case X86::POPCNT64rr:case X86::POPCNT64rm:
3537  return X86::COND_E;
3538  case X86::TZCNT16rr: case X86::TZCNT16rm:
3539  case X86::TZCNT32rr: case X86::TZCNT32rm:
3540  case X86::TZCNT64rr: case X86::TZCNT64rm:
3541  return X86::COND_B;
3542  case X86::BSF16rr: case X86::BSF16rm:
3543  case X86::BSF32rr: case X86::BSF32rm:
3544  case X86::BSF64rr: case X86::BSF64rm:
3545  case X86::BSR16rr: case X86::BSR16rm:
3546  case X86::BSR32rr: case X86::BSR32rm:
3547  case X86::BSR64rr: case X86::BSR64rm:
3548  return X86::COND_E;
3549  }
3550 }
3551 
3552 /// Check if there exists an earlier instruction that
3553 /// operates on the same source operands and sets flags in the same way as
3554 /// Compare; remove Compare if possible.
3555 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
3556  unsigned SrcReg2, int CmpMask,
3557  int CmpValue,
3558  const MachineRegisterInfo *MRI) const {
3559  // Check whether we can replace SUB with CMP.
3560  unsigned NewOpcode = 0;
3561  switch (CmpInstr.getOpcode()) {
3562  default: break;
3563  case X86::SUB64ri32:
3564  case X86::SUB64ri8:
3565  case X86::SUB32ri:
3566  case X86::SUB32ri8:
3567  case X86::SUB16ri:
3568  case X86::SUB16ri8:
3569  case X86::SUB8ri:
3570  case X86::SUB64rm:
3571  case X86::SUB32rm:
3572  case X86::SUB16rm:
3573  case X86::SUB8rm:
3574  case X86::SUB64rr:
3575  case X86::SUB32rr:
3576  case X86::SUB16rr:
3577  case X86::SUB8rr: {
3578  if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
3579  return false;
3580  // There is no use of the destination register, we can replace SUB with CMP.
3581  switch (CmpInstr.getOpcode()) {
3582  default: llvm_unreachable("Unreachable!");
3583  case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
3584  case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
3585  case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
3586  case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
3587  case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
3588  case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
3589  case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
3590  case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
3591  case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3592  case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
3593  case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
3594  case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
3595  case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
3596  case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
3597  case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
3598  }
3599  CmpInstr.setDesc(get(NewOpcode));
3600  CmpInstr.RemoveOperand(0);
3601  // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3602  if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3603  NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3604  return false;
3605  }
3606  }
3607 
3608  // Get the unique definition of SrcReg.
3609  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3610  if (!MI) return false;
3611 
3612  // CmpInstr is the first instruction of the BB.
3613  MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3614 
3615  // If we are comparing against zero, check whether we can use MI to update
3616  // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3617  bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
3618  if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
3619  return false;
3620 
3621  // If we have a use of the source register between the def and our compare
3622  // instruction we can eliminate the compare iff the use sets EFLAGS in the
3623  // right way.
3624  bool ShouldUpdateCC = false;
3625  bool NoSignFlag = false;
3627  if (IsCmpZero && !isDefConvertible(*MI, NoSignFlag)) {
3628  // Scan forward from the use until we hit the use we're looking for or the
3629  // compare instruction.
3630  for (MachineBasicBlock::iterator J = MI;; ++J) {
3631  // Do we have a convertible instruction?
3632  NewCC = isUseDefConvertible(*J);
3633  if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
3634  J->getOperand(1).getReg() == SrcReg) {
3635  assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
3636  ShouldUpdateCC = true; // Update CC later on.
3637  // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
3638  // with the new def.
3639  Def = J;
3640  MI = &*Def;
3641  break;
3642  }
3643 
3644  if (J == I)
3645  return false;
3646  }
3647  }
3648 
3649  // We are searching for an earlier instruction that can make CmpInstr
3650  // redundant and that instruction will be saved in Sub.
3651  MachineInstr *Sub = nullptr;
3653 
3654  // We iterate backward, starting from the instruction before CmpInstr and
3655  // stop when reaching the definition of a source register or done with the BB.
3656  // RI points to the instruction before CmpInstr.
3657  // If the definition is in this basic block, RE points to the definition;
3658  // otherwise, RE is the rend of the basic block.
3660  RI = ++I.getReverse(),
3661  RE = CmpInstr.getParent() == MI->getParent()
3662  ? Def.getReverse() /* points to MI */
3663  : CmpInstr.getParent()->rend();
3664  MachineInstr *Movr0Inst = nullptr;
3665  for (; RI != RE; ++RI) {
3666  MachineInstr &Instr = *RI;
3667  // Check whether CmpInstr can be made redundant by the current instruction.
3668  if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask,
3669  CmpValue, Instr)) {
3670  Sub = &Instr;
3671  break;
3672  }
3673 
3674  if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
3675  Instr.readsRegister(X86::EFLAGS, TRI)) {
3676  // This instruction modifies or uses EFLAGS.
3677 
3678  // MOV32r0 etc. are implemented with xor which clobbers condition code.
3679  // They are safe to move up, if the definition to EFLAGS is dead and
3680  // earlier instructions do not read or write EFLAGS.
3681  if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
3682  Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
3683  Movr0Inst = &Instr;
3684  continue;
3685  }
3686 
3687  // We can't remove CmpInstr.
3688  return false;
3689  }
3690  }
3691 
3692  // Return false if no candidates exist.
3693  if (!IsCmpZero && !Sub)
3694  return false;
3695 
3696  bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
3697  Sub->getOperand(2).getReg() == SrcReg);
3698 
3699  // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
3700  // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3701  // If we are done with the basic block, we need to check whether EFLAGS is
3702  // live-out.
3703  bool IsSafe = false;
3704  SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
3705  MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
3706  for (++I; I != E; ++I) {
3707  const MachineInstr &Instr = *I;
3708  bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3709  bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3710  // We should check the usage if this instruction uses and updates EFLAGS.
3711  if (!UseEFLAGS && ModifyEFLAGS) {
3712  // It is safe to remove CmpInstr if EFLAGS is updated again.
3713  IsSafe = true;
3714  break;
3715  }
3716  if (!UseEFLAGS && !ModifyEFLAGS)
3717  continue;
3718 
3719  // EFLAGS is used by this instruction.
3721  bool OpcIsSET = false;
3722  if (IsCmpZero || IsSwapped) {
3723  // We decode the condition code from opcode.
3724  if (Instr.isBranch())
3725  OldCC = X86::getCondFromBranchOpc(Instr.getOpcode());
3726  else {
3727  OldCC = X86::getCondFromSETOpc(Instr.getOpcode());
3728  if (OldCC != X86::COND_INVALID)
3729  OpcIsSET = true;
3730  else
3731  OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
3732  }
3733  if (OldCC == X86::COND_INVALID) return false;
3734  }
3735  X86::CondCode ReplacementCC = X86::COND_INVALID;
3736  if (IsCmpZero) {
3737  switch (OldCC) {
3738  default: break;
3739  case X86::COND_A: case X86::COND_AE:
3740  case X86::COND_B: case X86::COND_BE:
3741  case X86::COND_G: case X86::COND_GE:
3742  case X86::COND_L: case X86::COND_LE:
3743  case X86::COND_O: case X86::COND_NO:
3744  // CF and OF are used, we can't perform this optimization.
3745  return false;
3746  case X86::COND_S: case X86::COND_NS:
3747  // If SF is used, but the instruction doesn't update the SF, then we
3748  // can't do the optimization.
3749  if (NoSignFlag)
3750  return false;
3751  break;
3752  }
3753 
3754  // If we're updating the condition code check if we have to reverse the
3755  // condition.
3756  if (ShouldUpdateCC)
3757  switch (OldCC) {
3758  default:
3759  return false;
3760  case X86::COND_E:
3761  ReplacementCC = NewCC;
3762  break;
3763  case X86::COND_NE:
3764  ReplacementCC = GetOppositeBranchCondition(NewCC);
3765  break;
3766  }
3767  } else if (IsSwapped) {
3768  // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
3769  // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3770  // We swap the condition code and synthesize the new opcode.
3771  ReplacementCC = getSwappedCondition(OldCC);
3772  if (ReplacementCC == X86::COND_INVALID) return false;
3773  }
3774 
3775  if ((ShouldUpdateCC || IsSwapped) && ReplacementCC != OldCC) {
3776  // Synthesize the new opcode.
3777  bool HasMemoryOperand = Instr.hasOneMemOperand();
3778  unsigned NewOpc;
3779  if (Instr.isBranch())
3780  NewOpc = GetCondBranchFromCond(ReplacementCC);
3781  else if(OpcIsSET)
3782  NewOpc = getSETFromCond(ReplacementCC, HasMemoryOperand);
3783  else {
3784  unsigned DstReg = Instr.getOperand(0).getReg();
3785  const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
3786  NewOpc = getCMovFromCond(ReplacementCC, TRI->getRegSizeInBits(*DstRC)/8,
3787  HasMemoryOperand);
3788  }
3789 
3790  // Push the MachineInstr to OpsToUpdate.
3791  // If it is safe to remove CmpInstr, the condition code of these
3792  // instructions will be modified.
3793  OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
3794  }
3795  if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3796  // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
3797  IsSafe = true;
3798  break;
3799  }
3800  }
3801 
3802  // If EFLAGS is not killed nor re-defined, we should check whether it is
3803  // live-out. If it is live-out, do not optimize.
3804  if ((IsCmpZero || IsSwapped) && !IsSafe) {
3805  MachineBasicBlock *MBB = CmpInstr.getParent();
3806  for (MachineBasicBlock *Successor : MBB->successors())
3807  if (Successor->isLiveIn(X86::EFLAGS))
3808  return false;
3809  }
3810 
3811  // The instruction to be updated is either Sub or MI.
3812  Sub = IsCmpZero ? MI : Sub;
3813  // Move Movr0Inst to the appropriate place before Sub.
3814  if (Movr0Inst) {
3815  // Look backwards until we find a def that doesn't use the current EFLAGS.
3816  Def = Sub;
3818  InsertE = Sub->getParent()->rend();
3819  for (; InsertI != InsertE; ++InsertI) {
3820  MachineInstr *Instr = &*InsertI;
3821  if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
3822  Instr->modifiesRegister(X86::EFLAGS, TRI)) {
3823  Sub->getParent()->remove(Movr0Inst);
3824  Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
3825  Movr0Inst);
3826  break;
3827  }
3828  }
3829  if (InsertI == InsertE)
3830  return false;
3831  }
3832 
3833  // Make sure Sub instruction defines EFLAGS and mark the def live.
3834  unsigned i = 0, e = Sub->getNumOperands();
3835  for (; i != e; ++i) {
3836  MachineOperand &MO = Sub->getOperand(i);
3837  if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
3838  MO.setIsDead(false);
3839  break;
3840  }
3841  }
3842  assert(i != e && "Unable to locate a def EFLAGS operand");
3843 
3844  CmpInstr.eraseFromParent();
3845 
3846  // Modify the condition code of instructions in OpsToUpdate.
3847  for (auto &Op : OpsToUpdate)
3848  Op.first->setDesc(get(Op.second));
3849  return true;
3850 }
3851 
3852 /// Try to remove the load by folding it to a register
3853 /// operand at the use. We fold the load instructions if load defines a virtual
3854 /// register, the virtual register is used once in the same BB, and the
3855 /// instructions in-between do not load or store, and have no side effects.
3857  const MachineRegisterInfo *MRI,
3858  unsigned &FoldAsLoadDefReg,
3859  MachineInstr *&DefMI) const {
3860  // Check whether we can move DefMI here.
3861  DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
3862  assert(DefMI);
3863  bool SawStore = false;
3864  if (!DefMI->isSafeToMove(nullptr, SawStore))
3865  return nullptr;
3866 
3867  // Collect information about virtual register operands of MI.
3868  SmallVector<unsigned, 1> SrcOperandIds;
3869  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
3870  MachineOperand &MO = MI.getOperand(i);
3871  if (!MO.isReg())
3872  continue;
3873  unsigned Reg = MO.getReg();
3874  if (Reg != FoldAsLoadDefReg)
3875  continue;
3876  // Do not fold if we have a subreg use or a def.
3877  if (MO.getSubReg() || MO.isDef())
3878  return nullptr;
3879  SrcOperandIds.push_back(i);
3880  }
3881  if (SrcOperandIds.empty())
3882  return nullptr;
3883 
3884  // Check whether we can fold the def into SrcOperandId.
3885  if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
3886  FoldAsLoadDefReg = 0;
3887  return FoldMI;
3888  }
3889 
3890  return nullptr;
3891 }
3892 
3893 /// Expand a single-def pseudo instruction to a two-addr
3894 /// instruction with two undef reads of the register being defined.
3895 /// This is used for mapping:
3896 /// %xmm4 = V_SET0
3897 /// to:
3898 /// %xmm4 = PXORrr undef %xmm4, undef %xmm4
3899 ///
3901  const MCInstrDesc &Desc) {
3902  assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3903  unsigned Reg = MIB->getOperand(0).getReg();
3904  MIB->setDesc(Desc);
3905 
3906  // MachineInstr::addOperand() will insert explicit operands before any
3907  // implicit operands.
3908  MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3909  // But we don't trust that.
3910  assert(MIB->getOperand(1).getReg() == Reg &&
3911  MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
3912  return true;
3913 }
3914 
3915 /// Expand a single-def pseudo instruction to a two-addr
3916 /// instruction with two %k0 reads.
3917 /// This is used for mapping:
3918 /// %k4 = K_SET1
3919 /// to:
3920 /// %k4 = KXNORrr %k0, %k0
3922  const MCInstrDesc &Desc, unsigned Reg) {
3923  assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3924  MIB->setDesc(Desc);
3925  MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3926  return true;
3927 }
3928 
3930  bool MinusOne) {
3931  MachineBasicBlock &MBB = *MIB->getParent();
3932  DebugLoc DL = MIB->getDebugLoc();
3933  unsigned Reg = MIB->getOperand(0).getReg();
3934 
3935  // Insert the XOR.
3936  BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
3937  .addReg(Reg, RegState::Undef)
3938  .addReg(Reg, RegState::Undef);
3939 
3940  // Turn the pseudo into an INC or DEC.
3941  MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
3942  MIB.addReg(Reg);
3943 
3944  return true;
3945 }
3946 
3948  const TargetInstrInfo &TII,
3949  const X86Subtarget &Subtarget) {
3950  MachineBasicBlock &MBB = *MIB->getParent();
3951  DebugLoc DL = MIB->getDebugLoc();
3952  int64_t Imm = MIB->getOperand(1).getImm();
3953  assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
3955 
3956  int StackAdjustment;
3957 
3958  if (Subtarget.is64Bit()) {
3959  assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
3960  MIB->getOpcode() == X86::MOV32ImmSExti8);
3961 
3962  // Can't use push/pop lowering if the function might write to the red zone.
3963  X86MachineFunctionInfo *X86FI =
3965  if (X86FI->getUsesRedZone()) {
3966  MIB->setDesc(TII.get(MIB->getOpcode() ==
3967  X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
3968  return true;
3969  }
3970 
3971  // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
3972  // widen the register if necessary.
3973  StackAdjustment = 8;
3974  BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
3975  MIB->setDesc(TII.get(X86::POP64r));
3976  MIB->getOperand(0)
3978  } else {
3979  assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
3980  StackAdjustment = 4;
3981  BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
3982  MIB->setDesc(TII.get(X86::POP32r));
3983  }
3984 
3985  // Build CFI if necessary.
3986  MachineFunction &MF = *MBB.getParent();
3987  const X86FrameLowering *TFL = Subtarget.getFrameLowering();
3988  bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
3989  bool NeedsDwarfCFI =
3990  !IsWin64Prologue &&
3992  bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
3993  if (EmitCFI) {
3994  TFL->BuildCFI(MBB, I, DL,
3995  MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
3996  TFL->BuildCFI(MBB, std::next(I), DL,
3997  MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
3998  }
3999 
4000  return true;
4001 }
4002 
4003 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4004 // code sequence is needed for other targets.
4006  const TargetInstrInfo &TII) {
4007  MachineBasicBlock &MBB = *MIB->getParent();
4008  DebugLoc DL = MIB->getDebugLoc();
4009  unsigned Reg = MIB->getOperand(0).getReg();
4010  const GlobalValue *GV =
4011  cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4012  auto Flags = MachineMemOperand::MOLoad |
4016  MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
4018 
4019  BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4021  .addMemOperand(MMO);
4022  MIB->setDebugLoc(DL);
4023  MIB->setDesc(TII.get(X86::MOV64rm));
4024  MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4025 }
4026 
4028  MachineBasicBlock &MBB = *MIB->getParent();
4029  MachineFunction &MF = *MBB.getParent();
4030  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
4031  const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4032  unsigned XorOp =
4033  MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
4034  MIB->setDesc(TII.get(XorOp));
4035  MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
4036  return true;
4037 }
4038 
4039 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4040 // but not VLX. If it uses an extended register we need to use an instruction
4041 // that loads the lower 128/256-bit, but is available with only AVX512F.
4043  const TargetRegisterInfo *TRI,
4044  const MCInstrDesc &LoadDesc,
4045  const MCInstrDesc &BroadcastDesc,
4046  unsigned SubIdx) {
4047  unsigned DestReg = MIB->getOperand(0).getReg();
4048  // Check if DestReg is XMM16-31 or YMM16-31.
4049  if (TRI->getEncodingValue(DestReg) < 16) {
4050  // We can use a normal VEX encoded load.
4051  MIB->setDesc(LoadDesc);
4052  } else {
4053  // Use a 128/256-bit VBROADCAST instruction.
4054  MIB->setDesc(BroadcastDesc);
4055  // Change the destination to a 512-bit register.
4056  DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
4057  MIB->getOperand(0).setReg(DestReg);
4058  }
4059  return true;
4060 }
4061 
4062 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4063 // but not VLX. If it uses an extended register we need to use an instruction
4064 // that stores the lower 128/256-bit, but is available with only AVX512F.
4066  const TargetRegisterInfo *TRI,
4067  const MCInstrDesc &StoreDesc,
4068  const MCInstrDesc &ExtractDesc,
4069  unsigned SubIdx) {
4070  unsigned SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
4071  // Check if DestReg is XMM16-31 or YMM16-31.
4072  if (TRI->getEncodingValue(SrcReg) < 16) {
4073  // We can use a normal VEX encoded store.
4074  MIB->setDesc(StoreDesc);
4075  } else {
4076  // Use a VEXTRACTF instruction.
4077  MIB->setDesc(ExtractDesc);
4078  // Change the destination to a 512-bit register.
4079  SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
4080  MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
4081  MIB.addImm(0x0); // Append immediate to extract from the lower bits.
4082  }
4083 
4084  return true;
4085 }
4087  bool HasAVX = Subtarget.hasAVX();
4088  MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4089  switch (MI.getOpcode()) {
4090  case X86::MOV32r0:
4091  return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4092  case X86::MOV32r1:
4093  return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
4094  case X86::MOV32r_1:
4095  return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
4096  case X86::MOV32ImmSExti8:
4097  case X86::MOV64ImmSExti8:
4098  return ExpandMOVImmSExti8(MIB, *this, Subtarget);
4099  case X86::SETB_C8r:
4100  return Expand2AddrUndef(MIB, get(X86::SBB8rr));
4101  case X86::SETB_C16r:
4102  return Expand2AddrUndef(MIB, get(X86::SBB16rr));
4103  case X86::SETB_C32r:
4104  return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4105  case X86::SETB_C64r:
4106  return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4107  case X86::MMX_SET0:
4108  return Expand2AddrUndef(MIB, get(X86::MMX_PXORirr));
4109  case X86::V_SET0:
4110  case X86::FsFLD0SS:
4111  case X86::FsFLD0SD:
4112  return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4113  case X86::AVX_SET0: {
4114  assert(HasAVX && "AVX not supported");
4116  unsigned SrcReg = MIB->getOperand(0).getReg();
4117  unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4118  MIB->getOperand(0).setReg(XReg);
4119  Expand2AddrUndef(MIB, get(X86::VXORPSrr));
4120  MIB.addReg(SrcReg, RegState::ImplicitDefine);
4121  return true;
4122  }
4123  case X86::AVX512_128_SET0:
4124  case X86::AVX512_FsFLD0SS:
4125  case X86::AVX512_FsFLD0SD: {
4126  bool HasVLX = Subtarget.hasVLX();
4127  unsigned SrcReg = MIB->getOperand(0).getReg();
4129  if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
4130  return Expand2AddrUndef(MIB,
4131  get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4132  // Extended register without VLX. Use a larger XOR.
4133  SrcReg =
4134  TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
4135  MIB->getOperand(0).setReg(SrcReg);
4136  return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4137  }
4138  case X86::AVX512_256_SET0:
4139  case X86::AVX512_512_SET0: {
4140  bool HasVLX = Subtarget.hasVLX();
4141  unsigned SrcReg = MIB->getOperand(0).getReg();
4143  if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
4144  unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4145  MIB->getOperand(0).setReg(XReg);
4146  Expand2AddrUndef(MIB,
4147  get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4148  MIB.addReg(SrcReg, RegState::ImplicitDefine);
4149  return true;
4150  }
4151  return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4152  }
4153  case X86::V_SETALLONES:
4154  return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4155  case X86::AVX2_SETALLONES:
4156  return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4157  case X86::AVX1_SETALLONES: {
4158  unsigned Reg = MIB->getOperand(0).getReg();
4159  // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
4160  MIB->setDesc(get(X86::VCMPPSYrri));
4161  MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4162  return true;
4163  }
4164  case X86::AVX512_512_SETALLONES: {
4165  unsigned Reg = MIB->getOperand(0).getReg();
4166  MIB->setDesc(get(X86::VPTERNLOGDZrri));
4167  // VPTERNLOGD needs 3 register inputs and an immediate.
4168  // 0xff will return 1s for any input.
4169  MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4170  .addReg(Reg, RegState::Undef).addImm(0xff);
4171  return true;
4172  }
4173  case X86::AVX512_512_SEXT_MASK_32:
4174  case X86::AVX512_512_SEXT_MASK_64: {
4175  unsigned Reg = MIB->getOperand(0).getReg();
4176  unsigned MaskReg = MIB->getOperand(1).getReg();
4177  unsigned MaskState = getRegState(MIB->getOperand(1));
4178  unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
4179  X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
4180  MI.RemoveOperand(1);
4181  MIB->setDesc(get(Opc));
4182  // VPTERNLOG needs 3 register inputs and an immediate.
4183  // 0xff will return 1s for any input.
4184  MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4185  .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4186  return true;
4187  }
4188  case X86::VMOVAPSZ128rm_NOVLX:
4189  return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
4190  get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4191  case X86::VMOVUPSZ128rm_NOVLX:
4192  return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
4193  get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4194  case X86::VMOVAPSZ256rm_NOVLX:
4195  return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
4196  get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4197  case X86::VMOVUPSZ256rm_NOVLX:
4198  return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
4199  get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4200  case X86::VMOVAPSZ128mr_NOVLX:
4201  return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
4202  get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4203  case X86::VMOVUPSZ128mr_NOVLX:
4204  return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
4205  get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4206  case X86::VMOVAPSZ256mr_NOVLX:
4207  return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
4208  get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4209  case X86::VMOVUPSZ256mr_NOVLX:
4210  return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
4211  get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4212  case X86::MOV32ri64: {
4213  unsigned Reg = MIB->getOperand(0).getReg();
4214  unsigned Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
4215  MI.setDesc(get(X86::MOV32ri));
4216  MIB->getOperand(0).setReg(Reg32);
4217  MIB.addReg(Reg, RegState::ImplicitDefine);
4218  return true;
4219  }
4220 
4221  // KNL does not recognize dependency-breaking idioms for mask registers,
4222  // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
4223  // Using %k0 as the undef input register is a performance heuristic based
4224  // on the assumption that %k0 is used less frequently than the other mask
4225  // registers, since it is not usable as a write mask.
4226  // FIXME: A more advanced approach would be to choose the best input mask
4227  // register based on context.
4228  case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
4229  case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
4230  case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
4231  case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
4232  case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
4233  case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
4234  case TargetOpcode::LOAD_STACK_GUARD:
4235  expandLoadStackGuard(MIB, *this);
4236  return true;
4237  case X86::XOR64_FP:
4238  case X86::XOR32_FP:
4239  return expandXorFP(MIB, *this);
4240  case X86::ADD8rr_DB: MIB->setDesc(get(X86::OR8rr)); break;
4241  case X86::ADD16rr_DB: MIB->setDesc(get(X86::OR16rr)); break;
4242  case X86::ADD32rr_DB: MIB->setDesc(get(X86::OR32rr)); break;
4243  case X86::ADD64rr_DB: MIB->setDesc(get(X86::OR64rr)); break;
4244  case X86::ADD8ri_DB: MIB->setDesc(get(X86::OR8ri)); break;
4245  case X86::ADD16ri_DB: MIB->setDesc(get(X86::OR16ri)); break;
4246  case X86::ADD32ri_DB: MIB->setDesc(get(X86::OR32ri)); break;
4247  case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
4248  case X86::ADD16ri8_DB: MIB->setDesc(get(X86::OR16ri8)); break;
4249  case X86::ADD32ri8_DB: MIB->setDesc(get(X86::OR32ri8)); break;
4250  case X86::ADD64ri8_DB: MIB->setDesc(get(X86::OR64ri8)); break;
4251  }
4252  return false;
4253 }
4254 
4255 /// Return true for all instructions that only update
4256 /// the first 32 or 64-bits of the destination register and leave the rest
4257 /// unmodified. This can be used to avoid folding loads if the instructions
4258 /// only update part of the destination register, and the non-updated part is
4259 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4260 /// instructions breaks the partial register dependency and it can improve
4261 /// performance. e.g.:
4262 ///
4263 /// movss (%rdi), %xmm0
4264 /// cvtss2sd %xmm0, %xmm0
4265 ///
4266 /// Instead of
4267 /// cvtss2sd (%rdi), %xmm0
4268 ///
4269 /// FIXME: This should be turned into a TSFlags.
4270 ///
4271 static bool hasPartialRegUpdate(unsigned Opcode,
4272  const X86Subtarget &Subtarget,
4273  bool ForLoadFold = false) {
4274  switch (Opcode) {
4275  case X86::CVTSI2SSrr:
4276  case X86::CVTSI2SSrm:
4277  case X86::CVTSI642SSrr:
4278  case X86::CVTSI642SSrm:
4279  case X86::CVTSI2SDrr:
4280  case X86::CVTSI2SDrm:
4281  case X86::CVTSI642SDrr:
4282  case X86::CVTSI642SDrm:
4283  // Load folding won't effect the undef register update since the input is
4284  // a GPR.
4285  return !ForLoadFold;
4286  case X86::CVTSD2SSrr:
4287  case X86::CVTSD2SSrm:
4288  case X86::CVTSS2SDrr:
4289  case X86::CVTSS2SDrm:
4290  case X86::MOVHPDrm:
4291  case X86::MOVHPSrm:
4292  case X86::MOVLPDrm:
4293  case X86::MOVLPSrm:
4294  case X86::RCPSSr:
4295  case X86::RCPSSm:
4296  case X86::RCPSSr_Int:
4297  case X86::RCPSSm_Int:
4298  case X86::ROUNDSDr:
4299  case X86::ROUNDSDm:
4300  case X86::ROUNDSSr:
4301  case X86::ROUNDSSm:
4302  case X86::RSQRTSSr:
4303  case X86::RSQRTSSm:
4304  case X86::RSQRTSSr_Int:
4305  case X86::RSQRTSSm_Int:
4306  case X86::SQRTSSr:
4307  case X86::SQRTSSm:
4308  case X86::SQRTSSr_Int:
4309  case X86::SQRTSSm_Int:
4310  case X86::SQRTSDr:
4311  case X86::SQRTSDm:
4312  case X86::SQRTSDr_Int:
4313  case X86::SQRTSDm_Int:
4314  return true;
4315  // GPR
4316  case X86::POPCNT32rm:
4317  case X86::POPCNT32rr:
4318  case X86::POPCNT64rm:
4319  case X86::POPCNT64rr:
4320  return Subtarget.hasPOPCNTFalseDeps();
4321  case X86::LZCNT32rm:
4322  case X86::LZCNT32rr:
4323  case X86::LZCNT64rm:
4324  case X86::LZCNT64rr:
4325  case X86::TZCNT32rm:
4326  case X86::TZCNT32rr:
4327  case X86::TZCNT64rm:
4328  case X86::TZCNT64rr:
4329  return Subtarget.hasLZCNTFalseDeps();
4330  }
4331 
4332  return false;
4333 }
4334 
4335 /// Inform the BreakFalseDeps pass how many idle
4336 /// instructions we would like before a partial register update.
4338  const MachineInstr &MI, unsigned OpNum,
4339  const TargetRegisterInfo *TRI) const {
4340  if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
4341  return 0;
4342 
4343  // If MI is marked as reading Reg, the partial register update is wanted.
4344  const MachineOperand &MO = MI.getOperand(0);
4345  unsigned Reg = MO.getReg();
4347  if (MO.readsReg() || MI.readsVirtualRegister(Reg))
4348  return 0;
4349  } else {
4350  if (MI.readsRegister(Reg, TRI))
4351  return 0;
4352  }
4353 
4354  // If any instructions in the clearance range are reading Reg, insert a
4355  // dependency breaking instruction, which is inexpensive and is likely to
4356  // be hidden in other instruction's cycles.
4358 }
4359 
4360 // Return true for any instruction the copies the high bits of the first source
4361 // operand into the unused high bits of the destination operand.
4362 static bool hasUndefRegUpdate(unsigned Opcode, bool ForLoadFold = false) {
4363  switch (Opcode) {
4364  case X86::VCVTSI2SSrr:
4365  case X86::VCVTSI2SSrm:
4366  case X86::VCVTSI2SSrr_Int:
4367  case X86::VCVTSI2SSrm_Int:
4368  case X86::VCVTSI642SSrr:
4369  case X86::VCVTSI642SSrm:
4370  case X86::VCVTSI642SSrr_Int:
4371  case X86::VCVTSI642SSrm_Int:
4372  case X86::VCVTSI2SDrr:
4373  case X86::VCVTSI2SDrm:
4374  case X86::VCVTSI2SDrr_Int:
4375  case X86::VCVTSI2SDrm_Int:
4376  case X86::VCVTSI642SDrr:
4377  case X86::VCVTSI642SDrm:
4378  case X86::VCVTSI642SDrr_Int:
4379  case X86::VCVTSI642SDrm_Int:
4380  // AVX-512
4381  case X86::VCVTSI2SSZrr:
4382  case X86::VCVTSI2SSZrm:
4383  case X86::VCVTSI2SSZrr_Int:
4384  case X86::VCVTSI2SSZrrb_Int:
4385  case X86::VCVTSI2SSZrm_Int:
4386  case X86::VCVTSI642SSZrr:
4387  case X86::VCVTSI642SSZrm:
4388  case X86::VCVTSI642SSZrr_Int:
4389  case X86::VCVTSI642SSZrrb_Int:
4390  case X86::VCVTSI642SSZrm_Int:
4391  case X86::VCVTSI2SDZrr:
4392  case X86::VCVTSI2SDZrm:
4393  case X86::VCVTSI2SDZrr_Int:
4394  case X86::VCVTSI2SDZrm_Int:
4395  case X86::VCVTSI642SDZrr:
4396  case X86::VCVTSI642SDZrm:
4397  case X86::VCVTSI642SDZrr_Int:
4398  case X86::VCVTSI642SDZrrb_Int:
4399  case X86::VCVTSI642SDZrm_Int:
4400  case X86::VCVTUSI2SSZrr:
4401  case X86::VCVTUSI2SSZrm:
4402  case X86::VCVTUSI2SSZrr_Int:
4403  case X86::VCVTUSI2SSZrrb_Int:
4404  case X86::VCVTUSI2SSZrm_Int:
4405  case X86::VCVTUSI642SSZrr:
4406  case X86::VCVTUSI642SSZrm:
4407  case X86::VCVTUSI642SSZrr_Int:
4408  case X86::VCVTUSI642SSZrrb_Int:
4409  case X86::VCVTUSI642SSZrm_Int:
4410  case X86::VCVTUSI2SDZrr:
4411  case X86::VCVTUSI2SDZrm:
4412  case X86::VCVTUSI2SDZrr_Int:
4413  case X86::VCVTUSI2SDZrm_Int:
4414  case X86::VCVTUSI642SDZrr:
4415  case X86::VCVTUSI642SDZrm:
4416  case X86::VCVTUSI642SDZrr_Int:
4417  case X86::VCVTUSI642SDZrrb_Int:
4418  case X86::VCVTUSI642SDZrm_Int:
4419  // Load folding won't effect the undef register update since the input is
4420  // a GPR.
4421  return !ForLoadFold;
4422  case X86::VCVTSD2SSrr:
4423  case X86::VCVTSD2SSrm:
4424  case X86::VCVTSD2SSrr_Int:
4425  case X86::VCVTSD2SSrm_Int:
4426  case X86::VCVTSS2SDrr:
4427  case X86::VCVTSS2SDrm:
4428  case X86::VCVTSS2SDrr_Int:
4429  case X86::VCVTSS2SDrm_Int:
4430  case X86::VRCPSSr:
4431  case X86::VRCPSSr_Int:
4432  case X86::VRCPSSm:
4433  case X86::VRCPSSm_Int:
4434  case X86::VROUNDSDr:
4435  case X86::VROUNDSDm:
4436  case X86::VROUNDSDr_Int:
4437  case X86::VROUNDSDm_Int:
4438  case X86::VROUNDSSr:
4439  case X86::VROUNDSSm:
4440  case X86::VROUNDSSr_Int:
4441  case X86::VROUNDSSm_Int:
4442  case X86::VRSQRTSSr:
4443  case X86::VRSQRTSSr_Int:
4444  case X86::VRSQRTSSm:
4445  case X86::VRSQRTSSm_Int:
4446  case X86::VSQRTSSr:
4447  case X86::VSQRTSSr_Int:
4448  case X86::VSQRTSSm:
4449  case X86::VSQRTSSm_Int:
4450  case X86::VSQRTSDr:
4451  case X86::VSQRTSDr_Int:
4452  case X86::VSQRTSDm:
4453  case X86::VSQRTSDm_Int:
4454  // AVX-512
4455  case X86::VCVTSD2SSZrr:
4456  case X86::VCVTSD2SSZrr_Int:
4457  case X86::VCVTSD2SSZrrb_Int:
4458  case X86::VCVTSD2SSZrm:
4459  case X86::VCVTSD2SSZrm_Int:
4460  case X86::VCVTSS2SDZrr:
4461  case X86::VCVTSS2SDZrr_Int:
4462  case X86::VCVTSS2SDZrrb_Int:
4463  case X86::VCVTSS2SDZrm:
4464  case X86::VCVTSS2SDZrm_Int:
4465  case X86::VGETEXPSDZr:
4466  case X86::VGETEXPSDZrb:
4467  case X86::VGETEXPSDZm:
4468  case X86::VGETEXPSSZr:
4469  case X86::VGETEXPSSZrb:
4470  case X86::VGETEXPSSZm:
4471  case X86::VGETMANTSDZrri:
4472  case X86::VGETMANTSDZrrib:
4473  case X86::VGETMANTSDZrmi:
4474  case X86::VGETMANTSSZrri:
4475  case X86::VGETMANTSSZrrib:
4476  case X86::VGETMANTSSZrmi:
4477  case X86::VRNDSCALESDZr:
4478  case X86::VRNDSCALESDZr_Int:
4479  case X86::VRNDSCALESDZrb_Int:
4480  case X86::VRNDSCALESDZm:
4481  case X86::VRNDSCALESDZm_Int:
4482  case X86::VRNDSCALESSZr:
4483  case X86::VRNDSCALESSZr_Int:
4484  case X86::VRNDSCALESSZrb_Int:
4485  case X86::VRNDSCALESSZm:
4486  case X86::VRNDSCALESSZm_Int:
4487  case X86::VRCP14SDZrr:
4488  case X86::VRCP14SDZrm:
4489  case X86::VRCP14SSZrr:
4490  case X86::VRCP14SSZrm:
4491  case X86::VRCP28SDZr:
4492  case X86::VRCP28SDZrb:
4493  case X86::VRCP28SDZm:
4494  case X86::VRCP28SSZr:
4495  case X86::VRCP28SSZrb:
4496  case X86::VRCP28SSZm:
4497  case X86::VREDUCESSZrmi:
4498  case X86::VREDUCESSZrri:
4499  case X86::VREDUCESSZrrib:
4500  case X86::VRSQRT14SDZrr:
4501  case X86::VRSQRT14SDZrm:
4502  case X86::VRSQRT14SSZrr:
4503  case X86::VRSQRT14SSZrm:
4504  case X86::VRSQRT28SDZr:
4505  case X86::VRSQRT28SDZrb:
4506  case X86::VRSQRT28SDZm:
4507  case X86::VRSQRT28SSZr:
4508  case X86::VRSQRT28SSZrb:
4509  case X86::VRSQRT28SSZm:
4510  case X86::VSQRTSSZr:
4511  case X86::VSQRTSSZr_Int:
4512  case X86::VSQRTSSZrb_Int:
4513  case X86::VSQRTSSZm:
4514  case X86::VSQRTSSZm_Int:
4515  case X86::VSQRTSDZr:
4516  case X86::VSQRTSDZr_Int:
4517  case X86::VSQRTSDZrb_Int:
4518  case X86::VSQRTSDZm:
4519  case X86::VSQRTSDZm_Int:
4520  return true;
4521  }
4522 
4523  return false;
4524 }
4525 
4526 /// Inform the BreakFalseDeps pass how many idle instructions we would like
4527 /// before certain undef register reads.
4528 ///
4529 /// This catches the VCVTSI2SD family of instructions:
4530 ///
4531 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
4532 ///
4533 /// We should to be careful *not* to catch VXOR idioms which are presumably
4534 /// handled specially in the pipeline:
4535 ///
4536 /// vxorps undef %xmm1, undef %xmm1, %xmm1
4537 ///
4538 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4539 /// high bits that are passed-through are not live.
4540 unsigned
4542  const TargetRegisterInfo *TRI) const {
4543  if (!hasUndefRegUpdate(MI.getOpcode()))
4544  return 0;
4545 
4546  // Set the OpNum parameter to the first source operand.
4547  OpNum = 1;
4548 
4549  const MachineOperand &MO = MI.getOperand(OpNum);
4551  return UndefRegClearance;
4552  }
4553  return 0;
4554 }
4555 
4557  MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
4558  unsigned Reg = MI.getOperand(OpNum).getReg();
4559  // If MI kills this register, the false dependence is already broken.
4560  if (MI.killsRegister(Reg, TRI))
4561  return;
4562 
4563  if (X86::VR128RegClass.contains(Reg)) {
4564  // These instructions are all floating point domain, so xorps is the best
4565  // choice.
4566  unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
4567  BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
4568  .addReg(Reg, RegState::Undef)
4569  .addReg(Reg, RegState::Undef);
4570  MI.addRegisterKilled(Reg, TRI, true);
4571  } else if (X86::VR256RegClass.contains(Reg)) {
4572  // Use vxorps to clear the full ymm register.
4573  // It wants to read and write the xmm sub-register.
4574  unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4575  BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
4576  .addReg(XReg, RegState::Undef)
4577  .addReg(XReg, RegState::Undef)
4579  MI.addRegisterKilled(Reg, TRI, true);
4580  } else if (X86::GR64RegClass.contains(Reg)) {
4581  // Using XOR32rr because it has shorter encoding and zeros up the upper bits
4582  // as well.
4583  unsigned XReg = TRI->getSubReg(Reg, X86::sub_32bit);
4584  BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
4585  .addReg(XReg, RegState::Undef)
4586  .addReg(XReg, RegState::Undef)
4588  MI.addRegisterKilled(Reg, TRI, true);
4589  } else if (X86::GR32RegClass.contains(Reg)) {
4590  BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
4591  .addReg(Reg, RegState::Undef)
4592  .addReg(Reg, RegState::Undef);
4593  MI.addRegisterKilled(Reg, TRI, true);
4594  }
4595 }
4596 
4598  int PtrOffset = 0) {
4599  unsigned NumAddrOps = MOs.size();
4600 
4601  if (NumAddrOps < 4) {
4602  // FrameIndex only - add an immediate offset (whether its zero or not).
4603  for (unsigned i = 0; i != NumAddrOps; ++i)
4604  MIB.add(MOs[i]);
4605  addOffset(MIB, PtrOffset);
4606  } else {
4607  // General Memory Addressing - we need to add any offset to an existing
4608  // offset.
4609  assert(MOs.size() == 5 && "Unexpected memory operand list length");
4610  for (unsigned i = 0; i != NumAddrOps; ++i) {
4611  const MachineOperand &MO = MOs[i];
4612  if (i == 3 && PtrOffset != 0) {
4613  MIB.addDisp(MO, PtrOffset);
4614  } else {
4615  MIB.add(MO);
4616  }
4617  }
4618  }
4619 }
4620 
4622  MachineInstr &NewMI,
4623  const TargetInstrInfo &TII) {
4626 
4627  for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
4628  MachineOperand &MO = NewMI.getOperand(Idx);
4629  // We only need to update constraints on virtual register operands.
4630  if (!MO.isReg())
4631  continue;
4632  unsigned Reg = MO.getReg();
4633  if (!TRI.isVirtualRegister(Reg))
4634  continue;
4635 
4636  auto *NewRC = MRI.constrainRegClass(
4637  Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
4638  if (!NewRC) {
4639  LLVM_DEBUG(
4640  dbgs() << "WARNING: Unable to update register constraint for operand "
4641  << Idx << " of instruction:\n";
4642  NewMI.dump(); dbgs() << "\n");
4643  }
4644  }
4645 }
4646 
4647 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
4649  MachineBasicBlock::iterator InsertPt,
4650  MachineInstr &MI,
4651  const TargetInstrInfo &TII) {
4652  // Create the base instruction with the memory operand as the first part.
4653  // Omit the implicit operands, something BuildMI can't do.
4654  MachineInstr *NewMI =
4655  MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
4656  MachineInstrBuilder MIB(MF, NewMI);
4657  addOperands(MIB, MOs);
4658 
4659  // Loop over the rest of the ri operands, converting them over.
4660  unsigned NumOps = MI.getDesc().getNumOperands() - 2;
4661  for (unsigned i = 0; i != NumOps; ++i) {
4662  MachineOperand &MO = MI.getOperand(i + 2);
4663  MIB.add(MO);
4664  }
4665  for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
4666  MachineOperand &MO = MI.getOperand(i);
4667  MIB.add(MO);
4668  }
4669 
4670  updateOperandRegConstraints(MF, *NewMI, TII);
4671 
4672  MachineBasicBlock *MBB = InsertPt->getParent();
4673  MBB->insert(InsertPt, NewMI);
4674 
4675  return MIB;
4676 }
4677 
4678 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
4679  unsigned OpNo, ArrayRef<MachineOperand> MOs,
4680  MachineBasicBlock::iterator InsertPt,
4681  MachineInstr &MI, const TargetInstrInfo &TII,
4682  int PtrOffset = 0) {
4683  // Omit the implicit operands, something BuildMI can't do.
4684  MachineInstr *NewMI =
4685  MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
4686  MachineInstrBuilder MIB(MF, NewMI);
4687 
4688  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4689  MachineOperand &MO = MI.getOperand(i);
4690  if (i == OpNo) {
4691  assert(MO.isReg() && "Expected to fold into reg operand!");
4692  addOperands(MIB, MOs, PtrOffset);
4693  } else {
4694  MIB.add(MO);
4695  }
4696  }
4697 
4698  updateOperandRegConstraints(MF, *NewMI, TII);
4699 
4700  MachineBasicBlock *MBB = InsertPt->getParent();
4701  MBB->insert(InsertPt, NewMI);
4702 
4703  return MIB;
4704 }
4705 
4706 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
4708  MachineBasicBlock::iterator InsertPt,
4709  MachineInstr &MI) {
4710  MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
4711  MI.getDebugLoc(), TII.get(Opcode));
4712  addOperands(MIB, MOs);
4713  return MIB.addImm(0);
4714 }
4715 
4716 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
4717  MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
4719  unsigned Size, unsigned Align) const {
4720  switch (MI.getOpcode()) {
4721  case X86::INSERTPSrr:
4722  case X86::VINSERTPSrr:
4723  case X86::VINSERTPSZrr:
4724  // Attempt to convert the load of inserted vector into a fold load
4725  // of a single float.
4726  if (OpNum == 2) {
4727  unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
4728  unsigned ZMask = Imm & 15;
4729  unsigned DstIdx = (Imm >> 4) & 3;
4730  unsigned SrcIdx = (Imm >> 6) & 3;
4731 
4733  const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4734  unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4735  if (Size <= RCSize && 4 <= Align) {
4736  int PtrOffset = SrcIdx * 4;
4737  unsigned NewImm = (DstIdx << 4) | ZMask;
4738  unsigned NewOpCode =
4739  (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
4740  (MI.getOpcode() == X86::VINSERTPSrr) ? X86::VINSERTPSrm :
4741  X86::INSERTPSrm;
4742  MachineInstr *NewMI =
4743  FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
4744  NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
4745  return NewMI;
4746  }
4747  }
4748  break;
4749  case X86::MOVHLPSrr:
4750  case X86::VMOVHLPSrr:
4751  case X86::VMOVHLPSZrr:
4752  // Move the upper 64-bits of the second operand to the lower 64-bits.
4753  // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
4754  // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
4755  if (OpNum == 2) {
4757  const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4758  unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4759  if (Size <= RCSize && 8 <= Align) {
4760  unsigned NewOpCode =
4761  (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
4762  (MI.getOpcode() == X86::VMOVHLPSrr) ? X86::VMOVLPSrm :
4763  X86::MOVLPSrm;
4764  MachineInstr *NewMI =
4765  FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
4766  return NewMI;
4767  }
4768  }
4769  break;
4770  };
4771 
4772  return nullptr;
4773 }
4774 
4776  MachineInstr &MI) {
4777  if (!hasUndefRegUpdate(MI.getOpcode(), /*ForLoadFold*/true) ||
4778  !MI.getOperand(1).isReg())
4779  return false;
4780 
4781  // The are two cases we need to handle depending on where in the pipeline
4782  // the folding attempt is being made.
4783  // -Register has the undef flag set.
4784  // -Register is produced by the IMPLICIT_DEF instruction.
4785 
4786  if (MI.getOperand(1).isUndef())
4787  return true;
4788 
4789  MachineRegisterInfo &RegInfo = MF.getRegInfo();
4790  MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
4791  return VRegDef && VRegDef->isImplicitDef();
4792 }
4793 
4794 
4796  MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
4798  unsigned Size, unsigned Align, bool AllowCommute) const {
4799  bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
4800  bool isTwoAddrFold = false;
4801 
4802  // For CPUs that favor the register form of a call or push,
4803  // do not fold loads into calls or pushes, unless optimizing for size
4804  // aggressively.
4805  if (isSlowTwoMemOps && !MF.getFunction().optForMinSize() &&
4806  (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
4807  MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
4808  MI.getOpcode() == X86::PUSH64r))
4809  return nullptr;
4810 
4811  // Avoid partial and undef register update stalls unless optimizing for size.
4812  if (!MF.getFunction().optForSize() &&
4813  (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
4815  return nullptr;
4816 
4817  unsigned NumOps = MI.getDesc().getNumOperands();
4818  bool isTwoAddr =
4819  NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4820 
4821  // FIXME: AsmPrinter doesn't know how to handle
4822  // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4823  if (MI.getOpcode() == X86::ADD32ri &&
4825  return nullptr;
4826 
4827  // GOTTPOFF relocation loads can only be folded into add instructions.
4828  // FIXME: Need to exclude other relocations that only support specific
4829  // instructions.
4830  if (MOs.size() == X86::AddrNumOperands &&
4831  MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
4832  MI.getOpcode() != X86::ADD64rr)
4833  return nullptr;
4834 
4835  MachineInstr *NewMI = nullptr;
4836 
4837  // Attempt to fold any custom cases we have.
4838  if (MachineInstr *CustomMI =
4839  foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
4840  return CustomMI;
4841 
4842  const X86MemoryFoldTableEntry *I = nullptr;
4843 
4844  // Folding a memory location into the two-address part of a two-address
4845  // instruction is different than folding it other places. It requires
4846  // replacing the *two* registers with the memory location.
4847  if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
4848  MI.getOperand(1).isReg() &&
4849  MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
4851  isTwoAddrFold = true;
4852  } else {
4853  if (OpNum == 0) {
4854  if (MI.getOpcode() == X86::MOV32r0) {
4855  NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
4856  if (NewMI)
4857  return NewMI;
4858  }
4859  }
4860 
4861  I = lookupFoldTable(MI.getOpcode(), OpNum);
4862  }
4863 
4864  if (I != nullptr) {
4865  unsigned Opcode = I->DstOp;
4866  unsigned MinAlign = (I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
4867  if (Align < MinAlign)
4868  return nullptr;
4869  bool NarrowToMOV32rm = false;
4870  if (Size) {
4872  const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
4873  &RI, MF);
4874  unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4875  if (Size < RCSize) {
4876  // Check if it's safe to fold the load. If the size of the object is
4877  // narrower than the load width, then it's not.
4878  if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4879  return nullptr;
4880  // If this is a 64-bit load, but the spill slot is 32, then we can do
4881  // a 32-bit load which is implicitly zero-extended. This likely is
4882  // due to live interval analysis remat'ing a load from stack slot.
4883  if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
4884  return nullptr;
4885  Opcode = X86::MOV32rm;
4886  NarrowToMOV32rm = true;
4887  }
4888  }
4889 
4890  if (isTwoAddrFold)
4891  NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
4892  else
4893  NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
4894 
4895  if (NarrowToMOV32rm) {
4896  // If this is the special case where we use a MOV32rm to load a 32-bit
4897  // value and zero-extend the top bits. Change the destination register
4898  // to a 32-bit one.
4899  unsigned DstReg = NewMI->getOperand(0).getReg();
4901  NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
4902  else
4903  NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4904  }
4905  return NewMI;
4906  }
4907 
4908  // If the instruction and target operand are commutable, commute the
4909  // instruction and try again.
4910  if (AllowCommute) {
4911  unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
4912  if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
4913  bool HasDef = MI.getDesc().getNumDefs();
4914  unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
4915  unsigned Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
4916  unsigned Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
4917  bool Tied1 =
4918  0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
4919  bool Tied2 =
4920  0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
4921 
4922  // If either of the commutable operands are tied to the destination
4923  // then we can not commute + fold.
4924  if ((HasDef && Reg0 == Reg1 && Tied1) ||
4925  (HasDef && Reg0 == Reg2 && Tied2))
4926  return nullptr;
4927 
4928  MachineInstr *CommutedMI =
4929  commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
4930  if (!CommutedMI) {
4931  // Unable to commute.
4932  return nullptr;
4933  }
4934  if (CommutedMI != &MI) {
4935  // New instruction. We can't fold from this.
4936  CommutedMI->eraseFromParent();
4937  return nullptr;
4938  }
4939 
4940  // Attempt to fold with the commuted version of the instruction.
4941  NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
4942  Size, Align, /*AllowCommute=*/false);
4943  if (NewMI)
4944  return NewMI;
4945 
4946  // Folding failed again - undo the commute before returning.
4947  MachineInstr *UncommutedMI =
4948  commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
4949  if (!UncommutedMI) {
4950  // Unable to commute.
4951  return nullptr;
4952  }
4953  if (UncommutedMI != &MI) {
4954  // New instruction. It doesn't need to be kept.
4955  UncommutedMI->eraseFromParent();
4956  return nullptr;
4957  }
4958 
4959  // Return here to prevent duplicate fuse failure report.
4960  return nullptr;
4961  }
4962  }
4963 
4964  // No fusion
4965  if (PrintFailedFusing && !MI.isCopy())
4966  dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
4967  return nullptr;
4968 }
4969 
4970 MachineInstr *
4972  ArrayRef<unsigned> Ops,
4973  MachineBasicBlock::iterator InsertPt,
4974  int FrameIndex, LiveIntervals *LIS) const {
4975  // Check switch flag
4976  if (NoFusing)
4977  return nullptr;
4978 
4979  // Avoid partial and undef register update stalls unless optimizing for size.
4980  if (!MF.getFunction().optForSize() &&
4981  (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
4983  return nullptr;
4984 
4985  // Don't fold subreg spills, or reloads that use a high subreg.
4986  for (auto Op : Ops) {
4987  MachineOperand &MO = MI.getOperand(Op);
4988  auto SubReg = MO.getSubReg();
4989  if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
4990  return nullptr;
4991  }
4992 
4993  const MachineFrameInfo &MFI = MF.getFrameInfo();
4994  unsigned Size = MFI.getObjectSize(FrameIndex);
4995  unsigned Alignment = MFI.getObjectAlignment(FrameIndex);
4996  // If the function stack isn't realigned we don't want to fold instructions
4997  // that need increased alignment.
4998  if (!RI.needsStackRealignment(MF))
4999  Alignment =
5000  std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
5001  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5002  unsigned NewOpc = 0;
5003  unsigned RCSize = 0;
5004  switch (MI.getOpcode()) {
5005  default: return nullptr;
5006  case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
5007  case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5008  case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5009  case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
5010  }
5011  // Check if it's safe to fold the load. If the size of the object is
5012  // narrower than the load width, then it's not.
5013  if (Size < RCSize)
5014  return nullptr;
5015  // Change to CMPXXri r, 0 first.
5016  MI.setDesc(get(NewOpc));
5017  MI.getOperand(1).ChangeToImmediate(0);
5018  } else if (Ops.size() != 1)
5019  return nullptr;
5020 
5021  return foldMemoryOperandImpl(MF, MI, Ops[0],
5022  MachineOperand::CreateFI(FrameIndex), InsertPt,
5023  Size, Alignment, /*AllowCommute=*/true);
5024 }
5025 
5026 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
5027 /// because the latter uses contents that wouldn't be defined in the folded
5028 /// version. For instance, this transformation isn't legal:
5029 /// movss (%rdi), %xmm0
5030 /// addps %xmm0, %xmm0
5031 /// ->
5032 /// addps (%rdi), %xmm0
5033 ///
5034 /// But this one is:
5035 /// movss (%rdi), %xmm0
5036 /// addss %xmm0, %xmm0
5037 /// ->
5038 /// addss (%rdi), %xmm0
5039 ///
5041  const MachineInstr &UserMI,
5042  const MachineFunction &MF) {
5043  unsigned Opc = LoadMI.getOpcode();
5044  unsigned UserOpc = UserMI.getOpcode();
5046  const TargetRegisterClass *RC =
5047  MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
5048  unsigned RegSize = TRI.getRegSizeInBits(*RC);
5049 
5050  if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm) &&
5051  RegSize > 32) {
5052  // These instructions only load 32 bits, we can't fold them if the
5053  // destination register is wider than 32 bits (4 bytes), and its user
5054  // instruction isn't scalar (SS).
5055  switch (UserOpc) {
5056  case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
5057  case X86::CMPSSrr_Int: case X86::VCMPSSrr_Int: case X86::VCMPSSZrr_Int:
5058  case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
5059  case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
5060  case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
5061  case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
5062  case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
5063  case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
5064  case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
5065  case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
5066  case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
5067  case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
5068  case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
5069  case X86::VFMADDSS4rr_Int: case X86::VFNMADDSS4rr_Int:
5070  case X86::VFMSUBSS4rr_Int: case X86::VFNMSUBSS4rr_Int:
5071  case X86::VFMADD132SSr_Int: case X86::VFNMADD132SSr_Int:
5072  case X86::VFMADD213SSr_Int: case X86::VFNMADD213SSr_Int:
5073  case X86::VFMADD231SSr_Int: case X86::VFNMADD231SSr_Int:
5074  case X86::VFMSUB132SSr_Int: case X86::VFNMSUB132SSr_Int:
5075  case X86::VFMSUB213SSr_Int: case X86::VFNMSUB213SSr_Int:
5076  case X86::VFMSUB231SSr_Int: case X86::VFNMSUB231SSr_Int:
5077  case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
5078  case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
5079  case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
5080  case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
5081  case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
5082  case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
5083  case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
5084  case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
5085  case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
5086  case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
5087  case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
5088  case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
5089  case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
5090  case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
5091  case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
5092  case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
5093  case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
5094  case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
5095  return false;
5096  default:
5097  return true;
5098  }
5099  }
5100 
5101  if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm) &&
5102  RegSize > 64) {
5103  // These instructions only load 64 bits, we can't fold them if the
5104  // destination register is wider than 64 bits (8 bytes), and its user
5105  // instruction isn't scalar (SD).
5106  switch (UserOpc) {
5107  case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
5108  case X86::CMPSDrr_Int: case X86::VCMPSDrr_Int: case X86::VCMPSDZrr_Int:
5109  case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
5110  case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
5111  case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
5112  case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
5113  case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
5114  case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
5115  case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
5116  case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
5117  case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
5118  case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
5119  case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
5120  case X86::VFMADDSD4rr_Int: case X86::VFNMADDSD4rr_Int:
5121  case X86::VFMSUBSD4rr_Int: case X86::VFNMSUBSD4rr_Int:
5122  case X86::VFMADD132SDr_Int: case X86::VFNMADD132SDr_Int:
5123  case X86::VFMADD213SDr_Int: case X86::VFNMADD213SDr_Int:
5124  case X86::VFMADD231SDr_Int: case X86::VFNMADD231SDr_Int:
5125  case X86::VFMSUB132SDr_Int: case X86::VFNMSUB132SDr_Int:
5126  case X86::VFMSUB213SDr_Int: case X86::VFNMSUB213SDr_Int:
5127  case X86::VFMSUB231SDr_Int: case X86::VFNMSUB231SDr_Int:
5128  case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
5129  case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
5130  case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
5131  case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
5132  case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
5133  case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
5134  case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
5135  case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
5136  case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
5137  case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
5138  case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
5139  case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
5140  case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
5141  case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
5142  case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
5143  case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
5144  case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
5145  case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
5146  return false;
5147  default:
5148  return true;
5149  }
5150  }
5151 
5152  return false;
5153 }
5154 
5157  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
5158  LiveIntervals *LIS) const {
5159 
5160  // TODO: Support the case where LoadMI loads a wide register, but MI
5161  // only uses a subreg.
5162  for (auto Op : Ops) {
5163  if (MI.getOperand(Op).getSubReg())
5164  return nullptr;
5165  }
5166 
5167  // If loading from a FrameIndex, fold directly from the FrameIndex.
5168  unsigned NumOps = LoadMI.getDesc().getNumOperands();
5169  int FrameIndex;
5170  if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
5171  if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5172  return nullptr;
5173  return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
5174  }
5175 
5176  // Check switch flag
5177  if (NoFusing) return nullptr;
5178 
5179  // Avoid partial and undef register update stalls unless optimizing for size.
5180  if (!MF.getFunction().optForSize() &&
5181  (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5183  return nullptr;
5184 
5185  // Determine the alignment of the load.
5186  unsigned Alignment = 0;
5187  if (LoadMI.hasOneMemOperand())
5188  Alignment = (*LoadMI.memoperands_begin())->getAlignment();
5189  else
5190  switch (LoadMI.getOpcode()) {
5191  case X86::AVX512_512_SET0:
5192  case X86::AVX512_512_SETALLONES:
5193  Alignment = 64;
5194  break;
5195  case X86::AVX2_SETALLONES:
5196  case X86::AVX1_SETALLONES:
5197  case X86::AVX_SET0:
5198  case X86::AVX512_256_SET0:
5199  Alignment = 32;
5200  break;
5201  case X86::V_SET0:
5202  case X86::V_SETALLONES:
5203  case X86::AVX512_128_SET0:
5204  Alignment = 16;
5205  break;
5206  case X86::MMX_SET0:
5207  case X86::FsFLD0SD:
5208  case X86::AVX512_FsFLD0SD:
5209  Alignment = 8;
5210  break;
5211  case X86::FsFLD0SS:
5212  case X86::AVX512_FsFLD0SS:
5213  Alignment = 4;
5214  break;
5215  default:
5216  return nullptr;
5217  }
5218  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5219  unsigned NewOpc = 0;
5220  switch (MI.getOpcode()) {
5221  default: return nullptr;
5222  case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
5223  case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
5224  case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
5225  case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
5226  }
5227  // Change to CMPXXri r, 0 first.
5228  MI.setDesc(get(NewOpc));
5229  MI.getOperand(1).ChangeToImmediate(0);
5230  } else if (Ops.size() != 1)
5231  return nullptr;
5232 
5233  // Make sure the subregisters match.
5234  // Otherwise we risk changing the size of the load.
5235  if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
5236  return nullptr;
5237 
5239  switch (LoadMI.getOpcode()) {
5240  case X86::MMX_SET0:
5241  case X86::V_SET0:
5242  case X86::V_SETALLONES:
5243  case X86::AVX2_SETALLONES:
5244  case X86::AVX1_SETALLONES:
5245  case X86::AVX_SET0:
5246  case X86::AVX512_128_SET0:
5247  case X86::AVX512_256_SET0:
5248  case X86::AVX512_512_SET0:
5249  case X86::AVX512_512_SETALLONES:
5250  case X86::FsFLD0SD:
5251  case X86::AVX512_FsFLD0SD:
5252  case X86::FsFLD0SS:
5253  case X86::AVX512_FsFLD0SS: {
5254  // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
5255  // Create a constant-pool entry and operands to load from it.
5256 
5257  // Medium and large mode can't fold loads this way.
5258  if (MF.getTarget().getCodeModel() != CodeModel::Small &&
5260  return nullptr;
5261 
5262  // x86-32 PIC requires a PIC base register for constant pools.
5263  unsigned PICBase = 0;
5264  if (MF.getTarget().isPositionIndependent()) {
5265  if (Subtarget.is64Bit())
5266  PICBase = X86::RIP;
5267  else
5268  // FIXME: PICBase = getGlobalBaseReg(&MF);
5269  // This doesn't work for several reasons.
5270  // 1. GlobalBaseReg may have been spilled.
5271  // 2. It may not be live at MI.
5272  return nullptr;
5273  }
5274 
5275  // Create a constant-pool entry.
5276  MachineConstantPool &MCP = *MF.getConstantPool();
5277  Type *Ty;
5278  unsigned Opc = LoadMI.getOpcode();
5279  if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
5281  else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
5283  else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
5285  else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
5286  Opc == X86::AVX512_256_SET0 || Opc == X86::AVX1_SETALLONES)
5288  else if (Opc == X86::MMX_SET0)
5290  else
5292 
5293  bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
5294  Opc == X86::AVX512_512_SETALLONES ||
5295  Opc == X86::AVX1_SETALLONES);
5296  const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
5298  unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
5299 
5300  // Create operands to load from the constant pool entry.
5301  MOs.push_back(MachineOperand::CreateReg(PICBase, false));
5303  MOs.push_back(MachineOperand::CreateReg(0, false));
5304  MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
5305  MOs.push_back(MachineOperand::CreateReg(0, false));
5306  break;
5307  }
5308  default: {
5309  if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5310  return nullptr;
5311 
5312  // Folding a normal load. Just copy the load's address operands.
5313  MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
5314  LoadMI.operands_begin() + NumOps);
5315  break;
5316  }
5317  }
5318  return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
5319  /*Size=*/0, Alignment, /*AllowCommute=*/true);
5320 }
5321