LLVM  10.0.0svn
llvm::AMDGPUTargetLowering Member List

This is the complete list of members for llvm::AMDGPUTargetLowering, including all inherited members.

addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)llvm::TargetLoweringBaseinlineprotected
AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)llvm::TargetLoweringBaseinlineprotected
addRegisterClass(MVT VT, const TargetRegisterClass *RC)llvm::TargetLoweringBaseinlineprotected
addTokenForArgument(SDValue Chain, SelectionDAG &DAG, MachineFrameInfo &MFI, int ClobberedFI) constllvm::AMDGPUTargetLowering
AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) constllvm::TargetLoweringvirtual
aggressivelyPreferBuildVectorSources(EVT VecVT) const overridellvm::AMDGPUTargetLoweringvirtual
alignLoopsWithOptSize() constllvm::TargetLoweringBaseinlinevirtual
allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) constllvm::TargetLoweringBase
allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, bool *Fast=nullptr) constllvm::TargetLoweringBase
allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *=nullptr) constllvm::TargetLoweringBaseinlinevirtual
allowsMisalignedMemoryAccesses(LLT, unsigned AddrSpace=0, unsigned Align=1, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *=nullptr) constllvm::TargetLoweringBaseinlinevirtual
allowTruncateForTailCall(Type *FromTy, Type *ToTy) constllvm::TargetLoweringBaseinlinevirtual
allUsesHaveSourceMods(const SDNode *N, unsigned CostThreshold=4)llvm::AMDGPUTargetLoweringstatic
AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI)llvm::AMDGPUTargetLowering
analyzeFormalArgumentsCompute(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) constllvm::AMDGPUTargetLoweringprotected
areJTsAllowed(const Function *Fn) constllvm::TargetLoweringBaseinlinevirtual
ArgListTy typedefllvm::TargetLoweringBase
AsmOperandInfoVector typedefllvm::TargetLowering
AtomicExpansionKind enum namellvm::TargetLoweringBase
BooleanContent enum namellvm::TargetLoweringBase
buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0, SDValue N1, MutableArrayRef< int > Mask, SelectionDAG &DAG) constllvm::TargetLowering
BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl< SDNode *> &Created) constllvm::TargetLowering
BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode *> &Created) constllvm::TargetLoweringvirtual
BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl< SDNode *> &Created) constllvm::TargetLowering
C_Immediate enum valuellvm::TargetLowering
C_Memory enum valuellvm::TargetLowering
C_Other enum valuellvm::TargetLowering
C_Register enum valuellvm::TargetLowering
C_RegisterClass enum valuellvm::TargetLowering
C_Unknown enum valuellvm::TargetLowering
canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) constllvm::TargetLoweringBaseinlinevirtual
CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) constllvm::TargetLoweringinlinevirtual
canMergeStoresTo(unsigned AS, EVT MemVT, const SelectionDAG &DAG) constllvm::TargetLoweringBaseinlinevirtual
canOpTrap(unsigned Op, EVT VT) constllvm::TargetLoweringBasevirtual
CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg)llvm::AMDGPUTargetLoweringstatic
CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg)llvm::AMDGPUTargetLoweringstatic
combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLowering
combineRepeatedFPDivisors() constllvm::TargetLoweringinlinevirtual
ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) constllvm::TargetLoweringvirtual
computeKnownBitsForFrameIndex(const SDValue FIOp, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) constllvm::TargetLoweringvirtual
computeKnownBitsForTargetInstr(Register R, KnownBits &Known, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) constllvm::TargetLoweringvirtual
computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const overridellvm::AMDGPUTargetLoweringvirtual
ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const overridellvm::AMDGPUTargetLoweringvirtual
computeRegisterProperties(const TargetRegisterInfo *TRI)llvm::TargetLoweringBaseprotected
ConstraintType enum namellvm::TargetLowering
ConstraintWeight enum namellvm::TargetLowering
convertSelectOfConstantsToMath(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
convertSetCCLogicToBitwiseLogic(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
createFastISel(FunctionLoweringInfo &, const TargetLibraryInfo *) constllvm::TargetLoweringinlinevirtual
CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT, const SDLoc &SL, bool RawReg=false) constllvm::AMDGPUTargetLowering
CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) constllvm::AMDGPUTargetLoweringinline
CreateLiveInRegisterRaw(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) constllvm::AMDGPUTargetLoweringinline
Custom enum valuellvm::TargetLoweringBase
CW_Best enum valuellvm::TargetLowering
CW_Better enum valuellvm::TargetLowering
CW_Constant enum valuellvm::TargetLowering
CW_Default enum valuellvm::TargetLowering
CW_Good enum valuellvm::TargetLowering
CW_Invalid enum valuellvm::TargetLowering
CW_Memory enum valuellvm::TargetLowering
CW_Okay enum valuellvm::TargetLowering
CW_Register enum valuellvm::TargetLowering
CW_SpecificReg enum valuellvm::TargetLowering
decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) constllvm::TargetLoweringBaseinlinevirtual
Disabled enum valuellvm::TargetLoweringBase
emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) constllvm::TargetLoweringBaseinlinevirtual
EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) constllvm::TargetLoweringvirtual
emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) constllvm::TargetLoweringBaseinlinevirtual
emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) constllvm::TargetLoweringBaseinlinevirtual
emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) constllvm::TargetLoweringBaseinlinevirtual
emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) constllvm::TargetLoweringBaseinlinevirtual
emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) constllvm::TargetLoweringBaseprotected
emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) constllvm::TargetLoweringinlinevirtual
emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) constllvm::TargetLoweringBaseinlinevirtual
emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) constllvm::TargetLoweringBaseinlinevirtual
emitXRayCustomEvent(MachineInstr &MI, MachineBasicBlock *MBB) constllvm::TargetLoweringBaseprotected
emitXRayTypedEvent(MachineInstr &MI, MachineBasicBlock *MBB) constllvm::TargetLoweringBaseprotected
enableAggressiveFMAFusion(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
Enabled enum valuellvm::TargetLoweringBase
EnableExtLdPromotionllvm::TargetLoweringBaseprotected
enableExtLdPromotion() constllvm::TargetLoweringBaseinline
Expand enum valuellvm::TargetLoweringBase
expandABS(SDNode *N, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandAddSubSat(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandCTLZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandCTPOP(SDNode *N, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandCTTZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandFP_TO_UINT(SDNode *N, SDValue &Result, SDValue &Chain, SelectionDAG &DAG) constllvm::TargetLowering
expandFunnelShift(SDNode *N, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) constllvm::TargetLoweringinlinevirtual
ExpandInlineAsm(CallInst *) constllvm::TargetLoweringinlinevirtual
expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) constllvm::TargetLowering
expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS, SDValue RHS, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) constllvm::TargetLowering
expandMULO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) constllvm::TargetLowering
expandROT(SDNode *N, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandSADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) constllvm::TargetLowering
expandUADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) constllvm::TargetLowering
expandUINT_TO_FP(SDNode *N, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) constllvm::TargetLowering
expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) constllvm::TargetLowering
expandVecReduce(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
finalizeLowering(MachineFunction &MF) constllvm::TargetLoweringBasevirtual
findOptimalMemOpLowering(std::vector< EVT > &MemOps, unsigned Limit, uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, bool AllowOverlap, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes) constllvm::TargetLowering
findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) constllvm::TargetLoweringBaseprotectedvirtual
FIRST_IMPLICIT enum valuellvm::AMDGPUTargetLowering
functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) constllvm::TargetLoweringinlinevirtual
GatherAllAliasesMaxDepthllvm::TargetLoweringBaseprotected
getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) constllvm::TargetLoweringBaseinlinevirtual
getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value *> &, Type *&) constllvm::TargetLoweringBaseinlinevirtual
getBooleanContents(bool isVec, bool isFloat) constllvm::TargetLoweringBaseinline
getBooleanContents(EVT Type) constllvm::TargetLoweringBaseinline
getBypassSlowDivWidths() constllvm::TargetLoweringBaseinline
getByValTypeAlignment(Type *Ty, const DataLayout &DL) constllvm::TargetLoweringBasevirtual
getClearCacheBuiltinName() constllvm::TargetLoweringinlinevirtual
getCmpLibcallCC(RTLIB::Libcall Call) constllvm::TargetLoweringBaseinline
getCmpLibcallReturnType() constllvm::TargetLoweringBasevirtual
getCondCodeAction(ISD::CondCode CC, MVT VT) constllvm::TargetLoweringBaseinline
getConstraintType(StringRef Constraint) constllvm::TargetLoweringvirtual
getDefaultSafeStackPointerLocation(IRBuilder<> &IRB, bool UseTLS) constllvm::TargetLoweringBaseprotected
getDivRefinementSteps(EVT VT, MachineFunction &MF) constllvm::TargetLoweringBase
getEquivalentMemType(LLVMContext &Context, EVT VT)llvm::AMDGPUTargetLoweringprotectedstatic
getExceptionPointerRegister(const Constant *PersonalityFn) constllvm::TargetLoweringBaseinlinevirtual
getExceptionSelectorRegister(const Constant *PersonalityFn) constllvm::TargetLoweringBaseinlinevirtual
getExtendForAtomicOps() constllvm::TargetLoweringBaseinlinevirtual
getExtendForContent(BooleanContent Content)llvm::TargetLoweringBaseinlinestatic
getFenceOperandTy(const DataLayout &DL) const overridellvm::AMDGPUTargetLoweringinlinevirtual
getFixedPointOperationAction(unsigned Op, EVT VT, unsigned Scale) constllvm::TargetLoweringBaseinline
getFrameIndexTy(const DataLayout &DL) constllvm::TargetLoweringBaseinline
getGatherAllAliasesMaxDepth() constllvm::TargetLoweringBaseinline
getHiHalf64(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
getImplicitParameterOffset(const MachineFunction &MF, const ImplicitParameter Param) constllvm::AMDGPUTargetLowering
getIndexedLoadAction(unsigned IdxMode, MVT VT) constllvm::TargetLoweringBaseinline
getIndexedStoreAction(unsigned IdxMode, MVT VT) constllvm::TargetLoweringBaseinline
getInlineAsmMemConstraint(StringRef ConstraintCode) constllvm::TargetLoweringinlinevirtual
getIRStackGuard(IRBuilder<> &IRB) constllvm::TargetLoweringBasevirtual
getJumpTableEncoding() constllvm::TargetLoweringvirtual
getLibcallCallingConv(RTLIB::Libcall Call) constllvm::TargetLoweringBaseinline
getLibcallName(RTLIB::Libcall Call) constllvm::TargetLoweringBaseinline
getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
getLoHalf64(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
getMaxAtomicSizeInBitsSupported() constllvm::TargetLoweringBaseinline
getMaxExpandSizeMemcmp(bool OptSize) constllvm::TargetLoweringBaseinline
getMaxGluedStoresPerMemcpy() constllvm::TargetLoweringBaseinlinevirtual
getMaximumJumpTableSize() constllvm::TargetLoweringBase
getMaxStoresPerMemcpy(bool OptSize) constllvm::TargetLoweringBaseinline
getMaxStoresPerMemmove(bool OptSize) constllvm::TargetLoweringBaseinline
getMaxStoresPerMemset(bool OptSize) constllvm::TargetLoweringBaseinline
getMaxSupportedInterleaveFactor() constllvm::TargetLoweringBaseinlinevirtual
getMemValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) constllvm::TargetLoweringBaseinline
getMinCmpXchgSizeInBits() constllvm::TargetLoweringBaseinline
getMinFunctionAlignment() constllvm::TargetLoweringBaseinline
getMinimumJumpTableDensity(bool OptForSize) constllvm::TargetLoweringBase
getMinimumJumpTableEntries() constllvm::TargetLoweringBasevirtual
getMinStackArgumentAlignment() constllvm::TargetLoweringBaseinline
getMMOFlags(const Instruction &I) constllvm::TargetLoweringinlinevirtual
getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) constllvm::TargetLoweringvirtual
getNumRegisters(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinline
getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) constllvm::TargetLoweringBaseinlinevirtual
getOperationAction(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
getOptimalMemOpLLT(uint64_t, unsigned, unsigned, bool, bool, bool, const AttributeList &) constllvm::TargetLoweringBaseinlinevirtual
getOptimalMemOpType(uint64_t, unsigned, unsigned, bool, bool, bool, const AttributeList &) constllvm::TargetLoweringBaseinlinevirtual
getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) constllvm::TargetLoweringvirtual
getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) constllvm::TargetLoweringvirtual
getPointerMemTy(const DataLayout &DL, uint32_t AS=0) constllvm::TargetLoweringBaseinline
getPointerTy(const DataLayout &DL, uint32_t AS=0) constllvm::TargetLoweringBaseinlinevirtual
getPostIndexedAddressParts(SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) constllvm::TargetLoweringinlinevirtual
getPredictableBranchThreshold() constllvm::TargetLoweringBasevirtual
getPreferredVectorAction(MVT VT) constllvm::TargetLoweringBaseinlinevirtual
getPrefFunctionAlignment() constllvm::TargetLoweringBaseinline
getPrefLoopAlignment(MachineLoop *ML=nullptr) constllvm::TargetLoweringBaseinlinevirtual
getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) constllvm::TargetLoweringinlinevirtual
getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const overridellvm::AMDGPUTargetLoweringvirtual
getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) constllvm::TargetLoweringBase
getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) constllvm::TargetLoweringBase
getRegClassFor(MVT VT, bool isDivergent=false) constllvm::TargetLoweringBaseinlinevirtual
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) constllvm::TargetLoweringvirtual
getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) constllvm::TargetLoweringinlinevirtual
getRegisterType(MVT VT) constllvm::TargetLoweringBaseinline
getRegisterType(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinline
getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) constllvm::TargetLoweringBaseinlinevirtual
getRepRegClassCostFor(MVT VT) constllvm::TargetLoweringBaseinlinevirtual
getRepRegClassFor(MVT VT) constllvm::TargetLoweringBaseinlinevirtual
getSafeStackPointerLocation(IRBuilder<> &IRB) constllvm::TargetLoweringBasevirtual
getScalarShiftAmountTy(const DataLayout &, EVT) constllvm::TargetLoweringBasevirtual
getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS=0) constllvm::TargetLoweringBaseinlinevirtual
getSchedulingPreference() constllvm::TargetLoweringBaseinline
getSchedulingPreference(SDNode *) constllvm::TargetLoweringBaseinlinevirtual
getScratchRegisters(CallingConv::ID CC) constllvm::TargetLoweringinlinevirtual
getSDagStackGuard(const Module &M) constllvm::TargetLoweringBasevirtual
getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) constllvm::TargetLoweringBasevirtual
getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) constllvm::TargetLoweringBase
getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) constllvm::TargetLoweringBaseinline
getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) constllvm::TargetLoweringvirtual
getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const overridellvm::AMDGPUTargetLoweringvirtual
getSqrtRefinementSteps(EVT VT, MachineFunction &MF) constllvm::TargetLoweringBase
getSSPStackGuardCheck(const Module &M) constllvm::TargetLoweringBasevirtual
getStackPointerRegisterToSaveRestore() constllvm::TargetLoweringBaseinline
getStackProbeSymbolName(MachineFunction &MF) constllvm::TargetLoweringBaseinlinevirtual
getStrictFPOperationAction(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
getTargetConstantFromLoad(LoadSDNode *LD) constllvm::TargetLoweringvirtual
getTargetMachine() constllvm::TargetLoweringBaseinline
getTargetNodeName(unsigned Opcode) const overridellvm::AMDGPUTargetLoweringvirtual
getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) constllvm::TargetLoweringBaseinlinevirtual
getTruncStoreAction(EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
getTypeAction(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinline
getTypeAction(MVT VT) constllvm::TargetLoweringBaseinline
getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) constllvm::TargetLoweringinlinevirtual
getTypeLegalizationCost(const DataLayout &DL, Type *Ty) constllvm::TargetLoweringBase
getTypeToExpandTo(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinline
getTypeToPromoteTo(unsigned Op, MVT VT) constllvm::TargetLoweringBaseinline
getTypeToTransformTo(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinline
getVaListSizeInBits(const DataLayout &DL) constllvm::TargetLoweringBaseinlinevirtual
getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) constllvm::TargetLoweringBaseinline
getValueTypeActions() constllvm::TargetLoweringBaseinline
getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, SDValue Index) constllvm::TargetLowering
getVectorIdxTy(const DataLayout &) const overridellvm::AMDGPUTargetLoweringvirtual
getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) constllvm::TargetLoweringBase
getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) constllvm::TargetLoweringBaseinlinevirtual
GRID_DIM enum valuellvm::AMDGPUTargetLowering
GRID_OFFSET enum valuellvm::AMDGPUTargetLowering
HandleByVal(CCState *, unsigned &, unsigned) constllvm::TargetLoweringinlinevirtual
hasAndNot(SDValue X) constllvm::TargetLoweringBaseinlinevirtual
hasAndNotCompare(SDValue Y) constllvm::TargetLoweringBaseinlinevirtual
hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) constllvm::TargetLoweringBaseinline
hasBitPreservingFPLogic(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
hasBitTest(SDValue X, SDValue Y) constllvm::TargetLoweringBaseinlinevirtual
hasDefinedInitializer(const GlobalValue *GV)llvm::AMDGPUTargetLoweringstatic
hasExtractBitsInsn() constllvm::TargetLoweringBaseinline
hasFastEqualityCompare(unsigned NumBits) constllvm::TargetLoweringBaseinlinevirtual
hasMultipleConditionRegisters() constllvm::TargetLoweringBaseinline
hasPairedLoad(EVT, unsigned &) constllvm::TargetLoweringBaseinlinevirtual
hasStandaloneRem(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
hasTargetDAGCombine(ISD::NodeType NT) constllvm::TargetLoweringBaseinline
hasVectorBlend() constllvm::TargetLoweringBaseinlinevirtual
ImplicitParameter enum namellvm::AMDGPUTargetLowering
IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL, EVT DataVT, SelectionDAG &DAG, bool IsCompressedMemory) constllvm::TargetLowering
initActions()llvm::TargetLoweringBaseprotected
initializeSplitCSR(MachineBasicBlock *Entry) constllvm::TargetLoweringinlinevirtual
insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock *> &Exits) constllvm::TargetLoweringinlinevirtual
insertSSPDeclarations(Module &M) constllvm::TargetLoweringBasevirtual
InstructionOpcodeToISD(unsigned Opcode) constllvm::TargetLoweringBase
isBinOp(unsigned Opcode) constllvm::TargetLoweringBaseinlinevirtual
isCheapToSpeculateCtlz() const overridellvm::AMDGPUTargetLoweringvirtual
isCheapToSpeculateCttz() const overridellvm::AMDGPUTargetLoweringvirtual
isCommutativeBinOp(unsigned Opcode) constllvm::TargetLoweringBaseinlinevirtual
isCondCodeLegal(ISD::CondCode CC, MVT VT) constllvm::TargetLoweringBaseinline
isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) constllvm::TargetLoweringBaseinline
isConstantCostlierToNegate(SDValue N) constllvm::AMDGPUTargetLoweringprotected
isConstFalseVal(const SDNode *N) constllvm::TargetLowering
isConstTrueVal(const SDNode *N) constllvm::TargetLowering
isCtlzFast() constllvm::TargetLoweringBaseinlinevirtual
isDesirableToCombineBuildVectorToShuffleTruncate(ArrayRef< int > ShuffleMask, EVT SrcVT, EVT TruncVT) constllvm::TargetLoweringinlinevirtual
isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) constllvm::TargetLoweringinlinevirtual
IsDesirableToPromoteOp(SDValue, EVT &) constllvm::TargetLoweringinlinevirtual
isDesirableToTransformToIntegerOp(unsigned, EVT) constllvm::TargetLoweringinlinevirtual
isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) constllvm::TargetLowering
isExtFree(const Instruction *I) constllvm::TargetLoweringBaseinline
isExtFreeImpl(const Instruction *I) constllvm::TargetLoweringBaseinlineprotectedvirtual
isExtLoad(const LoadInst *Load, const Instruction *Ext, const DataLayout &DL) constllvm::TargetLoweringBaseinline
isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) constllvm::TargetLoweringBaseinlinevirtual
isExtractVecEltCheap(EVT VT, unsigned Index) constllvm::TargetLoweringBaseinlinevirtual
isFAbsFree(EVT VT) const overridellvm::AMDGPUTargetLoweringvirtual
isFMAFasterThanFMulAndFAdd(EVT) constllvm::TargetLoweringBaseinlinevirtual
isFNegFree(EVT VT) const overridellvm::AMDGPUTargetLoweringvirtual
isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) constllvm::TargetLoweringBaseinlinevirtual
isFPExtFree(EVT DestVT, EVT SrcVT) constllvm::TargetLoweringBaseinlinevirtual
isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const overridellvm::AMDGPUTargetLoweringvirtual
isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) constllvm::TargetLoweringBaseinlinevirtual
isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const overridellvm::AMDGPUTargetLoweringinlinevirtual
isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) constllvm::TargetLoweringvirtual
isIndexedLoadLegal(unsigned IdxMode, EVT VT) constllvm::TargetLoweringBaseinline
isIndexedStoreLegal(unsigned IdxMode, EVT VT) constllvm::TargetLoweringBaseinline
isIndexingLegal(MachineInstr &MI, Register Base, Register Offset, bool IsPre, MachineRegisterInfo &MRI) constllvm::TargetLoweringinlinevirtual
isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, SDValue &Chain) constllvm::TargetLowering
isIntDivCheap(EVT VT, AttributeList Attr) constllvm::TargetLoweringBaseinlinevirtual
isJumpExpensive() constllvm::TargetLoweringBaseinline
isJumpTableRelative() constllvm::TargetLoweringBaseinlinevirtual
isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const overridellvm::AMDGPUTargetLoweringvirtual
isLegalAddImmediate(int64_t) constllvm::TargetLoweringBaseinlinevirtual
isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) constllvm::TargetLoweringBasevirtual
isLegalICmpImmediate(int64_t) constllvm::TargetLoweringBaseinlinevirtual
isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) constllvm::TargetLoweringBaseprotected
isLegalStoreImmediate(int64_t Value) constllvm::TargetLoweringBaseinlinevirtual
isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const finalllvm::AMDGPUTargetLoweringvirtual
isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) constllvm::TargetLoweringBaseinlinevirtual
isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) constllvm::TargetLoweringBaseinlinevirtual
isNarrowingProfitable(EVT VT1, EVT VT2) const overridellvm::AMDGPUTargetLoweringvirtual
isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) constllvm::TargetLoweringBaseinlinevirtual
isOffsetFoldingLegal(const GlobalAddressSDNode *GA) constllvm::TargetLoweringvirtual
isOperationCustom(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
isOperationExpand(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
isOperationLegal(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
isOperationLegalOrCustom(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
isOperationLegalOrPromote(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
isPositionIndependent() constllvm::TargetLowering
isPredictableSelectExpensive() constllvm::TargetLoweringBaseinline
isProfitableToCombineMinNumMaxNum(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
isProfitableToHoist(Instruction *I) constllvm::TargetLoweringBaseinlinevirtual
isSafeMemOpType(MVT) constllvm::TargetLoweringBaseinlinevirtual
isSDNodeAlwaysUniform(const SDNode *N) const overridellvm::AMDGPUTargetLoweringvirtual
isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) constllvm::TargetLoweringinlinevirtual
isSelectSupported(SelectSupportKind) const overridellvm::AMDGPUTargetLoweringvirtual
isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) constllvm::TargetLoweringBaseinlinevirtual
isShuffleMaskLegal(ArrayRef< int >, EVT) constllvm::TargetLoweringBaseinlinevirtual
isSlowDivBypassed() constllvm::TargetLoweringBaseinline
isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) constllvm::TargetLoweringBaseinlinevirtual
isSuitableForBitTests(unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) constllvm::TargetLoweringBaseinline
isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range) constllvm::TargetLoweringBaseinlinevirtual
isSupportedFixedPointOperation(unsigned Op, EVT VT, unsigned Scale) constllvm::TargetLoweringBaseinlinevirtual
isTruncateFree(EVT Src, EVT Dest) const overridellvm::AMDGPUTargetLoweringvirtual
isTruncateFree(Type *Src, Type *Dest) const overridellvm::AMDGPUTargetLoweringvirtual
isTruncStoreLegal(EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
isTypeDesirableForOp(unsigned, EVT VT) constllvm::TargetLoweringinlinevirtual
isTypeLegal(EVT VT) constllvm::TargetLoweringBaseinline
isUsedByReturnOnly(SDNode *, SDValue &) constllvm::TargetLoweringinlinevirtual
isVectorClearMaskLegal(ArrayRef< int >, EVT) constllvm::TargetLoweringBaseinlinevirtual
isVectorLoadExtDesirable(SDValue ExtVal) constllvm::TargetLoweringBaseinlinevirtual
isVectorShiftByScalarCheap(Type *Ty) constllvm::TargetLoweringBaseinlinevirtual
isZExtFree(Type *Src, Type *Dest) const overridellvm::AMDGPUTargetLoweringvirtual
isZExtFree(EVT Src, EVT Dest) const overridellvm::AMDGPUTargetLoweringvirtual
isZExtFree(SDValue Val, EVT VT2) const overridellvm::AMDGPUTargetLoweringvirtual
Legal enum valuellvm::TargetLoweringBase
LegalizeAction enum namellvm::TargetLoweringBase
LegalizeKind typedefllvm::TargetLoweringBase
LegalizeTypeAction enum namellvm::TargetLoweringBase
LibCall enum valuellvm::TargetLoweringBase
loadInputValue(SelectionDAG &DAG, const TargetRegisterClass *RC, EVT VT, const SDLoc &SL, const ArgDescriptor &Arg) constllvm::AMDGPUTargetLowering
loadStackInputValue(SelectionDAG &DAG, EVT VT, const SDLoc &SL, int64_t Offset) constllvm::AMDGPUTargetLowering
LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) constllvm::TargetLoweringvirtual
LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag, SDLoc DL, const AsmOperandInfo &OpInfo, SelectionDAG &DAG) constllvm::TargetLoweringvirtual
lowerAtomicLoadAsLoadSDNode(const LoadInst &LI) constllvm::TargetLoweringinlinevirtual
lowerAtomicStoreAsStoreSDNode(const StoreInst &SI) constllvm::TargetLoweringinlinevirtual
LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const overridellvm::AMDGPUTargetLoweringvirtual
LowerCallTo(CallLoweringInfo &CLI) constllvm::TargetLowering
lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) constllvm::TargetLowering
LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) constllvm::TargetLoweringinlinevirtual
LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) constllvm::AMDGPUTargetLoweringprotected
LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLowering
LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFCEIL(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
lowerFEXP(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFFLOOR(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFLOG(SDValue Op, SelectionDAG &DAG, double Log2BaseInverted) constllvm::AMDGPUTargetLoweringprotected
LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFormalArguments(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::InputArg > &, const SDLoc &, SelectionDAG &, SmallVectorImpl< SDValue > &) constllvm::TargetLoweringinlinevirtual
LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) constllvm::AMDGPUTargetLoweringprotected
LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFREM(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFRINT(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFROUND(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFROUND32_16(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFROUND64(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFTRUNC(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotectedvirtual
lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) constllvm::TargetLoweringBaseinlinevirtual
LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) constllvm::AMDGPUTargetLoweringprotected
LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) constllvm::AMDGPUTargetLoweringprotected
lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst *> Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) constllvm::TargetLoweringBaseinlinevirtual
lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) constllvm::TargetLoweringBaseinlinevirtual
LowerOperation(SDValue Op, SelectionDAG &DAG) const overridellvm::AMDGPUTargetLoweringvirtual
LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) constllvm::TargetLoweringvirtual
LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const overridellvm::AMDGPUTargetLoweringvirtual
LowerSDIVREM(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerSTORE(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) constllvm::TargetLoweringvirtual
LowerUDIVREM(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results) constllvm::AMDGPUTargetLoweringprotected
LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
lowerUnhandledCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals, StringRef Reason) constllvm::AMDGPUTargetLowering
LowerXConstraint(EVT ConstraintVT) constllvm::TargetLoweringvirtual
makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, MakeLibCallOptions CallOptions, const SDLoc &dl) constllvm::TargetLowering
markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) constllvm::TargetLoweringBaseinlinevirtual
MaxGluedStoresPerMemcpyllvm::TargetLoweringBaseprotected
MaxLoadsPerMemcmpllvm::TargetLoweringBaseprotected
MaxLoadsPerMemcmpOptSizellvm::TargetLoweringBaseprotected
MaxStoresPerMemcpyllvm::TargetLoweringBaseprotected
MaxStoresPerMemcpyOptSizellvm::TargetLoweringBaseprotected
MaxStoresPerMemmovellvm::TargetLoweringBaseprotected
MaxStoresPerMemmoveOptSizellvm::TargetLoweringBaseprotected
MaxStoresPerMemsetllvm::TargetLoweringBaseprotected
MaxStoresPerMemsetOptSizellvm::TargetLoweringBaseprotected
mayBeEmittedAsTailCall(const CallInst *) constllvm::TargetLoweringinlinevirtual
mayIgnoreSignedZero(SDValue Op) constllvm::AMDGPUTargetLoweringinline
mergeStoresAfterLegalization(EVT) const overridellvm::AMDGPUTargetLoweringinlinevirtual
MulExpansionKind enum namellvm::TargetLoweringBase
needsFixedCatchObjects() constllvm::TargetLoweringBaseinlinevirtual
numBitsSigned(SDValue Op, SelectionDAG &DAG)llvm::AMDGPUTargetLoweringstatic
numBitsUnsigned(SDValue Op, SelectionDAG &DAG)llvm::AMDGPUTargetLoweringstatic
operator=(const TargetLowering &)=deletellvm::TargetLowering
llvm::TargetLoweringBase::operator=(const TargetLoweringBase &)=deletellvm::TargetLoweringBase
parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) constllvm::TargetLowering
ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, ImmutableCallSite CS) constllvm::TargetLoweringvirtual
performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS, SDValue RHS, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const overridellvm::AMDGPUTargetLoweringvirtual
performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performIntrinsicWOChainCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performMulCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performShlCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performSraCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const =0llvm::AMDGPUTargetLoweringpure virtual
PredictableSelectIsExpensivellvm::TargetLoweringBaseprotected
preferIncOfAddToSubOfNot(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) constllvm::TargetLoweringinlinevirtual
Promote enum valuellvm::TargetLoweringBase
rangeFitsInWord(const APInt &Low, const APInt &High, const DataLayout &DL) constllvm::TargetLoweringBaseinline
ReciprocalEstimate enum namellvm::TargetLoweringBase
reduceSelectOfFPConstantLoads(EVT CmpOpVT) constllvm::TargetLoweringBaseinlinevirtual
ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const overridellvm::AMDGPUTargetLoweringvirtual
requiresUniformRegister(MachineFunction &MF, const Value *) constllvm::TargetLoweringBaseinlinevirtual
ScalarCondVectorVal enum valuellvm::TargetLoweringBase
scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) constllvm::TargetLowering
scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) constllvm::TargetLowering
ScalarValSelect enum valuellvm::TargetLoweringBase
SelectFlatOffset(bool IsSigned, SelectionDAG &DAG, SDNode *N, SDValue Addr, SDValue &VAddr, SDValue &Offset, SDValue &SLC) constllvm::AMDGPUTargetLowering
SelectSupportKind enum namellvm::TargetLoweringBase
setBooleanContents(BooleanContent Ty)llvm::TargetLoweringBaseinlineprotected
setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy)llvm::TargetLoweringBaseinlineprotected
setBooleanVectorContents(BooleanContent Ty)llvm::TargetLoweringBaseinlineprotected
setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)llvm::TargetLoweringBaseinline
setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setHasExtractBitsInsn(bool hasExtractInsn=true)llvm::TargetLoweringBaseinlineprotected
setHasMultipleConditionRegisters(bool hasManyRegs=true)llvm::TargetLoweringBaseinlineprotected
setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setJumpIsExpensive(bool isExpensive=true)llvm::TargetLoweringBaseprotected
setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)llvm::TargetLoweringBaseinline
setLibcallName(RTLIB::Libcall Call, const char *Name)llvm::TargetLoweringBaseinline
setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)llvm::TargetLoweringBaseinlineprotected
setMaximumJumpTableSize(unsigned)llvm::TargetLoweringBaseprotected
setMinCmpXchgSizeInBits(unsigned SizeInBits)llvm::TargetLoweringBaseinlineprotected
setMinFunctionAlignment(llvm::Align Align)llvm::TargetLoweringBaseinlineprotected
setMinimumJumpTableEntries(unsigned Val)llvm::TargetLoweringBaseprotected
setMinStackArgumentAlignment(llvm::Align Align)llvm::TargetLoweringBaseinlineprotected
setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)llvm::TargetLoweringBaseinlineprotected
setPrefFunctionAlignment(llvm::Align Align)llvm::TargetLoweringBaseinlineprotected
setPrefLoopAlignment(llvm::Align Align)llvm::TargetLoweringBaseinlineprotected
setSchedulingPreference(Sched::Preference Pref)llvm::TargetLoweringBaseinlineprotected
setStackPointerRegisterToSaveRestore(unsigned R)llvm::TargetLoweringBaseinlineprotected
setSupportsUnalignedAtomics(bool UnalignedSupported)llvm::TargetLoweringBaseinlineprotected
setTargetDAGCombine(ISD::NodeType NT)llvm::TargetLoweringBaseinlineprotected
setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setUseUnderscoreLongJmp(bool Val)llvm::TargetLoweringBaseinlineprotected
setUseUnderscoreSetJmp(bool Val)llvm::TargetLoweringBaseinlineprotected
shouldAlignPointerArgs(CallInst *, unsigned &, unsigned &) constllvm::TargetLoweringBaseinlinevirtual
shouldCombineMemoryType(EVT VT) constllvm::AMDGPUTargetLoweringprotected
shouldConsiderGEPOffsetSplit() constllvm::TargetLoweringBaseinlinevirtual
shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) constllvm::TargetLoweringBaseinlinevirtual
shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) constllvm::TargetLoweringBaseinlinevirtual
shouldExpandAtomicLoadInIR(LoadInst *LI) constllvm::TargetLoweringBaseinlinevirtual
shouldExpandAtomicRMWInIR(AtomicRMWInst *) const overridellvm::AMDGPUTargetLoweringvirtual
shouldExpandAtomicStoreInIR(StoreInst *SI) constllvm::TargetLoweringBaseinlinevirtual
shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) constllvm::TargetLoweringBaseinlinevirtual
shouldExpandShift(SelectionDAG &DAG, SDNode *N) constllvm::TargetLoweringBaseinlinevirtual
shouldExtendTypeInLibCall(EVT Type) constllvm::TargetLoweringBaseinlinevirtual
shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) constllvm::TargetLoweringBaseinlinevirtual
shouldFoldMaskToVariableShiftPair(SDValue X) constllvm::TargetLoweringBaseinlinevirtual
shouldFormOverflowOp(unsigned Opcode, EVT VT) constllvm::TargetLoweringBaseinlinevirtual
shouldInsertFencesForAtomic(const Instruction *I) constllvm::TargetLoweringBaseinlinevirtual
shouldNormalizeToSelectSequence(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinlinevirtual
shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) constllvm::TargetLoweringBaseinlinevirtual
shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT) const overridellvm::AMDGPUTargetLoweringvirtual
shouldScalarizeBinop(SDValue VecOp) constllvm::TargetLoweringBaseinlinevirtual
ShouldShrinkFPConstant(EVT VT) const overridellvm::AMDGPUTargetLoweringvirtual
shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) constllvm::TargetLoweringBaseinlinevirtual
shouldSinkOperands(Instruction *I, SmallVectorImpl< Use *> &Ops) constllvm::TargetLoweringBaseinlinevirtual
shouldSplatInsEltVarIndex(EVT) constllvm::TargetLoweringBaseinlinevirtual
shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) constllvm::TargetLoweringinlinevirtual
shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) constllvm::TargetLoweringBaseinlinevirtual
shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, bool IsSigned) constllvm::TargetLoweringBaseinlinevirtual
ShrinkDemandedConstant(SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) constllvm::TargetLowering
ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, TargetLoweringOpt &TLO) constllvm::TargetLowering
SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) constllvm::TargetLowering
SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) constllvm::TargetLowering
SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, DAGCombinerInfo &DCI) constllvm::TargetLowering
SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0) constllvm::TargetLoweringvirtual
SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) constllvm::TargetLowering
SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, DAGCombinerInfo &DCI) constllvm::TargetLowering
SimplifyDemandedVectorEltsForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0) constllvm::TargetLoweringvirtual
SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) constllvm::TargetLowering
SimplifyMultipleUseDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) constllvm::TargetLoweringvirtual
SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, const SDLoc &dl) constllvm::TargetLowering
softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL, const SDValue OldLHS, const SDValue OldRHS) constllvm::TargetLowering
split64BitValue(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL, unsigned Opc, SDValue LHS, uint32_t ValLo, uint32_t ValHi) constllvm::AMDGPUTargetLoweringprotected
splitVector(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HighVT, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
SplitVectorLoad(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
SplitVectorStore(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AS) const overridellvm::AMDGPUTargetLoweringvirtual
storeStackInputValue(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, SDValue ArgVal, int64_t Offset) constllvm::AMDGPUTargetLowering
stripBitcast(SDValue Val)llvm::AMDGPUTargetLoweringinlinestatic
supportSplitCSR(MachineFunction *MF) constllvm::TargetLoweringinlinevirtual
supportsUnalignedAtomics() constllvm::TargetLoweringBaseinline
supportSwiftError() constllvm::TargetLoweringinlinevirtual
TargetLowering(const TargetLowering &)=deletellvm::TargetLowering
TargetLowering(const TargetMachine &TM)llvm::TargetLoweringexplicit
TargetLoweringBase(const TargetMachine &TM)llvm::TargetLoweringBaseexplicit
TargetLoweringBase(const TargetLoweringBase &)=deletellvm::TargetLoweringBase
targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) constllvm::TargetLoweringinlinevirtual
TypeExpandFloat enum valuellvm::TargetLoweringBase
TypeExpandInteger enum valuellvm::TargetLoweringBase
TypeLegal enum valuellvm::TargetLoweringBase
TypePromoteFloat enum valuellvm::TargetLoweringBase
TypePromoteInteger enum valuellvm::TargetLoweringBase
TypeScalarizeVector enum valuellvm::TargetLoweringBase
TypeSoftenFloat enum valuellvm::TargetLoweringBase
TypeSplitVector enum valuellvm::TargetLoweringBase
TypeWidenVector enum valuellvm::TargetLoweringBase
UndefinedBooleanContent enum valuellvm::TargetLoweringBase
Unspecified enum valuellvm::TargetLoweringBase
unwrapAddress(SDValue N) constllvm::TargetLoweringinlinevirtual
useLoadStackGuardNode() constllvm::TargetLoweringinlinevirtual
useSoftFloat() constllvm::TargetLoweringBaseinlinevirtual
useStackGuardXorFP() constllvm::TargetLoweringBaseinlinevirtual
usesUnderscoreLongJmp() constllvm::TargetLoweringBaseinline
usesUnderscoreSetJmp() constllvm::TargetLoweringBaseinline
VectorMaskSelect enum valuellvm::TargetLoweringBase
verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) constllvm::TargetLowering
WidenVectorLoad(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
ZeroOrNegativeOneBooleanContent enum valuellvm::TargetLoweringBase
ZeroOrOneBooleanContent enum valuellvm::TargetLoweringBase
~TargetLoweringBase()=defaultllvm::TargetLoweringBasevirtual