Helper class to build MachineInstr. More...

#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"

Inheritance diagram for llvm::MachineIRBuilder:

Public Member Functions
	MachineIRBuilder ()=default
	Some constructors for easy use. More...

	MachineIRBuilder (MachineFunction &MF)

	MachineIRBuilder (MachineInstr &MI)

virtual	~MachineIRBuilder ()=default

	MachineIRBuilder (const MachineIRBuilderState &BState)

const TargetInstrInfo &	getTII ()

MachineFunction &	getMF ()
	Getter for the function we currently build. More...

const MachineFunction &	getMF () const

const DataLayout &	getDataLayout () const

const DebugLoc &	getDL ()
	Getter for DebugLoc. More...

MachineRegisterInfo *	getMRI ()
	Getter for MRI. More...

const MachineRegisterInfo *	getMRI () const

MachineIRBuilderState &	getState ()
	Getter for the State. More...

const MachineBasicBlock &	getMBB () const
	Getter for the basic block we currently build. More...

MachineBasicBlock &	getMBB ()

GISelCSEInfo *	getCSEInfo ()

const GISelCSEInfo *	getCSEInfo () const

MachineBasicBlock::iterator	getInsertPt ()
	Current insertion point for new instructions. More...

void	setInsertPt (MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
	Set the insertion point before the specified position. More...

void	setCSEInfo (GISelCSEInfo *Info)

void	setChangeObserver (GISelChangeObserver &Observer)

void	stopObservingChanges ()

void	setDebugLoc (const DebugLoc &DL)
	Set the debug location to `DL` for all the next build instructions. More...

DebugLoc	getDebugLoc ()
	Get the current instruction's debug location. More...

MachineInstrBuilder	buildInstr (unsigned Opcode)
	Build and insert <empty> = `Opcode` <empty>. More...

MachineInstrBuilder	buildInstrNoInsert (unsigned Opcode)
	Build but don't insert <empty> = `Opcode` <empty>. More...

MachineInstrBuilder	insertInstr (MachineInstrBuilder MIB)
	Insert an existing instruction at the insertion point. More...

MachineInstrBuilder	buildDirectDbgValue (Register Reg, const MDNode Variable, const MDNode Expr)
	Build and insert a DBG_VALUE instruction expressing the fact that the associated `Variable` lives in `Reg` (suitably modified by `Expr`). More...

MachineInstrBuilder	buildIndirectDbgValue (Register Reg, const MDNode Variable, const MDNode Expr)
	Build and insert a DBG_VALUE instruction expressing the fact that the associated `Variable` lives in memory at `Reg` (suitably modified by `Expr`). More...

MachineInstrBuilder	buildFIDbgValue (int FI, const MDNode Variable, const MDNode Expr)
	Build and insert a DBG_VALUE instruction expressing the fact that the associated `Variable` lives in the stack slot specified by `FI` (suitably modified by `Expr`). More...

MachineInstrBuilder	buildConstDbgValue (const Constant &C, const MDNode Variable, const MDNode Expr)
	Build and insert a DBG_VALUE instructions specifying that `Variable` is given by `C` (suitably modified by `Expr`). More...

MachineInstrBuilder	buildDbgLabel (const MDNode *Label)
	Build and insert a DBG_LABEL instructions specifying that `Label` is given. More...

MachineInstrBuilder	buildDynStackAlloc (const DstOp &Res, const SrcOp &Size, unsigned Align)
	Build and insert `Res` = G_DYN_STACKALLOC `Size`, `Align`. More...

MachineInstrBuilder	buildFrameIndex (const DstOp &Res, int Idx)
	Build and insert `Res` = G_FRAME_INDEX `Idx`. More...

MachineInstrBuilder	buildGlobalValue (const DstOp &Res, const GlobalValue *GV)
	Build and insert `Res` = G_GLOBAL_VALUE `GV`. More...

MachineInstrBuilder	buildGEP (const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
	Build and insert `Res` = G_GEP `Op0`, `Op1`. More...

Optional< MachineInstrBuilder >	materializeGEP (Register &Res, Register Op0, const LLT &ValueTy, uint64_t Value)
	Materialize and insert `Res` = G_GEP `Op0`, (G_CONSTANT `Value`) More...

MachineInstrBuilder	buildPtrMask (const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)
	Build and insert `Res` = G_PTR_MASK `Op0`, `NumBits`. More...

MachineInstrBuilder	buildUAddo (const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
	Build and insert `Res`, `CarryOut` = G_UADDO `Op0`, `Op1`. More...

MachineInstrBuilder	buildUAdde (const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
	Build and insert `Res`, `CarryOut` = G_UADDE `Op0`, `Op1`, `CarryIn`. More...

MachineInstrBuilder	buildAnyExt (const DstOp &Res, const SrcOp &Op)
	Build and insert `Res` = G_ANYEXT `Op0`. More...

MachineInstrBuilder	buildSExt (const DstOp &Res, const SrcOp &Op)
	Build and insert `Res` = G_SEXT `Op`. More...

MachineInstrBuilder	buildPtrToInt (const DstOp &Dst, const SrcOp &Src)
	Build and insert a G_PTRTOINT instruction. More...

MachineInstrBuilder	buildIntToPtr (const DstOp &Dst, const SrcOp &Src)
	Build and insert a G_INTTOPTR instruction. More...

MachineInstrBuilder	buildBitcast (const DstOp &Dst, const SrcOp &Src)
	Build and insert `Dst` = G_BITCAST `Src`. More...

MachineInstrBuilder	buildAddrSpaceCast (const DstOp &Dst, const SrcOp &Src)
	Build and insert `Dst` = G_ADDRSPACE_CAST `Src`. More...

unsigned	getBoolExtOp (bool IsVec, bool IsFP) const

MachineInstrBuilder	buildBoolExt (const DstOp &Res, const SrcOp &Op, bool IsFP)

MachineInstrBuilder	buildZExt (const DstOp &Res, const SrcOp &Op)
	Build and insert `Res` = G_ZEXT `Op`. More...

MachineInstrBuilder	buildSExtOrTrunc (const DstOp &Res, const SrcOp &Op)
	Build and insert `Res` = G_SEXT `Op`, `Res` = G_TRUNC `Op`, or `Res` = COPY `Op` depending on the differing sizes of `Res` and `Op`. More...

MachineInstrBuilder	buildZExtOrTrunc (const DstOp &Res, const SrcOp &Op)
	Build and insert `Res` = G_ZEXT `Op`, `Res` = G_TRUNC `Op`, or `Res` = COPY `Op` depending on the differing sizes of `Res` and `Op`. More...

MachineInstrBuilder	buildAnyExtOrTrunc (const DstOp &Res, const SrcOp &Op)
	`Res` = COPY `Op` depending on the differing sizes of `Res` and `Op`. More...

MachineInstrBuilder	buildExtOrTrunc (unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
	Build and insert `Res` = `ExtOpc`, `Res` = G_TRUNC `Op`, or `Res` = COPY `Op` depending on the differing sizes of `Res` and `Op`. More...

MachineInstrBuilder	buildCast (const DstOp &Dst, const SrcOp &Src)
	Build and insert an appropriate cast between two registers of equal size. More...

MachineInstrBuilder	buildBr (MachineBasicBlock &Dest)
	Build and insert G_BR `Dest`. More...

MachineInstrBuilder	buildBrCond (Register Tst, MachineBasicBlock &Dest)
	Build and insert G_BRCOND `Tst`, `Dest`. More...

MachineInstrBuilder	buildBrIndirect (Register Tgt)
	Build and insert G_BRINDIRECT `Tgt`. More...

MachineInstrBuilder	buildBrJT (Register TablePtr, unsigned JTI, Register IndexReg)
	Build and insert G_BRJT `TablePtr`, `JTI`, `IndexReg`. More...

virtual MachineInstrBuilder	buildConstant (const DstOp &Res, const ConstantInt &Val)
	Build and insert `Res` = G_CONSTANT `Val`. More...

MachineInstrBuilder	buildConstant (const DstOp &Res, int64_t Val)
	Build and insert `Res` = G_CONSTANT `Val`. More...

MachineInstrBuilder	buildConstant (const DstOp &Res, const APInt &Val)

virtual MachineInstrBuilder	buildFConstant (const DstOp &Res, const ConstantFP &Val)
	Build and insert `Res` = G_FCONSTANT `Val`. More...

MachineInstrBuilder	buildFConstant (const DstOp &Res, double Val)

MachineInstrBuilder	buildFConstant (const DstOp &Res, const APFloat &Val)

MachineInstrBuilder	buildCopy (const DstOp &Res, const SrcOp &Op)
	Build and insert `Res` = COPY Op. More...

MachineInstrBuilder	buildLoad (const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
	Build and insert `Res = G_LOAD Addr, MMO`. More...

MachineInstrBuilder	buildLoadInstr (unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
	Build and insert `Res = <opcode> Addr, MMO`. More...

MachineInstrBuilder	buildStore (const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
	Build and insert `G_STORE Val, Addr, MMO`. More...

MachineInstrBuilder	buildExtract (const DstOp &Res, const SrcOp &Src, uint64_t Index)
	Build and insert `Res0, ... More...

MachineInstrBuilder	buildUndef (const DstOp &Res)
	Build and insert `Res` = IMPLICIT_DEF. More...

void	buildSequence (Register Res, ArrayRef< Register > Ops, ArrayRef< uint64_t > Indices)
	Build and insert instructions to put `Ops` together at the specified p Indices to form a larger register. More...

MachineInstrBuilder	buildMerge (const DstOp &Res, ArrayRef< Register > Ops)
	Build and insert `Res` = G_MERGE_VALUES `Op0`, ... More...

MachineInstrBuilder	buildUnmerge (ArrayRef< LLT > Res, const SrcOp &Op)
	Build and insert `Res0`, ... More...

MachineInstrBuilder	buildUnmerge (ArrayRef< Register > Res, const SrcOp &Op)

MachineInstrBuilder	buildUnmerge (LLT Res, const SrcOp &Op)
	Build and insert an unmerge of `Res` sized pieces to cover `Op`. More...

MachineInstrBuilder	buildBuildVector (const DstOp &Res, ArrayRef< Register > Ops)
	Build and insert `Res` = G_BUILD_VECTOR `Op0`, ... More...

MachineInstrBuilder	buildSplatVector (const DstOp &Res, const SrcOp &Src)
	Build and insert `Res` = G_BUILD_VECTOR with `Src` replicated to fill the number of elements. More...

MachineInstrBuilder	buildBuildVectorTrunc (const DstOp &Res, ArrayRef< Register > Ops)
	Build and insert `Res` = G_BUILD_VECTOR_TRUNC `Op0`, ... More...

MachineInstrBuilder	buildConcatVectors (const DstOp &Res, ArrayRef< Register > Ops)
	Build and insert `Res` = G_CONCAT_VECTORS `Op0`, ... More...

MachineInstrBuilder	buildInsert (Register Res, Register Src, Register Op, unsigned Index)

MachineInstrBuilder	buildIntrinsic (Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects)
	Build and insert either a G_INTRINSIC (if `HasSideEffects` is false) or G_INTRINSIC_W_SIDE_EFFECTS instruction. More...

MachineInstrBuilder	buildIntrinsic (Intrinsic::ID ID, ArrayRef< DstOp > Res, bool HasSideEffects)

MachineInstrBuilder	buildFPTrunc (const DstOp &Res, const SrcOp &Op)
	Build and insert `Res` = G_FPTRUNC `Op`. More...

MachineInstrBuilder	buildTrunc (const DstOp &Res, const SrcOp &Op)
	Build and insert `Res` = G_TRUNC `Op`. More...

MachineInstrBuilder	buildICmp (CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
	Build and insert a `Res` = G_ICMP `Pred`, `Op0`, `Op1`. More...

MachineInstrBuilder	buildFCmp (CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, Optional< unsigned > Flags=None)
	Build and insert a `Res` = G_FCMP `PredOp0,` `Op1`. More...

MachineInstrBuilder	buildSelect (const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, Optional< unsigned > Flags=None)
	Build and insert a `Res` = G_SELECT `Tst`, `Op0`, `Op1`. More...

MachineInstrBuilder	buildInsertVectorElement (const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
	Build and insert `Res` = G_INSERT_VECTOR_ELT `Val`, `Elt`, `Idx`. More...

MachineInstrBuilder	buildExtractVectorElement (const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
	Build and insert `Res` = G_EXTRACT_VECTOR_ELT `Val`, `Idx`. More...

MachineInstrBuilder	buildAtomicCmpXchgWithSuccess (Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
	Build and insert `OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`. More...

MachineInstrBuilder	buildAtomicCmpXchg (Register OldValRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
	Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO`. More...

MachineInstrBuilder	buildAtomicRMW (unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
	Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`. More...

MachineInstrBuilder	buildAtomicRMWXchg (Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
	Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`. More...

MachineInstrBuilder	buildAtomicRMWAdd (Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
	Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`. More...

MachineInstrBuilder	buildAtomicRMWSub (Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
	Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`. More...

MachineInstrBuilder	buildAtomicRMWAnd (Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
	Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`. More...

MachineInstrBuilder	buildAtomicRMWNand (Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
	Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`. More...

MachineInstrBuilder	buildAtomicRMWOr (Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
	Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`. More...

MachineInstrBuilder	buildAtomicRMWXor (Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
	Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`. More...

MachineInstrBuilder	buildAtomicRMWMax (Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
	Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`. More...

MachineInstrBuilder	buildAtomicRMWMin (Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
	Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`. More...

MachineInstrBuilder	buildAtomicRMWUmax (Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
	Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`. More...

MachineInstrBuilder	buildAtomicRMWUmin (Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
	Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`. More...

MachineInstrBuilder	buildAtomicRMWFAdd (const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
	Build and insert `OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO`. More...

MachineInstrBuilder	buildAtomicRMWFSub (const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
	Build and insert `OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO`. More...

MachineInstrBuilder	buildFence (unsigned Ordering, unsigned Scope)
	Build and insert `G_FENCE Ordering, Scope`. More...

MachineInstrBuilder	buildBlockAddress (Register Res, const BlockAddress *BA)
	Build and insert `Res` = G_BLOCK_ADDR `BA`. More...

MachineInstrBuilder	buildAdd (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
	Build and insert `Res` = G_ADD `Op0`, `Op1`. More...

MachineInstrBuilder	buildSub (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
	Build and insert `Res` = G_SUB `Op0`, `Op1`. More...

MachineInstrBuilder	buildMul (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
	Build and insert `Res` = G_MUL `Op0`, `Op1`. More...

MachineInstrBuilder	buildUMulH (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)

MachineInstrBuilder	buildSMulH (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)

MachineInstrBuilder	buildFMul (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)

MachineInstrBuilder	buildShl (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)

MachineInstrBuilder	buildLShr (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)

MachineInstrBuilder	buildAShr (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)

MachineInstrBuilder	buildAnd (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
	Build and insert `Res` = G_AND `Op0`, `Op1`. More...

MachineInstrBuilder	buildOr (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
	Build and insert `Res` = G_OR `Op0`, `Op1`. More...

MachineInstrBuilder	buildXor (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
	Build and insert `Res` = G_XOR `Op0`, `Op1`. More...

MachineInstrBuilder	buildNot (const DstOp &Dst, const SrcOp &Src0)
	Build and insert a bitwise not, `NegOne` = G_CONSTANT -1 `Res` = G_OR `Op0`, NegOne. More...

MachineInstrBuilder	buildCTPOP (const DstOp &Dst, const SrcOp &Src0)
	Build and insert `Res` = G_CTPOP `Op0`, `Src0`. More...

MachineInstrBuilder	buildCTLZ (const DstOp &Dst, const SrcOp &Src0)
	Build and insert `Res` = G_CTLZ `Op0`, `Src0`. More...

MachineInstrBuilder	buildCTLZ_ZERO_UNDEF (const DstOp &Dst, const SrcOp &Src0)
	Build and insert `Res` = G_CTLZ_ZERO_UNDEF `Op0`, `Src0`. More...

MachineInstrBuilder	buildCTTZ (const DstOp &Dst, const SrcOp &Src0)
	Build and insert `Res` = G_CTTZ `Op0`, `Src0`. More...

MachineInstrBuilder	buildCTTZ_ZERO_UNDEF (const DstOp &Dst, const SrcOp &Src0)
	Build and insert `Res` = G_CTTZ_ZERO_UNDEF `Op0`, `Src0`. More...

MachineInstrBuilder	buildFAdd (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
	Build and insert `Res` = G_FADD `Op0`, `Op1`. More...

MachineInstrBuilder	buildFSub (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
	Build and insert `Res` = G_FSUB `Op0`, `Op1`. More...

MachineInstrBuilder	buildFMA (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2)
	Build and insert `Res` = G_FMA `Op0`, `Op1`, `Op2`. More...

MachineInstrBuilder	buildFMAD (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, Optional< unsigned > Flags=None)
	Build and insert `Res` = G_FMAD `Op0`, `Op1`, `Op2`. More...

MachineInstrBuilder	buildFNeg (const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
	Build and insert `Res` = G_FNEG `Op0`. More...

MachineInstrBuilder	buildFAbs (const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
	Build and insert `Res` = G_FABS `Op0`. More...

MachineInstrBuilder	buildFCanonicalize (const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
	Build and insert `Dst` = G_FCANONICALIZE `Src0`. More...

MachineInstrBuilder	buildFCopysign (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
	Build and insert `Res` = G_FCOPYSIGN `Op0`, `Op1`. More...

MachineInstrBuilder	buildUITOFP (const DstOp &Dst, const SrcOp &Src0)
	Build and insert `Res` = G_UITOFP `Src0`. More...

MachineInstrBuilder	buildSITOFP (const DstOp &Dst, const SrcOp &Src0)
	Build and insert `Res` = G_SITOFP `Src0`. More...

MachineInstrBuilder	buildFPTOUI (const DstOp &Dst, const SrcOp &Src0)
	Build and insert `Res` = G_FPTOUI `Src0`. More...

MachineInstrBuilder	buildFPTOSI (const DstOp &Dst, const SrcOp &Src0)
	Build and insert `Res` = G_FPTOSI `Src0`. More...

MachineInstrBuilder	buildSMin (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
	Build and insert `Res` = G_SMIN `Op0`, `Op1`. More...

MachineInstrBuilder	buildSMax (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
	Build and insert `Res` = G_SMAX `Op0`, `Op1`. More...

MachineInstrBuilder	buildUMin (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
	Build and insert `Res` = G_UMIN `Op0`, `Op1`. More...

MachineInstrBuilder	buildUMax (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
	Build and insert `Res` = G_UMAX `Op0`, `Op1`. More...

MachineInstrBuilder	buildJumpTable (const LLT PtrTy, unsigned JTI)
	Build and insert `Res` = G_JUMP_TABLE `JTI`. More...

virtual MachineInstrBuilder	buildInstr (unsigned Opc, ArrayRef< DstOp > DstOps, ArrayRef< SrcOp > SrcOps, Optional< unsigned > Flags=None)

Setters for the insertion point.
Set the MachineFunction where to build instructions.
void	setMF (MachineFunction &MF)

void	setMBB (MachineBasicBlock &MBB)
	Set the insertion point to the end of `MBB`. More...

void	setInstr (MachineInstr &MI)
	Set the insertion point to before MI. More...

Protected Member Functions
void	validateTruncExt (const LLT &Dst, const LLT &Src, bool IsExtend)

void	validateBinaryOp (const LLT &Res, const LLT &Op0, const LLT &Op1)

void	validateShiftOp (const LLT &Res, const LLT &Op0, const LLT &Op1)

void	validateSelectOp (const LLT &ResTy, const LLT &TstTy, const LLT &Op0Ty, const LLT &Op1Ty)

void	recordInsertion (MachineInstr *MI) const

Detailed Description

Helper class to build MachineInstr.

It keeps internally the insertion point and debug location for all the new instructions we want to create. This information can be modify via the related setters.

Definition at line 221 of file MachineIRBuilder.h.

Constructor & Destructor Documentation

◆ MachineIRBuilder() [1/4]

llvm::MachineIRBuilder::MachineIRBuilder ( )

default

Some constructors for easy use.

◆ MachineIRBuilder() [2/4]

llvm::MachineIRBuilder::MachineIRBuilder ( MachineFunction & MF )

inline

Definition at line 238 of file MachineIRBuilder.h.

◆ MachineIRBuilder() [3/4]

llvm::MachineIRBuilder::MachineIRBuilder ( MachineInstr & MI )

inline

Definition at line 239 of file MachineIRBuilder.h.

◆ ~MachineIRBuilder()

virtual llvm::MachineIRBuilder::~MachineIRBuilder ( )

virtualdefault

◆ MachineIRBuilder() [4/4]

llvm::MachineIRBuilder::MachineIRBuilder ( const MachineIRBuilderState & BState )

inline

Definition at line 245 of file MachineIRBuilder.h.

Member Function Documentation

◆ buildAdd()

MachineInstrBuilder llvm::MachineIRBuilder::buildAdd	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		const SrcOp &	Src1,
		Optional< unsigned >	Flags = `None`
	)

inline

Build and insert Res = G_ADD Op0, Op1.

G_ADD sets Res to the sum of integer parameters Op0 and Op1, truncated to their width.

Precondition: setBasicBlock or setMI must have been called.; Res, Op0 and Op1 must be generic virtual registers with the same (scalar or vector) type).

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 1217 of file MachineIRBuilder.h.

Referenced by getBaseWithConstantOffset(), getOffsetFromIndices(), llvm::LegalizerHelper::lower(), llvm::LegalizerHelper::lowerSADDO_SSUBO(), llvm::LegalizerHelper::lowerSITOFP(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), and llvm::LegalizerHelper::moreElementsVector().

◆ buildAddrSpaceCast()

MachineInstrBuilder llvm::MachineIRBuilder::buildAddrSpaceCast	(	const DstOp &	Dst,
		const SrcOp &	Src
	)

inline

Build and insert Dst = G_ADDRSPACE_CAST Src.

Definition at line 536 of file MachineIRBuilder.h.

References llvm::None.

Referenced by llvm::AMDGPULegalizerInfo::legalizeLoad().

◆ buildAnd()

MachineInstrBuilder llvm::MachineIRBuilder::buildAnd	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		const SrcOp &	Src1
	)

inline

Build and insert Res = G_AND Op0, Op1.

G_AND sets Res to the bitwise and of integer parameters Op0 and Op1.

Precondition: setBasicBlock or setMI must have been called.; Res, Op0 and Op1 must be generic virtual registers with the same (scalar or vector) type).

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 1303 of file MachineIRBuilder.h.

Referenced by extractDLC(), getOffsetFromIndices(), llvm::AMDGPULegalizerInfo::legalizeFceil(), llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), llvm::AMDGPULegalizerInfo::loadInputValue(), llvm::LegalizerHelper::lowerFCopySign(), llvm::LegalizerHelper::lowerInsert(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), and llvm::LegalizationArtifactCombiner::tryCombineZExt().

◆ buildAnyExt()

MachineInstrBuilder MachineIRBuilder::buildAnyExt	(	const DstOp &	Res,
		const SrcOp &	Op
	)

Build and insert Res = G_ANYEXT Op0.

G_ANYEXT produces a register of the specified width, with bits 0 to sizeof(Ty) * 8 set to Op. The remaining bits are unspecified (i.e. this is neither zero nor sign-extension). For a vector register, each element is extended individually.

Precondition: setBasicBlock or setMI must have been called.; Res must be a generic virtual register with scalar or vector type.; Op must be a generic virtual register with scalar or vector type.; Op must be smaller than Res

Returns: The newly created instruction.

Definition at line 417 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by llvm::AArch64CallLowering::AArch64CallLowering(), llvm::CallLowering::ValueHandler::extendRegister(), extractDLC(), llvm::AMDGPULegalizerInfo::handleD16VData(), llvm::AMDGPULegalizerInfo::legalizeRawBufferStore(), llvm::LegalizerHelper::lower(), llvm::LegalizerHelper::narrowScalar(), unpackRegsToOrigType(), and llvm::X86CallLowering::X86CallLowering().

◆ buildAnyExtOrTrunc()

MachineInstrBuilder MachineIRBuilder::buildAnyExtOrTrunc	(	const DstOp &	Res,
		const SrcOp &	Op
	)

Res = COPY Op depending on the differing sizes of Res and Op.

///

Precondition: setBasicBlock or setMI must have been called.; Res must be a generic virtual register with scalar or vector type.; Op must be a generic virtual register with scalar or vector type.

Returns: The newly created instruction.

Definition at line 485 of file MachineIRBuilder.cpp.

References buildExtOrTrunc().

Referenced by llvm::LegalizerHelper::narrowScalar(), llvm::LegalizationArtifactCombiner::tryCombineAnyExt(), llvm::LegalizationArtifactCombiner::tryCombineSExt(), and llvm::LegalizationArtifactCombiner::tryCombineZExt().

◆ buildAShr()

MachineInstrBuilder llvm::MachineIRBuilder::buildAShr	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		const SrcOp &	Src1,
		Optional< unsigned >	Flags = `None`
	)

inline

Definition at line 1286 of file MachineIRBuilder.h.

Referenced by extractDLC(), llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), llvm::LegalizerHelper::lowerSITOFP(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizerHelper::narrowScalarShift(), and llvm::LegalizerHelper::narrowScalarShiftByConstant().

◆ buildAtomicCmpXchg()

MachineInstrBuilder MachineIRBuilder::buildAtomicCmpXchg	(	Register	OldValRes,
		Register	Addr,
		Register	CmpVal,
		Register	NewVal,
		MachineMemOperand &	MMO
	)

Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.

Atomically replace the value at Addr with NewVal if it is currently CmpVal otherwise leaves it unchanged. Puts the original value from Addr in Res.

Precondition: setBasicBlock or setMI must have been called.; OldValRes must be a generic virtual register of scalar type.; Addr must be a generic virtual register with pointer type.; OldValRes, CmpVal, and NewVal must be generic virtual registers of the same type.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 770 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addUse(), assert(), buildInstr(), getMRI(), llvm::MachineRegisterInfo::getType(), llvm::LLT::isPointer(), llvm::LLT::isScalar(), and llvm::LLT::isValid().

Referenced by llvm::LegalizerHelper::lower().

◆ buildAtomicCmpXchgWithSuccess()

MachineInstrBuilder MachineIRBuilder::buildAtomicCmpXchgWithSuccess	(	Register	OldValRes,
		Register	SuccessRes,
		Register	Addr,
		Register	CmpVal,
		Register	NewVal,
		MachineMemOperand &	MMO
	)

Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO.

Atomically replace the value at Addr with NewVal if it is currently CmpVal otherwise leaves it unchanged. Puts the original value from Addr in Res, along with an s1 indicating whether it was replaced.

Precondition: setBasicBlock or setMI must have been called.; OldValRes must be a generic virtual register of scalar type.; SuccessRes must be a generic virtual register of scalar type. It will be assigned 0 on failure and 1 on success.; Addr must be a generic virtual register with pointer type.; OldValRes, CmpVal, and NewVal must be generic virtual registers of the same type.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 742 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addUse(), assert(), buildInstr(), getMRI(), llvm::MachineRegisterInfo::getType(), llvm::LLT::isPointer(), llvm::LLT::isScalar(), and llvm::LLT::isValid().

Referenced by getOffsetFromIndices().

◆ buildAtomicRMW()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMW	(	unsigned	Opcode,
		const DstOp &	OldValRes,
		const SrcOp &	Addr,
		const SrcOp &	Val,
		MachineMemOperand &	MMO
	)

Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.

Atomically read-modify-update the value at Addr with Val. Puts the original value from Addr in OldValRes. The modification is determined by the opcode.

Precondition: setBasicBlock or setMI must have been called.; OldValRes must be a generic virtual register.; Addr must be a generic virtual register with pointer type.; OldValRes, and Val must be generic virtual registers of the same type.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 794 of file MachineIRBuilder.cpp.

References llvm::DstOp::addDefToMIB(), llvm::SrcOp::addSrcToMIB(), assert(), buildInstr(), llvm::DstOp::getLLTTy(), llvm::SrcOp::getLLTTy(), getMRI(), llvm::MachineMemOperand::isAtomic(), llvm::LLT::isPointer(), llvm::LLT::isScalar(), and llvm::LLT::isValid().

Referenced by buildAtomicRMWAdd(), buildAtomicRMWAnd(), buildAtomicRMWFAdd(), buildAtomicRMWFSub(), buildAtomicRMWMax(), buildAtomicRMWMin(), buildAtomicRMWNand(), buildAtomicRMWOr(), buildAtomicRMWSub(), buildAtomicRMWUmax(), buildAtomicRMWUmin(), buildAtomicRMWXchg(), buildAtomicRMWXor(), and getOffsetFromIndices().

◆ buildAtomicRMWAdd()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWAdd	(	Register	OldValRes,
		Register	Addr,
		Register	Val,
		MachineMemOperand &	MMO
	)

Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.

Atomically replace the value at Addr with the addition of Val and the original value. Puts the original value from Addr in OldValRes.

Precondition: setBasicBlock or setMI must have been called.; OldValRes must be a generic virtual register.; Addr must be a generic virtual register with pointer type.; OldValRes, and Val must be generic virtual registers of the same type.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 825 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildAtomicRMWAnd()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWAnd	(	Register	OldValRes,
		Register	Addr,
		Register	Val,
		MachineMemOperand &	MMO
	)

Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.

Atomically replace the value at Addr with the bitwise and of Val and the original value. Puts the original value from Addr in OldValRes.

Precondition: setBasicBlock or setMI must have been called.; OldValRes must be a generic virtual register.; Addr must be a generic virtual register with pointer type.; OldValRes, and Val must be generic virtual registers of the same type.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 837 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildAtomicRMWFAdd()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWFAdd	(	const DstOp &	OldValRes,
		const SrcOp &	Addr,
		const SrcOp &	Val,
		MachineMemOperand &	MMO
	)

Build and insert OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO.

Definition at line 887 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildAtomicRMWFSub()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWFSub	(	const DstOp &	OldValRes,
		const SrcOp &	Addr,
		const SrcOp &	Val,
		MachineMemOperand &	MMO
	)

Build and insert OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO.

Definition at line 895 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildAtomicRMWMax()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWMax	(	Register	OldValRes,
		Register	Addr,
		Register	Val,
		MachineMemOperand &	MMO
	)

Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.

Atomically replace the value at Addr with the signed maximum of Val and the original value. Puts the original value from Addr in OldValRes.

Precondition: setBasicBlock or setMI must have been called.; OldValRes must be a generic virtual register.; Addr must be a generic virtual register with pointer type.; OldValRes, and Val must be generic virtual registers of the same type.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 862 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildAtomicRMWMin()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWMin	(	Register	OldValRes,
		Register	Addr,
		Register	Val,
		MachineMemOperand &	MMO
	)

Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.

Atomically replace the value at Addr with the signed minimum of Val and the original value. Puts the original value from Addr in OldValRes.

Precondition: setBasicBlock or setMI must have been called.; OldValRes must be a generic virtual register.; Addr must be a generic virtual register with pointer type.; OldValRes, and Val must be generic virtual registers of the same type.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 868 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildAtomicRMWNand()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWNand	(	Register	OldValRes,
		Register	Addr,
		Register	Val,
		MachineMemOperand &	MMO
	)

Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.

Atomically replace the value at Addr with the bitwise nand of Val and the original value. Puts the original value from Addr in OldValRes.

Precondition: setBasicBlock or setMI must have been called.; OldValRes must be a generic virtual register.; Addr must be a generic virtual register with pointer type.; OldValRes, and Val must be generic virtual registers of the same type.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 843 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildAtomicRMWOr()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWOr	(	Register	OldValRes,
		Register	Addr,
		Register	Val,
		MachineMemOperand &	MMO
	)

Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.

Atomically replace the value at Addr with the bitwise or of Val and the original value. Puts the original value from Addr in OldValRes.

Precondition: setBasicBlock or setMI must have been called.; OldValRes must be a generic virtual register.; Addr must be a generic virtual register with pointer type.; OldValRes, and Val must be generic virtual registers of the same type.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 848 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildAtomicRMWSub()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWSub	(	Register	OldValRes,
		Register	Addr,
		Register	Val,
		MachineMemOperand &	MMO
	)

Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.

Atomically replace the value at Addr with the subtraction of Val and the original value. Puts the original value from Addr in OldValRes.

Precondition: setBasicBlock or setMI must have been called.; OldValRes must be a generic virtual register.; Addr must be a generic virtual register with pointer type.; OldValRes, and Val must be generic virtual registers of the same type.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 831 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildAtomicRMWUmax()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWUmax	(	Register	OldValRes,
		Register	Addr,
		Register	Val,
		MachineMemOperand &	MMO
	)

Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.

Atomically replace the value at Addr with the unsigned maximum of Val and the original value. Puts the original value from Addr in OldValRes.

Precondition: setBasicBlock or setMI must have been called.; OldValRes must be a generic virtual register.; Addr must be a generic virtual register with pointer type.; OldValRes, and Val must be generic virtual registers of the same type.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 874 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildAtomicRMWUmin()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWUmin	(	Register	OldValRes,
		Register	Addr,
		Register	Val,
		MachineMemOperand &	MMO
	)

Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.

Atomically replace the value at Addr with the unsigned minimum of Val and the original value. Puts the original value from Addr in OldValRes.

Precondition: setBasicBlock or setMI must have been called.; OldValRes must be a generic virtual register.; Addr must be a generic virtual register with pointer type.; OldValRes, and Val must be generic virtual registers of the same type.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 880 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildAtomicRMWXchg()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWXchg	(	Register	OldValRes,
		Register	Addr,
		Register	Val,
		MachineMemOperand &	MMO
	)

Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.

Atomically replace the value at Addr with Val. Puts the original value from Addr in OldValRes.

Precondition: setBasicBlock or setMI must have been called.; OldValRes must be a generic virtual register.; Addr must be a generic virtual register with pointer type.; OldValRes, and Val must be generic virtual registers of the same type.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 819 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildAtomicRMWXor()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWXor	(	Register	OldValRes,
		Register	Addr,
		Register	Val,
		MachineMemOperand &	MMO
	)

Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.

Atomically replace the value at Addr with the bitwise xor of Val and the original value. Puts the original value from Addr in OldValRes.

Precondition: setBasicBlock or setMI must have been called.; OldValRes must be a generic virtual register.; Addr must be a generic virtual register with pointer type.; OldValRes, and Val must be generic virtual registers of the same type.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 856 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildBitcast()

MachineInstrBuilder llvm::MachineIRBuilder::buildBitcast	(	const DstOp &	Dst,
		const SrcOp &	Src
	)

inline

Build and insert Dst = G_BITCAST Src.

Definition at line 531 of file MachineIRBuilder.h.

Referenced by extractDLC(), llvm::AArch64LegalizerInfo::legalizeIntrinsic(), llvm::LegalizerHelper::lowerExtract(), llvm::LegalizerHelper::lowerInsert(), and llvm::LegalizerHelper::lowerUnmergeValues().

◆ buildBlockAddress()

MachineInstrBuilder MachineIRBuilder::buildBlockAddress	(	Register	Res,
		const BlockAddress *	BA
	)

Build and insert Res = G_BLOCK_ADDR BA.

G_BLOCK_ADDR computes the address of a basic block.

Precondition: setBasicBlock or setMI must have been called.; Res must be a generic virtual register of a pointer type.

Returns: The newly created instruction.

Definition at line 909 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addBlockAddress(), llvm::MachineInstrBuilder::addDef(), assert(), buildInstr(), getMRI(), getType(), and llvm::LegalityPredicates::isPointer().

◆ buildBoolExt()

MachineInstrBuilder MachineIRBuilder::buildBoolExt	(	const DstOp &	Res,
		const SrcOp &	Op,
		bool	IsFP
	)

Definition at line 444 of file MachineIRBuilder.cpp.

References buildInstr(), getBoolExtOp(), getMRI(), llvm::SrcOp::getReg(), getType(), and llvm::LegalityPredicates::isVector().

◆ buildBr()

MachineInstrBuilder MachineIRBuilder::buildBr ( MachineBasicBlock & Dest )

Build and insert G_BR Dest.

G_BR is an unconditional branch to Dest.

Precondition: setBasicBlock or setMI must have been called.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 261 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addMBB(), and buildInstr().

Referenced by llvm::IRTranslator::getAnalysisUsage(), and getOffsetFromIndices().

◆ buildBrCond()

MachineInstrBuilder MachineIRBuilder::buildBrCond	(	Register	Tst,
		MachineBasicBlock &	Dest
	)

Build and insert G_BRCOND Tst, Dest.

G_BRCOND is a conditional branch to Dest.

Precondition: setBasicBlock or setMI must have been called.; Tst must be a generic virtual register with scalar type. At the beginning of legalization, this will be a single bit (s1). Targets with interesting flags registers may change this. For a wider type, whether the branch is taken must only depend on bit 0 (for now).

Returns: The newly created instruction.

Definition at line 361 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addUse(), assert(), buildInstr(), getMRI(), getType(), and llvm::LegalityPredicates::isScalar().

Referenced by llvm::IRTranslator::getAnalysisUsage().

◆ buildBrIndirect()

MachineInstrBuilder MachineIRBuilder::buildBrIndirect ( Register Tgt )

Build and insert G_BRINDIRECT Tgt.

G_BRINDIRECT is an indirect branch to Tgt.

Precondition: setBasicBlock or setMI must have been called.; Tgt must be a generic virtual register with pointer type.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 265 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addUse(), assert(), buildInstr(), getMRI(), getType(), and llvm::LegalityPredicates::isPointer().

◆ buildBrJT()

MachineInstrBuilder MachineIRBuilder::buildBrJT	(	Register	TablePtr,
		unsigned	JTI,
		Register	IndexReg
	)

Build and insert G_BRJT TablePtr, JTI, IndexReg.

G_BRJT is a jump table branch using a table base pointer TablePtr, jump table index JTI and index IndexReg

Precondition: setBasicBlock or setMI must have been called.; TablePtr must be a generic virtual register with pointer type.; JTI must be be a jump table index.; IndexReg must be a generic virtual register with pointer type.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 270 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addJumpTableIndex(), llvm::MachineInstrBuilder::addUse(), assert(), buildInstr(), getMRI(), getType(), and llvm::LegalityPredicates::isPointer().

Referenced by llvm::IRTranslator::getAnalysisUsage().

◆ buildBuildVector()

MachineInstrBuilder MachineIRBuilder::buildBuildVector	(	const DstOp &	Res,
		ArrayRef< Register >	Ops
	)

Build and insert Res = G_BUILD_VECTOR Op0, ...

G_BUILD_VECTOR creates a vector value from multiple scalar registers.

Precondition: setBasicBlock or setMI must have been called.; The entire register Res (and no more) must be covered by the input scalar registers.; The type of all Ops registers must be identical.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 619 of file MachineIRBuilder.cpp.

References llvm::ArrayRef< T >::begin(), buildInstr(), and llvm::ArrayRef< T >::end().

◆ buildBuildVectorTrunc()

MachineInstrBuilder MachineIRBuilder::buildBuildVectorTrunc	(	const DstOp &	Res,
		ArrayRef< Register >	Ops
	)

Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...

G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers which have types larger than the destination vector element type, and truncates the values to fit.

If the operands given are already the same size as the vector elt type, then this method will instead create a G_BUILD_VECTOR instruction.

Precondition: setBasicBlock or setMI must have been called.; The type of all Ops registers must be identical.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 635 of file MachineIRBuilder.cpp.

References llvm::ArrayRef< T >::begin(), buildInstr(), and llvm::ArrayRef< T >::end().

◆ buildCast()

MachineInstrBuilder MachineIRBuilder::buildCast	(	const DstOp &	Dst,
		const SrcOp &	Src
	)

Build and insert an appropriate cast between two registers of equal size.

Definition at line 490 of file MachineIRBuilder.cpp.

References assert(), buildCopy(), buildInstr(), llvm::DstOp::getLLTTy(), llvm::SrcOp::getLLTTy(), getMRI(), llvm::LLT::isPointer(), and llvm::LLT::isScalar().

Referenced by buildExtract(), buildInsert(), buildInstr(), getOffsetFromIndices(), and llvm::LegalizerHelper::lowerDynStackAlloc().

◆ buildConcatVectors()

MachineInstrBuilder MachineIRBuilder::buildConcatVectors	(	const DstOp &	Res,
		ArrayRef< Register >	Ops
	)

Build and insert Res = G_CONCAT_VECTORS Op0, ...

G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more vectors.

Precondition: setBasicBlock or setMI must have been called.; The entire register Res (and no more) must be covered by the input registers.; The type of all source operands must be identical.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 645 of file MachineIRBuilder.cpp.

References llvm::ArrayRef< T >::begin(), buildInstr(), and llvm::ArrayRef< T >::end().

Referenced by llvm::CombinerHelper::applyCombineShuffleVector(), llvm::LegalizerHelper::fewerElementsVectorBasic(), llvm::LegalizerHelper::fewerElementsVectorBuildVector(), llvm::LegalizerHelper::fewerElementsVectorCasts(), llvm::LegalizerHelper::fewerElementsVectorCmp(), llvm::LegalizerHelper::fewerElementsVectorImplicitDef(), llvm::LegalizerHelper::fewerElementsVectorSelect(), getGCDType(), llvm::LegalizerHelper::narrowScalar(), and packSplitRegsToOrigType().

◆ buildConstant() [1/3]

MachineInstrBuilder MachineIRBuilder::buildConstant	(	const DstOp &	Res,
		const ConstantInt &	Val
	)

virtual

Build and insert Res = G_CONSTANT Val.

G_CONSTANT is an integer constant with the specified size and value. Val will be extended or truncated to the size of Reg.

Precondition: setBasicBlock or setMI must have been called.; Res must be a generic virtual register with scalar or pointer type.

Returns: The newly created instruction.

Reimplemented in llvm::CSEMIRBuilder.

Definition at line 286 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addCImm(), llvm::MachineInstrBuilder::addDef(), llvm::DstOp::addDefToMIB(), assert(), buildInstr(), buildSplatVector(), llvm::ConstantInt::getBitWidth(), llvm::DstOp::getLLTTy(), getMRI(), llvm::LLT::getScalarSizeInBits(), llvm::LLT::getScalarType(), and llvm::LLT::isVector().

◆ buildConstant() [2/3]

MachineInstrBuilder MachineIRBuilder::buildConstant	(	const DstOp &	Res,
		int64_t	Val
	)

Build and insert Res = G_CONSTANT Val.

G_CONSTANT is an integer constant with the specified size and value.

Precondition: setBasicBlock or setMI must have been called.; Res must be a generic virtual register with scalar type.

Returns: The newly created instruction.

Definition at line 306 of file MachineIRBuilder.cpp.

References buildConstant(), llvm::IntegerType::get(), llvm::ConstantInt::get(), getFunction(), llvm::DstOp::getLLTTy(), getMF(), getMRI(), and llvm::LLT::getScalarSizeInBits().

◆ buildConstant() [3/3]

MachineInstrBuilder MachineIRBuilder::buildConstant	(	const DstOp &	Res,
		const APInt &	Val
	)

Definition at line 339 of file MachineIRBuilder.cpp.

References buildConstant(), llvm::ConstantInt::get(), getFunction(), and getMF().

◆ buildConstDbgValue()

MachineInstrBuilder MachineIRBuilder::buildConstDbgValue	(	const Constant &	C,
		const MDNode *	Variable,
		const MDNode *	Expr
	)

Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified by Expr).

Definition at line 138 of file MachineIRBuilder.cpp.

References assert(), buildInstr(), and getDL().

Referenced by getOffsetFromIndices().

◆ buildCopy()

MachineInstrBuilder MachineIRBuilder::buildCopy	(	const DstOp &	Res,
		const SrcOp &	Op
	)

Build and insert Res = COPY Op.

Register-to-register COPY sets Res to Op.

Precondition: setBasicBlock or setMI must have been called.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 281 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by llvm::AArch64CallLowering::AArch64CallLowering(), allocateHSAUserSGPRs(), buildCast(), changeFCMPPredToAArch64CC(), extractDLC(), findIntrinsicID(), llvm::IRTranslator::getAnalysisUsage(), getCallOpcode(), getExtendTypeForInst(), getOffsetFromIndices(), llvm::CallLowering::handleAssignments(), handleMustTailForwardedRegisters(), isSupportedType(), isSwiftError(), llvm::AMDGPULegalizerInfo::loadInputValue(), llvm::AArch64CallLowering::lowerCall(), llvm::LegalizerHelper::lowerDynStackAlloc(), llvm::AMDGPUCallLowering::lowerFormalArguments(), llvm::MipsCallLowering::lowerFormalArguments(), llvm::X86CallLowering::lowerReturn(), llvm::ARMCallLowering::lowerReturn(), llvm::AArch64CallLowering::lowerReturn(), llvm::AMDGPUCallLowering::lowerReturn(), llvm::LegalizerHelper::lowerShuffleVector(), llvm::LegalizerHelper::narrowScalar(), llvm::CombinerHelper::replaceRegWith(), selectSubregisterCopy(), and llvm::X86CallLowering::X86CallLowering().

◆ buildCTLZ()

MachineInstrBuilder llvm::MachineIRBuilder::buildCTLZ	(	const DstOp &	Dst,
		const SrcOp &	Src0
	)

inline

Build and insert Res = G_CTLZ Op0, Src0.

Definition at line 1343 of file MachineIRBuilder.h.

◆ buildCTLZ_ZERO_UNDEF()

MachineInstrBuilder llvm::MachineIRBuilder::buildCTLZ_ZERO_UNDEF	(	const DstOp &	Dst,
		const SrcOp &	Src0
	)

inline

Build and insert Res = G_CTLZ_ZERO_UNDEF Op0, Src0.

Definition at line 1348 of file MachineIRBuilder.h.

Referenced by llvm::LegalizerHelper::lowerU64ToF32BitOps().

◆ buildCTPOP()

MachineInstrBuilder llvm::MachineIRBuilder::buildCTPOP	(	const DstOp &	Dst,
		const SrcOp &	Src0
	)

inline

Build and insert Res = G_CTPOP Op0, Src0.

Definition at line 1338 of file MachineIRBuilder.h.

◆ buildCTTZ()

MachineInstrBuilder llvm::MachineIRBuilder::buildCTTZ	(	const DstOp &	Dst,
		const SrcOp &	Src0
	)

inline

Build and insert Res = G_CTTZ Op0, Src0.

Definition at line 1353 of file MachineIRBuilder.h.

◆ buildCTTZ_ZERO_UNDEF()

MachineInstrBuilder llvm::MachineIRBuilder::buildCTTZ_ZERO_UNDEF	(	const DstOp &	Dst,
		const SrcOp &	Src0
	)

inline

Build and insert Res = G_CTTZ_ZERO_UNDEF Op0, Src0.

Definition at line 1358 of file MachineIRBuilder.h.

◆ buildDbgLabel()

MachineInstrBuilder MachineIRBuilder::buildDbgLabel ( const MDNode * Label )

Build and insert a DBG_LABEL instructions specifying that Label is given.

Convert "llvm.dbg.label Label" to "DBG_LABEL Label".

Definition at line 162 of file MachineIRBuilder.cpp.

References assert(), buildInstr(), and llvm::MachineIRBuilderState::DL.

Referenced by getOffsetFromIndices().

◆ buildDirectDbgValue()

MachineInstrBuilder MachineIRBuilder::buildDirectDbgValue	(	Register	Reg,
		const MDNode *	Variable,
		const MDNode *	Expr
	)

Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Reg (suitably modified by Expr).

Definition at line 90 of file MachineIRBuilder.cpp.

References assert(), llvm::BuildMI(), getDL(), getMF(), getTII(), and insertInstr().

Referenced by getOffsetFromIndices().

◆ buildDynStackAlloc()

MachineInstrBuilder MachineIRBuilder::buildDynStackAlloc	(	const DstOp &	Res,
		const SrcOp &	Size,
		unsigned	Align
	)

Build and insert Res = G_DYN_STACKALLOC Size, Align.

G_DYN_STACKALLOC does a dynamic stack allocation and writes the address of the allocated memory into Res.

Precondition: setBasicBlock or setMI must have been called.; Res must be a generic virtual register with pointer type.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 171 of file MachineIRBuilder.cpp.

References llvm::DstOp::addDefToMIB(), llvm::SrcOp::addSrcToMIB(), assert(), buildInstr(), llvm::DstOp::getLLTTy(), getMRI(), and llvm::LLT::isPointer().

Referenced by getOffsetFromIndices().

◆ buildExtOrTrunc()

MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc	(	unsigned	ExtOpc,
		const DstOp &	Res,
		const SrcOp &	Op
	)

Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of Res and Op.

///

Precondition: setBasicBlock or setMI must have been called.; Res must be a generic virtual register with scalar or vector type.; Op must be a generic virtual register with scalar or vector type.

Returns: The newly created instruction.

Definition at line 451 of file MachineIRBuilder.cpp.

References assert(), buildInstr(), llvm::DstOp::getLLTTy(), llvm::SrcOp::getLLTTy(), getMRI(), llvm::LLT::getSizeInBits(), llvm::LLT::isScalar(), and llvm::LLT::isVector().

Referenced by buildAnyExtOrTrunc(), buildSExtOrTrunc(), and buildZExtOrTrunc().

◆ buildExtract()

MachineInstrBuilder MachineIRBuilder::buildExtract	(	const DstOp &	Res,
		const SrcOp &	Src,
		uint64_t	Index
	)

Build and insert `Res0, ...

= G_EXTRACT Src, Idx0`.

Precondition: setBasicBlock or setMI must have been called.; Res and Src must be generic virtual registers.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 510 of file MachineIRBuilder.cpp.

References llvm::DstOp::addDefToMIB(), llvm::SrcOp::addSrcToMIB(), assert(), buildCast(), buildInstr(), llvm::DstOp::getLLTTy(), llvm::SrcOp::getLLTTy(), getMRI(), llvm::LLT::getSizeInBits(), and llvm::LLT::isValid().

Referenced by llvm::AMDGPULegalizerInfo::buildPCRelGlobalAddress(), llvm::LegalizerHelper::fewerElementsVectorBasic(), llvm::LegalizerHelper::fewerElementsVectorBuildVector(), llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast(), llvm::AMDGPULegalizerInfo::legalizeExtractVectorElt(), llvm::AMDGPULegalizerInfo::legalizeGlobalValue(), llvm::LegalizerHelper::legalizeInstrStep(), llvm::AMDGPULegalizerInfo::legalizeIsAddrSpace(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizerHelper::narrowScalarExtract(), llvm::LegalizerHelper::narrowScalarInsert(), packSplitRegsToOrigType(), llvm::LegalizationArtifactCombiner::tryCombineExtract(), llvm::CallLowering::unpackRegs(), and unpackRegsToOrigType().

◆ buildExtractVectorElement()

MachineInstrBuilder MachineIRBuilder::buildExtractVectorElement	(	const DstOp &	Res,
		const SrcOp &	Val,
		const SrcOp &	Idx
	)

Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.

Precondition: setBasicBlock or setMI must have been called.; Res must be a generic virtual register with scalar type.; Val must be a generic virtual register with vector type.; Idx must be a generic virtual register with scalar type.

Returns: The newly created instruction.

Definition at line 737 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by getOffsetFromIndices(), getOtherVRegDef(), and llvm::LegalizerHelper::lowerShuffleVector().

◆ buildFAbs()

MachineInstrBuilder llvm::MachineIRBuilder::buildFAbs	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		Optional< unsigned >	Flags = `None`
	)

inline

Build and insert Res = G_FABS Op0.

Definition at line 1395 of file MachineIRBuilder.h.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFDIVFastIntrin(), and llvm::AMDGPULegalizerInfo::legalizeFrint().

◆ buildFAdd()

MachineInstrBuilder llvm::MachineIRBuilder::buildFAdd	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		const SrcOp &	Src1,
		Optional< unsigned >	Flags = `None`
	)

inline

Build and insert Res = G_FADD Op0, Op1.

Definition at line 1363 of file MachineIRBuilder.h.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFceil(), llvm::AMDGPULegalizerInfo::legalizeFrint(), llvm::AMDGPULegalizerInfo::legalizeITOFP(), and llvm::LegalizerHelper::lowerFMad().

◆ buildFCanonicalize()

MachineInstrBuilder llvm::MachineIRBuilder::buildFCanonicalize	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		Optional< unsigned >	Flags = `None`
	)

inline

Build and insert Dst = G_FCANONICALIZE Src0.

Definition at line 1401 of file MachineIRBuilder.h.

Referenced by llvm::LegalizerHelper::lowerFMinNumMaxNum().

◆ buildFCmp()

MachineInstrBuilder MachineIRBuilder::buildFCmp	(	CmpInst::Predicate	Pred,
		const DstOp &	Res,
		const SrcOp &	Op0,
		const SrcOp &	Op1,
		Optional< unsigned >	Flags = `None`
	)

Build and insert a Res = G_FCMP PredOp0, Op1.

Precondition: setBasicBlock or setMI must have been called.; Res must be a generic virtual register with scalar or vector type. Typically this starts as s1 or <N x="" s1>="">.; Op0 and Op1 must be generic virtual registers with the same number of elements as Res (or scalar, if Res is scalar).; Pred must be a floating-point predicate.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 712 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by llvm::LegalizerHelper::fewerElementsVectorCmp(), llvm::AMDGPULegalizerInfo::legalizeFceil(), llvm::AMDGPULegalizerInfo::legalizeFDIVFastIntrin(), and llvm::LegalizerHelper::lowerFPTOUI().

◆ buildFConstant() [1/3]

MachineInstrBuilder MachineIRBuilder::buildFConstant	(	const DstOp &	Res,
		const ConstantFP &	Val
	)

virtual

Build and insert Res = G_FCONSTANT Val.

G_FCONSTANT is a floating-point constant with the specified size and value.

Precondition: setBasicBlock or setMI must have been called.; Res must be a generic virtual register with scalar type.

Returns: The newly created instruction.

Reimplemented in llvm::CSEMIRBuilder.

Definition at line 314 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addDef(), llvm::DstOp::addDefToMIB(), llvm::MachineInstrBuilder::addFPImm(), assert(), buildInstr(), buildSplatVector(), llvm::DstOp::getLLTTy(), getMRI(), llvm::LLT::getScalarType(), llvm::APFloat::getSemantics(), llvm::LLT::getSizeInBits(), llvm::APFloatBase::getSizeInBits(), llvm::ConstantFP::getValueAPF(), llvm::LLT::isPointer(), and llvm::LLT::isVector().

Referenced by llvm::CSEMIRBuilder::buildFConstant(), buildFConstant(), llvm::MipsLegalizerInfo::legalizeCustom(), llvm::AMDGPULegalizerInfo::legalizeFceil(), llvm::AMDGPULegalizerInfo::legalizeFrint(), llvm::AMDGPULegalizerInfo::legalizeSinCos(), llvm::LegalizerHelper::lower(), and llvm::LegalizerHelper::lowerFPTOUI().

◆ buildFConstant() [2/3]

MachineInstrBuilder MachineIRBuilder::buildFConstant	(	const DstOp &	Res,
		double	Val
	)

Definition at line 345 of file MachineIRBuilder.cpp.

References buildFConstant(), llvm::ConstantFP::get(), llvm::getAPFloatFromSize(), llvm::Function::getContext(), llvm::MachineFunction::getFunction(), llvm::DstOp::getLLTTy(), getMF(), getMRI(), and llvm::LLT::getScalarSizeInBits().

◆ buildFConstant() [3/3]

MachineInstrBuilder MachineIRBuilder::buildFConstant	(	const DstOp &	Res,
		const APFloat &	Val
	)

Definition at line 354 of file MachineIRBuilder.cpp.

References buildFConstant(), llvm::ConstantFP::get(), llvm::Function::getContext(), llvm::MachineFunction::getFunction(), and getMF().

◆ buildFCopysign()

MachineInstrBuilder llvm::MachineIRBuilder::buildFCopysign	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		const SrcOp &	Src1
	)

inline

Build and insert Res = G_FCOPYSIGN Op0, Op1.

Definition at line 1407 of file MachineIRBuilder.h.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFrint().

◆ buildFence()

MachineInstrBuilder MachineIRBuilder::buildFence	(	unsigned	Ordering,
		unsigned	Scope
	)

Build and insert G_FENCE Ordering, Scope.

Definition at line 902 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addImm(), and buildInstr().

Referenced by getOffsetFromIndices().

◆ buildFIDbgValue()

MachineInstrBuilder MachineIRBuilder::buildFIDbgValue	(	int	FI,
		const MDNode *	Variable,
		const MDNode *	Expr
	)

Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in the stack slot specified by FI (suitably modified by Expr).

Definition at line 119 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addMetadata(), llvm::MachineInstrBuilder::addReg(), llvm::DIExpression::append(), assert(), buildInstr(), and getDL().

◆ buildFMA()

MachineInstrBuilder llvm::MachineIRBuilder::buildFMA	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		const SrcOp &	Src1,
		const SrcOp &	Src2
	)

inline

Build and insert Res = G_FMA Op0, Op1, Op2.

Definition at line 1376 of file MachineIRBuilder.h.

◆ buildFMAD()

MachineInstrBuilder llvm::MachineIRBuilder::buildFMAD	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		const SrcOp &	Src1,
		const SrcOp &	Src2,
		Optional< unsigned >	Flags = `None`
	)

inline

Build and insert Res = G_FMAD Op0, Op1, Op2.

Definition at line 1382 of file MachineIRBuilder.h.

◆ buildFMul()

MachineInstrBuilder llvm::MachineIRBuilder::buildFMul	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		const SrcOp &	Src1,
		Optional< unsigned >	Flags = `None`
	)

inline

Definition at line 1268 of file MachineIRBuilder.h.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFastUnsafeFDIV(), llvm::AMDGPULegalizerInfo::legalizeFDIVFastIntrin(), llvm::AMDGPULegalizerInfo::legalizeSinCos(), and llvm::LegalizerHelper::lowerFMad().

◆ buildFNeg()

MachineInstrBuilder llvm::MachineIRBuilder::buildFNeg	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		Optional< unsigned >	Flags = `None`
	)

inline

Build and insert Res = G_FNEG Op0.

Definition at line 1389 of file MachineIRBuilder.h.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFastUnsafeFDIV(), and llvm::LegalizerHelper::lowerSITOFP().

◆ buildFPTOSI()

MachineInstrBuilder llvm::MachineIRBuilder::buildFPTOSI	(	const DstOp &	Dst,
		const SrcOp &	Src0
	)

inline

Build and insert Res = G_FPTOSI Src0.

Definition at line 1428 of file MachineIRBuilder.h.

Referenced by llvm::LegalizerHelper::lowerFPTOUI().

◆ buildFPTOUI()

MachineInstrBuilder llvm::MachineIRBuilder::buildFPTOUI	(	const DstOp &	Dst,
		const SrcOp &	Src0
	)

inline

Build and insert Res = G_FPTOUI Src0.

Definition at line 1423 of file MachineIRBuilder.h.

◆ buildFPTrunc()

MachineInstrBuilder MachineIRBuilder::buildFPTrunc	(	const DstOp &	Res,
		const SrcOp &	Op
	)

Build and insert Res = G_FPTRUNC Op.

G_FPTRUNC converts a floating-point value into one with a smaller type.

Precondition: setBasicBlock or setMI must have been called.; Res must be a generic virtual register with scalar or vector type.; Op must be a generic virtual register with scalar or vector type.; Res must be smaller than Op

Returns: The newly created instruction.

Definition at line 700 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by llvm::MipsLegalizerInfo::legalizeCustom().

◆ buildFrameIndex()

MachineInstrBuilder MachineIRBuilder::buildFrameIndex	(	const DstOp &	Res,
		int	Idx
	)

Build and insert Res = G_FRAME_INDEX Idx.

G_FRAME_INDEX materializes the address of an alloca value or other stack-based object.

Precondition: setBasicBlock or setMI must have been called.; Res must be a generic virtual register with pointer type.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 182 of file MachineIRBuilder.cpp.

References llvm::DstOp::addDefToMIB(), assert(), buildInstr(), llvm::DstOp::getLLTTy(), getMRI(), and llvm::LLT::isPointer().

Referenced by llvm::AArch64CallLowering::AArch64CallLowering(), getOffsetFromIndices(), llvm::MipsCallLowering::lowerFormalArguments(), llvm::X86CallLowering::lowerReturn(), and llvm::ARMCallLowering::lowerReturn().

◆ buildFSub()

MachineInstrBuilder llvm::MachineIRBuilder::buildFSub	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		const SrcOp &	Src1
	)

inline

Build and insert Res = G_FSUB Op0, Op1.

Definition at line 1370 of file MachineIRBuilder.h.

Referenced by llvm::MipsLegalizerInfo::legalizeCustom(), llvm::AMDGPULegalizerInfo::legalizeFrint(), and llvm::LegalizerHelper::lowerFPTOUI().

◆ buildGEP()

MachineInstrBuilder MachineIRBuilder::buildGEP	(	const DstOp &	Res,
		const SrcOp &	Op0,
		const SrcOp &	Op1
	)

Build and insert Res = G_GEP Op0, Op1.

G_GEP adds Op1 bytes to the pointer specified by Op0, storing the resulting pointer in Res.

Precondition: setBasicBlock or setMI must have been called.; Res and Op0 must be generic virtual registers with pointer type.; Op1 must be a generic virtual register with scalar type.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 222 of file MachineIRBuilder.cpp.

References assert(), buildInstr(), llvm::DstOp::getLLTTy(), llvm::SrcOp::getLLTTy(), getMRI(), llvm::LLT::isPointer(), and llvm::LLT::isScalar().

Referenced by llvm::AArch64CallLowering::AArch64CallLowering(), getMemsetValue(), getOffsetFromIndices(), isSupportedType(), llvm::AMDGPULegalizerInfo::legalizeImplicitArgPtr(), llvm::AArch64LegalizerInfo::legalizeIntrinsic(), llvm::LegalizerHelper::lower(), llvm::AMDGPUCallLowering::lowerReturn(), materializeGEP(), and llvm::X86CallLowering::X86CallLowering().

◆ buildGlobalValue()

MachineInstrBuilder MachineIRBuilder::buildGlobalValue	(	const DstOp &	Res,
		const GlobalValue *	GV
	)

Build and insert Res = G_GLOBAL_VALUE GV.

G_GLOBAL_VALUE materializes the address of the specified global into Res.

Precondition: setBasicBlock or setMI must have been called.; Res must be a generic virtual register with pointer type in the same address space as GV.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 191 of file MachineIRBuilder.cpp.

References llvm::DstOp::addDefToMIB(), assert(), buildInstr(), llvm::LLT::getAddressSpace(), llvm::PointerType::getAddressSpace(), llvm::DstOp::getLLTTy(), getMRI(), llvm::GlobalValue::getType(), and llvm::LLT::isPointer().

Referenced by llvm::MipsCallLowering::lowerCall().

◆ buildICmp()

MachineInstrBuilder MachineIRBuilder::buildICmp	(	CmpInst::Predicate	Pred,
		const DstOp &	Res,
		const SrcOp &	Op0,
		const SrcOp &	Op1
	)

Build and insert a Res = G_ICMP Pred, Op0, Op1.

Precondition: setBasicBlock or setMI must have been called.; Res must be a generic virtual register with scalar or vector type. Typically this starts as s1 or <N x="" s1>="">.; Op0 and Op1 must be generic virtual registers with the same number of elements as Res. If Res is a scalar, Op0 must be either a scalar or pointer.; Pred must be an integer predicate.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 705 of file MachineIRBuilder.cpp.

References buildInstr().

◆ buildIndirectDbgValue()

MachineInstrBuilder MachineIRBuilder::buildIndirectDbgValue	(	Register	Reg,
		const MDNode *	Variable,
		const MDNode *	Expr
	)

Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in memory at Reg (suitably modified by Expr).

Definition at line 103 of file MachineIRBuilder.cpp.

References llvm::DIExpression::append(), assert(), llvm::BuildMI(), getDL(), getMF(), getTII(), and insertInstr().

Referenced by getOffsetFromIndices().

◆ buildInsert()

MachineInstrBuilder MachineIRBuilder::buildInsert	(	Register	Res,
		Register	Src,
		Register	Op,
		unsigned	Index
	)

Definition at line 653 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addUse(), assert(), buildCast(), buildInstr(), getMRI(), llvm::getSizeInBits(), and getType().

Referenced by buildSequence(), llvm::LegalizerHelper::fewerElementsVectorBasic(), getGCDType(), llvm::AMDGPULegalizerInfo::legalizeInsertVectorElt(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizerHelper::narrowScalarInsert(), llvm::CallLowering::packRegs(), and unpackRegsToOrigType().

◆ buildInsertVectorElement()

MachineInstrBuilder MachineIRBuilder::buildInsertVectorElement	(	const DstOp &	Res,
		const SrcOp &	Val,
		const SrcOp &	Elt,
		const SrcOp &	Idx
	)

Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.

Precondition: setBasicBlock or setMI must have been called.; Res and Val must be a generic virtual register; Elt and Idx must be a generic virtual register with scalar type.

Returns: The newly created instruction.

Definition at line 731 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by getOffsetFromIndices().

◆ buildInstr() [1/2]

MachineInstrBuilder MachineIRBuilder::buildInstr ( unsigned Opcode )

Build and insert <empty> = Opcode <empty>.

The insertion point is the one set by the last call of either setBasicBlock or setMI.

Precondition: setBasicBlock or setMI must have been called.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 74 of file MachineIRBuilder.cpp.

References buildInstrNoInsert(), and insertInstr().

◆ buildInstr() [2/2]

MachineInstrBuilder MachineIRBuilder::buildInstr	(	unsigned	Opc,
		ArrayRef< DstOp >	DstOps,
		ArrayRef< SrcOp >	SrcOps,
		Optional< unsigned >	Flags = `None`
	)

virtual

◆ buildInstrNoInsert()

MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert ( unsigned Opcode )

Build but don't insert <empty> = Opcode <empty>.

Precondition: setMF, setBasicBlock or setMI must have been called.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 78 of file MachineIRBuilder.cpp.

References llvm::BuildMI(), getDL(), getMF(), and getTII().

Referenced by buildInstr(), llvm::LegalizerHelper::fewerElementsVectorMultiEltType(), llvm::RegBankSelect::getAnalysisUsage(), getCallOpcode(), llvm::X86CallLowering::lowerCall(), llvm::ARMCallLowering::lowerCall(), llvm::AArch64CallLowering::lowerCall(), llvm::MipsCallLowering::lowerCall(), llvm::RISCVCallLowering::lowerReturn(), llvm::X86CallLowering::lowerReturn(), llvm::ARMCallLowering::lowerReturn(), llvm::AArch64CallLowering::lowerReturn(), llvm::AMDGPUCallLowering::lowerReturn(), and llvm::MipsCallLowering::lowerReturn().

◆ buildIntrinsic() [1/2]

MachineInstrBuilder MachineIRBuilder::buildIntrinsic	(	Intrinsic::ID	ID,
		ArrayRef< Register >	Res,
		bool	HasSideEffects
	)

Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS instruction.

Its first operand will be the result register definition unless Reg is NoReg (== 0). The second operand will be the intrinsic's ID.

Callers are expected to add the required definitions and uses afterwards.

Precondition: setBasicBlock or setMI must have been called.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 671 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by extractF64Exponent(), getOffsetFromIndices(), llvm::AMDGPULegalizerInfo::legalizeFastUnsafeFDIV(), llvm::AMDGPULegalizerInfo::legalizeFDIVFastIntrin(), llvm::AMDGPULegalizerInfo::legalizeITOFP(), and llvm::AMDGPULegalizerInfo::legalizeSinCos().

◆ buildIntrinsic() [2/2]

MachineInstrBuilder MachineIRBuilder::buildIntrinsic	(	Intrinsic::ID	ID,
		ArrayRef< DstOp >	Res,
		bool	HasSideEffects
	)

Definition at line 683 of file MachineIRBuilder.cpp.

References buildInstr(), and getMRI().

◆ buildIntToPtr()

MachineInstrBuilder llvm::MachineIRBuilder::buildIntToPtr	(	const DstOp &	Dst,
		const SrcOp &	Src
	)

inline

Build and insert a G_INTTOPTR instruction.

Definition at line 526 of file MachineIRBuilder.h.

Referenced by llvm::LegalizerHelper::narrowScalar().

◆ buildJumpTable()

MachineInstrBuilder MachineIRBuilder::buildJumpTable	(	const LLT	PtrTy,
		unsigned	JTI
	)

Build and insert Res = G_JUMP_TABLE JTI.

G_JUMP_TABLE sets Res to the address of the jump table specified by the jump table index JTI.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 204 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by llvm::IRTranslator::getAnalysisUsage().

◆ buildLoad()

MachineInstrBuilder MachineIRBuilder::buildLoad	(	const DstOp &	Res,
		const SrcOp &	Addr,
		MachineMemOperand &	MMO
	)

Build and insert Res = G_LOAD Addr, MMO.

Loads the value stored at Addr. Puts the result in Res.

Precondition: setBasicBlock or setMI must have been called.; Res must be a generic virtual register.; Addr must be a generic virtual register with pointer type.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 368 of file MachineIRBuilder.cpp.

References buildLoadInstr().

Referenced by llvm::AArch64CallLowering::AArch64CallLowering(), getMemsetValue(), llvm::AMDGPULegalizerInfo::getSegmentAperture(), llvm::MipsCallLowering::MipsHandler::handle(), isSwiftError(), llvm::AMDGPULegalizerInfo::legalizeGlobalValue(), llvm::MipsLegalizerInfo::legalizeIntrinsic(), llvm::AArch64LegalizerInfo::legalizeIntrinsic(), llvm::LegalizerHelper::lower(), llvm::X86CallLowering::lowerReturn(), llvm::ARMCallLowering::lowerReturn(), llvm::AMDGPUCallLowering::lowerReturn(), llvm::LegalizerHelper::narrowScalar(), and llvm::LegalizerHelper::reduceLoadStoreWidth().

◆ buildLoadInstr()

MachineInstrBuilder MachineIRBuilder::buildLoadInstr	(	unsigned	Opcode,
		const DstOp &	Res,
		const SrcOp &	Addr,
		MachineMemOperand &	MMO
	)

Build and insert Res = <opcode> Addr, MMO.

Loads the value stored at Addr. Puts the result in Res.

Precondition: setBasicBlock or setMI must have been called.; Res must be a generic virtual register.; Addr must be a generic virtual register with pointer type.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 374 of file MachineIRBuilder.cpp.

References llvm::DstOp::addDefToMIB(), llvm::SrcOp::addSrcToMIB(), assert(), buildInstr(), llvm::DstOp::getLLTTy(), llvm::SrcOp::getLLTTy(), getMRI(), llvm::LLT::isPointer(), and llvm::LLT::isValid().

Referenced by buildLoad().

◆ buildLShr()

MachineInstrBuilder llvm::MachineIRBuilder::buildLShr	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		const SrcOp &	Src1,
		Optional< unsigned >	Flags = `None`
	)

inline

Definition at line 1280 of file MachineIRBuilder.h.

Referenced by extractDLC(), llvm::AMDGPULegalizerInfo::loadInputValue(), llvm::LegalizerHelper::lower(), llvm::LegalizerHelper::lowerExtract(), llvm::LegalizerHelper::lowerFCopySign(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), llvm::LegalizerHelper::lowerUnmergeValues(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizerHelper::narrowScalarShift(), llvm::LegalizerHelper::narrowScalarShiftByConstant(), and llvm::LegalizerHelper::widenScalar().

◆ buildMerge()

MachineInstrBuilder MachineIRBuilder::buildMerge	(	const DstOp &	Res,
		ArrayRef< Register >	Ops
	)

Build and insert Res = G_MERGE_VALUES Op0, ...

G_MERGE_VALUES combines the input elements contiguously into a larger register.

Precondition: setBasicBlock or setMI must have been called.; The entire register Res (and no more) must be covered by the input registers.; The type of all Ops registers must be identical.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 580 of file MachineIRBuilder.cpp.

References assert(), llvm::ArrayRef< T >::begin(), buildInstr(), and llvm::ArrayRef< T >::end().

Referenced by buildSequence(), getGCDType(), getHalfSizedType(), llvm::CallLowering::handleAssignments(), llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast(), llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), llvm::X86CallLowering::lowerCall(), llvm::X86CallLowering::lowerFormalArguments(), llvm::ARMCallLowering::lowerReturn(), llvm::AArch64CallLowering::lowerReturn(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizerHelper::narrowScalarExtract(), llvm::LegalizerHelper::narrowScalarInsert(), llvm::LegalizerHelper::narrowScalarMul(), llvm::LegalizerHelper::narrowScalarShift(), llvm::LegalizerHelper::narrowScalarShiftByConstant(), packSplitRegsToOrigType(), substituteSimpleCopyRegs(), and llvm::LegalizationArtifactCombiner::tryCombineMerges().

◆ buildMul()

MachineInstrBuilder llvm::MachineIRBuilder::buildMul	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		const SrcOp &	Src1,
		Optional< unsigned >	Flags = `None`
	)

inline

Build and insert Res = G_MUL Op0, Op1.

G_MUL sets Res to the sum of integer parameters Op0 and Op1, truncated to their width.

Precondition: setBasicBlock or setMI must have been called.; Res, Op0 and Op1 must be generic virtual registers with the same (scalar or vector) type).

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 1250 of file MachineIRBuilder.h.

Referenced by getMemsetValue(), getOffsetFromIndices(), llvm::LegalizerHelper::lower(), and llvm::LegalizerHelper::moreElementsVector().

◆ buildNot()

MachineInstrBuilder llvm::MachineIRBuilder::buildNot	(	const DstOp &	Dst,
		const SrcOp &	Src0
	)

inline

Build and insert a bitwise not, NegOne = G_CONSTANT -1 Res = G_OR Op0, NegOne.

Definition at line 1332 of file MachineIRBuilder.h.

References llvm::DstOp::getLLTTy().

Referenced by llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc().

◆ buildOr()

MachineInstrBuilder llvm::MachineIRBuilder::buildOr	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		const SrcOp &	Src1
	)

inline

Build and insert Res = G_OR Op0, Op1.

G_OR sets Res to the bitwise or of integer parameters Op0 and Op1.

Precondition: setBasicBlock or setMI must have been called.; Res, Op0 and Op1 must be generic virtual registers with the same (scalar or vector) type).

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 1318 of file MachineIRBuilder.h.

Referenced by extractDLC(), llvm::ARMLegalizerInfo::legalizeCustom(), llvm::LegalizerHelper::lower(), llvm::LegalizerHelper::lowerFCopySign(), llvm::LegalizerHelper::lowerInsert(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizerHelper::narrowScalarShift(), llvm::LegalizerHelper::narrowScalarShiftByConstant(), and llvm::LegalizerHelper::widenScalar().

◆ buildPtrMask()

MachineInstrBuilder MachineIRBuilder::buildPtrMask	(	const DstOp &	Res,
		const SrcOp &	Op0,
		uint32_t	NumBits
	)

Build and insert Res = G_PTR_MASK Op0, NumBits.

G_PTR_MASK clears the low bits of a pointer operand without destroying its pointer properties. This has the effect of rounding the address down to a specified alignment in bits.

Precondition: setBasicBlock or setMI must have been called.; Res and Op0 must be generic virtual registers with pointer type.; NumBits must be an integer representing the number of low bits to be cleared in Op0.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 248 of file MachineIRBuilder.cpp.

References llvm::DstOp::addDefToMIB(), llvm::SrcOp::addSrcToMIB(), assert(), buildInstr(), llvm::DstOp::getLLTTy(), llvm::SrcOp::getLLTTy(), getMRI(), and llvm::LLT::isPointer().

Referenced by llvm::AArch64LegalizerInfo::legalizeIntrinsic().

◆ buildPtrToInt()

MachineInstrBuilder llvm::MachineIRBuilder::buildPtrToInt	(	const DstOp &	Dst,
		const SrcOp &	Src
	)

inline

Build and insert a G_PTRTOINT instruction.

Definition at line 521 of file MachineIRBuilder.h.

Referenced by llvm::LegalizerHelper::narrowScalar().

◆ buildSelect()

MachineInstrBuilder MachineIRBuilder::buildSelect	(	const DstOp &	Res,
		const SrcOp &	Tst,
		const SrcOp &	Op0,
		const SrcOp &	Op1,
		Optional< unsigned >	Flags = `None`
	)

Build and insert a Res = G_SELECT Tst, Op0, Op1.

Precondition: setBasicBlock or setMI must have been called.; Res, Op0 and Op1 must be generic virtual registers with the same type.; Tst must be a generic virtual register with scalar, pointer or vector type. If vector then it must have the same number of elements as the other parameters.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 721 of file MachineIRBuilder.cpp.

References buildInstr().

◆ buildSequence()

void MachineIRBuilder::buildSequence	(	Register	Res,
		ArrayRef< Register >	Ops,
		ArrayRef< uint64_t >	Indices
	)

Build and insert instructions to put Ops together at the specified p Indices to form a larger register.

If the types of the input registers are uniform and cover the entirity of Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF followed by a sequence of G_INSERT instructions.

Precondition: setBasicBlock or setMI must have been called.; The final element of the sequence must not extend past the end of the destination register.; The bits defined by each Op (derived from index and scalar size) must not overlap.; Indices must be in ascending order of bit position.

Definition at line 535 of file MachineIRBuilder.cpp.

References assert(), llvm::ArrayRef< T >::begin(), buildInsert(), buildMerge(), buildUndef(), llvm::MachineRegisterInfo::createGenericVirtualRegister(), llvm::ArrayRef< T >::empty(), llvm::ArrayRef< T >::end(), getMRI(), llvm::LLT::getSizeInBits(), getType(), llvm::MachineRegisterInfo::getType(), and llvm::ArrayRef< T >::size().

◆ buildSExt()

MachineInstrBuilder MachineIRBuilder::buildSExt	(	const DstOp &	Res,
		const SrcOp &	Op
	)

Build and insert Res = G_SEXT Op.

G_SEXT produces a register of the specified width, with bits 0 to sizeof(Ty) * 8 set to Op. The remaining bits are duplicated from the high bit of Op (i.e. 2s-complement sign extended).

Precondition: setBasicBlock or setMI must have been called.; Res must be a generic virtual register with scalar or vector type.; Op must be a generic virtual register with scalar or vector type.; Op must be smaller than Res

Returns: The newly created instruction.

Definition at line 422 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by llvm::CallLowering::ValueHandler::extendRegister(), llvm::LegalizerHelper::lower(), and llvm::LegalizerHelper::narrowScalar().

◆ buildSExtOrTrunc()

MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc	(	const DstOp &	Res,
		const SrcOp &	Op
	)

Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of Res and Op.

///

Precondition: setBasicBlock or setMI must have been called.; Res must be a generic virtual register with scalar or vector type.; Op must be a generic virtual register with scalar or vector type.

Returns: The newly created instruction.

Definition at line 475 of file MachineIRBuilder.cpp.

References buildExtOrTrunc().

Referenced by extractDLC(), and getOffsetFromIndices().

◆ buildShl()

MachineInstrBuilder llvm::MachineIRBuilder::buildShl	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		const SrcOp &	Src1,
		Optional< unsigned >	Flags = `None`
	)

inline

Definition at line 1274 of file MachineIRBuilder.h.

Referenced by extractDLC(), llvm::LegalizerHelper::lower(), llvm::LegalizerHelper::lowerFCopySign(), llvm::LegalizerHelper::lowerInsert(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizerHelper::narrowScalarShift(), and llvm::LegalizerHelper::narrowScalarShiftByConstant().

◆ buildSITOFP()

MachineInstrBuilder llvm::MachineIRBuilder::buildSITOFP	(	const DstOp &	Dst,
		const SrcOp &	Src0
	)

inline

Build and insert Res = G_SITOFP Src0.

Definition at line 1418 of file MachineIRBuilder.h.

Referenced by llvm::AMDGPULegalizerInfo::legalizeITOFP().

◆ buildSMax()

MachineInstrBuilder llvm::MachineIRBuilder::buildSMax	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		const SrcOp &	Src1
	)

inline

Build and insert Res = G_SMAX Op0, Op1.

Definition at line 1439 of file MachineIRBuilder.h.

◆ buildSMin()

MachineInstrBuilder llvm::MachineIRBuilder::buildSMin	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		const SrcOp &	Src1
	)

inline

Build and insert Res = G_SMIN Op0, Op1.

Definition at line 1433 of file MachineIRBuilder.h.

◆ buildSMulH()

MachineInstrBuilder llvm::MachineIRBuilder::buildSMulH	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		const SrcOp &	Src1,
		Optional< unsigned >	Flags = `None`
	)

inline

Definition at line 1262 of file MachineIRBuilder.h.

◆ buildSplatVector()

MachineInstrBuilder MachineIRBuilder::buildSplatVector	(	const DstOp &	Res,
		const SrcOp &	Src
	)

Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.

Definition at line 628 of file MachineIRBuilder.cpp.

References buildInstr(), llvm::DstOp::getLLTTy(), getMRI(), and llvm::LLT::getNumElements().

Referenced by llvm::CSEMIRBuilder::buildConstant(), buildConstant(), llvm::CSEMIRBuilder::buildFConstant(), and buildFConstant().

◆ buildStore()

MachineInstrBuilder MachineIRBuilder::buildStore	(	const SrcOp &	Val,
		const SrcOp &	Addr,
		MachineMemOperand &	MMO
	)

Build and insert G_STORE Val, Addr, MMO.

Stores the value Val to Addr.

Precondition: setBasicBlock or setMI must have been called.; Val must be a generic virtual register.; Addr must be a generic virtual register with pointer type.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 388 of file MachineIRBuilder.cpp.

References llvm::SrcOp::addSrcToMIB(), assert(), buildInstr(), llvm::SrcOp::getLLTTy(), getMRI(), llvm::LLT::isPointer(), and llvm::LLT::isValid().

Referenced by llvm::AArch64CallLowering::AArch64CallLowering(), getMemsetValue(), getOffsetFromIndices(), isSupportedType(), isSwiftError(), llvm::MipsLegalizerInfo::legalizeIntrinsic(), llvm::AArch64LegalizerInfo::legalizeIntrinsic(), llvm::LegalizerHelper::lower(), llvm::MipsCallLowering::lowerFormalArguments(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizerHelper::reduceLoadStoreWidth(), and llvm::X86CallLowering::X86CallLowering().

◆ buildSub()

MachineInstrBuilder llvm::MachineIRBuilder::buildSub	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		const SrcOp &	Src1,
		Optional< unsigned >	Flags = `None`
	)

inline

Build and insert Res = G_SUB Op0, Op1.

G_SUB sets Res to the sum of integer parameters Op0 and Op1, truncated to their width.

Precondition: setBasicBlock or setMI must have been called.; Res, Op0 and Op1 must be generic virtual registers with the same (scalar or vector) type).

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 1234 of file MachineIRBuilder.h.

Referenced by extractF64Exponent(), llvm::IRTranslator::getAnalysisUsage(), llvm::LegalizerHelper::lower(), llvm::LegalizerHelper::lowerSADDO_SSUBO(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), and llvm::LegalizerHelper::narrowScalarShift().

◆ buildTrunc()

MachineInstrBuilder MachineIRBuilder::buildTrunc	(	const DstOp &	Res,
		const SrcOp &	Op
	)

Build and insert Res = G_TRUNC Op.

G_TRUNC extracts the low bits of a type. For a vector type each element is truncated independently before being packed into the destination.

Precondition: setBasicBlock or setMI must have been called.; Res must be a generic virtual register with scalar or vector type.; Op must be a generic virtual register with scalar or vector type.; Res must be smaller than Op

Returns: The newly created instruction.

Definition at line 695 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by llvm::AArch64CallLowering::AArch64CallLowering(), llvm::CombinerHelper::applyCombineExtendingLoads(), extractDLC(), getMemsetValue(), llvm::CallLowering::handleAssignments(), llvm::ARMLegalizerInfo::legalizeCustom(), llvm::LegalizerHelper::lower(), llvm::LegalizerHelper::lowerExtract(), llvm::LegalizerHelper::lowerFCopySign(), llvm::X86CallLowering::lowerReturn(), llvm::ARMCallLowering::lowerReturn(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), llvm::LegalizerHelper::lowerUnmergeValues(), llvm::LegalizerHelper::narrowScalar(), packSplitRegsToOrigType(), and llvm::LegalizerHelper::widenScalar().

◆ buildUAdde()

MachineInstrBuilder MachineIRBuilder::buildUAdde	(	const DstOp &	Res,
		const DstOp &	CarryOut,
		const SrcOp &	Op0,
		const SrcOp &	Op1,
		const SrcOp &	CarryIn
	)

Build and insert Res, CarryOut = G_UADDE Op0, Op1, CarryIn.

G_UADDE sets Res to Op0 + Op1 + CarryIn (truncated to the bit width) and sets CarryOut to 1 if the result overflowed in unsigned arithmetic.

Precondition: setBasicBlock or setMI must have been called.; Res, Op0 and Op1 must be generic virtual registers with the same scalar type.; CarryOut and CarryIn must be generic virtual registers with the same scalar type (typically s1)

Returns: The newly created instruction.

Definition at line 408 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by llvm::LegalizerHelper::narrowScalar().

◆ buildUAddo()

MachineInstrBuilder MachineIRBuilder::buildUAddo	(	const DstOp &	Res,
		const DstOp &	CarryOut,
		const SrcOp &	Op0,
		const SrcOp &	Op1
	)

Build and insert Res, CarryOut = G_UADDO Op0, Op1.

G_UADDO sets Res to Op0 + Op1 (truncated to the bit width) and sets CarryOut to 1 if the result overflowed in unsigned arithmetic.

Precondition: setBasicBlock or setMI must have been called.; Res, Op0 and Op1 must be generic virtual registers with the same scalar type.; CarryOut must be generic virtual register with scalar type (typically s1)

Returns: The newly created instruction.

Definition at line 401 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by llvm::LegalizerHelper::moreElementsVector(), and llvm::LegalizerHelper::narrowScalar().

◆ buildUITOFP()

MachineInstrBuilder llvm::MachineIRBuilder::buildUITOFP	(	const DstOp &	Dst,
		const SrcOp &	Src0
	)

inline

Build and insert Res = G_UITOFP Src0.

Definition at line 1413 of file MachineIRBuilder.h.

Referenced by llvm::AMDGPULegalizerInfo::legalizeITOFP(), and llvm::LegalizerHelper::lowerSITOFP().

◆ buildUMax()

MachineInstrBuilder llvm::MachineIRBuilder::buildUMax	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		const SrcOp &	Src1
	)

inline

Build and insert Res = G_UMAX Op0, Op1.

Definition at line 1451 of file MachineIRBuilder.h.

References llvm::None.

◆ buildUMin()

MachineInstrBuilder llvm::MachineIRBuilder::buildUMin	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		const SrcOp &	Src1
	)

inline

Build and insert Res = G_UMIN Op0, Op1.

Definition at line 1445 of file MachineIRBuilder.h.

◆ buildUMulH()

MachineInstrBuilder llvm::MachineIRBuilder::buildUMulH	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		const SrcOp &	Src1,
		Optional< unsigned >	Flags = `None`
	)

inline

Definition at line 1256 of file MachineIRBuilder.h.

Referenced by llvm::LegalizerHelper::moreElementsVector().

◆ buildUndef()

MachineInstrBuilder MachineIRBuilder::buildUndef ( const DstOp & Res )

Build and insert Res = IMPLICIT_DEF.

Definition at line 576 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by llvm::CombinerHelper::applyCombineConcatVectors(), buildSequence(), llvm::LegalizerHelper::fewerElementsVectorBasic(), llvm::LegalizerHelper::fewerElementsVectorBuildVector(), llvm::LegalizerHelper::fewerElementsVectorImplicitDef(), getGCDType(), getHalfSizedType(), getOffsetFromIndices(), llvm::AMDGPULegalizerInfo::legalizeExtractVectorElt(), llvm::AMDGPULegalizerInfo::legalizeInsertVectorElt(), llvm::AMDGPUCallLowering::lowerFormalArguments(), llvm::AArch64CallLowering::lowerReturn(), llvm::LegalizerHelper::lowerShuffleVector(), llvm::CombinerHelper::matchCombineConcatVectors(), llvm::CombinerHelper::matchCombineShuffleVector(), llvm::LegalizerHelper::narrowScalar(), llvm::CallLowering::packRegs(), and unpackRegsToOrigType().

◆ buildUnmerge() [1/3]

MachineInstrBuilder MachineIRBuilder::buildUnmerge	(	ArrayRef< LLT >	Res,
		const SrcOp &	Op
	)

Build and insert Res0, ...

= G_UNMERGE_VALUES Op

G_UNMERGE_VALUES splits contiguous bits of the input into multiple

Precondition: setBasicBlock or setMI must have been called.; The entire register Res (and no more) must be covered by the input registers.; The type of all Res registers must be identical.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 590 of file MachineIRBuilder.cpp.

References assert(), llvm::ArrayRef< T >::begin(), buildInstr(), and llvm::ArrayRef< T >::end().

Referenced by buildUnmerge(), llvm::LegalizerHelper::fewerElementsVectorUnmergeValues(), getHalfSizedType(), llvm::CallLowering::handleAssignments(), llvm::AMDGPULegalizerInfo::handleD16VData(), isSupportedType(), llvm::LegalizerHelper::legalizeInstrStep(), llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), llvm::AMDGPULegalizerInfo::legalizeITOFP(), llvm::X86CallLowering::lowerCall(), llvm::X86CallLowering::lowerReturn(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizerHelper::narrowScalarShift(), llvm::LegalizerHelper::narrowScalarShiftByConstant(), substituteSimpleCopyRegs(), llvm::LegalizationArtifactCombiner::tryCombineMerges(), and unpackRegsToOrigType().

◆ buildUnmerge() [2/3]

MachineInstrBuilder MachineIRBuilder::buildUnmerge	(	ArrayRef< Register >	Res,
		const SrcOp &	Op
	)

Definition at line 609 of file MachineIRBuilder.cpp.

References assert(), llvm::ArrayRef< T >::begin(), buildInstr(), and llvm::ArrayRef< T >::end().

◆ buildUnmerge() [3/3]

MachineInstrBuilder MachineIRBuilder::buildUnmerge	(	LLT	Res,
		const SrcOp &	Op
	)

Build and insert an unmerge of Res sized pieces to cover Op.

Definition at line 600 of file MachineIRBuilder.cpp.

References buildUnmerge(), llvm::SrcOp::getLLTTy(), getMRI(), llvm::LLT::getSizeInBits(), I, and llvm::SmallVectorTemplateBase< T >::push_back().

◆ buildXor()

MachineInstrBuilder llvm::MachineIRBuilder::buildXor	(	const DstOp &	Dst,
		const SrcOp &	Src0,
		const SrcOp &	Src1
	)

inline

Build and insert Res = G_XOR Op0, Op1.

Definition at line 1324 of file MachineIRBuilder.h.

Referenced by llvm::LegalizerHelper::lowerFPTOUI(), llvm::LegalizerHelper::lowerSADDO_SSUBO(), llvm::LegalizerHelper::lowerSITOFP(), and llvm::LegalizerHelper::narrowScalar().

◆ buildZExt()

MachineInstrBuilder MachineIRBuilder::buildZExt	(	const DstOp &	Res,
		const SrcOp &	Op
	)

Build and insert Res = G_ZEXT Op.

G_ZEXT produces a register of the specified width, with bits 0 to sizeof(Ty) * 8 set to Op. The remaining bits are 0. For a vector register, each element is extended individually.

Precondition: setBasicBlock or setMI must have been called.; Res must be a generic virtual register with scalar or vector type.; Op must be a generic virtual register with scalar or vector type.; Op must be smaller than Res

Returns: The newly created instruction.

Definition at line 427 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by llvm::CallLowering::ValueHandler::extendRegister(), extractDLC(), llvm::AArch64LegalizerInfo::legalizeIntrinsic(), llvm::LegalizerHelper::lower(), llvm::LegalizerHelper::lowerFCopySign(), llvm::LegalizerHelper::lowerInsert(), llvm::AArch64CallLowering::lowerReturn(), llvm::LegalizerHelper::moreElementsVector(), llvm::LegalizerHelper::narrowScalar(), and llvm::LegalizerHelper::widenScalar().

◆ buildZExtOrTrunc()

MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc	(	const DstOp &	Res,
		const SrcOp &	Op
	)

Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of Res and Op.

///

Precondition: setBasicBlock or setMI must have been called.; Res must be a generic virtual register with scalar or vector type.; Op must be a generic virtual register with scalar or vector type.

Returns: The newly created instruction.

Definition at line 480 of file MachineIRBuilder.cpp.

References buildExtOrTrunc().

Referenced by extractDLC(), llvm::IRTranslator::getAnalysisUsage(), getMemsetValue(), getOffsetFromIndices(), and llvm::LegalizerHelper::widenScalar().

◆ getBoolExtOp()

unsigned MachineIRBuilder::getBoolExtOp	(	bool	IsVec,
		bool	IsFP
	)		const

Returns: The opcode of the extension the target wants to use for boolean values.

Definition at line 432 of file MachineIRBuilder.cpp.

References getMF(), llvm::MachineFunction::getSubtarget(), llvm::TargetSubtargetInfo::getTargetLowering(), llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.

Referenced by buildBoolExt(), and llvm::LegalizerHelper::widenScalar().

◆ getCSEInfo() [1/2]

GISelCSEInfo* llvm::MachineIRBuilder::getCSEInfo ( )

inline

Definition at line 288 of file MachineIRBuilder.h.

References llvm::MachineIRBuilderState::CSEInfo.

Referenced by llvm::CSEMIRBuilder::buildInstr().

◆ getCSEInfo() [2/2]

const GISelCSEInfo* llvm::MachineIRBuilder::getCSEInfo ( ) const

inline

Definition at line 289 of file MachineIRBuilder.h.

References llvm::MachineIRBuilderState::CSEInfo.

◆ getDataLayout()

const DataLayout& llvm::MachineIRBuilder::getDataLayout ( ) const

inline

Definition at line 263 of file MachineIRBuilder.h.

Referenced by getLaneCopyOpcode(), llvm::AMDGPULegalizerInfo::legalizeGlobalValue(), and llvm::LegalizerHelper::narrowScalar().

◆ getDebugLoc()

DebugLoc llvm::MachineIRBuilder::getDebugLoc ( )

inline

Get the current instruction's debug location.

Definition at line 324 of file MachineIRBuilder.h.

References buildGEP(), C, llvm::MachineIRBuilderState::DL, Reg, and Size.

Referenced by getBufferStoreFormatOpcode(), and getOffsetFromIndices().

◆ getDL()

const DebugLoc& llvm::MachineIRBuilder::getDL ( )

inline

Getter for DebugLoc.

Definition at line 268 of file MachineIRBuilder.h.

References llvm::MachineIRBuilderState::DL.

Referenced by buildConstDbgValue(), buildDirectDbgValue(), buildFIDbgValue(), buildIndirectDbgValue(), buildInstrNoInsert(), and getHalfSizedType().

◆ getInsertPt()

MachineBasicBlock::iterator llvm::MachineIRBuilder::getInsertPt ( )

inline

Current insertion point for new instructions.

Definition at line 292 of file MachineIRBuilder.h.

References llvm::MachineIRBuilderState::II, Info, llvm::MachineIRBuilderState::MBB, llvm::MachineIRBuilderState::MF, and llvm::MachineIRBuilderState::Observer.

Referenced by getBufferStoreFormatOpcode(), getOffsetFromIndices(), insertInstr(), llvm::AMDGPULegalizerInfo::loadInputValue(), llvm::LegalizerHelper::narrowScalar(), and llvm::LegalizerHelper::widenScalar().

◆ getMBB() [1/2]

const MachineBasicBlock& llvm::MachineIRBuilder::getMBB ( ) const

inline

Getter for the basic block we currently build.

Definition at line 278 of file MachineIRBuilder.h.

References assert(), and llvm::MachineIRBuilderState::MBB.

Referenced by llvm::AArch64CallLowering::AArch64CallLowering(), allocateHSAUserSGPRs(), changeFCMPPredToAArch64CC(), llvm::IRTranslator::getAnalysisUsage(), getBufferStoreFormatOpcode(), getHalfSizedType(), getOffsetFromIndices(), llvm::MipsCallLowering::MipsHandler::handle(), handleMustTailForwardedRegisters(), insertInstr(), isSwiftError(), llvm::AMDGPULegalizerInfo::loadInputValue(), llvm::X86CallLowering::lowerFormalArguments(), llvm::ARMCallLowering::lowerFormalArguments(), llvm::AArch64CallLowering::lowerFormalArguments(), llvm::AMDGPUCallLowering::lowerFormalArguments(), llvm::MipsCallLowering::lowerFormalArguments(), llvm::X86CallLowering::lowerReturn(), llvm::ARMCallLowering::lowerReturn(), llvm::LegalizerHelper::narrowScalar(), and llvm::LegalizerHelper::widenScalar().

◆ getMBB() [2/2]

MachineBasicBlock& llvm::MachineIRBuilder::getMBB ( )

inline

Definition at line 283 of file MachineIRBuilder.h.

◆ getMF() [1/2]

MachineFunction& llvm::MachineIRBuilder::getMF ( )

inline

Getter for the function we currently build.

Definition at line 253 of file MachineIRBuilder.h.

References assert(), and llvm::MachineIRBuilderState::MF.

◆ getMF() [2/2]

const MachineFunction& llvm::MachineIRBuilder::getMF ( ) const

inline

Definition at line 258 of file MachineIRBuilder.h.

References assert(), and llvm::MachineIRBuilderState::MF.

◆ getMRI() [1/2]

MachineRegisterInfo* llvm::MachineIRBuilder::getMRI ( )

inline

Getter for MRI.

Definition at line 271 of file MachineIRBuilder.h.

References llvm::MachineIRBuilderState::MRI.

Referenced by llvm::AArch64CallLowering::AArch64CallLowering(), buildAtomicCmpXchg(), buildAtomicCmpXchgWithSuccess(), buildAtomicRMW(), buildBlockAddress(), buildBoolExt(), buildBrCond(), buildBrIndirect(), buildBrJT(), buildCast(), llvm::CSEMIRBuilder::buildConstant(), buildConstant(), buildDynStackAlloc(), buildExtOrTrunc(), buildExtract(), llvm::CSEMIRBuilder::buildFConstant(), buildFConstant(), buildFrameIndex(), buildGEP(), buildGlobalValue(), buildInsert(), llvm::ConstantFoldingMIRBuilder::buildInstr(), llvm::CSEMIRBuilder::buildInstr(), buildInstr(), buildIntrinsic(), buildLoadInstr(), llvm::AMDGPULegalizerInfo::buildPCRelGlobalAddress(), buildPtrMask(), buildSequence(), buildSplatVector(), buildStore(), buildUnmerge(), extractDLC(), getBaseWithConstantOffset(), getExtendTypeForInst(), getInsertVecEltOpInfo(), llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappings(), getLaneCopyOpcode(), getMemsetValue(), llvm::MipsCallLowering::MipsHandler::handle(), llvm::CallLowering::handleAssignments(), llvm::AMDGPULegalizerInfo::loadInputValue(), llvm::X86CallLowering::lowerReturn(), llvm::ARMCallLowering::lowerReturn(), materializeGEP(), and llvm::CallLowering::packRegs().

◆ getMRI() [2/2]

const MachineRegisterInfo* llvm::MachineIRBuilder::getMRI ( ) const

inline

Definition at line 272 of file MachineIRBuilder.h.

References llvm::MachineIRBuilderState::MRI.

◆ getState()

MachineIRBuilderState& llvm::MachineIRBuilder::getState ( )

inline

Getter for the State.

Definition at line 275 of file MachineIRBuilder.h.

◆ getTII()

const TargetInstrInfo& llvm::MachineIRBuilder::getTII ( )

inline

Definition at line 247 of file MachineIRBuilder.h.

References assert(), and llvm::MachineIRBuilderState::TII.

Referenced by llvm::CombinerHelper::applyCombineExtendingLoads(), buildDirectDbgValue(), buildIndirectDbgValue(), buildInstrNoInsert(), llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast(), llvm::MipsLegalizerInfo::legalizeCustom(), and SelectMSA3OpIntrinsic().

◆ insertInstr()

MachineInstrBuilder MachineIRBuilder::insertInstr ( MachineInstrBuilder MIB )

Insert an existing instruction at the insertion point.

Definition at line 83 of file MachineIRBuilder.cpp.

References getInsertPt(), getMBB(), llvm::MachineBasicBlock::insert(), and recordInsertion().

Referenced by buildDirectDbgValue(), buildIndirectDbgValue(), buildInstr(), llvm::LegalizerHelper::fewerElementsVectorMultiEltType(), getCallOpcode(), llvm::X86CallLowering::lowerCall(), llvm::ARMCallLowering::lowerCall(), llvm::AArch64CallLowering::lowerCall(), llvm::RISCVCallLowering::lowerReturn(), llvm::X86CallLowering::lowerReturn(), llvm::ARMCallLowering::lowerReturn(), llvm::AArch64CallLowering::lowerReturn(), llvm::AMDGPUCallLowering::lowerReturn(), and llvm::MipsCallLowering::lowerReturn().

◆ materializeGEP()

Optional< MachineInstrBuilder > MachineIRBuilder::materializeGEP	(	Register &	Res,
		Register	Op0,
		const LLT &	ValueTy,
		uint64_t	Value
	)

Materialize and insert Res = G_GEP Op0, (G_CONSTANT Value)

G_GEP adds Value bytes to the pointer specified by Op0, storing the resulting pointer in Res. If Value is zero then no G_GEP or G_CONSTANT will be created and

Precondition: Op0 will be assigned to Res.; setBasicBlock or setMI must have been called.; Op0 must be a generic virtual register with pointer type.; ValueTy must be a scalar type.; Res must be 0. This is to detect confusion between materializeGEP() and buildGEP().

Postcondition: Res will either be a new generic virtual register of the same type as Op0 or Op0 itself.

Returns: a MachineInstrBuilder for the newly created instruction.

Definition at line 233 of file MachineIRBuilder.cpp.

References assert(), buildConstant(), buildGEP(), llvm::MachineRegisterInfo::createGenericVirtualRegister(), getMRI(), getType(), llvm::LLT::isScalar(), and llvm::None.

Referenced by llvm::AMDGPULegalizerInfo::getSegmentAperture(), isSwiftError(), and llvm::LegalizerHelper::reduceLoadStoreWidth().

◆ recordInsertion()

void MachineIRBuilder::recordInsertion ( MachineInstr * MI ) const

protected

Definition at line 59 of file MachineIRBuilder.cpp.

References llvm::GISelChangeObserver::createdInstr(), and llvm::MachineIRBuilderState::Observer.

Referenced by insertInstr().

◆ setChangeObserver()

void MachineIRBuilder::setChangeObserver ( GISelChangeObserver & Observer )

Definition at line 64 of file MachineIRBuilder.cpp.

References llvm::MachineIRBuilderState::Observer.

Referenced by getOtherVRegDef(), and llvm::LegalizerHelper::LegalizerHelper().

◆ setCSEInfo()

void MachineIRBuilder::setCSEInfo ( GISelCSEInfo * Info )

Definition at line 49 of file MachineIRBuilder.cpp.

References llvm::MachineIRBuilderState::CSEInfo, and Info.

◆ setDebugLoc()

void llvm::MachineIRBuilder::setDebugLoc ( const DebugLoc & DL )

inline

Set the debug location to DL for all the next build instructions.

Definition at line 321 of file MachineIRBuilder.h.

References llvm::MachineIRBuilderState::DL.

Referenced by llvm::IRTranslator::getAnalysisUsage().

◆ setInsertPt()

void MachineIRBuilder::setInsertPt	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	II
	)

Set the insertion point before the specified position.

Precondition: MBB must be in getMF().; II must be a valid iterator in MBB.

Definition at line 51 of file MachineIRBuilder.cpp.

References assert(), getMF(), llvm::MachineBasicBlock::getParent(), llvm::MachineIRBuilderState::II, and llvm::MachineIRBuilderState::MBB.

Referenced by llvm::CombinerHelper::applyCombineConcatVectors(), llvm::CombinerHelper::applyCombineExtendingLoads(), llvm::CombinerHelper::applyCombineShuffleVector(), changeFCMPPredToAArch64CC(), llvm::LegalizerHelper::fewerElementsVectorPhi(), getBufferStoreFormatOpcode(), getHalfSizedType(), getOtherVRegDef(), llvm::AMDGPULegalizerInfo::loadInputValue(), llvm::CombinerHelper::matchCombineConcatVectors(), llvm::CombinerHelper::matchCombineShuffleVector(), llvm::LegalizerHelper::moreElementsVectorPhi(), llvm::LegalizerHelper::narrowScalar(), and llvm::LegalizerHelper::widenScalar().

◆ setInstr()

void MachineIRBuilder::setInstr ( MachineInstr & MI )

Set the insertion point to before MI.

Precondition: MI must be in getMF().

Definition at line 43 of file MachineIRBuilder.cpp.

References assert(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getParent(), llvm::MachineIRBuilderState::II, and setMBB().

◆ setMBB()

void MachineIRBuilder::setMBB ( MachineBasicBlock & MBB )

Set the insertion point to the end of MBB.

Precondition: MBB must be contained by getMF().

Definition at line 36 of file MachineIRBuilder.cpp.

References assert(), llvm::MachineBasicBlock::end(), getMF(), llvm::MachineBasicBlock::getParent(), llvm::MachineIRBuilderState::II, and llvm::MachineIRBuilderState::MBB.

Referenced by llvm::IRTranslator::getAnalysisUsage(), getHalfSizedType(), llvm::AMDGPULegalizerInfo::legalizeFMad(), llvm::X86CallLowering::lowerFormalArguments(), llvm::ARMCallLowering::lowerFormalArguments(), llvm::AArch64CallLowering::lowerFormalArguments(), llvm::AMDGPUCallLowering::lowerFormalArguments(), llvm::RegBankSelect::runOnMachineFunction(), and setInstr().

◆ setMF()

void MachineIRBuilder::setMF ( MachineFunction & MF )

Definition at line 26 of file MachineIRBuilder.cpp.

References llvm::MachineIRBuilderState::DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineIRBuilderState::II, llvm::MachineIRBuilderState::MBB, llvm::MachineIRBuilderState::MF, llvm::MachineIRBuilderState::MRI, llvm::MachineIRBuilderState::Observer, and llvm::MachineIRBuilderState::TII.

Referenced by INITIALIZE_PASS_END(), and llvm::LegalizerHelper::LegalizerHelper().

◆ stopObservingChanges()

void MachineIRBuilder::stopObservingChanges ( )

Definition at line 68 of file MachineIRBuilder.cpp.

References llvm::MachineIRBuilderState::Observer.

◆ validateBinaryOp()

void MachineIRBuilder::validateBinaryOp	(	const LLT &	Res,
		const LLT &	Op0,
		const LLT &	Op1
	)

protected

Definition at line 210 of file MachineIRBuilder.cpp.

References assert(), llvm::LLT::isScalar(), and llvm::LLT::isVector().

Referenced by buildInstr().

◆ validateSelectOp()

void MachineIRBuilder::validateSelectOp	(	const LLT &	ResTy,
		const LLT &	TstTy,
		const LLT &	Op0Ty,
		const LLT &	Op1Ty
	)

protected

Definition at line 936 of file MachineIRBuilder.cpp.

References assert(), llvm::LLT::getNumElements(), llvm::LLT::isPointer(), llvm::LLT::isScalar(), and llvm::LLT::isVector().

Referenced by buildInstr().

◆ validateShiftOp()

void MachineIRBuilder::validateShiftOp	(	const LLT &	Res,
		const LLT &	Op0,
		const LLT &	Op1
	)

protected

Definition at line 216 of file MachineIRBuilder.cpp.

References assert(), llvm::LLT::isScalar(), and llvm::LLT::isVector().

Referenced by buildInstr().

◆ validateTruncExt()

void MachineIRBuilder::validateTruncExt	(	const LLT &	Dst,
		const LLT &	Src,
		bool	IsExtend
	)

protected

Definition at line 917 of file MachineIRBuilder.cpp.

References assert(), llvm::LLT::getNumElements(), llvm::LLT::getSizeInBits(), llvm::LLT::isScalar(), and llvm::LLT::isVector().

Referenced by buildInstr().

The documentation for this class was generated from the following files:

include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

Public Member Functions

Protected Member Functions

Detailed Description

Constructor & Destructor Documentation

◆ MachineIRBuilder() [1/4]

◆ MachineIRBuilder() [2/4]

◆ MachineIRBuilder() [3/4]

◆ ~MachineIRBuilder()

◆ MachineIRBuilder() [4/4]

Member Function Documentation

◆ buildAdd()

◆ buildAddrSpaceCast()

◆ buildAnd()

◆ buildAnyExt()

◆ buildAnyExtOrTrunc()

◆ buildAShr()

◆ buildAtomicCmpXchg()

◆ buildAtomicCmpXchgWithSuccess()

◆ buildAtomicRMW()

◆ buildAtomicRMWAdd()

◆ buildAtomicRMWAnd()

◆ buildAtomicRMWFAdd()

◆ buildAtomicRMWFSub()

◆ buildAtomicRMWMax()

◆ buildAtomicRMWMin()

◆ buildAtomicRMWNand()

◆ buildAtomicRMWOr()

◆ buildAtomicRMWSub()

◆ buildAtomicRMWUmax()

◆ buildAtomicRMWUmin()

◆ buildAtomicRMWXchg()

◆ buildAtomicRMWXor()

◆ buildBitcast()

◆ buildBlockAddress()

◆ buildBoolExt()

◆ buildBr()

◆ buildBrCond()

◆ buildBrIndirect()

◆ buildBrJT()

◆ buildBuildVector()

◆ buildBuildVectorTrunc()

◆ buildCast()

◆ buildConcatVectors()

◆ buildConstant() [1/3]

◆ buildConstant() [2/3]

◆ buildConstant() [3/3]

◆ buildConstDbgValue()

◆ buildCopy()

◆ buildCTLZ()

◆ buildCTLZ_ZERO_UNDEF()

◆ buildCTPOP()

◆ buildCTTZ()

◆ buildCTTZ_ZERO_UNDEF()

◆ buildDbgLabel()

◆ buildDirectDbgValue()

◆ buildDynStackAlloc()

◆ buildExtOrTrunc()

◆ buildExtract()

◆ buildExtractVectorElement()

◆ buildFAbs()

◆ buildFAdd()

◆ buildFCanonicalize()

◆ buildFCmp()

◆ buildFConstant() [1/3]

◆ buildFConstant() [2/3]

◆ buildFConstant() [3/3]

◆ buildFCopysign()

◆ buildFence()

◆ buildFIDbgValue()

◆ buildFMA()

◆ buildFMAD()

◆ buildFMul()

◆ buildFNeg()

◆ buildFPTOSI()

◆ buildFPTOUI()

◆ buildFPTrunc()

◆ buildFrameIndex()

◆ buildFSub()

◆ buildGEP()

◆ buildGlobalValue()