LLVM  10.0.0svn
Public Member Functions | Friends | List of all members
llvm::SDValue Class Reference

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation. More...

#include "llvm/CodeGen/SelectionDAGNodes.h"

Public Member Functions

 SDValue ()=default
 
 SDValue (SDNode *node, unsigned resno)
 
unsigned getResNo () const
 get the index which selects a specific result in the SDNode More...
 
SDNodegetNode () const
 get the SDNode which holds the desired result More...
 
void setNode (SDNode *N)
 set the SDNode More...
 
SDNodeoperator-> () const
 
bool operator== (const SDValue &O) const
 
bool operator!= (const SDValue &O) const
 
bool operator< (const SDValue &O) const
 
 operator bool () const
 
SDValue getValue (unsigned R) const
 
bool isOperandOf (const SDNode *N) const
 Return true if this node is an operand of N. More...
 
EVT getValueType () const
 Return the ValueType of the referenced return value. More...
 
MVT getSimpleValueType () const
 Return the simple ValueType of the referenced return value. More...
 
unsigned getValueSizeInBits () const
 Returns the size of the value in bits. More...
 
unsigned getScalarValueSizeInBits () const
 
unsigned getOpcode () const
 
unsigned getNumOperands () const
 
const SDValuegetOperand (unsigned i) const
 
uint64_t getConstantOperandVal (unsigned i) const
 
const APIntgetConstantOperandAPInt (unsigned i) const
 
bool isTargetMemoryOpcode () const
 
bool isTargetOpcode () const
 
bool isMachineOpcode () const
 
bool isUndef () const
 
unsigned getMachineOpcode () const
 
const DebugLocgetDebugLoc () const
 
void dump () const
 
void dump (const SelectionDAG *G) const
 
void dumpr () const
 
void dumpr (const SelectionDAG *G) const
 
bool reachesChainWithoutSideEffects (SDValue Dest, unsigned Depth=2) const
 Return true if this operand (which must be a chain) reaches the specified operand without crossing any side-effecting instructions. More...
 
bool use_empty () const
 Return true if there are no nodes using value ResNo of Node. More...
 
bool hasOneUse () const
 Return true if there is exactly one node using value ResNo of Node. More...
 

Friends

struct DenseMapInfo< SDValue >
 

Detailed Description

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

Many nodes return multiple values, from loads (which define a token and a return value) to ADDC (which returns a result and a carry value), to calls (which may return an arbitrary number of values).

As such, each use of a SelectionDAG computation must indicate the node that computes it as well as which return value to use from that node. This pair of information is represented with the SDValue value type.

Definition at line 123 of file SelectionDAGNodes.h.

Constructor & Destructor Documentation

◆ SDValue() [1/2]

llvm::SDValue::SDValue ( )
default

◆ SDValue() [2/2]

llvm::SDValue::SDValue ( SDNode node,
unsigned  resno 
)
inline

Definition at line 1148 of file SelectionDAGNodes.h.

References assert().

Member Function Documentation

◆ dump() [1/2]

void llvm::SDValue::dump ( ) const
inline

◆ dump() [2/2]

void llvm::SDValue::dump ( const SelectionDAG G) const
inline

Definition at line 1218 of file SelectionDAGNodes.h.

References Node::dump().

◆ dumpr() [1/2]

void llvm::SDValue::dumpr ( ) const
inline

Definition at line 1222 of file SelectionDAGNodes.h.

◆ dumpr() [2/2]

void llvm::SDValue::dumpr ( const SelectionDAG G) const
inline

Definition at line 1226 of file SelectionDAGNodes.h.

References llvm::SDNode::addUse(), getNode(), N, and setNode().

◆ getConstantOperandAPInt()

const APInt & llvm::SDValue::getConstantOperandAPInt ( unsigned  i) const
inline

◆ getConstantOperandVal()

uint64_t llvm::SDValue::getConstantOperandVal ( unsigned  i) const
inline

Definition at line 1174 of file SelectionDAGNodes.h.

Referenced by callingConvSupported(), checkBoolTestSetCCCombine(), combineAddOrSubToADCOrSBB(), combineAnd(), combineCarryThroughADD(), combineCompareEqual(), combineConcatVectorOfExtracts(), combineInsertSubvector(), combineTargetShuffle(), combineX86ShuffleChainWithExtract(), llvm::SelectionDAG::computeKnownBits(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::SelectionDAG::ComputeNumSignBits(), EmitKORTEST(), findEltLoadSrc(), foldCONCAT_VECTORS(), FoldIntToFPToInt(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), getFauxShuffleMask(), llvm::SelectionDAG::getNode(), getPermuteMask(), getPowerOf2Factor(), getTargetShuffleMask(), getVPermMask(), gwsIntrinToOpcode(), llvm::SelectionDAG::InferPtrAlignment(), isCalleeLoad(), isHopBuildVector(), isTargetConstant(), lowerAddSubToHorizontalOp(), LowerAsSplatVectorLoad(), LowerATOMIC_FENCE(), LowerBuildVectorv4x32(), LowerFRAMEADDR(), LowerINTRINSIC_W_CHAIN(), LowerRETURNADDR(), mayTailCallThisCC(), mayUseP9Setb(), narrowExtractedVectorLoad(), parseTexFail(), PeepholePPC64ZExtGather(), PrepareCall(), recoverFramePointer(), reduceBuildVecToShuffleWithZero(), scalarizeExtractedBinop(), selectI64Imm(), llvm::AArch64TargetLowering::shouldReduceLoadWidth(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), simplifyShuffleOfShuffle(), vectorizeExtractedCast(), and willShiftRightEliminate().

◆ getDebugLoc()

const DebugLoc & llvm::SDValue::getDebugLoc ( ) const
inline

Definition at line 1210 of file SelectionDAGNodes.h.

Referenced by llvm::SITargetLowering::shouldEmitPCReloc().

◆ getMachineOpcode()

unsigned llvm::SDValue::getMachineOpcode ( ) const
inline

◆ getNode()

SDNode* llvm::SDValue::getNode ( ) const
inline

get the SDNode which holds the desired result

Definition at line 137 of file SelectionDAGNodes.h.

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64bitMLAL(), AddCombineTo64BitSMLAL16(), AddCombineTo64bitUMAAL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), llvm::DOTGraphTraits< SelectionDAG * >::addCustomGraphFeatures(), AddGlue(), AddNodeIDOperands(), addStackMapLiveVars(), llvm::AMDGPUTargetLowering::addTokenForArgument(), llvm::analyzeArguments(), AnalyzeReturnValues(), BuildExactSDIV(), buildFromShuffleMostly(), llvm::TargetLowering::BuildSDIV(), llvm::PPCTargetLowering::BuildSDIVPow2(), llvm::TargetLowering::BuildUDIV(), calculateByteProvider(), CalculateTailCallArgDest(), callingConvSupported(), canChangeToInt(), canEnableCoalescing(), canFoldInAddressingMode(), CC_Lanai32_VarArg(), CC_RISCV_FastCC(), llvm::ARMTargetLowering::CCAssignFnForReturn(), llvm::checkForCycles(), checkForCyclesHelper(), CheckForMaskedLoad(), checkHighLaneIndex(), checkV64LaneV128(), checkValueWidth(), ChooseConstraint(), combineADDCARRYDiamond(), combineAddOrSubToADCOrSBB(), combineADDToADDZE(), combineAnd(), combineAndnp(), CombineANDShift(), CombineBaseUpdate(), combineBitcast(), combineBVOfVecSExt(), combineCarryThroughADD(), combineCastedMaskArithmetic(), combineCCMask(), combineConcatVectorOfExtracts(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineExtInVec(), combineExtractSubvector(), combineInsertSubvector(), combineLogicBlendIntoConditionalNegate(), combineLoopMAddPattern(), combineMaskedLoadConstantMask(), combineMaskedStore(), combineMOVMSK(), combineMul(), combineOrCmpEqZeroToCtlzSrl(), combinePMULDQ(), combinePMULH(), combineRedundantDWordShuffle(), combineSelectAndUse(), combineSelectAndUseCommutative(), combineSetCC(), combineSetCCAtomicArith(), combineSextInRegCmov(), combineShiftAnd1ToBitTest(), combineShiftOfShiftedLogic(), combineShuffle(), combineShuffleOfScalars(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineToExtendCMOV(), combineTruncatedArithmetic(), combineVectorPack(), combineVectorShiftImm(), combineVectorShiftVar(), CombineVLDDUP(), combinevXi1ConstantToInteger(), combineX86INT_TO_FP(), combineX86ShufflesRecursively(), llvm::TargetLowering::DAGCombinerInfo::CommitTargetLoweringOpt(), llvm::BaseIndexOffset::computeAliasing(), llvm::TargetLowering::ComputeConstraintToUse(), llvm::SelectionDAG::computeKnownBits(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), computeZeroableShuffleElements(), ConstantBuildVector(), ConvertI1VectorToInteger(), convertShiftLeftToScale(), createBSWAPShuffleMask(), createGPRPairNode(), llvm::createMSP430ISelDag(), llvm::createR600ISelDag(), llvm::X86TargetLowering::decomposeMulByConstant(), detectSSatPattern(), detectUSatPattern(), dumpr(), EltsFromConsecutiveLoads(), emitConjunctionRec(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), emitIntrinsicWithCC(), emitIntrinsicWithCCAndChain(), EmitKORTEST(), EmitTest(), EmitVectorComparison(), llvm::BaseIndexOffset::equalBaseIndex(), Expand64BitShift(), ExpandBVWithShuffles(), expandIntrinsicWChainHelper(), llvm::TargetLowering::expandMUL_LOHI(), ExpandPowI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), ExtendToType(), ExtendUsesToFormExtLoad(), ExtractBitFromMaskVector(), extractBooleanFlip(), FindBFIToCombineWith(), findConsecutiveLoad(), findEltLoadSrc(), findMatchingInlineAsmOperand(), findMemSDNode(), findUnwindDestinations(), findUser(), FixedPointIntrinsicToOpcode(), foldAddSubOfSignBit(), foldBitcastedFPLogic(), llvm::SelectionDAG::foldConstantFPMath(), foldExtendedSignBitTest(), FoldIntToFPToInt(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), foldShuffleOfHorizOp(), foldVectorXorShiftIntoCmp(), fp16SrcZerosHighBits(), generateEquivalentSub(), GenerateTBL(), llvm::PPC::get_VSPLTI_elt(), getAArch64Cmp(), getAL(), getARClassRegisterMask(), getAsCarry(), getAVX2GatherNode(), getBuildPairElt(), llvm::SelectionDAG::getCALLSEQ_END(), getCCResult(), getContiguousRangeOfSetBits(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::DAGTypeLegalizer::getDAG(), llvm::SelectionDAG::GetDemandedBits(), getDUPLANEOp(), getFauxShuffleMask(), GetFPLibCall(), getGatherNode(), getGeneralPermuteNode(), llvm::MipsDAGToDAGISel::getGlobalBaseReg(), llvm::DenseMapInfo< SDValue >::getHashValue(), getHopForBuildVector(), getInputChainForNode(), getIPMConversion(), llvm::XCoreTargetLowering::getJumpTableEncoding(), getLoadExtOrTrunc(), getMemCmpLoad(), llvm::SelectionDAG::getMemcpy(), getMemcpyLoadsAndStores(), llvm::SelectionDAG::getMemmove(), llvm::SelectionDAG::getMemset(), getMOVL(), llvm::X86TargetLowering::getNegatedExpression(), llvm::SDUse::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAGBuilder::getNonRegisterValue(), getNormalLoadInput(), llvm::MipsTargetLowering::getOpndList(), getPermuteMask(), llvm::HexagonTargetLowering::getPostIndexedAddressParts(), getPowerOf2Factor(), llvm::HexagonTargetLowering::getPreferredVectorAction(), llvm::ARMTargetLowering::getPreIndexedAddressParts(), llvm::PPCTargetLowering::getPreIndexedAddressParts(), getPromotedVectorElementType(), GetPromotionOpcode(), getPSHUFShuffleMask(), getPTXCmpMode(), getReductionSDNode(), llvm::AVRTargetLowering::getSetCCResultType(), getShiftAmountTyForConstant(), getShuffleScalarElt(), llvm::simplify_type< SDValue >::getSimplifiedValue(), llvm::simplify_type< const SDValue >::getSimplifiedValue(), getSPDenormModeValue(), llvm::ARCTargetLowering::getTargetNodeName(), getTargetShuffleAndZeroables(), getTargetVShiftByConstNode(), getUnderlyingArgRegs(), getUniformBase(), llvm::SelectionDAGISel::getUninvalidatedNodeId(), getUsefulBitsFromAndWithImmediate(), getUsefulBitsFromBFM(), getUsefulBitsFromOrWithShiftedReg(), getUsefulBitsFromUBFM(), llvm::SelectionDAGBuilder::getValue(), llvm::SelectionDAGBuilder::getValueImpl(), GetVBR(), getVectorCompareInfo(), getVPTESTMOpc(), getVShiftImm(), getZeroVector(), gwsIntrinToOpcode(), llvm::SelectionDAGBuilder::handleDebugValue(), hasNormalLoadOperand(), hasSingleUsesFromRoot(), haveEfficientBuildVectorPattern(), incDecVectorConstant(), llvm::SelectionDAG::InferPtrAlignment(), insert1BitVector(), InsertBitToMaskVector(), insertDAGNode(), isADDADDMUL(), isAddSubSExt(), isAddSubZExt(), isAnyConstantBuildVector(), isBitfieldExtractOp(), isBitfieldExtractOpFromAnd(), isBitfieldExtractOpFromSExtInReg(), isBitfieldExtractOpFromShr(), isBitfieldPositioningOp(), isBLACompatibleAddress(), isBSwapHWordElement(), isBSwapHWordPair(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), isCalleeLoad(), isClampZeroToOne(), isConsecutiveLSLoc(), isConstantFPBuildVectorOrConstantFP(), llvm::SelectionDAG::isConstantFPBuildVectorOrConstantFP(), llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt(), isContractable(), isCopyFromRegOfInlineAsm(), llvm::AArch64TargetLowering::isDesirableToCommuteWithShift(), isExtendedBUILD_VECTOR(), isFloatingPointZero(), isFNEG(), isFPExtLoad(), isFusableLoadOpStorePattern(), llvm::TargetLowering::isGAPlusOffset(), isHorizontalBinOp(), isInt32Immediate(), isInt64Immediate(), isIntImmediate(), llvm::isIntS16Immediate(), isLegalMaskCompare(), llvm::SelectionDAGISel::IsLegalToFold(), isMemOPCandidate(), isNaturalMemoryOperand(), llvm::X86TargetLowering::isNegatibleForFree(), IsNOT(), isNullFPScalarOrVectorConst(), isOpcodeHandled(), isOpcWithIntImmediate(), llvm::SDNode::isOperandOf(), isPerfectIncrement(), isPermutation(), IsPredicateKnownToFail(), isSETCCorConvertedSETCC(), isSeveralBitsExtractOpFromShr(), isShuffleFoldableLoad(), isSlicingProfitable(), isSubBorrowChain(), isTargetConstant(), isTruncateOf(), isValidIndexedLoad(), isVectorElementSwap(), llvm::ARMTargetLowering::isVectorLoadExtDesirable(), isWordAligned(), isWorthFoldingADDlow(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::HexagonTargetLowering::LowerAddSubCarry(), LowerADDSUBCARRY(), LowerAndToBT(), llvm::SparcTargetLowering::LowerAsmOperandForConstraint(), llvm::LanaiTargetLowering::LowerAsmOperandForConstraint(), llvm::AVRTargetLowering::LowerAsmOperandForConstraint(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), llvm::PPCTargetLowering::LowerAsmOperandForConstraint(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), lowerAtomicArith(), LowerAVXCONCAT_VECTORS(), llvm::HexagonTargetLowering::LowerBITCAST(), LowerBUILD_VECTOR_i1(), LowerBUILD_VECTORAsVariablePermute(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallFromStatepointLoweringInfo(), lowerCallResult(), LowerCallResult(), llvm::SelectionDAGBuilder::LowerCallSiteWithDeoptBundle(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), lowerDSPIntr(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerF128Load(), LowerF128Store(), LowerFNEGorFABS(), llvm::NVPTXTargetLowering::LowerFormalArguments(), LowerInterruptReturn(), LowerINTRINSIC_W_CHAIN(), llvm::HexagonTargetLowering::LowerLoad(), LowerLOAD(), LowerLoad(), LowerMGATHER(), LowerMLOAD(), lowerMSABinaryBitImmIntr(), LowerMSCATTER(), LowerMSTORE(), LowerMUL(), LowerMULH(), llvm::R600TargetLowering::LowerOperation(), llvm::BPFTargetLowering::LowerOperation(), llvm::XCoreTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerOperation(), llvm::ARMTargetLowering::LowerOperation(), llvm::SITargetLowering::LowerOperation(), llvm::NVPTXTargetLowering::LowerOperation(), llvm::X86TargetLowering::LowerOperationWrapper(), LowerPredicateLoad(), LowerPredicateStore(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), LowerREADCYCLECOUNTER(), llvm::HexagonTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), LowerRotate(), llvm::HexagonTargetLowering::LowerROTL(), LowerShift(), llvm::MSP430TargetLowering::LowerShifts(), lowerShuffleAsBlend(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleWithVPMOV(), lowerStatepointMetaArgs(), llvm::HexagonTargetLowering::LowerStore(), LowerSTORE(), LowerStore(), llvm::HexagonTargetLowering::LowerUAddSubO(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), LowerVACOPY(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), LowerVECTOR_SHUFFLEv8i8(), LowerVectorCTPOP(), LowerVectorFP_TO_INT(), LowerVectorINT_TO_FP(), lowerVectorShuffle(), LowerVSETCC(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), maskMatters(), MatchingStackOffset(), matchLSNode(), matchPMADDWD(), matchRotateSub(), matchVectorShuffleAsBlend(), materializeVectorConstant(), MayFoldIntoStore(), MayFoldIntoZeroExtend(), MayFoldLoad(), llvm::AMDGPUTargetLowering::mayIgnoreSignedZero(), mayTailCallThisCC(), mayUseP9Setb(), moveBelowOrigChain(), narrowExtractedVectorBinOp(), narrowExtractedVectorSelect(), narrowInsertExtractVectorBinOp(), NewSDValueDbgMsg(), numVectorEltsOrZero(), llvm::SDNodeIterator::operator*(), parseCachePolicy(), parsePredicateConstraint(), parseTexFail(), llvm::SITargetLowering::passSpecialInputs(), Passv64i1ArgInRegs(), PeepholePPC64ZExtGather(), PerformADDCombineWithOperands(), performAddSubLongCombine(), performANDCombine(), PerformANDCombine(), PerformARMBUILD_VECTORCombine(), PerformBFICombine(), PerformBUILD_VECTORCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), performCONDCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::MipsSETargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performExtendCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), PerformInsertEltCombine(), performIntegerAbsCombine(), performIntToFpCombine(), performMulCombine(), llvm::AMDGPUTargetLowering::performMulhsCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), performNEONPostLDSTCombine(), PerformORCombine(), PerformORCombineToSMULWBT(), performPostLD1Combine(), PerformSplittingToWideningLoad(), PerformSTORECombine(), PerformSUBCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformUMLALCombine(), PerformVDIVCombine(), PerformVDUPCombine(), PerformVMOVDRRCombine(), PerformVMOVRRDCombine(), performXORCombine(), performXorCombine(), pickOpcodeForVT(), PrepareCall(), PromoteMaskArithmetic(), llvm::ResourcePriorityQueue::rawRegPressureDelta(), recoverFramePointer(), llvm::SelectionDAG::ReplaceAllUsesOfValuesWith(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SelectionDAG::ReplaceAllUsesWith(), replaceInChain(), ReplaceINTRINSIC_W_CHAIN(), llvm::ARMTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::SelectionDAGISel::ReplaceUses(), reservePreviousStackSlotForValue(), llvm::SelectionDAGBuilder::resolveDanglingDebugInfo(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), llvm::SelectionDAG::salvageDebugInfo(), scalarizeBinOpOfSplats(), scalarizeExtractedBinop(), llvm::ResourcePriorityQueue::scheduledNode(), llvm::SelectionDAGISel::SelectCodeCommon(), selectI64Imm(), llvm::HexagonDAGToDAGISel::SelectIndexedLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::HexagonDAGToDAGISel::SelectIntrinsicWOChain(), llvm::HvxSelector::selectRor(), selectSGPRVectorRegClassID(), llvm::HvxSelector::selectShuffle(), llvm::HexagonDAGToDAGISel::SelectTypecast(), llvm::HexagonDAGToDAGISel::SelectVAlign(), llvm::HexagonDAGToDAGISel::SelectVAlignAddr(), llvm::SelectionDAG::setRoot(), llvm::SelectionDAGBuilder::setUnusedArgValue(), llvm::SelectionDAGBuilder::setValue(), llvm::SITargetLowering::shouldEmitPCReloc(), llvm::TargetLowering::ShrinkDemandedConstant(), llvm::TargetLowering::ShrinkDemandedOp(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), simplifyDivRem(), llvm::SelectionDAG::simplifyShift(), simplifyShuffleOfShuffle(), SkipExtensionForVMULL(), spillIncomingStatepointValue(), llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(), llvm::SITargetLowering::splitBinaryVectorOp(), llvm::SITargetLowering::splitTernaryVectorOp(), llvm::SITargetLowering::splitUnaryVectorOp(), llvm::HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic(), stripModuloOnShift(), stripTruncAndExt(), llvm::SelectionDAG::transferDbgValues(), TranslateX86CC(), tryBitfieldInsertOpFromOr(), tryBitfieldInsertOpFromOrAndImm(), tryBuildVectorShuffle(), tryCombineLongOpWithDup(), tryFoldToZero(), llvm::HexagonDAGToDAGISel::tryLoadOfLoadIntrinsic(), tryLowerToSLI(), tryToElideArgumentCopy(), tryToFoldExtendOfConstant(), tryToFoldExtOfExtload(), tryToFoldExtOfLoad(), UnpackFromArgumentSlot(), unrollVectorShift(), llvm::SelectionDAG::updateDivergence(), useSinCos(), vectorEltWillFoldAway(), llvm::SelectionDAG::VerifyDAGDiverence(), visitFMinMax(), visitORCommutative(), WinDBZCheckDenominator(), XFormVExtractWithShuffleIntoLoad(), and zeroExtendToMatch().

◆ getNumOperands()

unsigned llvm::SDValue::getNumOperands ( ) const
inline

Definition at line 1166 of file SelectionDAGNodes.h.

Referenced by buildFromShuffleMostly(), callingConvSupported(), CheckChild2CondCode(), CheckChildInteger(), CheckChildSame(), CheckChildType(), combineBitcast(), combineConcatVectorOfExtracts(), combineMOVMSK(), combineShuffleOfConcatUndef(), combinevXi1ConstantToInteger(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), computeZeroableShuffleElements(), ConvertI1VectorToInteger(), createBSWAPShuffleMask(), llvm::InstrEmitter::EmitDbgValue(), emitIntrinsicWithCC(), emitIntrinsicWithCCAndChain(), ExtendToType(), foldShuffleOfConcatUndefs(), generateEquivalentSub(), llvm::X86TargetLowering::getNegatedExpression(), llvm::SelectionDAG::getNode(), getPermuteMask(), getVectorCompareInfo(), getZeroVector(), isCalleeLoad(), llvm::SITargetLowering::isCanonicalized(), isFusableLoadOpStorePattern(), isScalarToVector(), LowerAVXCONCAT_VECTORS(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), LowerBUILD_VECTORAsVariablePermute(), LowerBUILD_VECTORvXi1(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), llvm::HexagonTargetLowering::LowerINLINEASM(), LowerScalarVariableShift(), LowerShiftParts(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), LowerVECTOR_SHUFFLE(), llvm::ISD::matchBinaryPredicate(), matchPMADDWD_2(), llvm::ISD::matchUnaryPredicate(), moveBelowOrigChain(), partitionShuffleOfConcats(), PerformVECTOR_SHUFFLECombine(), recoverFramePointer(), llvm::ARMTargetLowering::ReplaceNodeResults(), llvm::SelectionDAGISel::SelectCodeCommon(), selectI64Imm(), llvm::TargetLowering::ShrinkDemandedOp(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), simplifyDivRem(), and simplifyShuffleOfShuffle().

◆ getOpcode()

unsigned llvm::SDValue::getOpcode ( ) const
inline

Definition at line 1158 of file SelectionDAGNodes.h.

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64BitSMLAL16(), AddCombineTo64bitUMAAL(), AddCombineVUZPToVPADDL(), llvm::AVRDAGToDAGISel::select< AVRISD::CALL >(), buildFromShuffleMostly(), buildScalarToVector(), calculateByteProvider(), callingConvSupported(), CanCombineFCOPYSIGN_EXTEND_ROUND(), canFoldInAddressingMode(), canonicalizeBitSelect(), checkBitcastSrcVectorSize(), checkBoolTestSetCCCombine(), checkHighLaneIndex(), checkV64LaneV128(), collectConcatOps(), combineAdd(), combineADDCARRYDiamond(), combineAddOrSubToADCOrSBB(), combineADDToADDZE(), combineAnd(), combineBasicSADPattern(), combineBitcast(), combineBitcastvxi1(), combineBVOfConsecutiveLoads(), combineBVOfVecSExt(), combineCarryThroughADD(), combineCastedMaskArithmetic(), combineCMP(), combineCompareEqual(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineConcatVectorOps(), combineExtractSubvector(), combineExtractVectorElt(), combineExtractWithShuffle(), combineExtSetcc(), combineFAndFNotToFAndn(), combineFneg(), combineGatherScatter(), combineInsertSubvector(), combineLoopMAddPattern(), combineLoopSADPattern(), combineMaskedStore(), combineMOVMSK(), combineMulToPMADDWD(), combineOr(), combineOrCmpEqZeroToCtlzSrl(), combineParity(), combinePMULDQ(), combinePMULH(), combineRedundantDWordShuffle(), combineSBB(), combineScalarToVector(), combineSetCC(), combineSetCCAtomicArith(), combineSext(), combineSextInRegCmov(), combineShiftAnd1ToBitTest(), combineShiftLeft(), combineShiftOfShiftedLogic(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShuffle(), combineShuffleOfConcatUndef(), combineShuffleToFMAddSub(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineSub(), combineSubToSubus(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToExtendCMOV(), combineToFPTruncExtElt(), combineTruncate(), combineTruncatedArithmetic(), combineTruncationShuffle(), combineVectorPack(), combineVectorShiftImm(), combineVectorSizedSetCCEquality(), CombineVMOVDRRCandidateWithVecOp(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineX86ShufflesRecursively(), combineZext(), llvm::TargetLowering::ComputeConstraintToUse(), llvm::SelectionDAG::computeKnownBits(), llvm::SparcTargetLowering::computeKnownBitsForTargetNode(), llvm::LanaiTargetLowering::computeKnownBitsForTargetNode(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), llvm::AArch64TargetLowering::computeKnownBitsForTargetNode(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::SystemZTargetLowering::computeKnownBitsForTargetNode(), llvm::PPCTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::TargetLowering::computeKnownBitsForTargetNode(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::RISCVTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::SelectionDAG::computeOverflowKind(), computeZeroableShuffleElements(), ConstantAddressBlock(), ConstantBuildVector(), ConvertCarryFlagToBooleanCarry(), convertIntLogicToFPLogic(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), llvm::createARCISelDag(), createFPCmp(), llvm::createMSP430ISelDag(), llvm::createXCoreISelDag(), detectAVGPattern(), detectPMADDUBSW(), detectSSatPattern(), detectUSatPattern(), llvm::HexagonDAGToDAGISel::DetectUseSxtw(), detectZextAbsDiff(), EmitCMP(), emitComparison(), emitConditionalComparison(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), EmitKORTEST(), EmitTest(), EmitUnrolledSetTag(), ExpandBITCAST(), expandDisp(), llvm::PPCTargetLowering::expandVSXStoreForLE(), ExtendToType(), ExtendUsesToFormExtLoad(), extractBooleanFlip(), extractShiftForRotate(), extractSubVector(), FindBFIToCombineWith(), findEltLoadSrc(), findEXTRHalf(), findMatchingInlineAsmOperand(), findMemSDNode(), foldAddSubBoolOfMaskedVal(), foldAddSubMasked1(), foldAddSubOfSignBit(), foldBitcastedFPLogic(), foldCONCAT_VECTORS(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::FoldConstantVectorArithmetic(), foldExtendedSignBitTest(), foldFPToIntToFP(), FoldIntToFPToInt(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), foldShuffleOfConcatUndefs(), foldShuffleOfHorizOp(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), fp16SrcZerosHighBits(), generateEquivalentSub(), getAArch64XALUOOp(), getARMIndexedAddressParts(), getAsCarry(), getAsNonOpaqueConstant(), llvm::MemSDNode::getBasePtr(), llvm::MaskedLoadStoreSDNode::getBasePtr(), getBuildPairElt(), getCmpOperandFoldingProfit(), getContiguousRangeOfSetBits(), llvm::SelectionDAGBuilder::getControlRoot(), llvm::SelectionDAG::GetDemandedBits(), getDemandedSrcElements(), getDUPLANEOp(), getExtendTypeForNode(), getFauxShuffleMask(), getGeneralPermuteNode(), getIndexFromUnindexedLoad(), getInputChainForNode(), getKnownUndefForVectorBinop(), getMad64_32(), llvm::MaskedLoadStoreSDNode::getMask(), llvm::X86TargetLowering::getNegatedExpression(), llvm::TargetLowering::getNegatedExpression(), llvm::SelectionDAG::getNode(), llvm::LSBaseSDNode::getOffset(), getPermuteMask(), getPowerOf2Factor(), llvm::HexagonTargetLowering::getPreferredVectorAction(), getPSHUFShuffleMask(), getReductionSDNode(), getScalarMaskingNode(), getScalarValueForVectorElement(), llvm::AVRTargetLowering::getSetCCResultType(), getShiftTypeForNode(), getShuffleScalarElt(), getSPDenormModeValue(), llvm::SelectionDAG::getSplatBuildVector(), getSplatConstantFP(), llvm::SelectionDAG::getSplatSourceVector(), getSubVectorSrc(), llvm::SystemZTargetLowering::getTargetNodeName(), getTargetShuffleAndZeroables(), getTargetShuffleMask(), getTargetVShiftNode(), getUnderlyingArgRegs(), getVectorCompareInfo(), llvm::SelectionDAG::getVectorShuffle(), getVPermMask(), getVPTESTMOpc(), getVShiftImm(), getZeroVector(), gwsIntrinToOpcode(), hasSingleUsesFromRoot(), haveEfficientBuildVectorPattern(), InferPointerInfo(), insertDAGNode(), isAbsolute(), isADDADDMUL(), isAddCarryChain(), isAddSubOrSubAdd(), isAndOrOfSetCCs(), isAnyConstantBuildVector(), llvm::SelectionDAG::isBaseWithConstantOffset(), llvm::isBitwiseNot(), isBoolSGPR(), isBSwapHWordElement(), isBSwapHWordPair(), isCalleeLoad(), llvm::SITargetLowering::isCanonicalized(), isClampZeroToOne(), isCMN(), llvm::AtomicSDNode::isCompareAndSwap(), isConditionalZeroOrAllOnes(), isConsecutiveLSLoc(), llvm::BuildVectorSDNode::isConstant(), isConstantOrConstantVector(), isContractable(), llvm::RISCVTargetLowering::isDesirableToCommuteWithShift(), llvm::AArch64TargetLowering::isDesirableToCommuteWithShift(), llvm::X86TargetLowering::IsDesirableToPromoteOp(), isDispSafeForFrameIndex(), isEssentiallyExtractHighSubvector(), isFloatingPointZero(), isFMAddSubOrFMSubAdd(), isFNEG(), isFPExtLoad(), isFrameIndexOp(), isFunctionGlobalAddress(), isFusableLoadOpStorePattern(), isHopBuildVector(), isHorizontalBinOp(), isHorizontalBinOpPart(), llvm::SelectionDAG::isKnownNeverNaN(), llvm::AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(), llvm::SITargetLowering::isKnownNeverNaNForTargetNode(), llvm::TargetLowering::isKnownNeverNaNForTargetNode(), llvm::SelectionDAG::isKnownNeverZero(), llvm::SelectionDAG::isKnownToBeAPowerOfTwo(), isLegalMaskCompare(), isMemOPCandidate(), isMemSrcFromConstant(), IsMulWideOperandDemotable(), llvm::X86TargetLowering::isNegatibleForFree(), llvm::TargetLowering::isNegatibleForFree(), IsNOT(), isOpcWithIntImmediate(), isOverflowIntrOpRes(), isPerfectIncrement(), isPermutation(), isPreferredADD(), isSaturatingConditional(), isSetCC(), isSETCCorConvertedSETCC(), isSetCCOrZExtSetCC(), isSHL16(), isSlicingProfitable(), llvm::SelectionDAG::isSplatValue(), isSRA16(), isSRL16(), isSubBorrowChain(), isTargetConstant(), isTruncateOf(), isTruncWithZeroHighBitsInput(), isValidIndexedLoad(), isVectorElementSwap(), isVShiftRImm(), isWorthFoldingADDlow(), isWorthFoldingSHL(), isX86LogicalCmp(), isXor1OfSetCC(), llvm::XCoreTargetLowering::isZExtFree(), llvm::AArch64TargetLowering::isZExtFree(), llvm::ARMTargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), LookThroughSetCC(), Lower256IntVSETCC(), LowerADDC_ADDE_SUBC_SUBE(), LowerADDSAT_SUBSAT(), llvm::HexagonTargetLowering::LowerAddSubCarry(), LowerADDSUBCARRY(), lowerAddSubToHorizontalOp(), LowerAndToBT(), llvm::TargetLowering::LowerAsmOperandForConstraint(), LowerAVXExtend(), LowerBUILD_VECTOR_i1(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), lowerBuildVectorToBitOp(), LowerBuildVectorv4x32(), LowerCTLZ(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), LowerCTTZ(), lowerDSPIntr(), LowerEXTEND_VECTOR_INREG(), LowerFABSorFNEG(), LowerFNEGorFABS(), llvm::AMDGPUTargetLowering::LowerFP_TO_SINT(), lowerFP_TO_SINT_STORE(), llvm::AMDGPUTargetLowering::LowerFP_TO_UINT(), LowerFunnelShift(), LowerI64IntToFP_AVX512DQ(), llvm::HexagonTargetLowering::LowerINLINEASM(), LowerInterruptReturn(), LowerMINMAX(), llvm::R600TargetLowering::LowerOperation(), llvm::BPFTargetLowering::LowerOperation(), llvm::MipsSETargetLowering::LowerOperation(), llvm::SparcTargetLowering::LowerOperation(), llvm::ARCTargetLowering::LowerOperation(), llvm::LanaiTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), llvm::MSP430TargetLowering::LowerOperation(), llvm::AVRTargetLowering::LowerOperation(), llvm::XCoreTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerOperation(), llvm::AMDGPUTargetLowering::LowerOperation(), llvm::AArch64TargetLowering::LowerOperation(), llvm::ARMTargetLowering::LowerOperation(), llvm::MipsTargetLowering::LowerOperation(), llvm::SITargetLowering::LowerOperation(), llvm::NVPTXTargetLowering::LowerOperation(), llvm::SystemZTargetLowering::LowerOperation(), llvm::PPCTargetLowering::LowerOperation(), llvm::X86TargetLowering::LowerOperation(), LowerPREFETCH(), LowerRotate(), LowerScalarImmediateShift(), LowerScalarVariableShift(), llvm::MSP430TargetLowering::LowerSETCC(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), LowerShiftParts(), llvm::MSP430TargetLowering::LowerShifts(), lowerShuffleAsBroadcast(), lowerShuffleAsTruncBroadcast(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithVPMOV(), LowerSIGN_EXTEND_Mask(), llvm::AMDGPUTargetLowering::LowerSINT_TO_FP(), LowerTruncateVecI1(), llvm::HexagonTargetLowering::LowerUAddSubO(), llvm::AMDGPUTargetLowering::LowerUINT_TO_FP(), LowerUMULO_SMULO(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), LowerVectorAllZeroTest(), LowerVectorCTLZ_AVX512CDI(), LowerVectorFP_TO_INT(), LowerVectorINT_TO_FP(), LowerVectorIntUnary(), LowerVSETCC(), LowerXOR(), maskMatters(), llvm::ISD::matchBinaryPredicate(), llvm::SelectionDAG::matchBinOpReduction(), matchBitOpReduction(), MatchingStackOffset(), matchLogicBlend(), matchPMADDWD(), matchPMADDWD_2(), matchRotateHalf(), matchRotateSub(), llvm::ISD::matchUnaryPredicate(), mayTailCallThisCC(), mayUseP9Setb(), moveBelowOrigChain(), narrowExtractedVectorBinOp(), narrowExtractedVectorLoad(), narrowExtractedVectorSelect(), narrowInsertExtractVectorBinOp(), NormalizeBuildVector(), numVectorEltsOrZero(), optimizeLogicalImm(), llvm::peekThroughBitcasts(), llvm::peekThroughExtractSubvectors(), llvm::peekThroughOneUseBitcasts(), performADDCombine(), PerformADDCombineWithOperands(), performAddSubLongCombine(), performANDCombine(), PerformANDCombine(), PerformARMBUILD_VECTORCombine(), llvm::AMDGPUTargetLowering::performAssertSZExtCombine(), PerformBFICombine(), llvm::ARMTargetLowering::PerformBRCONDCombine(), performBRCONDCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), performCONDCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::HexagonTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performExtendCombine(), PerformExtendCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFpToIntCombine(), performIntegerAbsCombine(), performMADD_MSUBCombine(), llvm::AMDGPUTargetLowering::performMulCombine(), performORCombine(), PerformORCombine(), PerformORCombineToBFI(), PerformORCombineToSMULWBT(), performSELECTCombine(), performSelectCombine(), PerformShiftCombine(), performSHLCombine(), PerformSHLSimplify(), PerformSplittingToWideningLoad(), llvm::AMDGPUTargetLowering::performSrlCombine(), performSRLCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformVCVTCombine(), PerformVDUPLANECombine(), PerformVECTOR_SHUFFLECombine(), PerformVMOVDRRCombine(), PerformVMOVRRDCombine(), PerformVMULCombine(), performVSELECTCombine(), performVSelectCombine(), PrepareCall(), promoteExtBeforeAdd(), PromoteMaskArithmetic(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceBuildVecToShuffleWithZero(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), replaceSplatVectorStore(), replaceZeroVectorStore(), scalarizeBinOpOfSplats(), scalarizeExtractedBinop(), llvm::AVRDAGToDAGISel::SelectAddr(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::PPCTargetLowering::SelectAddressRegReg(), llvm::PPCTargetLowering::SelectAddressRegRegOnly(), llvm::HexagonDAGToDAGISel::SelectAddrFI(), llvm::HexagonDAGToDAGISel::SelectAnyImmediate(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectGlobalAddress(), selectI64Imm(), selectSGPRVectorRegClassID(), llvm::HexagonDAGToDAGISel::SelectSHL(), llvm::HexagonTargetLowering::shouldExpandAtomicRMWInIR(), llvm::X86TargetLowering::shouldFoldConstantShiftPairToMask(), llvm::AArch64TargetLowering::shouldReduceLoadWidth(), llvm::X86TargetLowering::shouldReduceLoadWidth(), llvm::X86TargetLowering::shouldScalarizeBinop(), shouldUseLA(), shouldUseZeroOffsetLdSt(), llvm::TargetLowering::ShrinkDemandedConstant(), llvm::TargetLowering::ShrinkDemandedOp(), ShrinkLoadReplaceStoreWithStore(), signExtendBitcastSrcVector(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), simplifyDivRem(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), simplifyShuffleOfShuffle(), split256IntArith(), split512IntArith(), llvm::SITargetLowering::splitBinaryVectorOp(), llvm::SITargetLowering::splitTernaryVectorOp(), llvm::SITargetLowering::splitUnaryVectorOp(), llvm::AMDGPUTargetLowering::stripBitcast(), stripConstantMask(), stripModuloOnShift(), stripTruncAndExt(), llvm::AArch64TargetLowering::targetShrinkDemandedConstant(), llvm::ARMTargetLowering::targetShrinkDemandedConstant(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), tryBuildVectorShuffle(), tryCombineCRC32(), tryCombineFixedPointConvert(), tryCombineToBSL(), tryExtendDUPToExtractHigh(), tryFoldToZero(), tryLowerToSLI(), tryToElideArgumentCopy(), unrollVectorShift(), vectorEltWillFoldAway(), vectorizeExtractedCast(), visitFMinMax(), visitORCommutative(), widenVec(), willShiftRightEliminate(), XFormVExtractWithShuffleIntoLoad(), and zeroExtendToMatch().

◆ getOperand()

const SDValue & llvm::SDValue::getOperand ( unsigned  i) const
inline

Definition at line 1170 of file SelectionDAGNodes.h.

Referenced by AddCombineTo64BitSMLAL16(), AddCombineVUZPToVPADDL(), llvm::AVRDAGToDAGISel::select< ISD::STORE >(), llvm::X86TargetLowering::BuildFILD(), buildFromShuffleMostly(), callingConvSupported(), CanCombineFCOPYSIGN_EXTEND_ROUND(), canLowerToLDG(), canonicalizeBitSelect(), CheckAndImm(), checkBitcastSrcVectorSize(), checkBoolTestSetCCCombine(), CheckChild2CondCode(), CheckChildInteger(), CheckChildSame(), CheckChildType(), checkHighLaneIndex(), CheckOrImm(), checkV64LaneV128(), collectConcatOps(), combineAdd(), combineADDCARRYDiamond(), combineAddOrSubToADCOrSBB(), combineADDToADDZE(), combineAnd(), combineBasicSADPattern(), combineBitcast(), combineBitcastvxi1(), combineBVOfConsecutiveLoads(), combineBVOfVecSExt(), combineCarryThroughADD(), combineCastedMaskArithmetic(), combineCMP(), combineCompareEqual(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineConcatVectorOps(), combineExtractSubvector(), combineExtractVectorElt(), combineExtractWithShuffle(), combineExtSetcc(), combineFAndFNotToFAndn(), combineFMA(), combineFneg(), combineGatherScatter(), combineInsertSubvector(), combineLoopMAddPattern(), combineMaskedStore(), combineMOVMSK(), combineMulToPMADDWD(), combineOr(), combineOrCmpEqZeroToCtlzSrl(), combineParity(), combinePMULDQ(), combinePMULH(), combineRedundantDWordShuffle(), combineSBB(), combineScalarToVector(), combineSetCC(), combineSetCCAtomicArith(), combineSext(), combineSextInRegCmov(), combineShiftAnd1ToBitTest(), combineShiftLeft(), combineShiftOfShiftedLogic(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShuffle(), combineShuffleOfConcatUndef(), combineShuffleOfScalars(), combineShuffleToFMAddSub(), combineSignExtendInReg(), combineStore(), combineSub(), combineSubToSubus(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToExtendCMOV(), combineToFPTruncExtElt(), combineTruncate(), combineTruncatedArithmetic(), combineTruncationShuffle(), combineVectorCompareAndMaskUnaryOp(), combineVectorPack(), combineVectorShiftImm(), combineVectorSizedSetCCEquality(), CombineVMOVDRRCandidateWithVecOp(), combinevXi1ConstantToInteger(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineZext(), llvm::SelectionDAG::computeKnownBits(), computeKnownBitsBinOp(), llvm::SparcTargetLowering::computeKnownBitsForTargetNode(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), llvm::AArch64TargetLowering::computeKnownBitsForTargetNode(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::SystemZTargetLowering::computeKnownBitsForTargetNode(), llvm::PPCTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::SelectionDAG::ComputeNumSignBits(), computeNumSignBitsBinOp(), llvm::AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), computeZeroableShuffleElements(), ConstantAddressBlock(), ConstantBuildVector(), ConvertCarryFlagToBooleanCarry(), ConvertI1VectorToInteger(), convertIntLogicToFPLogic(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), llvm::createARCISelDag(), createBSWAPShuffleMask(), createFPCmp(), llvm::createMSP430ISelDag(), createPSADBW(), llvm::createXCoreISelDag(), detectAVGPattern(), detectPMADDUBSW(), detectSSatPattern(), detectUSatPattern(), llvm::HexagonDAGToDAGISel::DetectUseSxtw(), detectZextAbsDiff(), elementPairIsContiguous(), emitComparison(), emitConditionalComparison(), llvm::MipsSETargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), emitIntrinsicWithCC(), emitIntrinsicWithCCAndChain(), EmitKORTEST(), EmitTest(), EmitVectorComparison(), ExpandBITCAST(), expandDisp(), expandf64Toi32(), llvm::TargetLowering::expandUnalignedLoad(), llvm::PPCTargetLowering::expandVSXStoreForLE(), ExtendToType(), ExtendUsesToFormExtLoad(), ExtractBitFromMaskVector(), extractBooleanFlip(), extractShiftForRotate(), FindBFIToCombineWith(), findEltLoadSrc(), findEXTRHalf(), findMemSDNode(), foldAddSubBoolOfMaskedVal(), foldAddSubMasked1(), foldAddSubOfSignBit(), foldBitcastedFPLogic(), foldCONCAT_VECTORS(), foldExtendedSignBitTest(), foldFPToIntToFP(), FoldIntToFPToInt(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), foldShuffleOfConcatUndefs(), foldShuffleOfHorizOp(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), fp16SrcZerosHighBits(), generateEquivalentSub(), GeneratePerfectShuffle(), GenerateTBL(), getAArch64Cmp(), getAArch64XALUOOp(), getAbsolute(), getAsCarry(), getAsNonOpaqueConstant(), llvm::MemSDNode::getBasePtr(), llvm::AtomicSDNode::getBasePtr(), llvm::LoadSDNode::getBasePtr(), llvm::StoreSDNode::getBasePtr(), llvm::MaskedLoadStoreSDNode::getBasePtr(), llvm::MaskedLoadSDNode::getBasePtr(), llvm::MaskedStoreSDNode::getBasePtr(), llvm::MaskedGatherScatterSDNode::getBasePtr(), getBaseWithConstantOffset(), getBufferOffsetForMMO(), getBuildPairElt(), getCCResult(), llvm::MemSDNode::getChain(), getCmpOperandFoldingProfit(), llvm::SDNode::getConstantOperandAPInt(), llvm::SDNode::getConstantOperandVal(), getContiguousRangeOfSetBits(), llvm::SelectionDAG::GetDemandedBits(), getDemandedSrcElements(), getDUPLANEOp(), getExtendTypeForNode(), getFauxShuffleMask(), getFPTernOp(), llvm::LifetimeSDNode::getFrameIndex(), getGeneralPermuteNode(), llvm::MaskedGatherScatterSDNode::getIndex(), getIndexFromUnindexedLoad(), llvm::XCoreTargetLowering::getJumpTableEncoding(), getKnownUndefForVectorBinop(), getMad64_32(), llvm::MaskedLoadStoreSDNode::getMask(), llvm::MaskedLoadSDNode::getMask(), llvm::MaskedStoreSDNode::getMask(), llvm::MaskedGatherScatterSDNode::getMask(), llvm::X86TargetLowering::getNegatedExpression(), llvm::TargetLowering::getNegatedExpression(), llvm::SelectionDAG::getNode(), getNormalLoadInput(), llvm::LSBaseSDNode::getOffset(), llvm::LoadSDNode::getOffset(), llvm::StoreSDNode::getOffset(), llvm::MaskedLoadSDNode::getPassThru(), llvm::MaskedGatherSDNode::getPassThru(), getPermuteMask(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), getPowerOf2Factor(), llvm::HexagonTargetLowering::getPreferredVectorAction(), getReductionSDNode(), getScalarValueForVectorElement(), llvm::MaskedGatherScatterSDNode::getScale(), getShuffleScalarElt(), getSPDenormModeValue(), getSplatConstantFP(), llvm::SelectionDAG::getSplatSourceVector(), getSubVectorSrc(), getTargetConstantBitsFromNode(), llvm::ARCTargetLowering::getTargetNodeName(), llvm::SystemZTargetLowering::getTargetNodeName(), getTargetShuffleAndZeroables(), getTargetShuffleMask(), getTargetVShiftNode(), getUnderlyingArgRegs(), getUsefulBitsFromAndWithImmediate(), getUsefulBitsFromBFM(), getUsefulBitsFromOrWithShiftedReg(), getUsefulBitsFromUBFM(), llvm::AtomicSDNode::getVal(), getValidMinimumShiftAmountConstant(), getValidShiftAmountConstant(), llvm::StoreSDNode::getValue(), llvm::MaskedStoreSDNode::getValue(), llvm::MaskedScatterSDNode::getValue(), getVectorCompareInfo(), getVPermMask(), getVPTESTMOpc(), getVShiftImm(), getZeroVector(), gwsIntrinToOpcode(), hasSingleUsesFromRoot(), haveEfficientBuildVectorPattern(), InferPointerInfo(), llvm::SelectionDAG::InferPtrAlignment(), insert1BitVector(), InsertBitToMaskVector(), insertDAGNode(), llvm::intCCToAVRCC(), isAbsolute(), isADDADDMUL(), isAddCarryChain(), isAddSubOrSubAdd(), isAndOrOfSetCCs(), isAnyConstantBuildVector(), llvm::SelectionDAG::isBaseWithConstantOffset(), isBitfieldExtractOpFromAnd(), isBitfieldExtractOpFromSExtInReg(), isBitfieldExtractOpFromShr(), isBitfieldPositioningOp(), llvm::isBitwiseNot(), isBSwapHWordElement(), isBSwapHWordPair(), isCalleeLoad(), llvm::SITargetLowering::isCanonicalized(), isClampZeroToOne(), isCMN(), isContractable(), llvm::X86TargetLowering::IsDesirableToPromoteOp(), isDispSafeForFrameIndex(), isEssentiallyExtractHighSubvector(), isFloatingPointZero(), isFMAddSubOrFMSubAdd(), isFNEG(), isFPExtLoad(), isFrameIndexOp(), isFusableLoadOpStorePattern(), isHopBuildVector(), isHorizontalBinOp(), isHorizontalBinOpPart(), isIntrinsicWithCC(), isIntrinsicWithCCAndChain(), llvm::SelectionDAG::isKnownNeverNaN(), llvm::AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(), llvm::SITargetLowering::isKnownNeverNaNForTargetNode(), llvm::SelectionDAG::isKnownNeverZero(), llvm::SelectionDAG::isKnownToBeAPowerOfTwo(), llvm::ARCTargetLowering::isLegalAddressingMode(), llvm::PPCTargetLowering::isLegalAddressingMode(), isLegalMaskCompare(), isLowerSaturatingConditional(), isMemOPCandidate(), isMemSrcFromConstant(), IsMulWideOperandDemotable(), llvm::X86TargetLowering::isNegatibleForFree(), llvm::TargetLowering::isNegatibleForFree(), IsNOT(), isOpcWithIntImmediate(), isPerfectIncrement(), isPermutation(), isPreferredADD(), llvm::ARMTargetLowering::isReadOnly(), isS16(), isSaturatingConditional(), isScalarToVector(), isSetCC(), isSETCCorConvertedSETCC(), isSeveralBitsExtractOpFromShr(), isSHL16(), isSimpleShift(), isSlicingProfitable(), llvm::SelectionDAG::isSplatValue(), isSRA16(), isSRL16(), isStackPtrRelative(), isSubBorrowChain(), isTargetConstant(), isTruncateOf(), isTruncWithZeroHighBitsInput(), isVectorElementSwap(), llvm::X86TargetLowering::isVectorLoadExtDesirable(), isVShiftRImm(), isWorthFoldingADDlow(), isWorthFoldingSHL(), isXor1OfSetCC(), LookThroughSetCC(), Lower256IntVSETCC(), LowerABS(), LowerADDC_ADDE_SUBC_SUBE(), LowerADDSAT_SUBSAT(), lowerAddSub(), llvm::HexagonTargetLowering::LowerAddSubCarry(), LowerADDSUBCARRY(), lowerAddSubToHorizontalOp(), LowerADJUST_TRAMPOLINE(), LowerAndToBT(), llvm::TargetLowering::LowerAsmOperandForConstraint(), LowerAsSplatVectorLoad(), llvm::HexagonTargetLowering::LowerATOMIC_FENCE(), LowerATOMIC_FENCE(), LowerAVXCONCAT_VECTORS(), LowerAVXExtend(), llvm::HexagonTargetLowering::LowerBITCAST(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), llvm::LanaiTargetLowering::LowerBR_CC(), llvm::MSP430TargetLowering::LowerBR_CC(), LowerBR_CC(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), LowerBUILD_VECTOR_i1(), LowerBUILD_VECTORAsVariablePermute(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), LowerBuildVectorAsInsert(), lowerBuildVectorToBitOp(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), llvm::SparcTargetLowering::LowerCall_64(), LowerCMP_SWAP(), llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS_i1(), LowerCONCAT_VECTORSvXi1(), LowerCTLZ(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), LowerCTTZ(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::HexagonTargetLowering::LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_SUBVECTOR(), llvm::HexagonTargetLowering::LowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT_i1(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerF128_FPEXTEND(), LowerF128_FPROUND(), lowerFABS32(), lowerFABS64(), LowerFABSorFNEG(), llvm::AMDGPUTargetLowering::LowerFCEIL(), LowerFCOPYSIGN(), lowerFCOPYSIGN32(), lowerFCOPYSIGN64(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), LowerFGETSIGN(), llvm::AMDGPUTargetLowering::LowerFLOG(), llvm::AMDGPUTargetLowering::LowerFNEARBYINT(), LowerFNEGorFABS(), llvm::AMDGPUTargetLowering::LowerFP64_TO_INT(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), llvm::AMDGPUTargetLowering::LowerFP_TO_SINT(), LowerFP_TO_SINT(), lowerFP_TO_SINT_STORE(), llvm::AMDGPUTargetLowering::LowerFP_TO_UINT(), LowerFP_TO_UINT(), LowerFPOWI(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), llvm::AMDGPUTargetLowering::LowerFREM(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerFROUND32_16(), llvm::AMDGPUTargetLowering::LowerFROUND64(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), LowerFunnelShift(), LowerI64IntToFP_AVX512DQ(), llvm::HexagonTargetLowering::LowerINLINEASM(), llvm::HexagonTargetLowering::LowerINSERT_SUBVECTOR(), llvm::HexagonTargetLowering::LowerINSERT_VECTOR_ELT(), LowerINSERT_VECTOR_ELT_i1(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP64(), LowerInterruptReturn(), llvm::HexagonTargetLowering::LowerINTRINSIC_VOID(), LowerINTRINSIC_W_CHAIN(), llvm::SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(), LowerIntVSETCC_AVX512(), LowerMGATHER(), LowerMINMAX(), LowerMUL(), LowerMULH(), llvm::R600TargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerPREFETCH(), LowerPREFETCH(), llvm::HexagonTargetLowering::LowerREADCYCLECOUNTER(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(), LowerRotate(), llvm::HexagonTargetLowering::LowerROTL(), LowerSCALAR_TO_VECTOR(), LowerScalarImmediateShift(), LowerScalarVariableShift(), LowerSDIV(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::LanaiTargetLowering::LowerSELECT_CC(), llvm::MSP430TargetLowering::LowerSELECT_CC(), LowerSELECT_CC(), llvm::LanaiTargetLowering::LowerSETCC(), llvm::MSP430TargetLowering::LowerSETCC(), llvm::HexagonTargetLowering::LowerSETCC(), LowerSETCCCARRY(), LowerShift(), LowerShiftParts(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), lowerShuffleAsBroadcast(), lowerShuffleAsTruncBroadcast(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithVPMOV(), llvm::MSP430TargetLowering::LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), llvm::AMDGPUTargetLowering::LowerSINT_TO_FP(), LowerSINT_TO_FP(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), llvm::MipsTargetLowering::lowerSTORE(), LowerSTRICT_FP_ROUND(), LowerTruncateVecI1(), llvm::HexagonTargetLowering::LowerUAddSubO(), LowerUDIV(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), llvm::AMDGPUTargetLowering::LowerUINT_TO_FP(), LowerUINT_TO_FP(), LowerUINT_TO_FP_i32(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vec(), LowerUMULO_SMULO(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), LowerVACOPY(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::MSP430TargetLowering::LowerVASTART(), llvm::HexagonTargetLowering::LowerVASTART(), LowerVASTART(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), LowerVECTOR_SHUFFLEv8i8(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), LowerVectorFP_TO_INT(), LowerVectorINT_TO_FP(), LowerVectorIntUnary(), lowerVectorShuffle(), llvm::HexagonTargetLowering::LowerVSELECT(), LowerVSETCC(), lowerX86CmpEqZeroToCtlzSrl(), LowerXOR(), LowerZERO_EXTEND(), MarkEHGuard(), MarkEHRegistrationNode(), maskMatters(), llvm::ISD::matchBinaryPredicate(), llvm::SelectionDAG::matchBinOpReduction(), matchBitOpReduction(), MatchingStackOffset(), matchLogicBlend(), matchPMADDWD(), matchPMADDWD_2(), matchRotateSub(), llvm::ISD::matchUnaryPredicate(), mayTailCallThisCC(), mayUseP9Setb(), minMaxOpcToMin3Max3Opc(), moveBelowOrigChain(), narrowExtractedVectorBinOp(), narrowExtractedVectorLoad(), narrowExtractedVectorSelect(), narrowInsertExtractVectorBinOp(), llvm::X86TargetLowering::needsFixedCatchObjects(), NegateCC(), optimizeLogicalImm(), parseTexFail(), partitionShuffleOfConcats(), llvm::peekThroughBitcasts(), llvm::peekThroughExtractSubvectors(), llvm::peekThroughOneUseBitcasts(), PeepholePPC64ZExtGather(), performADDCombine(), PerformADDCombineWithOperands(), performAddSubLongCombine(), performANDCombine(), PerformARMBUILD_VECTORCombine(), llvm::AMDGPUTargetLowering::performAssertSZExtCombine(), PerformBFICombine(), llvm::ARMTargetLowering::PerformBRCONDCombine(), performBRCONDCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::HexagonTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformExtendCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), performFDivCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performIntegerAbsCombine(), llvm::AMDGPUTargetLowering::performMulCombine(), performORCombine(), PerformORCombineToBFI(), PerformORCombineToSMULWBT(), performSELECTCombine(), performSelectCombine(), PerformShiftCombine(), performSHLCombine(), PerformSHLSimplify(), PerformSplittingToNarrowingStores(), llvm::AMDGPUTargetLowering::performSrlCombine(), performSRLCombine(), PerformSTORECombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformVDIVCombine(), PerformVDUPLANECombine(), PerformVECTOR_SHUFFLECombine(), PerformVMOVDRRCombine(), PerformVMOVRRDCombine(), performVSELECTCombine(), performVSelectCombine(), PrepareCall(), promoteExtBeforeAdd(), PromoteMaskArithmetic(), llvm::AArch64TargetLowering::ReconstructShuffle(), recoverFramePointer(), reduceBuildVecToShuffleWithZero(), ReorganizeVector(), llvm::R600TargetLowering::ReplaceNodeResults(), replaceSplatVectorStore(), replaceZeroVectorStore(), scalarizeBinOpOfSplats(), scalarizeExtEltFP(), scalarizeExtractedBinop(), SearchLoopIntrinsic(), llvm::AVRDAGToDAGISel::SelectAddr(), llvm::PPCTargetLowering::SelectAddressEVXRegReg(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::PPCTargetLowering::SelectAddressRegReg(), llvm::PPCTargetLowering::SelectAddressRegRegOnly(), llvm::HexagonDAGToDAGISel::SelectAnyImmediate(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectGlobalAddress(), selectI64Imm(), selectSGPRVectorRegClassID(), llvm::HexagonDAGToDAGISel::SelectSHL(), llvm::SITargetLowering::shouldEmitPCReloc(), llvm::X86TargetLowering::shouldFoldConstantShiftPairToMask(), llvm::AArch64TargetLowering::shouldReduceLoadWidth(), llvm::X86TargetLowering::shouldReduceLoadWidth(), shouldUseZeroOffsetLdSt(), llvm::TargetLowering::ShrinkDemandedConstant(), llvm::TargetLowering::ShrinkDemandedOp(), ShrinkLoadReplaceStoreWithStore(), signExtendBitcastSrcVector(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), simplifyDivRem(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), simplifyShuffleOfShuffle(), split256IntArith(), split512IntArith(), llvm::AMDGPUTargetLowering::stripBitcast(), stripConstantMask(), stripModuloOnShift(), stripTruncAndExt(), llvm::AArch64TargetLowering::targetShrinkDemandedConstant(), llvm::ARMTargetLowering::targetShrinkDemandedConstant(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), tryBitfieldInsertOpFromOrAndImm(), tryBuildVectorShuffle(), tryCombineCRC32(), tryCombineFixedPointConvert(), tryFoldToZero(), tryFormConcatFromShuffle(), tryLowerToSLI(), tryToElideArgumentCopy(), tryToFoldExtendOfConstant(), unrollVectorShift(), vectorEltWillFoldAway(), vectorizeExtractedCast(), llvm::TargetLowering::verifyReturnAddressArgumentIsConstant(), visitFMinMax(), visitORCommutative(), widenVec(), willShiftRightEliminate(), XFormVExtractWithShuffleIntoLoad(), and zeroExtendToMatch().

◆ getResNo()

unsigned llvm::SDValue::getResNo ( ) const
inline

get the index which selects a specific result in the SDNode

Definition at line 134 of file SelectionDAGNodes.h.

Referenced by llvm::DOTGraphTraits< SelectionDAG * >::addCustomGraphFeatures(), AddNodeIDOperands(), checkBoolTestSetCCCombine(), CheckForPhysRegDependency(), combineADDCARRYDiamond(), combineAddOrSubToADCOrSBB(), CombineBaseUpdate(), combineCarryThroughADD(), combineShiftAnd1ToBitTest(), CombineVLDDUP(), llvm::SelectionDAG::computeKnownBits(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::SystemZTargetLowering::computeKnownBitsForTargetNode(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::ScheduleDAGSDNodes::computeOperandLatency(), llvm::SelectionDAG::computeOverflowKind(), createBSWAPShuffleMask(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), EmitTest(), ExtendUsesToFormExtLoad(), findUnwindDestinations(), FixedPointIntrinsicToOpcode(), foldAddSubMasked1(), foldMaskedShiftToBEXTR(), getAsCarry(), getBuildPairElt(), getCondFromNode(), getContiguousRangeOfSetBits(), llvm::RegsForValue::getCopyToRegs(), llvm::DenseMapInfo< SDValue >::getHashValue(), llvm::SDUse::getResNo(), getUnderlyingArgRegs(), isFusableLoadOpStorePattern(), isOverflowIntrOpRes(), isX86LogicalCmp(), matchLSNode(), mayUseCarryFlag(), performNEONPostLDSTCombine(), performPostLD1Combine(), PerformVMOVDRRCombine(), llvm::ResourcePriorityQueue::rawRegPressureDelta(), llvm::SelectionDAG::ReplaceAllUsesOfValuesWith(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SelectionDAG::ReplaceAllUsesWith(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), llvm::SelectionDAG::salvageDebugInfo(), llvm::ResourcePriorityQueue::scheduledNode(), selectI64Imm(), and llvm::SelectionDAG::transferDbgValues().

◆ getScalarValueSizeInBits()

unsigned llvm::SDValue::getScalarValueSizeInBits ( ) const
inline

Definition at line 177 of file SelectionDAGNodes.h.

References llvm::Depth, llvm::dump(), G, getDebugLoc(), getOpcode(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), hasOneUse(), and isUndef().

Referenced by calculateByteProvider(), combineExtractWithShuffle(), combineGatherScatter(), combineHorizontalPredicateResult(), combineMaskedStore(), combineMOVMSK(), combineMulToPMADDWD(), combineScalarToVector(), combineShiftAnd1ToBitTest(), combineShiftOfShiftedLogic(), combineTargetShuffle(), combineTruncatedArithmetic(), combineTruncationShuffle(), combineVectorPack(), combineX86GatherScatter(), combineZext(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), computeNumSignBitsBinOp(), llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), ConvertI1VectorToInteger(), detectSSatPattern(), EmitTest(), findEltLoadSrc(), foldAddSubMasked1(), foldAddSubOfSignBit(), foldExtendedSignBitTest(), FoldIntToFPToInt(), foldShuffleOfHorizOp(), foldVectorXorShiftIntoCmp(), llvm::SelectionDAG::GetDemandedBits(), getShiftAmountTyForConstant(), getUsefulBits(), getValidMinimumShiftAmountConstant(), getValidShiftAmountConstant(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::isAllOnesOrAllOnesSplat(), llvm::isBitwiseNot(), isCalleeLoad(), isConstantOrConstantVector(), llvm::X86::isConstantSplat(), llvm::isOneOrOneSplat(), isTruncateOf(), LowerEXTRACT_VECTOR_ELT(), LowerScalarVariableShift(), lowerShuffleAsBroadcast(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformVDUPLANECombine(), ShrinkLoadReplaceStoreWithStore(), llvm::SelectionDAG::SignBitIsZero(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), simplifyDivRem(), llvm::SelectionDAG::simplifyShift(), truncateVecElts(), tryFoldToZero(), visitFMinMax(), and widenSubVector().

◆ getSimpleValueType()

MVT llvm::SDValue::getSimpleValueType ( ) const
inline

Return the simple ValueType of the referenced return value.

Definition at line 168 of file SelectionDAGNodes.h.

References llvm::EVT::getSimpleVT().

Referenced by buildFromShuffleMostly(), callingConvSupported(), canFoldInAddressingMode(), combineAcrossLanesIntrinsic(), combineBasicSADPattern(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineExtInVec(), combineExtractSubvector(), combineInsertSubvector(), combineLoopMAddPattern(), combineMOVMSK(), combineRedundantDWordShuffle(), combineTargetShuffle(), combineX86AddSub(), combineX86INT_TO_FP(), combineX86ShuffleChain(), combineX86ShufflesConstants(), combineX86ShufflesRecursively(), convertShiftLeftToScale(), EmitKORTEST(), ExpandHorizontalBinOp(), ExtendToType(), ExtractBitFromMaskVector(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), getAVX2GatherNode(), getCopyFromPartsVector(), getFauxShuffleMask(), getGatherNode(), getMaskNode(), llvm::SelectionDAG::getNode(), getNullFPConstForNullVal(), getPMOVMSKB(), getPrefetchNode(), getPromotedVectorElementType(), getPSHUFShuffleMask(), getPTXCmpMode(), getReductionSDNode(), getScalarMaskingNode(), getScalarValueForVectorElement(), getScatterNode(), getShuffleHalfVectors(), getShuffleScalarElt(), getShuffleVectorZeroOrUndef(), getTargetShuffleAndZeroables(), getTargetVShiftByConstNode(), getTargetVShiftNode(), getUnderlyingExtractedFromVec(), getVectorMaskingNode(), getVPTESTMOpc(), hasSingleUsesFromRoot(), incDecVectorConstant(), insert1BitVector(), InsertBitToMaskVector(), isAddSubOrSubAdd(), isCalleeLoad(), isHorizontalBinOp(), Lower256IntUnary(), Lower256IntVSETCC(), Lower512IntUnary(), LowerABS(), LowerADDSAT_SUBSAT(), lowerAddSub(), lowerAddSubToHorizontalOp(), LowerADJUST_TRAMPOLINE(), LowerANY_EXTEND(), LowerAVXCONCAT_VECTORS(), LowerAVXExtend(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), LowerBUILD_VECTORAsVariablePermute(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), LowerBuildVectorAsInsert(), LowerBuildVectorv4x32(), LowerCMP_SWAP(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), LowerCTLZ(), LowerCTPOP(), LowerCTTZ(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_VECTOR_ELT_SSE4(), lowerFABS64(), LowerFABSorFNEG(), LowerFCOPYSIGN(), LowerFGETSIGN(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), LowerFPToInt(), LowerFunnelShift(), LowerHorizontalByteSum(), LowerI64IntToFP_AVX512DQ(), LowerINSERT_SUBVECTOR(), LowerIntVSETCC_AVX512(), LowerLoad(), LowerMGATHER(), LowerMINMAX(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerMUL(), LowerMULH(), LowerRotate(), LowerSCALAR_TO_VECTOR(), LowerScalarImmediateShift(), LowerScalarVariableShift(), LowerShift(), LowerShiftParts(), lowerShuffleAsBroadcast(), lowerShuffleAsInsertPS(), lowerShuffleWithVPMOV(), LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), LowerSIGN_EXTEND_Mask(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), LowerStore(), LowerTruncateVecI1(), LowerUINT_TO_FP_i32(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vec(), lowerUINT_TO_FP_vXi32(), lowerV16F32Shuffle(), lowerV16I16Shuffle(), lowerV16I32Shuffle(), lowerV16I8Shuffle(), lowerV2F64Shuffle(), lowerV2I64Shuffle(), lowerV32I16Shuffle(), lowerV32I8Shuffle(), lowerV4F32Shuffle(), lowerV4F64Shuffle(), lowerV4I32Shuffle(), lowerV4I64Shuffle(), lowerV64I8Shuffle(), lowerV8F32Shuffle(), lowerV8F64Shuffle(), lowerV8I16Shuffle(), lowerV8I32Shuffle(), lowerV8I64Shuffle(), LowerVectorCTLZ(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), LowerVectorCTPOPInRegLUT(), LowerVectorIntUnary(), lowerVectorShuffle(), LowerVSETCC(), LowerZERO_EXTEND(), LowerZERO_EXTEND_Mask(), matchShuffleAsInsertPS(), materializeVectorConstant(), narrowExtractedVectorSelect(), parseTexFail(), llvm::SparcTargetLowering::PerformBITCASTCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performFDivCombine(), performFpToIntCombine(), PerformVCVTCombine(), PerformVDIVCombine(), PrepareCall(), recoverFramePointer(), llvm::SITargetLowering::shouldEmitPCReloc(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), simplifyDivRem(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), split256IntArith(), split512IntArith(), splitAndLowerShuffle(), splitVectorStore(), stripTruncAndExt(), tryExtendDUPToExtractHigh(), unrollVectorShift(), vectorizeExtractedCast(), and widenSubVector().

◆ getValue()

SDValue llvm::SDValue::getValue ( unsigned  R) const
inline

Definition at line 157 of file SelectionDAGNodes.h.

References isOperandOf(), and N.

Referenced by AddCombineTo64bitMLAL(), addStackMapLiveVars(), adjustLoadValueTypeImpl(), llvm::analyzeArguments(), AnalyzeReturnValues(), llvm::AVRDAGToDAGISel::select< AVRISD::CALL >(), llvm::AVRDAGToDAGISel::select< ISD::BRIND >(), llvm::AVRDAGToDAGISel::select< ISD::LOAD >(), llvm::X86TargetLowering::BuildFILD(), callingConvSupported(), canFoldInAddressingMode(), CC_Lanai32_VarArg(), CC_RISCV_FastCC(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), llvm::ARMTargetLowering::CCAssignFnForReturn(), checkVSELConstraints(), CollectOpsToWiden(), combineADDCARRYDiamond(), combineBitcast(), combineCMP(), combineCVTP2I_CVTTP2I(), combineExtInVec(), combineExtractSubvector(), combineExtractWithShuffle(), combineInsertSubvector(), combineLoad(), combineMaskedLoadConstantMask(), combineParity(), combineSetCCAtomicArith(), combineShiftAnd1ToBitTest(), combineShuffle(), combineSIntToFP(), combineTargetShuffle(), combineX86INT_TO_FP(), ConvertBooleanCarryToCarryFlag(), ConvertCarryFlagToBooleanCarry(), createBSWAPShuffleMask(), llvm::createR600ISelDag(), llvm::MipsSETargetLowering::EmitInstrWithCustomInserter(), emitRepmovs(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemcmp(), llvm::BPFSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), EmitTest(), EnsureStackAlignment(), Expand64BitShift(), ExpandBITCAST(), expandIntrinsicWChainHelper(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), ExtendUsesToFormExtLoad(), extractBooleanFlip(), findMatchingInlineAsmOperand(), findUnwindDestinations(), FixedPointIntrinsicToOpcode(), foldBitcastedFPLogic(), foldExtendedSignBitTest(), FoldIntToFPToInt(), fp16SrcZerosHighBits(), generateEquivalentSub(), getAArch64XALUOOp(), getARClassRegisterMask(), getAVX2GatherNode(), getBufferOffsetForMMO(), getContiguousRangeOfSetBits(), llvm::RegsForValue::getCopyFromRegs(), llvm::RegsForValue::getCopyToRegs(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getExpandedMinMaxOps(), getFPBinOp(), GetFPLibCall(), getFPTernOp(), getGatherNode(), llvm::XCoreTargetLowering::getJumpTableEncoding(), llvm::ARMTargetLowering::getJumpTableEncoding(), getLoadExtOrTrunc(), getMemCmpLoad(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), getMOVL(), getMul24(), llvm::MipsTargetLowering::getOpndList(), getPromotedVectorElementType(), GetPromotionOpcode(), getReadTimeStampCounter(), getReductionSDNode(), getScatterNode(), getShiftAmountTyForConstant(), getSPDenormModeValue(), llvm::ARCTargetLowering::getTargetNodeName(), GetTLSADDR(), getUniformBase(), getv64i1Argument(), GetVBR(), getVCmpInst(), getVectorCompareInfo(), getVPTESTMOpc(), isCalleeLoad(), isFloatingPointZero(), isFusableLoadOpStorePattern(), IsPredicateKnownToFail(), isSlicingProfitable(), isSubBorrowChain(), isTruncateOf(), llvm::SITargetLowering::isTypeDesirableForOp(), isVectorElementSwap(), isWordAligned(), llvm::SITargetLowering::legalizeTargetIndependentNode(), LowerADDC_ADDE_SUBC_SUBE(), llvm::HexagonTargetLowering::LowerAddSubCarry(), LowerADDSUBCARRY(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), lowerAtomicArith(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), llvm::HexagonTargetLowering::LowerCallResult(), llvm::SITargetLowering::LowerCallResult(), LowerCallResult(), llvm::SelectionDAGBuilder::LowerCallSiteWithDeoptBundle(), LowerCMP_SWAP(), LowerCTLZ(), LowerCTTZ(), LowerDYNAMIC_STACKALLOC(), lowerFABS64(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerInterruptReturn(), LowerINTRINSIC_W_CHAIN(), llvm::MipsTargetLowering::lowerLOAD(), LowerMGATHER(), LowerMLOAD(), llvm::BPFTargetLowering::LowerOperation(), llvm::MipsTargetLowering::LowerOperationWrapper(), llvm::SystemZTargetLowering::LowerOperationWrapper(), llvm::X86TargetLowering::LowerOperationWrapper(), LowerPredicateLoad(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), lowerRegToMasks(), llvm::HexagonTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), LowerToTLSExecModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), LowerToTLSGeneralDynamicModel32(), LowerToTLSLocalDynamicModel(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vec(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), LowerVASTART(), LowerVECTOR_SHUFFLE(), LowerVectorINT_TO_FP(), LowerXOR(), mayTailCallThisCC(), numVectorEltsOrZero(), parseTexFail(), Passv64i1ArgInRegs(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performDivRemCombine(), performIntToFpCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), PerformSETCCCombine(), PerformSTORECombine(), PerformVDUPCombine(), PerformVMOVRRDCombine(), PrepareCall(), PrepareTailCall(), recoverFramePointer(), reduceMaskedLoadToScalarLoad(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), ReplaceLongIntrinsic(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::AVRTargetLowering::ReplaceNodeResults(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::ARMTargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceREADCYCLECOUNTER(), scalarizeBinOpOfSplats(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::SelectionDAGISel::SelectCodeCommon(), selectI64Imm(), selectSGPRVectorRegClassID(), llvm::SITargetLowering::shouldEmitPCReloc(), ShrinkLoadReplaceStoreWithStore(), simplifyDivRem(), SkipExtensionForVMULL(), splitStores(), splitStoreSplat(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), tryToElideArgumentCopy(), tryToFoldExtOfExtload(), tryToFoldExtOfLoad(), UnpackFromArgumentSlot(), llvm::SelectionDAG::UnrollVectorOverflowOp(), llvm::SelectionDAGBuilder::visitJumpTable(), and llvm::AMDGPUTargetLowering::WidenVectorLoad().

◆ getValueSizeInBits()

unsigned llvm::SDValue::getValueSizeInBits ( ) const
inline

Returns the size of the value in bits.

Definition at line 173 of file SelectionDAGNodes.h.

References llvm::EVT::getSizeInBits().

Referenced by llvm::X86TargetLowering::BuildFILD(), calculateByteProvider(), CalculateTailCallArgDest(), llvm::SelectionDAGISel::CheckAndMask(), checkBitcastSrcVectorSize(), CheckForMaskedLoad(), llvm::SelectionDAGISel::CheckOrMask(), combineBT(), combineExtractSubvector(), combineExtractWithShuffle(), combineHorizontalPredicateResult(), combineInsertSubvector(), combineLoopSADPattern(), combineReductionToHorizontal(), combineShiftAnd1ToBitTest(), combineShiftLeft(), combineStore(), combineVectorCompareAndMaskUnaryOp(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineZext(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), ConstantBuildVector(), ConvertI1VectorToInteger(), createBSWAPShuffleMask(), createVariablePermute(), EltsFromConsecutiveLoads(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), foldBitcastedFPLogic(), foldMaskedShiftToBEXTR(), foldShuffleOfHorizOp(), generateEquivalentSub(), GenerateTBL(), getHopForBuildVector(), getNextIntArgReg(), llvm::SelectionDAG::getNode(), getPermuteMask(), getTestBitOperand(), insertDAGNode(), isSimpleShift(), isTruncateOf(), isTruncWithZeroHighBitsInput(), LowerAndToBT(), lowerBuildVectorAsBroadcast(), lowerBuildVectorToBitOp(), lowerFCOPYSIGN64(), lowerFP_TO_SINT_STORE(), llvm::NVPTXTargetLowering::LowerReturn(), lowerShuffleAsBroadcast(), llvm::MipsTargetLowering::lowerSTORE(), lowerV8I16GeneralSingleInputShuffle(), maskMatters(), MatchingStackOffset(), mayTailCallThisCC(), mayUseP9Setb(), llvm::RISCVTargetLowering::PerformDAGCombine(), performIntToFpCombine(), reduceBuildVecToShuffleWithZero(), scalarizeExtractedBinop(), selectI64Imm(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), simplifyI24(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), spillIncomingStatepointValue(), splitVectorStore(), stripTruncAndExt(), tryCombineFixedPointConvert(), tryFormConcatFromShuffle(), VerifySDNode(), and widenSubVector().

◆ getValueType()

EVT llvm::SDValue::getValueType ( ) const
inline

Return the ValueType of the referenced return value.

Definition at line 1162 of file SelectionDAGNodes.h.

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64bitMLAL(), AddCombineVUZPToVPADDL(), addShuffleForVecExtend(), llvm::AVRDAGToDAGISel::select< ISD::STORE >(), llvm::X86TargetLowering::BuildFILD(), buildFromShuffleMostly(), BuildIntrinsicOp(), buildPCRelGlobalAddress(), calculateByteProvider(), callingConvSupported(), canChangeToInt(), CanCombineFCOPYSIGN_EXTEND_ROUND(), canEmitConjunction(), canFoldInAddressingMode(), canReduceVMulWidth(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), CheckForMaskedLoad(), CheckType(), clampDynamicVectorIndex(), collectConcatOps(), CollectOpsToWiden(), combineAdd(), combineADDCARRYDiamond(), combineAddOrSubToADCOrSBB(), combineADDToADDZE(), combineAnd(), combineAndMaskToShift(), CombineBaseUpdate(), combineBasicSADPattern(), combineBitcast(), combineBitcastvxi1(), combineBVOfVecSExt(), combineCarryThroughADD(), combineCastedMaskArithmetic(), combineCMP(), combineCompareEqual(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineConcatVectorOps(), combineConcatVectors(), combineExtInVec(), combineExtractSubvector(), combineExtractVectorElt(), combineExtractWithShuffle(), combineExtSetcc(), combineFneg(), combineGatherScatter(), combineHorizontalMinMaxResult(), combineHorizontalPredicateResult(), combineLogicBlendIntoConditionalNegate(), combineLogicBlendIntoPBLENDV(), combineMaskedStore(), combineOr(), combineOrCmpEqZeroToCtlzSrl(), combinePMULDQ(), combinePMULH(), combineReductionToHorizontal(), combineRedundantDWordShuffle(), combineScalarToVector(), combineSetCC(), combineSetCCAtomicArith(), combineSext(), combineShiftAnd1ToBitTest(), combineShiftLeft(), combineShiftOfShiftedLogic(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShuffle(), combineShuffleOfScalars(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineSub(), combineSubToSubus(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToExtendCMOV(), combineToFPTruncExtElt(), combineTruncate(), combineTruncateWithSat(), combineUIntToFP(), combineVectorPack(), combineVectorShiftImm(), combineVectorSignBitsTruncation(), combineVectorSizedSetCCEquality(), combineVectorTruncation(), combineVectorTruncationWithPACKSS(), combineVectorTruncationWithPACKUS(), CombineVMOVDRRCandidateWithVecOp(), combinevXi1ConstantToInteger(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineX86ShufflesRecursively(), CompactSwizzlableVector(), llvm::SelectionDAG::computeKnownBits(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), llvm::AArch64TargetLowering::computeKnownBitsForTargetNode(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::SystemZTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::SelectionDAG::ComputeNumSignBits(), computeNumSignBitsBinOp(), llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), concatSubVectors(), ConstantAddressBlock(), ConstantBuildVector(), ConvertBooleanCarryToCarryFlag(), ConvertCarryFlagToBooleanCarry(), convertIntLogicToFPLogic(), createBSWAPShuffleMask(), createFPCmp(), createLoadLR(), createPSADBW(), llvm::createR600ISelDag(), createStoreLR(), createVariablePermute(), detectAVGPattern(), detectPMADDUBSW(), detectUSatPattern(), llvm::HexagonDAGToDAGISel::DetectUseSxtw(), detectZextAbsDiff(), elementPairIsContiguous(), EltsFromConsecutiveLoads(), emitCLC(), EmitCMP(), emitComparison(), emitConditionalComparison(), emitConjunctionRec(), emitConstantSizeRepmov(), llvm::MipsSETargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), EmitKORTEST(), emitMemMem(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrlen(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrnlen(), EmitTest(), EmitTruncSStore(), EmitVectorComparison(), EnsureStackAlignment(), ExpandBITCAST(), ExpandBVWithShuffles(), expandExp(), expandExp2(), expandf64Toi32(), expandLog(), expandLog10(), expandLog2(), expandPow(), ExpandPowI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::PPCTargetLowering::expandVSXStoreForLE(), ExtendToType(), ExtendUsesToFormExtLoad(), extract128BitVector(), extract256BitVector(), ExtractBitFromMaskVector(), extractBooleanFlip(), extractShiftForRotate(), extractSubVector(), findMatchingInlineAsmOperand(), findMemSDNode(), findUnwindDestinations(), FixedPointIntrinsicToOpcode(), flipBoolean(), foldAddSubBoolOfMaskedVal(), foldAddSubMasked1(), foldAddSubOfSignBit(), foldBitcastedFPLogic(), foldCONCAT_VECTORS(), llvm::SelectionDAG::FoldConstantVectorArithmetic(), foldExtendedSignBitTest(), foldFPToIntToFP(), FoldIntToFPToInt(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldShuffleOfHorizOp(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), fp16SrcZerosHighBits(), generateEquivalentSub(), GeneratePerfectShuffle(), GenerateTBL(), getAArch64Cmp(), getAArch64XALUOOp(), getAbsolute(), llvm::SelectionDAG::getAnyExtOrTrunc(), getAsCarry(), getAsNonOpaqueConstant(), llvm::SelectionDAG::getAtomic(), llvm::SelectionDAG::getAtomicCmpSwap(), getAVX2GatherNode(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBoolExtOrTrunc(), getBoundedStrlen(), getBufferOffsetForMMO(), getBuildDwordsVector(), getCCResult(), getCmpOperandFoldingProfit(), getCopyFromParts(), getCopyFromPartsVector(), getCopyToParts(), getCopyToPartsVector(), llvm::SelectionDAG::getCopyToReg(), llvm::DAGTypeLegalizer::getDAG(), llvm::SelectionDAG::GetDemandedBits(), getDemandedSrcElements(), getDUPLANEOp(), getEstimate(), getEstimateRefinementSteps(), getExpandedMinMaxOps(), getExtendInVec(), getExtendTypeForNode(), getExtFactor(), llvm::SelectionDAG::getExtLoad(), getFauxShuffleMask(), llvm::SelectionDAG::getFPExtendOrRound(), GetFPLibCall(), getFRAMEADDR(), getGatherNode(), getGeneralPermuteNode(), llvm::SelectionDAG::getIndexedLoad(), llvm::SelectionDAG::getIndexedStore(), getInputChainForNode(), llvm::XCoreTargetLowering::getJumpTableEncoding(), getKnownUndefForVectorBinop(), getLeftShift(), llvm::SelectionDAG::getLoad(), getLoadExtOrTrunc(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getMaskedStore(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getMemBasePlusOffset(), getMemCmpLoad(), getMemsetStores(), getMemsetValue(), getMOVL(), llvm::X86TargetLowering::getNegatedExpression(), llvm::TargetLowering::getNegatedExpression(), llvm::SelectionDAG::getNode(), getNormalLoadInput(), getNullFPConstForNullVal(), llvm::SelectionDAG::getObjectPtrOffset(), getPermuteMask(), llvm::HexagonTargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), GetPromotionOpcode(), llvm::AMDGPUTargetLowering::getRecipEstimate(), getReductionSDNode(), getScalarMaskingNode(), getScatterNode(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSelectCC(), llvm::SelectionDAG::getSetCC(), llvm::AVRTargetLowering::getSetCCResultType(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::SelectionDAG::getShiftAmountOperand(), getShiftAmountTyForConstant(), getShuffleHalfVectors(), getShuffleScalarElt(), getSPDenormModeValue(), llvm::SelectionDAG::getSplatBuildVector(), getSplatConstantFP(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::SelectionDAG::getSplatSourceVector(), llvm::AMDGPUTargetLowering::getSqrtEstimate(), llvm::NVPTXTargetLowering::getSqrtEstimate(), llvm::SelectionDAG::getStore(), getSubVectorSrc(), getTargetNode(), llvm::ARCTargetLowering::getTargetNodeName(), llvm::SystemZTargetLowering::getTargetNodeName(), getTargetShuffleAndZeroables(), getTargetShuffleInputs(), getTargetShuffleMask(), llvm::SelectionDAG::getTruncStore(), getUnderlyingArgRegs(), getUniformBase(), llvm::SDUse::getValueType(), GetVBR(), getVCmpInst(), getVectorCompareInfo(), llvm::TargetLowering::getVectorElementPointer(), llvm::SelectionDAG::getVectorShuffle(), getVPermMask(), getVPTESTMOpc(), llvm::SelectionDAG::getZeroExtendInReg(), getZeroVector(), llvm::SelectionDAG::getZExtOrTrunc(), gwsIntrinToOpcode(), llvm::AArch64TargetLowering::hasAndNot(), llvm::X86TargetLowering::hasAndNot(), llvm::AArch64TargetLowering::hasAndNotCompare(), llvm::X86TargetLowering::hasAndNotCompare(), llvm::HexagonTargetLowering::hasBitTest(), llvm::X86TargetLowering::hasBitTest(), hasSingleUsesFromRoot(), haveEfficientBuildVectorPattern(), llvm::SelectionDAG::haveNoCommonBitsSet(), llvm::TargetLowering::IncrementMemoryAddress(), insert128BitVector(), InsertBitToMaskVector(), insertDAGNode(), insertSubVector(), llvm::intCCToAVRCC(), IntCondCCodeToICC(), isBitfieldExtractOpFromShr(), isBitfieldPositioningOp(), isBoolSGPR(), isBSwapHWordPair(), llvm::SITargetLowering::isCanonicalized(), isClampZeroToOne(), isConditionalZeroOrAllOnes(), llvm::isConstOrConstSplat(), isContractable(), llvm::RISCVTargetLowering::isDesirableToCommuteWithShift(), llvm::X86TargetLowering::IsDesirableToPromoteOp(), isEssentiallyExtractHighSubvector(), isFloatingPointZero(), isFPExtLoad(), isHorizontalBinOp(), isHorizontalBinOpPart(), isI24(), llvm::SelectionDAG::isKnownNeverZero(), llvm::SelectionDAG::isKnownNeverZeroFloat(), llvm::SelectionDAG::isKnownToBeAPowerOfTwo(), llvm::ARCTargetLowering::isLegalAddressingMode(), llvm::PPCTargetLowering::isLegalAddressingMode(), isLegalMaskCompare(), isLegalToCombineMinNumMaxNum(), llvm::SelectionDAGISel::IsLegalToFold(), isLowerSaturatingConditional(), isMemOPCandidate(), IsMulWideOperandDemotable(), llvm::X86TargetLowering::isNegatibleForFree(), llvm::TargetLowering::isNegatibleForFree(), isNegativeOne(), IsNOT(), isOpcWithIntImmediate(), llvm::SelectionDAGISel::isOrEquivalentToAdd(), isPerfectIncrement(), llvm::ARMTargetLowering::isReadOnly(), IsSmallObject(), llvm::ShuffleVectorSDNode::isSplat(), llvm::SelectionDAG::isSplatValue(), isSubBorrowChain(), isTargetConstant(), isTruncateOf(), isVectorElementSwap(), llvm::ARMTargetLowering::isVectorLoadExtDesirable(), llvm::X86TargetLowering::isVectorLoadExtDesirable(), isVectorReductionOp(), isVMOVModifiedImm(), isVShiftRImm(), llvm::XCoreTargetLowering::isZExtFree(), llvm::MSP430TargetLowering::isZExtFree(), llvm::AMDGPUTargetLowering::isZExtFree(), llvm::AArch64TargetLowering::isZExtFree(), llvm::ARMTargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), llvm::TargetLoweringBase::isZExtFree(), llvm::SITargetLowering::legalizeTargetIndependentNode(), LowerADDC_ADDE_SUBC_SUBE(), LowerADDSUBCARRY(), lowerAddSubToHorizontalOp(), LowerAndToBT(), llvm::SparcTargetLowering::LowerAsmOperandForConstraint(), llvm::LanaiTargetLowering::LowerAsmOperandForConstraint(), llvm::AVRTargetLowering::LowerAsmOperandForConstraint(), llvm::SystemZTargetLowering::LowerAsmOperandForConstraint(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), LowerAsSplatVectorLoad(), LowerBITCAST(), llvm::MSP430TargetLowering::LowerBR_CC(), LowerBR_CC(), LowerBUILD_VECTOR_i1(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), llvm::HexagonTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS_i1(), llvm::HexagonTargetLowering::LowerConstantPool(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), lowerDSPIntr(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT_i1(), LowerF128_FPEXTEND(), LowerF128_FPROUND(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Compare(), LowerF128Load(), llvm::SparcTargetLowering::LowerF128Op(), LowerF128Store(), LowerF64Op(), lowerFABS32(), lowerFABS64(), lowerFCMPIntrinsic(), lowerFCOPYSIGN32(), lowerFCOPYSIGN64(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::AMDGPUTargetLowering::LowerFLOG(), llvm::AMDGPUTargetLowering::LowerFNEARBYINT(), LowerFNEGorFABS(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), llvm::AMDGPUTargetLowering::LowerFP_TO_SINT(), LowerFP_TO_SINT(), llvm::AMDGPUTargetLowering::LowerFP_TO_UINT(), LowerFP_TO_UINT(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), llvm::AMDGPUTargetLowering::LowerFREM(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerFROUND(), llvm::AMDGPUTargetLowering::LowerFROUND32_16(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), LowerFunnelShift(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), lowerICMPIntrinsic(), lowerIncomingStatepointValue(), llvm::HexagonTargetLowering::LowerINLINEASM(), LowerINSERT_VECTOR_ELT_i1(), LowerInterruptReturn(), LowerINTRINSIC_W_CHAIN(), llvm::HexagonTargetLowering::LowerJumpTable(), LowerLabelRef(), llvm::MipsTargetLowering::lowerLOAD(), lowerMasksToReg(), LowerMSCATTER(), LowerMUL(), LowerMULH(), llvm::R600TargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), llvm::ARMTargetLowering::LowerOperation(), llvm::NVPTXTargetLowering::LowerOperation(), LowerPredicateLoad(), LowerPredicateStore(), LowerPREFETCH(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(), LowerSDIV(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::MSP430TargetLowering::LowerSELECT_CC(), LowerSELECT_CC(), llvm::MSP430TargetLowering::LowerSETCC(), LowerShift(), llvm::MSP430TargetLowering::LowerShifts(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), lowerShuffleAsBroadcast(), lowerShuffleAsElementInsertion(), lowerShuffleAsTruncBroadcast(), lowerShuffleOfExtractsAsVperm(), lowerShuffleToEXPAND(), llvm::MSP430TargetLowering::LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSINT_TO_FP(), LowerSINT_TO_FP(), lowerStatepointMetaArgs(), llvm::MipsTargetLowering::lowerSTORE(), LowerStore(), LowerSTRICT_FP_ROUND(), LowerTruncateVectorStore(), LowerUDIV(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), llvm::AMDGPUTargetLowering::LowerUINT_TO_FP(), LowerUINT_TO_FP(), lowerUINT_TO_FP_vec(), LowerUMULO_SMULO(), lowerUnalignedIntStore(), LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), LowerVectorFP_TO_INT(), LowerVectorINT_TO_FP(), LowerVSETCC(), LowerWRITE_REGISTER(), lowerX86CmpEqZeroToCtlzSrl(), LowerXALUO(), LowerXOR(), llvm::SparcTargetLowering::makeAddress(), llvm::SparcTargetLowering::makeHiLoPair(), llvm::SelectionDAG::MaskedValueIsZero(), maskMatters(), llvm::ISD::matchBinaryPredicate(), llvm::SelectionDAG::matchBinOpReduction(), matchBitOpReduction(), MatchingStackOffset(), matchPMADDWD(), matchPMADDWD_2(), matchRotateSub(), llvm::ISD::matchUnaryPredicate(), mayTailCallThisCC(), mayUseP9Setb(), narrowExtractedVectorBinOp(), narrowExtractedVectorLoad(), narrowIfNeeded(), narrowInsertExtractVectorBinOp(), NarrowVector(), needCarryOrOverflowFlag(), NegateCC(), NormalizeBuildVector(), llvm::AMDGPUTargetLowering::numBitsSigned(), llvm::AMDGPUTargetLowering::numBitsUnsigned(), numVectorEltsOrZero(), onlyZeroFlagUsed(), optimizeLogicalImm(), parsePredicateConstraint(), parseTexFail(), partitionShuffleOfConcats(), Passv64i1ArgInRegs(), PeepholePPC64ZExtGather(), PerformADDCombineWithOperands(), PerformANDCombine(), PerformARMBUILD_VECTORCombine(), llvm::AMDGPUTargetLowering::performAssertSZExtCombine(), performBRCONDCombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), performConcatVectorsCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::ARMTargetLowering::PerformDAGCombine(), llvm::SITargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformExtendCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), performFDivCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFpToIntCombine(), PerformIntrinsicCombine(), performNEONPostLDSTCombine(), performNVCASTCombine(), PerformPREDICATE_CASTCombine(), performSELECTCombine(), performSelectCombine(), performSetccAddFolding(), PerformSETCCCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), PerformSTORECombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformTruncatingStoreCombine(), PerformVCVTCombine(), PerformVDIVCombine(), PerformVECTOR_SHUFFLECombine(), performVSelectCombine(), pickOpcodeForVT(), PrepareCall(), PromoteMaskArithmetic(), llvm::AArch64TargetLowering::ReconstructShuffle(), recoverFramePointer(), reduceBuildVecToShuffleWithZero(), reduceMaskedStoreToScalarStore(), reduceVMULWidth(), ReorganizeVector(), ReplaceBITCASTResults(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceSplatVectorStore(), replaceZeroVectorStore(), scalarizeBinOpOfSplats(), scalarizeExtractedBinop(), llvm::TargetLowering::scalarizeVectorStore(), scalarizeVectorStore(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::PPCTargetLowering::SelectAddressRegRegOnly(), llvm::HexagonDAGToDAGISel::SelectAnyImmediate(), llvm::HexagonDAGToDAGISel::SelectAnyInt(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectGlobalAddress(), selectI64Imm(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::HexagonDAGToDAGISel::SelectTypecast(), llvm::HexagonDAGToDAGISel::SelectV2Q(), llvm::SelectionDAG::setRoot(), setUsesTOCBasePtr(), llvm::SITargetLowering::shouldEmitPCReloc(), llvm::HexagonTargetLowering::shouldExpandAtomicRMWInIR(), llvm::MipsTargetLowering::shouldFoldConstantShiftPairToMask(), llvm::X86TargetLowering::shouldFoldMaskToVariableShiftPair(), llvm::AArch64TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(), llvm::X86TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(), llvm::X86TargetLowering::shouldScalarizeBinop(), llvm::TargetLowering::ShrinkDemandedConstant(), llvm::TargetLowering::ShrinkDemandedOp(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), simplifyDivRem(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), llvm::SelectionDAG::simplifyShift(), simplifyShuffleOfShuffle(), llvm::TargetLowering::softenSetCCOperands(), spillIncomingStatepointValue(), llvm::SITargetLowering::splitBinaryVectorOp(), splitStores(), splitStoreSplat(), llvm::SITargetLowering::splitTernaryVectorOp(), llvm::SITargetLowering::splitUnaryVectorOp(), llvm::AMDGPUTargetLowering::splitVector(), llvm::SelectionDAG::SplitVector(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), splitVectorStore(), stripModuloOnShift(), stripTruncAndExt(), llvm::AArch64TargetLowering::targetShrinkDemandedConstant(), llvm::ARMTargetLowering::targetShrinkDemandedConstant(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), TranslateX86CC(), truncateVectorWithPACK(), tryAdvSIMDModImm16(), tryAdvSIMDModImm32(), tryAdvSIMDModImm321s(), tryAdvSIMDModImm64(), tryAdvSIMDModImm8(), tryAdvSIMDModImmFP(), tryBitfieldInsertOpFromOr(), tryCombineFixedPointConvert(), tryCombineLongOpWithDup(), tryFoldToZero(), tryFormConcatFromShuffle(), tryLowerToSLI(), tryToElideArgumentCopy(), tryToFoldExtendOfConstant(), tryToFoldExtOfLoad(), llvm::SelectionDAG::UnrollVectorOp(), unrollVectorShift(), llvm::SelectionDAG::updateDivergence(), vectorEltWillFoldAway(), llvm::SelectionDAG::VerifyDAGDiverence(), VerifySDNode(), llvm::SelectionDAGBuilder::visitBitTestHeader(), visitFMinMax(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), visitORCommutative(), widenSubVector(), widenVec(), llvm::SelectionDAG::WidenVector(), WidenVector(), llvm::AMDGPUTargetLowering::WidenVectorLoad(), widenVectorToPartType(), willShiftRightEliminate(), WinDBZCheckDenominator(), llvm::SparcTargetLowering::withTargetFlags(), XFormVExtractWithShuffleIntoLoad(), and zeroExtendToMatch().

◆ hasOneUse()

bool llvm::SDValue::hasOneUse ( ) const
inline

Return true if there is exactly one node using value ResNo of Node.

Definition at line 1206 of file SelectionDAGNodes.h.

Referenced by calculateByteProvider(), canEmitConjunction(), canonicalizeBitSelect(), CheckForMaskedLoad(), combineAddOrSubToADCOrSBB(), combineADDToADDZE(), combineBitcast(), combineBitcastvxi1(), combineCastedMaskArithmetic(), combineCMP(), combineConcatVectorOfExtracts(), combineCVTP2I_CVTTP2I(), combineExtInVec(), combineExtractSubvector(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFneg(), combineInsertSubvector(), combineOr(), combineParity(), combinePMULDQ(), combineRedundantDWordShuffle(), combineScalarToVector(), combineSetCC(), combineSetCCAtomicArith(), combineSext(), combineSextInRegCmov(), combineShiftAnd1ToBitTest(), combineShiftOfShiftedLogic(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShuffle(), combineShuffleToFMAddSub(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineToExtendCMOV(), combineToFPTruncExtElt(), CombineVMOVDRRCandidateWithVecOp(), combineX86INT_TO_FP(), combineX86ShufflesConstants(), combineZext(), llvm::createR600ISelDag(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), EmitKORTEST(), ExtendUsesToFormExtLoad(), foldAddSubMasked1(), foldAddSubOfSignBit(), foldBitcastedFPLogic(), foldExtendedSignBitTest(), FoldIntToFPToInt(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), fp16SrcZerosHighBits(), generateEquivalentSub(), getAsNonOpaqueConstant(), getCmpOperandFoldingProfit(), getGeneralPermuteNode(), getInputChainForNode(), llvm::X86TargetLowering::getNegatedExpression(), getPermuteMask(), getSplatConstantFP(), getVPTESTMOpc(), isADDADDMUL(), isAndOrOfSetCCs(), isAnyConstantBuildVector(), isBitfieldPositioningOp(), isCalleeLoad(), isClampZeroToOne(), isContractable(), llvm::X86TargetLowering::IsDesirableToPromoteOp(), isFusableLoadOpStorePattern(), isHopBuildVector(), isLegalMaskCompare(), llvm::X86TargetLowering::isNegatibleForFree(), llvm::TargetLowering::isNegatibleForFree(), IsNOT(), llvm::SelectionDAGISel::IsProfitableToFold(), isTargetConstant(), isTruncateOf(), isValidIndexedLoad(), isVectorElementSwap(), isXor1OfSetCC(), lowerAddSubToHorizontalOp(), LowerEXTRACT_VECTOR_ELT_SSE4(), llvm::MSP430TargetLowering::LowerSETCC(), lowerShuffleAsBroadcast(), lowerShuffleOfExtractsAsVperm(), LowerStore(), MayFoldIntoStore(), MayFoldIntoZeroExtend(), MayFoldLoad(), mayUseP9Setb(), narrowExtractedVectorBinOp(), narrowExtractedVectorLoad(), llvm::peekThroughOneUseBitcasts(), PeepholePPC64ZExtGather(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performIntToFpCombine(), performMADD_MSUBCombine(), PerformORCombine(), PerformSplittingToWideningLoad(), llvm::AMDGPUTargetLowering::performStoreCombine(), PerformVDUPCombine(), reachesChainWithoutSideEffects(), reduceBuildVecToShuffleWithZero(), replaceZeroVectorStore(), scalarizeBinOpOfSplats(), scalarizeExtractedBinop(), llvm::PPCTargetLowering::SelectAddressRegRegOnly(), selectI64Imm(), llvm::AArch64TargetLowering::shouldReduceLoadWidth(), shouldUseZeroOffsetLdSt(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), simplifyDivRem(), simplifyShuffleOfShuffle(), stripTruncAndExt(), tryBitfieldInsertOpFromOr(), tryBitfieldInsertOpFromOrAndImm(), tryFoldToZero(), tryToFoldExtOfExtload(), tryToFoldExtOfLoad(), usePartialVectorLoads(), vectorEltWillFoldAway(), visitFMinMax(), and XFormVExtractWithShuffleIntoLoad().

◆ isMachineOpcode()

bool llvm::SDValue::isMachineOpcode ( ) const
inline

◆ isOperandOf()

bool SDValue::isOperandOf ( const SDNode N) const

Return true if this node is an operand of N.

isOperand - Return true if this node is an operand of N.

Definition at line 8935 of file SelectionDAG.cpp.

References llvm::any_of(), and llvm::SDNode::op_values().

Referenced by isCalleeLoad().

◆ isTargetMemoryOpcode()

bool llvm::SDValue::isTargetMemoryOpcode ( ) const
inline

Definition at line 1186 of file SelectionDAGNodes.h.

◆ isTargetOpcode()

bool llvm::SDValue::isTargetOpcode ( ) const
inline

Definition at line 1182 of file SelectionDAGNodes.h.

◆ isUndef()

bool llvm::SDValue::isUndef ( ) const
inline

Definition at line 1198 of file SelectionDAGNodes.h.

Referenced by buildMergeScalars(), buildScalarToVector(), callingConvSupported(), CollectOpsToWiden(), combineBitcast(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineConcatVectorOps(), combineInsertSubvector(), combineMaskedLoadConstantMask(), combineMOVMSK(), combineShiftOfShiftedLogic(), combineShuffle(), combineShuffleOfConcatUndef(), combineShuffleOfScalars(), combineShuffleOfSplatVal(), combineTargetShuffle(), combineVectorPack(), combinevXi1ConstantToInteger(), combineX86ShuffleChain(), combineZext(), computeZeroableShuffleElements(), ConstantAddressBlock(), ConstantBuildVector(), ConvertI1VectorToInteger(), createMMXBuildVector(), elementPairIsContiguous(), EltsFromConsecutiveLoads(), ExpandBVWithShuffles(), ExtendToType(), foldAddSubOfSignBit(), foldBitcastedFPLogic(), FoldBUILD_VECTOR(), foldCONCAT_VECTORS(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::foldConstantFPMath(), llvm::SelectionDAG::FoldConstantVectorArithmetic(), foldFPToIntToFP(), FoldIntToFPToInt(), foldShuffleOfConcatUndefs(), foldShuffleOfHorizOp(), fp16SrcZerosHighBits(), GeneratePerfectShuffle(), llvm::PPC::get_VSPLTI_elt(), getAsNonOpaqueConstant(), getAVX2GatherNode(), getFauxShuffleMask(), getGatherNode(), getGeneralPermuteNode(), getHopForBuildVector(), llvm::SelectionDAG::getIndexedLoad(), llvm::SelectionDAG::getIndexedStore(), getKnownUndefForVectorBinop(), llvm::SelectionDAG::getLoad(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), getMemsetStores(), getMemsetValue(), llvm::SelectionDAG::getNode(), getNormalLoadInput(), getOneTrueElt(), getScalarMaskingNode(), llvm::BuildVectorSDNode::getSplatValue(), getTargetConstantBitsFromNode(), getTargetShuffleAndZeroables(), getVectorMaskingNode(), llvm::SelectionDAG::getVectorShuffle(), gwsIntrinToOpcode(), haveEfficientBuildVectorPattern(), InferPointerInfo(), insert1BitVector(), insertSubVector(), isAddSubOrSubAdd(), isBSwapHWordPair(), llvm::ISD::isBuildVectorAllOnes(), isClampZeroToOne(), isConstantOrConstantVector(), llvm::BuildVectorSDNode::isConstantSplat(), isFNEG(), isFPExtLoad(), isHopBuildVector(), isHorizontalBinOp(), isHorizontalBinOpPart(), isLegalMaskCompare(), isOpcWithIntImmediate(), isScalarToVector(), llvm::SelectionDAG::isSplatValue(), isSplatZeroExtended(), isTruncateOf(), isVectorElementSwap(), llvm::PPC::isXXINSERTWMask(), llvm::PPC::isXXPERMDIShuffleMask(), llvm::PPC::isXXSLDWIShuffleMask(), joinDwords(), lower1BitShuffleAsKSHIFTR(), LowerAVXCONCAT_VECTORS(), llvm::HexagonTargetLowering::LowerBITCAST(), LowerBUILD_VECTOR_i1(), LowerBUILD_VECTORAsVariablePermute(), LowerBUILD_VECTORvXi1(), LowerBuildVectorv4x32(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), LowerF128Load(), LowerF128Store(), LowerMLOAD(), LowerShift(), lowerShuffleAsLanePermuteAndRepeatedMask(), lowerShuffleAsLanePermuteAndShuffle(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsSplitOrBlend(), lowerShuffleAsUNPCKAndPermute(), lowerShuffleWithPERMV(), lowerShuffleWithUndefHalf(), LowerToHorizontalOp(), lowerV16F32Shuffle(), lowerV16I16Shuffle(), lowerV16I32Shuffle(), lowerV16I8Shuffle(), lowerV2F64Shuffle(), lowerV2I64Shuffle(), lowerV2X128Shuffle(), lowerV32I16Shuffle(), lowerV32I8Shuffle(), lowerV4F64Shuffle(), lowerV4I64Shuffle(), lowerV64I8Shuffle(), lowerV8F32Shuffle(), lowerV8F64Shuffle(), lowerV8I32Shuffle(), lowerV8I64Shuffle(), LowerVECTOR_SHUFFLE(), lowerVectorShuffle(), llvm::ISD::matchBinaryPredicate(), llvm::ISD::matchUnaryPredicate(), matchVectorShuffleAsBlend(), matchVectorShuffleWithPACK(), narrowExtractedVectorLoad(), numVectorEltsOrZero(), partitionShuffleOfConcats(), PerformARMBUILD_VECTORCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::SITargetLowering::PerformDAGCombine(), PerformVECTOR_SHUFFLECombine(), PrepareCall(), llvm::AArch64TargetLowering::ReconstructShuffle(), recoverFramePointer(), reduceBuildVecToShuffleWithZero(), scalarizeBinOpOfSplats(), scalarizeExtractedBinop(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), simplifyDivRem(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::SelectionDAG::simplifyShift(), simplifyShuffleOfShuffle(), stripTruncAndExt(), tryBuildVectorShuffle(), tryFoldToZero(), tryToFoldExtendOfConstant(), and vectorEltWillFoldAway().

◆ operator bool()

llvm::SDValue::operator bool ( ) const
inlineexplicit

Definition at line 153 of file SelectionDAGNodes.h.

◆ operator!=()

bool llvm::SDValue::operator!= ( const SDValue O) const
inline

Definition at line 147 of file SelectionDAGNodes.h.

References llvm::operator==().

◆ operator->()

SDNode* llvm::SDValue::operator-> ( ) const
inline

Definition at line 142 of file SelectionDAGNodes.h.

◆ operator<()

bool llvm::SDValue::operator< ( const SDValue O) const
inline

Definition at line 150 of file SelectionDAGNodes.h.

◆ operator==()

bool llvm::SDValue::operator== ( const SDValue O) const
inline

Definition at line 144 of file SelectionDAGNodes.h.

Referenced by llvm::SDNodeIterator::operator!=().

◆ reachesChainWithoutSideEffects()

bool SDValue::reachesChainWithoutSideEffects ( SDValue  Dest,
unsigned  Depth = 2 
) const

Return true if this operand (which must be a chain) reaches the specified operand without crossing any side-effecting instructions.

reachesChainWithoutSideEffects - Return true if this operand (which must be a chain) reaches the specified operand without crossing any side-effecting instructions on any chain path.

In practice, this looks through token factors and non-volatile loads. In order to remain efficient, this only looks a couple of nodes in, it does not do an exhaustive search.

In practice, this looks through token factors and non-volatile loads. In order to remain efficient, this only looks a couple of nodes in, it does not do an exhaustive search.

Note that we only need to examine chains when we're searching for side-effects; SelectionDAG requires that all side-effects are represented by chains, even if another operand would force a specific ordering. This constraint is necessary to allow transformations like splitting loads.

Definition at line 8954 of file SelectionDAG.cpp.

References llvm::all_of(), llvm::SDNode::getOpcode(), hasOneUse(), llvm::is_contained(), reachesChainWithoutSideEffects(), and llvm::ISD::TokenFactor.

Referenced by llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), and reachesChainWithoutSideEffects().

◆ setNode()

void llvm::SDValue::setNode ( SDNode N)
inline

set the SDNode

Definition at line 140 of file SelectionDAGNodes.h.

References N.

Referenced by dumpr(), and PrepareCall().

◆ use_empty()

bool llvm::SDValue::use_empty ( ) const
inline

Return true if there are no nodes using value ResNo of Node.

Definition at line 1202 of file SelectionDAGNodes.h.

Referenced by combineADC(), getContiguousRangeOfSetBits(), and getVPTESTMOpc().

Friends And Related Function Documentation

◆ DenseMapInfo< SDValue >

friend struct DenseMapInfo< SDValue >
friend

Definition at line 124 of file SelectionDAGNodes.h.


The documentation for this class was generated from the following files: