llvm::SIRegisterInfo Class Reference

#include "Target/AMDGPU/SIRegisterInfo.h"

Inheritance diagram for llvm::SIRegisterInfo:

Collaboration diagram for llvm::SIRegisterInfo:

Public Member Functions
	SIRegisterInfo (const GCNSubtarget &ST)
bool	spillSGPRToVGPR () const
unsigned	reservedPrivateSegmentBufferReg (const MachineFunction &MF) const
	Return the end register initially reserved for the scratch buffer in case spilling is needed. More...
unsigned	reservedPrivateSegmentWaveByteOffsetReg (const MachineFunction &MF) const
	Return the end register initially reserved for the scratch wave offset in case spilling is needed. More...
BitVector	getReservedRegs (const MachineFunction &MF) const override
const MCPhysReg *	getCalleeSavedRegs (const MachineFunction *MF) const override
const MCPhysReg *	getCalleeSavedRegsViaCopy (const MachineFunction *MF) const
const uint32_t *	getCallPreservedMask (const MachineFunction &MF, CallingConv::ID) const override
unsigned	getCSRFirstUseCost () const override
Register	getFrameRegister (const MachineFunction &MF) const override
bool	canRealignStack (const MachineFunction &MF) const override
bool	requiresRegisterScavenging (const MachineFunction &Fn) const override
bool	requiresFrameIndexScavenging (const MachineFunction &MF) const override
bool	requiresFrameIndexReplacementScavenging (const MachineFunction &MF) const override
bool	requiresVirtualBaseRegisters (const MachineFunction &Fn) const override
bool	trackLivenessAfterRegAlloc (const MachineFunction &MF) const override
int64_t	getMUBUFInstrOffset (const MachineInstr *MI) const
int64_t	getFrameIndexInstrOffset (const MachineInstr *MI, int Idx) const override
bool	needsFrameBaseReg (MachineInstr *MI, int64_t Offset) const override
void	materializeFrameBaseRegister (MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
void	resolveFrameIndex (MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
bool	isFrameOffsetLegal (const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
const TargetRegisterClass *	getPointerRegClass (const MachineFunction &MF, unsigned Kind=0) const override
bool	spillSGPR (MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, bool OnlyToVGPR=false) const
	If OnlyToVGPR is true, this will only succeed if this. More...
bool	restoreSGPR (MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, bool OnlyToVGPR=false) const
void	eliminateFrameIndex (MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
bool	eliminateSGPRToVGPRSpillFrameIndex (MachineBasicBlock::iterator MI, int FI, RegScavenger *RS) const
	Special case of eliminateFrameIndex. More...
StringRef	getRegAsmName (unsigned Reg) const override
unsigned	getHWRegIndex (unsigned Reg) const
const TargetRegisterClass *	getPhysRegClass (unsigned Reg) const
	Return the 'base' register class for this register. More...
bool	isSGPRClass (const TargetRegisterClass *RC) const
bool	isSGPRClassID (unsigned RCID) const
bool	isSGPRReg (const MachineRegisterInfo &MRI, unsigned Reg) const
bool	hasVGPRs (const TargetRegisterClass *RC) const
bool	hasAGPRs (const TargetRegisterClass *RC) const
bool	hasVectorRegisters (const TargetRegisterClass *RC) const
const TargetRegisterClass *	getEquivalentVGPRClass (const TargetRegisterClass *SRC) const
const TargetRegisterClass *	getEquivalentAGPRClass (const TargetRegisterClass *SRC) const
const TargetRegisterClass *	getEquivalentSGPRClass (const TargetRegisterClass *VRC) const
const TargetRegisterClass *	getSubRegClass (const TargetRegisterClass *RC, unsigned SubIdx) const
bool	shouldRewriteCopySrc (const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
bool	opCanUseLiteralConstant (unsigned OpType) const
bool	opCanUseInlineConstant (unsigned OpType) const
unsigned	findUnusedRegister (const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF) const
	Returns a register that is not used at any point in the function. More...
unsigned	getSGPRPressureSet () const
unsigned	getVGPRPressureSet () const
unsigned	getAGPRPressureSet () const
const TargetRegisterClass *	getRegClassForReg (const MachineRegisterInfo &MRI, unsigned Reg) const
bool	isVGPR (const MachineRegisterInfo &MRI, unsigned Reg) const
bool	isAGPR (const MachineRegisterInfo &MRI, unsigned Reg) const
bool	isVectorRegister (const MachineRegisterInfo &MRI, unsigned Reg) const
virtual bool	isDivergentRegClass (const TargetRegisterClass *RC) const override
bool	isSGPRPressureSet (unsigned SetID) const
bool	isVGPRPressureSet (unsigned SetID) const
bool	isAGPRPressureSet (unsigned SetID) const
ArrayRef< int16_t >	getRegSplitParts (const TargetRegisterClass *RC, unsigned EltSize) const
bool	shouldCoalesce (MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
unsigned	getRegPressureLimit (const TargetRegisterClass *RC, MachineFunction &MF) const override
unsigned	getRegPressureSetLimit (const MachineFunction &MF, unsigned Idx) const override
const int *	getRegUnitPressureSets (unsigned RegUnit) const override
unsigned	getReturnAddressReg (const MachineFunction &MF) const
const TargetRegisterClass *	getRegClassForSizeOnBank (unsigned Size, const RegisterBank &Bank, const MachineRegisterInfo &MRI) const
const TargetRegisterClass *	getRegClassForTypeOnBank (LLT Ty, const RegisterBank &Bank, const MachineRegisterInfo &MRI) const
const TargetRegisterClass *	getConstrainedRegClassForOperand (const MachineOperand &MO, const MachineRegisterInfo &MRI) const override
const TargetRegisterClass *	getBoolRC () const
const TargetRegisterClass *	getWaveMaskRegClass () const
unsigned	getVCC () const
const TargetRegisterClass *	getRegClass (unsigned RCID) const
MachineInstr *	findReachingDef (unsigned Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const
const uint32_t *	getAllVGPRRegMask () const
const uint32_t *	getAllAllocatableSRegMask () const
Public Member Functions inherited from llvm::AMDGPURegisterInfo
	AMDGPURegisterInfo ()
void	reserveRegisterTuples (BitVector &, unsigned Reg) const

Additional Inherited Members
Static Public Member Functions inherited from llvm::AMDGPURegisterInfo
static unsigned	getSubRegFromChannel (unsigned Channel, unsigned NumRegs=1)

Detailed Description

Definition at line 28 of file SIRegisterInfo.h.

Constructor & Destructor Documentation

SIRegisterInfo()

SIRegisterInfo::SIRegisterInfo

(

const GCNSubtarget &

ST

)

Definition at line 57 of file SIRegisterInfo.cpp.

References assert(), llvm::numbers::e, getRegUnitPressureSets(), isAGPRPressureSet(), isSGPRPressureSet(), and isVGPRPressureSet().

Member Function Documentation

canRealignStack()

bool SIRegisterInfo::canRealignStack ( const MachineFunction &  MF ) const

override

Definition at line 263 of file SIRegisterInfo.cpp.

References llvm::TargetRegisterInfo::canRealignStack(), llvm::MachineFunction::getInfo(), Info, and llvm::AMDGPUMachineFunction::isEntryFunction().

Referenced by getCSRFirstUseCost().

eliminateFrameIndex()

void SIRegisterInfo::eliminateFrameIndex ( MachineBasicBlock::iterator  MI, int  SPAdj, unsigned  FIOperandNum, RegScavenger *  RS  ) const

override

Definition at line 983 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::SIMachineFunctionInfo::addToSpilledVGPRs(), assert(), llvm::BuildMI(), buildMUBUFOffsetLoadStore(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::ChangeToRegister(), llvm::SIInstrInfo::getAddNoCarry(), llvm::MachineFunction::getFrameInfo(), getFrameRegister(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getInstrInfo(), llvm::SIInstrInfo::getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), getNumSubRegsForSpillOp(), llvm::MachineOperand::getReg(), llvm::SIMachineFunctionInfo::getScratchWaveOffsetReg(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::GCNSubtarget::getWavefrontSizeLog2(), llvm::AMDGPUSubtarget::hasInv2PiInlineImm(), llvm::AMDGPUMachineFunction::isEntryFunction(), llvm::SIInstrInfo::isImmOperandLegal(), llvm::AMDGPU::isInlinableLiteral32(), llvm::MachineOperand::isKill(), llvm::SIInstrInfo::isMUBUF(), llvm::Register::isValid(), llvm::RegState::Kill, restoreSGPR(), llvm::RegScavenger::scavengeRegister(), llvm::MachineOperand::setReg(), spillSGPR(), and TII.

Referenced by getCSRFirstUseCost().

eliminateSGPRToVGPRSpillFrameIndex()

bool SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex	(	MachineBasicBlock::iterator	MI,
		int	FI,
		RegScavenger *	RS
	)		const

Special case of eliminateFrameIndex.

Returns true if the SGPR was spilled to a VGPR and the stack slot can be safely eliminated when all other users are handled.

Definition at line 955 of file SIRegisterInfo.cpp.

References llvm_unreachable, restoreSGPR(), and spillSGPR().

Referenced by getCSRFirstUseCost().

findReachingDef()

MachineInstr * SIRegisterInfo::findReachingDef	(	unsigned	Reg,
		unsigned	SubReg,
		MachineInstr &	Use,
		MachineRegisterInfo &	MRI,
		LiveIntervals *	LIS
	)		const

Definition at line 1864 of file SIRegisterInfo.cpp.

References assert(), llvm::tgtok::Def, llvm::VNInfo::def, llvm::Pass::getAnalysis(), llvm::LiveIntervals::getInstructionFromIndex(), llvm::LiveIntervals::getInstructionIndex(), llvm::LiveIntervals::getInterval(), llvm::MachineRegisterInfo::getMaxLaneMaskForVReg(), llvm::LiveIntervals::getRegUnit(), llvm::LiveRange::getVNInfoAt(), llvm::LiveIntervals::hasInterval(), llvm::LiveInterval::hasSubRanges(), llvm::SlotIndex::isValid(), llvm::MCRegisterInfo::DiffListIterator::isValid(), llvm::Register::isVirtualRegister(), llvm::MachineInstr::modifiesRegister(), and llvm::LiveInterval::subranges().

Referenced by getWaveMaskRegClass(), and optimizeVcndVcmpPair().

findUnusedRegister()

unsigned SIRegisterInfo::findUnusedRegister	(	const MachineRegisterInfo &	MRI,
		const TargetRegisterClass *	RC,
		const MachineFunction &	MF
	)		const

Returns a register that is not used at any point in the function.

If all registers are used, then this function will return

Definition at line 1505 of file SIRegisterInfo.cpp.

References llvm::MachineRegisterInfo::isAllocatable(), and llvm::MachineRegisterInfo::isPhysRegUsed().

Referenced by llvm::SIInstrInfo::calculateLDSSpillAddress(), and opCanUseLiteralConstant().

getAGPRPressureSet()

unsigned llvm::SIRegisterInfo::getAGPRPressureSet ( ) const

inline

Definition at line 200 of file SIRegisterInfo.h.

References getRegClassForReg(), isAGPR(), and isVGPR().

Referenced by getRegPressureSetLimit().

getAllAllocatableSRegMask()

const uint32_t * SIRegisterInfo::getAllAllocatableSRegMask

(

)

const

Definition at line 140 of file AMDGPURegisterInfo.cpp.

Referenced by getWaveMaskRegClass().

getAllVGPRRegMask()

const uint32_t * SIRegisterInfo::getAllVGPRRegMask

(

)

const

Definition at line 136 of file AMDGPURegisterInfo.cpp.

Referenced by getWaveMaskRegClass().

getBoolRC()

const TargetRegisterClass* llvm::SIRegisterInfo::getBoolRC ( ) const

inline

Definition at line 265 of file SIRegisterInfo.h.

Referenced by getLogicalBitOpcode(), getRegClass(), getV_CMPOpcode(), llvm::SIInstrInfo::insertEQ(), llvm::SIInstrInfo::insertNE(), isConstant(), and isSCC().

getCalleeSavedRegs()

const MCPhysReg * SIRegisterInfo::getCalleeSavedRegs ( const MachineFunction *  MF ) const

override

Definition at line 95 of file AMDGPURegisterInfo.cpp.

References llvm::CallingConv::C, llvm::CallingConv::Cold, llvm::CallingConv::Fast, llvm::Function::getCallingConv(), and llvm::MachineFunction::getFunction().

Referenced by spillSGPRToVGPR().

getCalleeSavedRegsViaCopy()

const MCPhysReg * SIRegisterInfo::getCalleeSavedRegsViaCopy

(

const MachineFunction *

MF

)

const

Definition at line 112 of file AMDGPURegisterInfo.cpp.

Referenced by llvm::SITargetLowering::insertCopiesSplitCSR(), llvm::SITargetLowering::LowerReturn(), and spillSGPRToVGPR().

getCallPreservedMask()

const uint32_t * SIRegisterInfo::getCallPreservedMask ( const MachineFunction &  MF, CallingConv::ID  CC  ) const

override

Definition at line 116 of file AMDGPURegisterInfo.cpp.

References llvm::CallingConv::C, llvm::CallingConv::Cold, and llvm::CallingConv::Fast.

Referenced by llvm::SIMachineFunctionInfo::allocateVGPRSpillToAGPR(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), and spillSGPRToVGPR().

getConstrainedRegClassForOperand()

const TargetRegisterClass * SIRegisterInfo::getConstrainedRegClassForOperand ( const MachineOperand &  MO, const MachineRegisterInfo &  MRI  ) const

override

Definition at line 1834 of file SIRegisterInfo.cpp.

References llvm::PointerUnion< PTs >::dyn_cast(), llvm::PointerUnion< PTs >::get(), llvm::MachineOperand::getReg(), getRegClassForTypeOnBank(), llvm::MachineRegisterInfo::getRegClassOrRegBank(), and llvm::MachineRegisterInfo::getType().

Referenced by getFPTrueImmVal(), getLogicalBitOpcode(), getRegClassForTypeOnBank(), and isSCC().

getCSRFirstUseCost()

unsigned llvm::SIRegisterInfo::getCSRFirstUseCost ( ) const

inlineoverride

Definition at line 67 of file SIRegisterInfo.h.

References canRealignStack(), eliminateFrameIndex(), eliminateSGPRToVGPRSpillFrameIndex(), getFrameIndexInstrOffset(), getFrameRegister(), getMUBUFInstrOffset(), getPointerRegClass(), getRegAsmName(), isFrameOffsetLegal(), materializeFrameBaseRegister(), MI, needsFrameBaseReg(), requiresFrameIndexReplacementScavenging(), requiresFrameIndexScavenging(), requiresRegisterScavenging(), requiresVirtualBaseRegisters(), resolveFrameIndex(), restoreSGPR(), spillSGPR(), and trackLivenessAfterRegAlloc().

getEquivalentAGPRClass()

const TargetRegisterClass * SIRegisterInfo::getEquivalentAGPRClass

(

const TargetRegisterClass *

SRC

)

const

Returns

An AGPR reg class with the same width as SRC

Definition at line 1362 of file SIRegisterInfo.cpp.

References llvm_unreachable.

Referenced by foldVGPRCopyIntoRegSequence(), and hasVectorRegisters().

getEquivalentSGPRClass()

const TargetRegisterClass * SIRegisterInfo::getEquivalentSGPRClass

(

const TargetRegisterClass *

VRC

)

const

Returns

A SGPR reg class with the same width as SRC

Definition at line 1380 of file SIRegisterInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SITargetLowering::getRegClassFor(), hasVectorRegisters(), and tryChangeVGPRtoSGPRinCopy().

getEquivalentVGPRClass()

const TargetRegisterClass * SIRegisterInfo::getEquivalentVGPRClass

(

const TargetRegisterClass *

SRC

)

const

Returns

A VGPR reg class with the same width as SRC

Definition at line 1336 of file SIRegisterInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection(), foldVGPRCopyIntoRegSequence(), llvm::SITargetLowering::getRegClassFor(), and hasVectorRegisters().

getFrameIndexInstrOffset()

int64_t SIRegisterInfo::getFrameIndexInstrOffset ( const MachineInstr *  MI, int  Idx  ) const

override

Definition at line 321 of file SIRegisterInfo.cpp.

References assert(), getMUBUFInstrOffset(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), and llvm::SIInstrInfo::isMUBUF().

Referenced by getCSRFirstUseCost().

getFrameRegister()

Register SIRegisterInfo::getFrameRegister ( const MachineFunction &  MF ) const

override

Definition at line 128 of file AMDGPURegisterInfo.cpp.

References llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::MachineFunction::getInfo(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::MachineFunction::getSubtarget(), and llvm::SIFrameLowering::hasFP().

Referenced by eliminateFrameIndex(), getCSRFirstUseCost(), and llvm::SIFrameLowering::getFrameIndexReference().

getHWRegIndex()

unsigned llvm::SIRegisterInfo::getHWRegIndex ( unsigned  Reg ) const

inline

Definition at line 120 of file SIRegisterInfo.h.

References getPhysRegClass().

Referenced by llvm::SIInstrInfo::copyPhysReg(), hasAnyNonFlatUseOfReg(), and shrinkScalarCompare().

getMUBUFInstrOffset()

int64_t SIRegisterInfo::getMUBUFInstrOffset

(

const MachineInstr *

MI

)

const

Definition at line 313 of file SIRegisterInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::SIInstrInfo::isMUBUF().

Referenced by getCSRFirstUseCost(), getFrameIndexInstrOffset(), isFrameOffsetLegal(), and needsFrameBaseReg().

getPhysRegClass()

const TargetRegisterClass * SIRegisterInfo::getPhysRegClass

(

unsigned

Reg

)

const

Return the 'base' register class for this register.

e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.

Definition at line 1244 of file SIRegisterInfo.cpp.

References assert(), and llvm::Register::isVirtualRegister().

Referenced by addRegsToSet(), llvm::SIInstrInfo::copyPhysReg(), llvm::createR600ISelDag(), llvm::SIInstrInfo::FoldImmediate(), getCopyRegClasses(), getHWRegIndex(), getRegClassForReg(), isSGPRReg(), restoreSGPR(), llvm::SIInstrInfo::shouldClusterMemOps(), and spillSGPR().

getPointerRegClass()

const TargetRegisterClass * SIRegisterInfo::getPointerRegClass ( const MachineFunction &  MF, unsigned  Kind = 0  ) const

override

Definition at line 424 of file SIRegisterInfo.cpp.

Referenced by getCSRFirstUseCost().

getRegAsmName()

StringRef SIRegisterInfo::getRegAsmName ( unsigned  Reg ) const

override

Definition at line 1238 of file SIRegisterInfo.cpp.

References llvm::AMDGPUInstPrinter::getRegisterName().

Referenced by getCSRFirstUseCost().

getRegClass()

const TargetRegisterClass * SIRegisterInfo::getRegClass

(

unsigned

RCID

)

const

Definition at line 1849 of file SIRegisterInfo.cpp.

References getBoolRC(), and getRegClass().

Referenced by findSingleRegDef(), llvm::SIInstrInfo::getOpSize(), llvm::SIInstrInfo::getRegClass(), getWaveMaskRegClass(), isSGPRClassID(), and llvm::SIInstrInfo::verifyInstruction().

getRegClassForReg()

const TargetRegisterClass * SIRegisterInfo::getRegClassForReg	(	const MachineRegisterInfo &	MRI,
		unsigned	Reg
	)		const

Definition at line 1690 of file SIRegisterInfo.cpp.

References getPhysRegClass(), llvm::MachineRegisterInfo::getRegClass(), and llvm::Register::isVirtualRegister().

Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection(), buildMUBUFOffsetLoadStore(), getAGPRPressureSet(), getFPTrueImmVal(), isAGPR(), isVGPR(), and llvm::SIInstrInfo::verifyInstruction().

getRegClassForSizeOnBank()

const TargetRegisterClass * SIRegisterInfo::getRegClassForSizeOnBank	(	unsigned	Size,
		const RegisterBank &	Bank,
		const MachineRegisterInfo &	MRI
	)		const

Definition at line 1776 of file SIRegisterInfo.cpp.

References llvm::RegisterBank::getID(), and llvm_unreachable.

Referenced by getLogicalBitOpcode(), getRegClassForTypeOnBank(), isAGPRPressureSet(), and sizeToSubRegIndex().

getRegClassForTypeOnBank()

const TargetRegisterClass* llvm::SIRegisterInfo::getRegClassForTypeOnBank ( LLT  Ty, const RegisterBank &  Bank, const MachineRegisterInfo &  MRI  ) const

inline

Definition at line 255 of file SIRegisterInfo.h.

References getConstrainedRegClassForOperand(), getRegClassForSizeOnBank(), llvm::LLT::getSizeInBits(), and MRI.

Referenced by getConstrainedRegClassForOperand(), isConstant(), and isSCC().

getRegPressureLimit()

unsigned SIRegisterInfo::getRegPressureLimit ( const TargetRegisterClass *  RC, MachineFunction &  MF  ) const

override

Definition at line 1733 of file SIRegisterInfo.cpp.

References llvm::MachineFunction::getFunction(), llvm::TargetRegisterClass::getID(), llvm::MachineFunction::getInfo(), llvm::AMDGPUMachineFunction::getLDSSize(), llvm::GCNSubtarget::getMaxNumSGPRs(), llvm::GCNSubtarget::getMaxNumVGPRs(), and llvm::AMDGPUSubtarget::getOccupancyWithLocalMemSize().

Referenced by llvm::SIInstrInfo::copyPhysReg(), getRegPressureSetLimit(), and isAGPRPressureSet().

getRegPressureSetLimit()

unsigned SIRegisterInfo::getRegPressureSetLimit ( const MachineFunction &  MF, unsigned  Idx  ) const

override

Definition at line 1749 of file SIRegisterInfo.cpp.

References getAGPRPressureSet(), getRegPressureLimit(), getSGPRPressureSet(), and getVGPRPressureSet().

Referenced by llvm::GCNMaxOccupancySchedStrategy::initialize(), and isAGPRPressureSet().

getRegSplitParts()

ArrayRef< int16_t > SIRegisterInfo::getRegSplitParts	(	const TargetRegisterClass *	RC,
		unsigned	EltSize
	)		const

Definition at line 1515 of file SIRegisterInfo.cpp.

References assert(), llvm::AMDGPU::getRegBitWidth(), llvm_unreachable, llvm::makeArrayRef(), and llvm::TargetRegisterClass::MC.

Referenced by llvm::SIInstrInfo::copyPhysReg(), getLogicalBitOpcode(), isAGPRPressureSet(), llvm::SIInstrInfo::materializeImmediate(), restoreSGPR(), and spillSGPR().

getRegUnitPressureSets()

const int * SIRegisterInfo::getRegUnitPressureSets ( unsigned  RegUnit ) const

override

Definition at line 1762 of file SIRegisterInfo.cpp.

References llvm::Empty.

Referenced by hasPressureSet(), isAGPRPressureSet(), and SIRegisterInfo().

getReservedRegs()

BitVector SIRegisterInfo::getReservedRegs ( const MachineFunction &  MF ) const

override

Definition at line 139 of file SIRegisterInfo.cpp.

References assert(), llvm::SIMachineFunctionInfo::getAGPRSpillVGPRs(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getMaxNumSGPRs(), llvm::GCNSubtarget::getMaxNumVGPRs(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), llvm::SIMachineFunctionInfo::getScratchWaveOffsetReg(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::SIMachineFunctionInfo::getVGPRSpillAGPRs(), llvm::GCNSubtarget::hasMAIInsts(), llvm::AMDGPURegisterInfo::reserveRegisterTuples(), llvm::BitVector::set(), and llvm::SIMachineFunctionInfo::WWMReservedRegs.

Referenced by spillSGPRToVGPR().

getReturnAddressReg()

unsigned SIRegisterInfo::getReturnAddressReg

(

const MachineFunction &

MF

)

const

Definition at line 1770 of file SIRegisterInfo.cpp.

Referenced by llvm::SITargetLowering::EmitInstrWithCustomInserter(), isAGPRPressureSet(), llvm::SITargetLowering::LowerCall(), llvm::AMDGPUCallLowering::lowerReturn(), llvm::SITargetLowering::LowerReturn(), and llvm::SITargetLowering::shouldEmitPCReloc().

getSGPRPressureSet()

unsigned llvm::SIRegisterInfo::getSGPRPressureSet ( ) const

inline

Definition at line 198 of file SIRegisterInfo.h.

Referenced by getRegPressureSetLimit(), llvm::GCNMaxOccupancySchedStrategy::initialize(), and llvm::SIScheduleDAGMI::SIScheduleDAGMI().

getSubRegClass()

const TargetRegisterClass * SIRegisterInfo::getSubRegClass	(	const TargetRegisterClass *	RC,
		unsigned	SubIdx
	)		const

Returns

The register class that is used for a sub-register of RC for the given SubIdx. If SubIdx equals NoSubRegister, RC will be returned.

Definition at line 1404 of file SIRegisterInfo.cpp.

References hasAGPRs(), isSGPRClass(), and llvm_unreachable.

Referenced by foldVGPRCopyIntoRegSequence(), hasVectorRegisters(), and llvm::SIInstrInfo::isLegalRegOperand().

getVCC()

unsigned SIRegisterInfo::getVCC

(

)

const

Definition at line 1844 of file SIRegisterInfo.cpp.

Referenced by findSingleRegDef(), getWaveMaskRegClass(), isConstant(), isSCC(), and selectSGPRVectorRegClassID().

getVGPRPressureSet()

unsigned llvm::SIRegisterInfo::getVGPRPressureSet ( ) const

inline

Definition at line 199 of file SIRegisterInfo.h.

Referenced by getRegPressureSetLimit(), llvm::GCNMaxOccupancySchedStrategy::initialize(), and llvm::SIScheduleDAGMI::SIScheduleDAGMI().

getWaveMaskRegClass()

const TargetRegisterClass* llvm::SIRegisterInfo::getWaveMaskRegClass ( ) const

inline

Definition at line 270 of file SIRegisterInfo.h.

References findReachingDef(), getAllAllocatableSRegMask(), getAllVGPRRegMask(), getRegClass(), and getVCC().

Referenced by llvm::SIFrameLowering::emitEpilogue(), llvm::SIFrameLowering::emitPrologue(), getHalfSizedType(), getLogicalBitOpcode(), and llvm::AMDGPULegalizerInfo::legalizeIntrinsic().

hasAGPRs()

bool SIRegisterInfo::hasAGPRs

(

const TargetRegisterClass *

RC

)

const

Returns

true if this class contains AGPR registers.

Definition at line 1311 of file SIRegisterInfo.cpp.

References llvm_unreachable, and Size.

Referenced by buildMUBUFOffsetLoadStore(), llvm::SIInstrInfo::copyPhysReg(), foldVGPRCopyIntoRegSequence(), llvm::SIInstrInfo::getMovOpcode(), getSubRegClass(), hasVectorRegisters(), isAGPR(), isSGPRClass(), isSGPRReg(), llvm::SIInstrInfo::loadRegFromStackSlot(), and llvm::SIInstrInfo::storeRegToStackSlot().

hasVectorRegisters()

bool llvm::SIRegisterInfo::hasVectorRegisters ( const TargetRegisterClass *  RC ) const

inline

Returns

true if this class contains any vector registers.

Definition at line 154 of file SIRegisterInfo.h.

References getEquivalentAGPRClass(), getEquivalentSGPRClass(), getEquivalentVGPRClass(), getSubRegClass(), hasAGPRs(), hasVGPRs(), and shouldRewriteCopySrc().

Referenced by hasVectorOperands(), isSGPRToVGPRCopy(), and isVGPRToSGPRCopy().

hasVGPRs()

bool SIRegisterInfo::hasVGPRs

(

const TargetRegisterClass *

RC

)

const

Returns

true if this class contains VGPR registers.

Definition at line 1284 of file SIRegisterInfo.cpp.

References assert(), and Size.

Referenced by llvm::SIInstrInfo::canInsertSelect(), llvm::SIInstrInfo::copyPhysReg(), findSingleRegDef(), findSRegBaseAndIndex(), hasVectorRegisters(), isSGPRClass(), isSGPRReg(), isVGPR(), and llvm::SIInstrInfo::verifyInstruction().

isAGPR()

bool SIRegisterInfo::isAGPR	(	const MachineRegisterInfo &	MRI,
		unsigned	Reg
	)		const

Definition at line 1705 of file SIRegisterInfo.cpp.

References assert(), getRegClassForReg(), and hasAGPRs().

Referenced by addRegsToSet(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::SIInstrInfo::FoldImmediate(), getAGPRPressureSet(), and isVectorRegister().

isAGPRPressureSet()

bool llvm::SIRegisterInfo::isAGPRPressureSet ( unsigned  SetID ) const

inline

Definition at line 223 of file SIRegisterInfo.h.

References getRegClassForSizeOnBank(), getRegPressureLimit(), getRegPressureSetLimit(), getRegSplitParts(), getRegUnitPressureSets(), getReturnAddressReg(), shouldCoalesce(), Size, SubReg, and llvm::BitVector::test().

Referenced by SIRegisterInfo().

isDivergentRegClass()

virtual bool llvm::SIRegisterInfo::isDivergentRegClass ( const TargetRegisterClass *  RC ) const

inlineoverridevirtual

Definition at line 211 of file SIRegisterInfo.h.

References isSGPRClass().

isFrameOffsetLegal()

bool SIRegisterInfo::isFrameOffsetLegal ( const MachineInstr *  MI, unsigned  BaseReg, int64_t  Offset  ) const

override

Definition at line 413 of file SIRegisterInfo.cpp.

References getMUBUFInstrOffset(), and llvm::SIInstrInfo::isMUBUF().

Referenced by getCSRFirstUseCost().

isSGPRClass()

bool llvm::SIRegisterInfo::isSGPRClass ( const TargetRegisterClass *  RC ) const

inline

Returns

true if this class contains only SGPR registers

Definition at line 129 of file SIRegisterInfo.h.

References hasAGPRs(), and hasVGPRs().

Referenced by addRegsToSet(), llvm::SIInstrInfo::canInsertSelect(), llvm::SIInstrInfo::copyPhysReg(), llvm::SIInstrInfo::FoldImmediate(), foldVGPRCopyIntoRegSequence(), getFPTrueImmVal(), llvm::SIInstrInfo::getMovOpcode(), llvm::AMDGPURegisterBankInfo::getRegBankFromRegClass(), llvm::SITargetLowering::getRegClassFor(), getSubRegClass(), isDivergentRegClass(), llvm::isEqual(), isSGPRClassID(), isSGPRReg(), isSGPRToVGPRCopy(), isVGPRToSGPRCopy(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::materializeImmediate(), llvm::SITargetLowering::requiresUniformRegister(), setM0ToIndexFromSGPR(), llvm::SIInstrInfo::storeRegToStackSlot(), and llvm::SIInstrInfo::usesConstantBus().

isSGPRClassID()

bool llvm::SIRegisterInfo::isSGPRClassID ( unsigned  RCID ) const

inline

Returns

true if this class ID contains only SGPR registers

Definition at line 134 of file SIRegisterInfo.h.

References getRegClass(), and isSGPRClass().

isSGPRPressureSet()

bool llvm::SIRegisterInfo::isSGPRPressureSet ( unsigned  SetID ) const

inline

Definition at line 215 of file SIRegisterInfo.h.

References llvm::BitVector::test().

Referenced by SIRegisterInfo().

isSGPRReg()

bool llvm::SIRegisterInfo::isSGPRReg ( const MachineRegisterInfo &  MRI, unsigned  Reg  ) const

inline

Definition at line 138 of file SIRegisterInfo.h.

References getPhysRegClass(), llvm::MachineRegisterInfo::getRegClass(), hasAGPRs(), hasVGPRs(), isSGPRClass(), and llvm::Register::isVirtualRegister().

Referenced by addRegsToSet(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::SIInstrInfo::convertToThreeAddress(), findSingleRegDef(), findSRegBaseAndIndex(), llvm::SITargetLowering::isSDNodeSourceOfDivergence(), llvm::SIInstrInfo::isVGPRCopy(), llvm::SIInstrInfo::mayReadEXEC(), llvm::SITargetLowering::requiresUniformRegister(), and tryConstantFoldOp().

isVectorRegister()

bool llvm::SIRegisterInfo::isVectorRegister ( const MachineRegisterInfo &  MRI, unsigned  Reg  ) const

inline

Definition at line 206 of file SIRegisterInfo.h.

References isAGPR(), and isVGPR().

isVGPR()

bool SIRegisterInfo::isVGPR	(	const MachineRegisterInfo &	MRI,
		unsigned	Reg
	)		const

Definition at line 1698 of file SIRegisterInfo.cpp.

References assert(), getRegClassForReg(), and hasVGPRs().

Referenced by addRegsToSet(), llvm::SIInstrInfo::canShrink(), findSingleRegDef(), llvm::SIInstrInfo::FoldImmediate(), getAGPRPressureSet(), llvm::SIInstrInfo::hasVGPRUses(), isVectorRegister(), matchSwap(), and tryAddToFoldList().

isVGPRPressureSet()

bool llvm::SIRegisterInfo::isVGPRPressureSet ( unsigned  SetID ) const

inline

Definition at line 219 of file SIRegisterInfo.h.

References llvm::BitVector::test().

Referenced by SIRegisterInfo().

materializeFrameBaseRegister()

void SIRegisterInfo::materializeFrameBaseRegister ( MachineBasicBlock *  MBB, unsigned  BaseReg, int  FrameIdx, int64_t  Offset  ) const

override

Definition at line 342 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineBasicBlock::end(), llvm::SIInstrInfo::getAddNoCarry(), llvm::GCNSubtarget::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MipsISD::Ins, llvm::RegState::Kill, MRI, and TII.

Referenced by getCSRFirstUseCost().

needsFrameBaseReg()

bool SIRegisterInfo::needsFrameBaseReg ( MachineInstr *  MI, int64_t  Offset  ) const

override

Definition at line 333 of file SIRegisterInfo.cpp.

References getMUBUFInstrOffset(), and llvm::MachineInstr::mayLoadOrStore().

Referenced by getCSRFirstUseCost().

opCanUseInlineConstant()

bool SIRegisterInfo::opCanUseInlineConstant

(

unsigned

OpType

)

const

Returns

True if operands defined with this operand type can accept an inline constant. i.e. An integer value in the range (-16, 64) or -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.

Definition at line 1468 of file SIRegisterInfo.cpp.

References llvm::GCNSubtarget::hasMFMAInlineLiteralBug(), llvm::AMDGPU::OPERAND_REG_INLINE_AC_FIRST, llvm::AMDGPU::OPERAND_REG_INLINE_AC_LAST, llvm::AMDGPU::OPERAND_SRC_FIRST, and llvm::AMDGPU::OPERAND_SRC_LAST.

Referenced by llvm::SIInstrInfo::isImmOperandLegal(), and opCanUseLiteralConstant().

opCanUseLiteralConstant()

bool llvm::SIRegisterInfo::opCanUseLiteralConstant ( unsigned  OpType ) const

inline

Returns

True if operands defined with this operand type can accept a literal constant (i.e. any 32-bit immediate).

Definition at line 183 of file SIRegisterInfo.h.

References findUnusedRegister(), MRI, opCanUseInlineConstant(), llvm::AMDGPU::OPERAND_REG_IMM_FIRST, and llvm::AMDGPU::OPERAND_REG_IMM_LAST.

Referenced by llvm::SIInstrInfo::isImmOperandLegal().

requiresFrameIndexReplacementScavenging()

bool SIRegisterInfo::requiresFrameIndexReplacementScavenging ( const MachineFunction &  MF ) const

override

Definition at line 296 of file SIRegisterInfo.cpp.

References llvm::MachineFunction::getFrameInfo(), and llvm::MachineFrameInfo::hasStackObjects().

Referenced by getCSRFirstUseCost().

requiresFrameIndexScavenging()

bool SIRegisterInfo::requiresFrameIndexScavenging ( const MachineFunction &  MF ) const

override

Definition at line 287 of file SIRegisterInfo.cpp.

Referenced by getCSRFirstUseCost().

requiresRegisterScavenging()

bool SIRegisterInfo::requiresRegisterScavenging ( const MachineFunction &  Fn ) const

override

Definition at line 276 of file SIRegisterInfo.cpp.

References llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::MachineFrameInfo::hasCalls(), llvm::MachineFrameInfo::hasStackObjects(), Info, and llvm::AMDGPUMachineFunction::isEntryFunction().

Referenced by getCSRFirstUseCost().

requiresVirtualBaseRegisters()

bool SIRegisterInfo::requiresVirtualBaseRegisters ( const MachineFunction &  Fn ) const

override

Definition at line 302 of file SIRegisterInfo.cpp.

Referenced by getCSRFirstUseCost().

reservedPrivateSegmentBufferReg()

unsigned SIRegisterInfo::reservedPrivateSegmentBufferReg

(

const MachineFunction &

MF

)

const

Return the end register initially reserved for the scratch buffer in case spilling is needed.

Definition at line 109 of file SIRegisterInfo.cpp.

References llvm::alignDown(), and llvm::GCNSubtarget::getMaxNumSGPRs().

Referenced by buildEpilogReload(), reservePrivateMemoryRegs(), and spillSGPRToVGPR().

reservedPrivateSegmentWaveByteOffsetReg()

unsigned SIRegisterInfo::reservedPrivateSegmentWaveByteOffsetReg

(

const MachineFunction &

MF

)

const

Return the end register initially reserved for the scratch wave offset in case spilling is needed.

Definition at line 133 of file SIRegisterInfo.cpp.

References findPrivateSegmentWaveByteOffsetRegIndex(), and llvm::GCNSubtarget::getMaxNumSGPRs().

Referenced by buildEpilogReload(), reservePrivateMemoryRegs(), and spillSGPRToVGPR().

resolveFrameIndex()

void SIRegisterInfo::resolveFrameIndex ( MachineInstr &  MI, unsigned  BaseReg, int64_t  Offset  ) const

override

Definition at line 377 of file SIRegisterInfo.cpp.

References assert(), llvm::MachineOperand::ChangeToRegister(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getInstrInfo(), llvm::SIInstrInfo::getNamedOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), llvm::SIInstrInfo::isMUBUF(), llvm_unreachable, llvm::MachineInstr::operands(), and TII.

Referenced by getCSRFirstUseCost().

restoreSGPR()

bool SIRegisterInfo::restoreSGPR	(	MachineBasicBlock::iterator	MI,
		int	FI,
		RegScavenger *	RS,
		bool	OnlyToVGPR = false
	)		const

Definition at line 863 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::numbers::e, llvm::ArrayRef< T >::empty(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getInstrInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::SIInstrInfo::getMCOpcodeFromPseudo(), llvm::MachineFrameInfo::getObjectAlignment(), getPhysRegClass(), getRegSplitParts(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), llvm::SIMachineFunctionInfo::getSGPRToVGPRSpills(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::RegState::ImplicitDefine, llvm::Register::isValid(), llvm::RegState::Kill, llvm::SIMachineFunctionInfo::SpilledReg::Lane, llvm::MinAlign(), llvm::MachineMemOperand::MOLoad, llvm::RegScavenger::scavengeRegister(), llvm::ArrayRef< T >::size(), SubReg, TII, and llvm::SIMachineFunctionInfo::SpilledReg::VGPR.

Referenced by eliminateFrameIndex(), eliminateSGPRToVGPRSpillFrameIndex(), and getCSRFirstUseCost().

shouldCoalesce()

bool SIRegisterInfo::shouldCoalesce ( MachineInstr *  MI, const TargetRegisterClass *  SrcRC, unsigned  SubReg, const TargetRegisterClass *  DstRC, unsigned  DstSubReg, const TargetRegisterClass *  NewRC, LiveIntervals &  LIS  ) const

override

Definition at line 1712 of file SIRegisterInfo.cpp.

Referenced by isAGPRPressureSet().

shouldRewriteCopySrc()

bool SIRegisterInfo::shouldRewriteCopySrc ( const TargetRegisterClass *  DefRC, unsigned  DefSubReg, const TargetRegisterClass *  SrcRC, unsigned  SrcSubReg  ) const

override

Definition at line 1477 of file SIRegisterInfo.cpp.

Referenced by hasVectorRegisters().

spillSGPR()

bool SIRegisterInfo::spillSGPR	(	MachineBasicBlock::iterator	MI,
		int	FI,
		RegScavenger *	RS,
		bool	OnlyToVGPR = false
	)		const

If OnlyToVGPR is true, this will only succeed if this.

Definition at line 745 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::SIMachineFunctionInfo::addToSpilledSGPRs(), assert(), llvm::BuildMI(), llvm::numbers::e, llvm::ArrayRef< T >::empty(), llvm::MachineFunction::front(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::SIInstrInfo::getMCOpcodeFromPseudo(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineBasicBlock::getParent(), getPhysRegClass(), getRegSplitParts(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), llvm::SIMachineFunctionInfo::getScratchWaveOffsetReg(), llvm::SIMachineFunctionInfo::getSGPRToVGPRSpills(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::RegState::Implicit, llvm::Register::isValid(), llvm::RegState::Kill, llvm::SIMachineFunctionInfo::SpilledReg::Lane, llvm::MinAlign(), llvm::MachineMemOperand::MOStore, llvm::RegScavenger::scavengeRegister(), llvm::ArrayRef< T >::size(), SubReg, TII, llvm::RegState::Undef, and llvm::SIMachineFunctionInfo::SpilledReg::VGPR.

Referenced by eliminateFrameIndex(), eliminateSGPRToVGPRSpillFrameIndex(), and getCSRFirstUseCost().

spillSGPRToVGPR()

bool llvm::SIRegisterInfo::spillSGPRToVGPR ( ) const

inline

Definition at line 45 of file SIRegisterInfo.h.

References getCalleeSavedRegs(), getCalleeSavedRegsViaCopy(), getCallPreservedMask(), getReservedRegs(), reservedPrivateSegmentBufferReg(), and reservedPrivateSegmentWaveByteOffsetReg().

Referenced by llvm::SIInstrInfo::loadRegFromStackSlot(), and llvm::SIInstrInfo::storeRegToStackSlot().

trackLivenessAfterRegAlloc()

bool SIRegisterInfo::trackLivenessAfterRegAlloc ( const MachineFunction &  MF ) const

override

Definition at line 308 of file SIRegisterInfo.cpp.

Referenced by getCSRFirstUseCost().

---

The documentation for this class was generated from the following files:

• lib/Target/AMDGPU/SIRegisterInfo.h
• lib/Target/AMDGPU/AMDGPURegisterInfo.cpp
• lib/Target/AMDGPU/SIRegisterInfo.cpp