LLVM 19.0.0git
llvm::TargetSubtargetInfo Member List

This is the complete list of members for llvm::TargetSubtargetInfo, including all inherited members.

addrSinkUsingGEPs() constllvm::TargetSubtargetInfoinlinevirtual
adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep) constllvm::TargetSubtargetInfoinlinevirtual
AntiDepBreakMode typedefllvm::TargetSubtargetInfo
ApplyFeatureFlag(StringRef FS)llvm::MCSubtargetInfo
checkFeatures(StringRef FS) constllvm::MCSubtargetInfo
classifyGlobalFunctionReference(const GlobalValue *GV) constllvm::TargetSubtargetInfoinlinevirtual
ClearFeatureBitsTransitively(const FeatureBitset &FB)llvm::MCSubtargetInfo
enableAtomicExpand() constllvm::TargetSubtargetInfovirtual
enableEarlyIfConversion() constllvm::TargetSubtargetInfoinlinevirtual
enableIndirectBrExpand() constllvm::TargetSubtargetInfovirtual
enableJoinGlobalCopies() constllvm::TargetSubtargetInfovirtual
enableMachinePipeliner() constllvm::TargetSubtargetInfoinlinevirtual
enableMachineSchedDefaultSched() constllvm::TargetSubtargetInfoinlinevirtual
enableMachineScheduler() constllvm::TargetSubtargetInfovirtual
enablePostRAMachineScheduler() constllvm::TargetSubtargetInfovirtual
enablePostRAScheduler() constllvm::TargetSubtargetInfovirtual
enableRALocalReassignment(CodeGenOptLevel OptLevel) constllvm::TargetSubtargetInfovirtual
enableSpillageCopyElimination() constllvm::TargetSubtargetInfoinlinevirtual
enableSubRegLiveness() constllvm::TargetSubtargetInfoinlinevirtual
enableWritePrefetching() constllvm::MCSubtargetInfovirtual
getAllProcessorDescriptions() constllvm::MCSubtargetInfoinline
getAllProcessorFeatures() constllvm::MCSubtargetInfoinline
getAntiDepBreakMode() constllvm::TargetSubtargetInfoinlinevirtual
getCacheAssociativity(unsigned Level) constllvm::MCSubtargetInfovirtual
getCacheLineSize(unsigned Level) constllvm::MCSubtargetInfovirtual
getCacheLineSize() constllvm::MCSubtargetInfoinlinevirtual
getCacheSize(unsigned Level) constllvm::MCSubtargetInfovirtual
getCallLowering() constllvm::TargetSubtargetInfoinlinevirtual
getCPU() constllvm::MCSubtargetInfoinline
getCriticalPathRCs(RegClassVector &CriticalPathRCs) constllvm::TargetSubtargetInfoinlinevirtual
getCustomPBQPConstraints() constllvm::TargetSubtargetInfoinlinevirtual
getDAGScheduler(CodeGenOptLevel) constllvm::TargetSubtargetInfoinlinevirtual
getFeatureBits() constllvm::MCSubtargetInfoinline
getFeatureString() constllvm::MCSubtargetInfoinline
getFrameLowering() constllvm::TargetSubtargetInfoinlinevirtual
getHwMode() constllvm::MCSubtargetInfoinlinevirtual
getInlineAsmLowering() constllvm::TargetSubtargetInfoinlinevirtual
getInstrInfo() constllvm::TargetSubtargetInfoinlinevirtual
getInstrItineraryData() constllvm::TargetSubtargetInfoinlinevirtual
getInstrItineraryForCPU(StringRef CPU) constllvm::MCSubtargetInfo
getInstructionSelector() constllvm::TargetSubtargetInfoinlinevirtual
getLegalizerInfo() constllvm::TargetSubtargetInfoinlinevirtual
getMacroFusions() constllvm::TargetSubtargetInfoinlinevirtual
getMaxPrefetchIterationsAhead() constllvm::MCSubtargetInfovirtual
getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) constllvm::MCSubtargetInfovirtual
getOptLevelToEnablePostRAScheduler() constllvm::TargetSubtargetInfoinlinevirtual
getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) constllvm::TargetSubtargetInfoinlinevirtual
getPrefetchDistance() constllvm::MCSubtargetInfovirtual
getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) constllvm::MCSubtargetInfoinline
getReadAdvanceEntries(const MCSchedClassDesc &SC) constllvm::MCSubtargetInfoinline
getRegBankInfo() constllvm::TargetSubtargetInfoinlinevirtual
getRegisterInfo() constllvm::TargetSubtargetInfoinlinevirtual
getSchedModel() constllvm::MCSubtargetInfoinline
getSchedModelForCPU(StringRef CPU) constllvm::MCSubtargetInfo
getSelectionDAGInfo() constllvm::TargetSubtargetInfoinlinevirtual
getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) constllvm::TargetSubtargetInfoinlinevirtual
getTargetLowering() constllvm::TargetSubtargetInfoinlinevirtual
getTargetTriple() constllvm::MCSubtargetInfoinline
getTuneCPU() constllvm::MCSubtargetInfoinline
getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) constllvm::MCSubtargetInfoinline
getWriteProcResBegin(const MCSchedClassDesc *SC) constllvm::MCSubtargetInfoinline
getWriteProcResEnd(const MCSchedClassDesc *SC) constllvm::MCSubtargetInfoinline
hasFeature(unsigned Feature) constllvm::MCSubtargetInfoinline
ignoreCSRForAllocationOrder(const MachineFunction &MF, unsigned PhysReg) constllvm::TargetSubtargetInfoinlinevirtual
initInstrItins(InstrItineraryData &InstrItins) constllvm::MCSubtargetInfo
InitMCProcessorInfo(StringRef CPU, StringRef TuneCPU, StringRef FS)llvm::MCSubtargetInfoprotected
isCPUStringValid(StringRef CPU) constllvm::MCSubtargetInfoinline
isDependencyBreaking(const MachineInstr *MI, APInt &Mask) constllvm::TargetSubtargetInfoinlinevirtual
isOptimizableRegisterMove(const MachineInstr *MI) constllvm::TargetSubtargetInfoinlinevirtual
isXRaySupported() constllvm::TargetSubtargetInfoinlinevirtual
isZeroIdiom(const MachineInstr *MI, APInt &Mask) constllvm::TargetSubtargetInfoinlinevirtual
MCSubtargetInfo(const MCSubtargetInfo &)=defaultllvm::MCSubtargetInfo
MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetSubTypeKV > PD, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP)llvm::MCSubtargetInfo
MCSubtargetInfo()=deletellvm::MCSubtargetInfo
mirFileLoaded(MachineFunction &MF) constllvm::TargetSubtargetInfovirtual
operator=(const TargetSubtargetInfo &)=deletellvm::TargetSubtargetInfo
llvm::MCSubtargetInfo::operator=(const MCSubtargetInfo &)=deletellvm::MCSubtargetInfo
llvm::MCSubtargetInfo::operator=(MCSubtargetInfo &&)=deletellvm::MCSubtargetInfo
overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) constllvm::TargetSubtargetInfoinlinevirtual
RegClassVector typedefllvm::TargetSubtargetInfo
resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) constllvm::TargetSubtargetInfoinlinevirtual
resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) constllvm::MCSubtargetInfoinlinevirtual
setDefaultFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)llvm::MCSubtargetInfo
setFeatureBits(const FeatureBitset &FeatureBits_)llvm::MCSubtargetInfoinline
SetFeatureBitsTransitively(const FeatureBitset &FB)llvm::MCSubtargetInfo
shouldPrefetchAddressSpace(unsigned AS) constllvm::MCSubtargetInfovirtual
supportsInitUndef() constllvm::TargetSubtargetInfoinlinevirtual
TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetSubTypeKV > PD, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP)llvm::TargetSubtargetInfoprotected
TargetSubtargetInfo()=deletellvm::TargetSubtargetInfo
TargetSubtargetInfo(const TargetSubtargetInfo &)=deletellvm::TargetSubtargetInfo
ToggleFeature(uint64_t FB)llvm::MCSubtargetInfo
ToggleFeature(const FeatureBitset &FB)llvm::MCSubtargetInfo
ToggleFeature(StringRef FS)llvm::MCSubtargetInfo
useAA() constllvm::TargetSubtargetInfovirtual
useDFAforSMS() constllvm::TargetSubtargetInfoinlinevirtual
~MCSubtargetInfo()=defaultllvm::MCSubtargetInfovirtual
~TargetSubtargetInfo() overridellvm::TargetSubtargetInfo