LLVM 19.0.0git
llvm::Thumb2InstrInfo Member List

This is the complete list of members for llvm::Thumb2InstrInfo, including all inherited members.

AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) constllvm::ARMBaseInstrInfo
analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const overridellvm::ARMBaseInstrInfo
analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const overridellvm::ARMBaseInstrInfo
analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const overridellvm::ARMBaseInstrInfo
analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const overridellvm::ARMBaseInstrInfo
areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const overridellvm::ARMBaseInstrInfo
ARMBaseInstrInfo(const ARMSubtarget &STI)llvm::ARMBaseInstrInfoexplicitprotected
breakPartialRegDependency(MachineInstr &, unsigned, const TargetRegisterInfo *TRI) const overridellvm::ARMBaseInstrInfo
buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const overridellvm::ARMBaseInstrInfo
canCauseFpMLxStall(unsigned Opcode) constllvm::ARMBaseInstrInfoinline
ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const overridellvm::ARMBaseInstrInfo
commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const overridellvm::Thumb2InstrInfo
convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const overridellvm::ARMBaseInstrInfo
copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, bool KillSrc, const ARMSubtarget &Subtarget) constllvm::ARMBaseInstrInfo
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const overridellvm::Thumb2InstrInfo
copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) constllvm::ARMBaseInstrInfo
createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const overridellvm::ARMBaseInstrInfo
CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const overridellvm::ARMBaseInstrInfo
CreateTargetMIHazardRecognizer(const InstrItineraryData *II, const ScheduleDAGMI *DAG) const overridellvm::ARMBaseInstrInfo
CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const overridellvm::ARMBaseInstrInfo
decomposeMachineOperandsTargetFlags(unsigned TF) const overridellvm::ARMBaseInstrInfo
describeLoadedValue(const MachineInstr &MI, Register Reg) const overridellvm::ARMBaseInstrInfoprotected
duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const overridellvm::ARMBaseInstrInfo
expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) constllvm::ARMBaseInstrInfoprotected
expandPostRAPseudo(MachineInstr &MI) const overridellvm::ARMBaseInstrInfo
extraSizeToPredicateInstructions(const MachineFunction &MF, unsigned NumInsts) const overridellvm::ARMBaseInstrInfo
foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const overridellvm::ARMBaseInstrInfo
getExecutionDomain(const MachineInstr &MI) const overridellvm::ARMBaseInstrInfo
getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const overridellvm::ARMBaseInstrInfoprotected
getFramePred(const MachineInstr &MI) constllvm::ARMBaseInstrInfoinline
getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const overridellvm::ARMBaseInstrInfoprotected
getInstSizeInBytes(const MachineInstr &MI) const overridellvm::ARMBaseInstrInfo
getNop() const overridellvm::Thumb2InstrInfo
getNumLDMAddresses(const MachineInstr &MI) constllvm::ARMBaseInstrInfo
getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const overridellvm::ARMBaseInstrInfo
getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const overridellvm::ARMBaseInstrInfo
getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const overridellvm::ARMBaseInstrInfo
getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const overridellvm::ARMBaseInstrInfo
getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const overridellvm::ARMBaseInstrInfo
getPartialRegUpdateClearance(const MachineInstr &, unsigned, const TargetRegisterInfo *) const overridellvm::ARMBaseInstrInfo
getPredicate(const MachineInstr &MI) constllvm::ARMBaseInstrInfoinline
getRegisterInfo() const overridellvm::Thumb2InstrInfoinlinevirtual
getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const overridellvm::ARMBaseInstrInfoprotected
getSerializableBitmaskMachineOperandTargetFlags() const overridellvm::ARMBaseInstrInfo
getSerializableDirectMachineOperandTargetFlags() const overridellvm::ARMBaseInstrInfo
getSubtarget() constllvm::ARMBaseInstrInfoinline
getUndefInitOpcode(unsigned RegClassID) const overridellvm::ARMBaseInstrInfoinline
getUnindexedOpcode(unsigned Opc) const overridellvm::Thumb2InstrInfovirtual
hasNOP() constllvm::ARMBaseInstrInfo
insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const overridellvm::ARMBaseInstrInfo
insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const overridellvm::ARMBaseInstrInfo
isAddImmediate(const MachineInstr &MI, Register Reg) const overridellvm::ARMBaseInstrInfo
isCopyInstrImpl(const MachineInstr &MI) const overridellvm::ARMBaseInstrInfoprotected
isCPSRDefined(const MachineInstr &MI)llvm::ARMBaseInstrInfostatic
isFpMLxInstruction(unsigned Opcode) constllvm::ARMBaseInstrInfoinline
isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, unsigned &AddSubOpc, bool &NegAcc, bool &HasLane) constllvm::ARMBaseInstrInfo
isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const overridellvm::ARMBaseInstrInfo
isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const overridellvm::Thumb2InstrInfo
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::ARMBaseInstrInfo
isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const overridellvm::ARMBaseInstrInfo
isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const overridellvm::ARMBaseInstrInfo
isPredicable(const MachineInstr &MI) const overridellvm::ARMBaseInstrInfo
isPredicated(const MachineInstr &MI) const overridellvm::ARMBaseInstrInfo
isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const overridellvm::ARMBaseInstrInfoinline
isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const overridellvm::ARMBaseInstrInfo
isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const overridellvm::ARMBaseInstrInfo
isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const overridellvm::ARMBaseInstrInfo
isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const overridellvm::ARMBaseInstrInfo
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::ARMBaseInstrInfo
isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const overridellvm::ARMBaseInstrInfo
isSwiftFastImmShift(const MachineInstr *MI) constllvm::ARMBaseInstrInfo
isUnspillableTerminatorImpl(const MachineInstr *MI) const overridellvm::ARMBaseInstrInfoinline
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const overridellvm::Thumb2InstrInfo
mergeOutliningCandidateAttributes(Function &F, std::vector< outliner::Candidate > &Candidates) const overridellvm::ARMBaseInstrInfo
optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const overridellvm::ARMBaseInstrInfo
optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const overridellvm::Thumb2InstrInfo
PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const overridellvm::ARMBaseInstrInfo
predictBranchSizeForIfCvt(MachineInstr &MI) const overridellvm::ARMBaseInstrInfo
produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const overridellvm::ARMBaseInstrInfo
reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const overridellvm::ARMBaseInstrInfo
removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const overridellvm::ARMBaseInstrInfo
ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const overridellvm::Thumb2InstrInfo
reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const overridellvm::ARMBaseInstrInfo
setExecutionDomain(MachineInstr &MI, unsigned Domain) const overridellvm::ARMBaseInstrInfo
shouldOutlineFromFunctionByDefault(MachineFunction &MF) const overridellvm::ARMBaseInstrInfo
shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const overridellvm::ARMBaseInstrInfo
shouldSink(const MachineInstr &MI) const overridellvm::ARMBaseInstrInfo
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const overridellvm::Thumb2InstrInfo
SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const overridellvm::ARMBaseInstrInfo
Thumb2InstrInfo(const ARMSubtarget &STI)llvm::Thumb2InstrInfoexplicit