LLVM  12.0.0git
Enumerations
llvm::AArch64ISD Namespace Reference

Enumerations

enum  NodeType : unsigned {
  FIRST_NUMBER = ISD::BUILTIN_OP_END, WrapperLarge, CALL, TLSDESC_CALLSEQ,
  ADRP, ADR, ADDlow, LOADgot,
  RET_FLAG, BRCOND, CSEL, FCSEL,
  CSINV, CSNEG, CSINC, THREAD_POINTER,
  ADC, SBC, ADD_PRED, FADD_PRED,
  SDIV_PRED, UDIV_PRED, FMA_PRED, SMIN_MERGE_OP1,
  UMIN_MERGE_OP1, SMAX_MERGE_OP1, UMAX_MERGE_OP1, SHL_MERGE_OP1,
  SRL_MERGE_OP1, SRA_MERGE_OP1, SETCC_MERGE_ZERO, ADDS,
  SUBS, ADCS, SBCS, ANDS,
  CCMP, CCMN, FCCMP, FCMP,
  EXTR, DUP, DUPLANE8, DUPLANE16,
  DUPLANE32, DUPLANE64, MOVI, MOVIshift,
  MOVIedit, MOVImsl, FMOV, MVNIshift,
  MVNImsl, BICi, ORRi, BSP,
  NEG, ZIP1, ZIP2, UZP1,
  UZP2, TRN1, TRN2, REV16,
  REV32, REV64, EXT, VSHL,
  VLSHR, VASHR, SQSHL_I, UQSHL_I,
  SQSHLU_I, SRSHR_I, URSHR_I, VSLI,
  VSRI, CMEQ, CMGE, CMGT,
  CMHI, CMHS, FCMEQ, FCMGE,
  FCMGT, CMEQz, CMGEz, CMGTz,
  CMLEz, CMLTz, FCMEQz, FCMGEz,
  FCMGTz, FCMLEz, FCMLTz, SADDV,
  UADDV, SRHADD, URHADD, SMINV,
  UMINV, SMAXV, UMAXV, SMAXV_PRED,
  UMAXV_PRED, SMINV_PRED, UMINV_PRED, ORV_PRED,
  EORV_PRED, ANDV_PRED, NOT, BIT,
  CBZ, CBNZ, TBZ, TBNZ,
  TC_RETURN, PREFETCH, SITOF, UITOF,
  NVCAST, SMULL, UMULL, FRECPE,
  FRECPS, FRSQRTE, FRSQRTS, SUNPKHI,
  SUNPKLO, UUNPKHI, UUNPKLO, CLASTA_N,
  CLASTB_N, LASTA, LASTB, REV,
  TBL, FADDA_PRED, FADDV_PRED, FMAXV_PRED,
  FMAXNMV_PRED, FMINV_PRED, FMINNMV_PRED, INSR,
  PTEST, PTRUE, DUP_MERGE_PASSTHRU, INDEX_VECTOR,
  REINTERPRET_CAST, LD1_MERGE_ZERO, LD1S_MERGE_ZERO, LDNF1_MERGE_ZERO,
  LDNF1S_MERGE_ZERO, LDFF1_MERGE_ZERO, LDFF1S_MERGE_ZERO, LD1RQ_MERGE_ZERO,
  LD1RO_MERGE_ZERO, SVE_LD2_MERGE_ZERO, SVE_LD3_MERGE_ZERO, SVE_LD4_MERGE_ZERO,
  GLD1_MERGE_ZERO, GLD1_SCALED_MERGE_ZERO, GLD1_UXTW_MERGE_ZERO, GLD1_SXTW_MERGE_ZERO,
  GLD1_UXTW_SCALED_MERGE_ZERO, GLD1_SXTW_SCALED_MERGE_ZERO, GLD1_IMM_MERGE_ZERO, GLD1S_MERGE_ZERO,
  GLD1S_SCALED_MERGE_ZERO, GLD1S_UXTW_MERGE_ZERO, GLD1S_SXTW_MERGE_ZERO, GLD1S_UXTW_SCALED_MERGE_ZERO,
  GLD1S_SXTW_SCALED_MERGE_ZERO, GLD1S_IMM_MERGE_ZERO, GLDFF1_MERGE_ZERO, GLDFF1_SCALED_MERGE_ZERO,
  GLDFF1_UXTW_MERGE_ZERO, GLDFF1_SXTW_MERGE_ZERO, GLDFF1_UXTW_SCALED_MERGE_ZERO, GLDFF1_SXTW_SCALED_MERGE_ZERO,
  GLDFF1_IMM_MERGE_ZERO, GLDFF1S_MERGE_ZERO, GLDFF1S_SCALED_MERGE_ZERO, GLDFF1S_UXTW_MERGE_ZERO,
  GLDFF1S_SXTW_MERGE_ZERO, GLDFF1S_UXTW_SCALED_MERGE_ZERO, GLDFF1S_SXTW_SCALED_MERGE_ZERO, GLDFF1S_IMM_MERGE_ZERO,
  GLDNT1_MERGE_ZERO, GLDNT1_INDEX_MERGE_ZERO, GLDNT1S_MERGE_ZERO, ST1_PRED,
  SST1_PRED, SST1_SCALED_PRED, SST1_UXTW_PRED, SST1_SXTW_PRED,
  SST1_UXTW_SCALED_PRED, SST1_SXTW_SCALED_PRED, SST1_IMM_PRED, SSTNT1_PRED,
  SSTNT1_INDEX_PRED, STRICT_FCMP = ISD::FIRST_TARGET_STRICTFP_OPCODE, STRICT_FCMPE, LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
  LD3post, LD4post, ST2post, ST3post,
  ST4post, LD1x2post, LD1x3post, LD1x4post,
  ST1x2post, ST1x3post, ST1x4post, LD1DUPpost,
  LD2DUPpost, LD3DUPpost, LD4DUPpost, LD1LANEpost,
  LD2LANEpost, LD3LANEpost, LD4LANEpost, ST2LANEpost,
  ST3LANEpost, ST4LANEpost, STG, STZG,
  ST2G, STZ2G, LDP, STP,
  STNP
}
 

Enumeration Type Documentation

◆ NodeType

Enumerator
FIRST_NUMBER 
WrapperLarge 
CALL 
TLSDESC_CALLSEQ 
ADRP 
ADR 
ADDlow 
LOADgot 
RET_FLAG 
BRCOND 
CSEL 
FCSEL 
CSINV 
CSNEG 
CSINC 
THREAD_POINTER 
ADC 
SBC 
ADD_PRED 
FADD_PRED 
SDIV_PRED 
UDIV_PRED 
FMA_PRED 
SMIN_MERGE_OP1 
UMIN_MERGE_OP1 
SMAX_MERGE_OP1 
UMAX_MERGE_OP1 
SHL_MERGE_OP1 
SRL_MERGE_OP1 
SRA_MERGE_OP1 
SETCC_MERGE_ZERO 
ADDS 
SUBS 
ADCS 
SBCS 
ANDS 
CCMP 
CCMN 
FCCMP 
FCMP 
EXTR 
DUP 
DUPLANE8 
DUPLANE16 
DUPLANE32 
DUPLANE64 
MOVI 
MOVIshift 
MOVIedit 
MOVImsl 
FMOV 
MVNIshift 
MVNImsl 
BICi 
ORRi 
BSP 
NEG 
ZIP1 
ZIP2 
UZP1 
UZP2 
TRN1 
TRN2 
REV16 
REV32 
REV64 
EXT 
VSHL 
VLSHR 
VASHR 
SQSHL_I 
UQSHL_I 
SQSHLU_I 
SRSHR_I 
URSHR_I 
VSLI 
VSRI 
CMEQ 
CMGE 
CMGT 
CMHI 
CMHS 
FCMEQ 
FCMGE 
FCMGT 
CMEQz 
CMGEz 
CMGTz 
CMLEz 
CMLTz 
FCMEQz 
FCMGEz 
FCMGTz 
FCMLEz 
FCMLTz 
SADDV 
UADDV 
SRHADD 
URHADD 
SMINV 
UMINV 
SMAXV 
UMAXV 
SMAXV_PRED 
UMAXV_PRED 
SMINV_PRED 
UMINV_PRED 
ORV_PRED 
EORV_PRED 
ANDV_PRED 
NOT 
BIT 
CBZ 
CBNZ 
TBZ 
TBNZ 
TC_RETURN 
PREFETCH 
SITOF 
UITOF 
NVCAST 

Natural vector cast.

ISD::BITCAST is not natural in the big-endian world w.r.t vectors; which causes additional REV instructions to be generated to compensate for the byte-swapping. But sometimes we do need to re-interpret the data in SIMD vector registers in big-endian mode without emitting such REV instructions.

SMULL 
UMULL 
FRECPE 
FRECPS 
FRSQRTE 
FRSQRTS 
SUNPKHI 
SUNPKLO 
UUNPKHI 
UUNPKLO 
CLASTA_N 
CLASTB_N 
LASTA 
LASTB 
REV 
TBL 
FADDA_PRED 
FADDV_PRED 
FMAXV_PRED 
FMAXNMV_PRED 
FMINV_PRED 
FMINNMV_PRED 
INSR 
PTEST 
PTRUE 
DUP_MERGE_PASSTHRU 
INDEX_VECTOR 
REINTERPRET_CAST 
LD1_MERGE_ZERO 
LD1S_MERGE_ZERO 
LDNF1_MERGE_ZERO 
LDNF1S_MERGE_ZERO 
LDFF1_MERGE_ZERO 
LDFF1S_MERGE_ZERO 
LD1RQ_MERGE_ZERO 
LD1RO_MERGE_ZERO 
SVE_LD2_MERGE_ZERO 
SVE_LD3_MERGE_ZERO 
SVE_LD4_MERGE_ZERO 
GLD1_MERGE_ZERO 
GLD1_SCALED_MERGE_ZERO 
GLD1_UXTW_MERGE_ZERO 
GLD1_SXTW_MERGE_ZERO 
GLD1_UXTW_SCALED_MERGE_ZERO 
GLD1_SXTW_SCALED_MERGE_ZERO 
GLD1_IMM_MERGE_ZERO 
GLD1S_MERGE_ZERO 
GLD1S_SCALED_MERGE_ZERO 
GLD1S_UXTW_MERGE_ZERO 
GLD1S_SXTW_MERGE_ZERO 
GLD1S_UXTW_SCALED_MERGE_ZERO 
GLD1S_SXTW_SCALED_MERGE_ZERO 
GLD1S_IMM_MERGE_ZERO 
GLDFF1_MERGE_ZERO 
GLDFF1_SCALED_MERGE_ZERO 
GLDFF1_UXTW_MERGE_ZERO 
GLDFF1_SXTW_MERGE_ZERO 
GLDFF1_UXTW_SCALED_MERGE_ZERO 
GLDFF1_SXTW_SCALED_MERGE_ZERO 
GLDFF1_IMM_MERGE_ZERO 
GLDFF1S_MERGE_ZERO 
GLDFF1S_SCALED_MERGE_ZERO 
GLDFF1S_UXTW_MERGE_ZERO 
GLDFF1S_SXTW_MERGE_ZERO 
GLDFF1S_UXTW_SCALED_MERGE_ZERO 
GLDFF1S_SXTW_SCALED_MERGE_ZERO 
GLDFF1S_IMM_MERGE_ZERO 
GLDNT1_MERGE_ZERO 
GLDNT1_INDEX_MERGE_ZERO 
GLDNT1S_MERGE_ZERO 
ST1_PRED 
SST1_PRED 
SST1_SCALED_PRED 
SST1_UXTW_PRED 
SST1_SXTW_PRED 
SST1_UXTW_SCALED_PRED 
SST1_SXTW_SCALED_PRED 
SST1_IMM_PRED 
SSTNT1_PRED 
SSTNT1_INDEX_PRED 
STRICT_FCMP 
STRICT_FCMPE 
LD2post 
LD3post 
LD4post 
ST2post 
ST3post 
ST4post 
LD1x2post 
LD1x3post 
LD1x4post 
ST1x2post 
ST1x3post 
ST1x4post 
LD1DUPpost 
LD2DUPpost 
LD3DUPpost 
LD4DUPpost 
LD1LANEpost 
LD2LANEpost 
LD3LANEpost 
LD4LANEpost 
ST2LANEpost 
ST3LANEpost 
ST4LANEpost 
STG 
STZG 
ST2G 
STZ2G 
LDP 
STP 
STNP 

Definition at line 48 of file AArch64ISelLowering.h.