LLVM 19.0.0git
Enumerations | Functions
llvm::PPC Namespace Reference

Define some predicates that are used for node matching. More...

Enumerations

enum  Fixups {
  fixup_ppc_br24 = FirstTargetFixupKind , fixup_ppc_br24_notoc , fixup_ppc_brcond14 , fixup_ppc_br24abs ,
  fixup_ppc_brcond14abs , fixup_ppc_half16 , fixup_ppc_half16ds , fixup_ppc_pcrel34 ,
  fixup_ppc_imm34 , fixup_ppc_nofixup , fixup_ppc_half16dq , LastTargetFixupKind ,
  NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
}
 
enum  Predicate {
  PRED_LT = (0 << 5) | 12 , PRED_LE = (1 << 5) | 4 , PRED_EQ = (2 << 5) | 12 , PRED_GE = (0 << 5) | 4 ,
  PRED_GT = (1 << 5) | 12 , PRED_NE = (2 << 5) | 4 , PRED_UN = (3 << 5) | 12 , PRED_NU = (3 << 5) | 4 ,
  PRED_LT_MINUS = (0 << 5) | 14 , PRED_LE_MINUS = (1 << 5) | 6 , PRED_EQ_MINUS = (2 << 5) | 14 , PRED_GE_MINUS = (0 << 5) | 6 ,
  PRED_GT_MINUS = (1 << 5) | 14 , PRED_NE_MINUS = (2 << 5) | 6 , PRED_UN_MINUS = (3 << 5) | 14 , PRED_NU_MINUS = (3 << 5) | 6 ,
  PRED_LT_PLUS = (0 << 5) | 15 , PRED_LE_PLUS = (1 << 5) | 7 , PRED_EQ_PLUS = (2 << 5) | 15 , PRED_GE_PLUS = (0 << 5) | 7 ,
  PRED_GT_PLUS = (1 << 5) | 15 , PRED_NE_PLUS = (2 << 5) | 7 , PRED_UN_PLUS = (3 << 5) | 15 , PRED_NU_PLUS = (3 << 5) | 7 ,
  PRED_SPE = PRED_GT , PRED_BIT_SET = 1024 , PRED_BIT_UNSET = 1025
}
 Predicate - These are "(BI << 5) | BO" for various predicates. More...
 
enum  BranchHintBit { BR_NO_HINT = 0x0 , BR_NONTAKEN_HINT = 0x2 , BR_TAKEN_HINT = 0x3 , BR_HINT_MASK = 0X3 }
 
enum  MemOpFlags {
  MOF_None = 0 , MOF_SExt = 1 , MOF_ZExt = 1 << 1 , MOF_NoExt = 1 << 2 ,
  MOF_NotAddNorCst = 1 << 5 , MOF_RPlusSImm16 = 1 << 6 , MOF_RPlusLo = 1 << 7 , MOF_RPlusSImm16Mult4 = 1 << 8 ,
  MOF_RPlusSImm16Mult16 = 1 << 9 , MOF_RPlusSImm34 = 1 << 10 , MOF_RPlusR = 1 << 11 , MOF_PCRel = 1 << 12 ,
  MOF_AddrIsSImm32 = 1 << 13 , MOF_SubWordInt = 1 << 15 , MOF_WordInt = 1 << 16 , MOF_DoubleWordInt = 1 << 17 ,
  MOF_ScalarFloat = 1 << 18 , MOF_Vector = 1 << 19 , MOF_Vector256 = 1 << 20 , MOF_SubtargetBeforeP9 = 1 << 22 ,
  MOF_SubtargetP9 = 1 << 23 , MOF_SubtargetP10 = 1 << 24 , MOF_SubtargetSPE = 1 << 25
}
 
enum  AddrMode {
  AM_None , AM_DForm , AM_DSForm , AM_DQForm ,
  AM_PrefixDForm , AM_XForm , AM_PCRel
}
 
enum  {
  DIR_NONE , DIR_32 , DIR_440 , DIR_601 ,
  DIR_602 , DIR_603 , DIR_7400 , DIR_750 ,
  DIR_970 , DIR_A2 , DIR_E500 , DIR_E500mc ,
  DIR_E5500 , DIR_PWR3 , DIR_PWR4 , DIR_PWR5 ,
  DIR_PWR5X , DIR_PWR6 , DIR_PWR6X , DIR_PWR7 ,
  DIR_PWR8 , DIR_PWR9 , DIR_PWR10 , DIR_PWR_FUTURE ,
  DIR_64
}
 

Functions

const charstripRegisterPrefix (const char *RegName)
 stripRegisterPrefix - This method strips the character prefix from a register name so that only the number is left.
 
unsigned getRegNumForOperand (const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)
 getRegNumForOperand - some operands use different numbering schemes for the same registers.
 
static bool isVFRegister (unsigned Reg)
 
static bool isVRRegister (unsigned Reg)
 
Predicate InvertPredicate (Predicate Opcode)
 Invert the specified predicate. != -> ==, < -> >=.
 
Predicate getSwappedPredicate (Predicate Opcode)
 Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions such that condition register is set by MI(b,a).
 
unsigned getPredicateCondition (Predicate Opcode)
 Return the condition without hint bits.
 
unsigned getPredicateHint (Predicate Opcode)
 Return the hint bits of the predicate.
 
Predicate getPredicate (unsigned Condition, unsigned Hint)
 Return predicate consisting of specified condition and hint bits.
 
int getNonRecordFormOpcode (uint16_t)
 
bool isVPKUHUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
 isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction.
 
bool isVPKUWUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
 isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction.
 
bool isVPKUDUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
 isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction.
 
bool isVMRGLShuffleMask (ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
 isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
 
bool isVMRGHShuffleMask (ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
 isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
 
bool isVMRGEOShuffleMask (ShuffleVectorSDNode *N, bool CheckEven, unsigned ShuffleKind, SelectionDAG &DAG)
 isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instruction
 
bool isXXSLDWIShuffleMask (ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
 isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable for a XXSLDWI instruction.
 
bool isXXBRHShuffleMask (ShuffleVectorSDNode *N)
 isXXBRHShuffleMask - Return true if this is a shuffle mask suitable for a XXBRH instruction.
 
bool isXXBRWShuffleMask (ShuffleVectorSDNode *N)
 isXXBRWShuffleMask - Return true if this is a shuffle mask suitable for a XXBRW instruction.
 
bool isXXBRDShuffleMask (ShuffleVectorSDNode *N)
 isXXBRDShuffleMask - Return true if this is a shuffle mask suitable for a XXBRD instruction.
 
bool isXXBRQShuffleMask (ShuffleVectorSDNode *N)
 isXXBRQShuffleMask - Return true if this is a shuffle mask suitable for a XXBRQ instruction.
 
bool isXXPERMDIShuffleMask (ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
 isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable for a XXPERMDI instruction.
 
int isVSLDOIShuffleMask (SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
 isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1.
 
bool isSplatShuffleMask (ShuffleVectorSDNode *N, unsigned EltSize)
 isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a single element that is suitable for input to VSPLTB/VSPLTH/VSPLTW.
 
bool isXXINSERTWMask (ShuffleVectorSDNode *N, unsigned &ShiftElts, unsigned &InsertAtByte, bool &Swap, bool IsLE)
 isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by the XXINSERTW instruction introduced in ISA 3.0.
 
unsigned getSplatIdxForPPCMnemonics (SDNode *N, unsigned EltSize, SelectionDAG &DAG)
 getSplatIdxForPPCMnemonics - Return the splat index as a value that is appropriate for PPC mnemonics (which have a big endian bias - namely elements are counted from the left of the vector register).
 
SDValue get_VSPLTI_elt (SDNode *N, unsigned ByteSize, SelectionDAG &DAG)
 get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] instruction of the specified element size, return the constant being splatted.
 
FastISelcreateFastISel (FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)
 
int getAltVSXFMAOpcode (uint16_t Opcode)
 

Detailed Description

Define some predicates that are used for node matching.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
DIR_NONE 
DIR_32 
DIR_440 
DIR_601 
DIR_602 
DIR_603 
DIR_7400 
DIR_750 
DIR_970 
DIR_A2 
DIR_E500 
DIR_E500mc 
DIR_E5500 
DIR_PWR3 
DIR_PWR4 
DIR_PWR5 
DIR_PWR5X 
DIR_PWR6 
DIR_PWR6X 
DIR_PWR7 
DIR_PWR8 
DIR_PWR9 
DIR_PWR10 
DIR_PWR_FUTURE 
DIR_64 

Definition at line 40 of file PPCSubtarget.h.

◆ AddrMode

Enumerator
AM_None 
AM_DForm 
AM_DSForm 
AM_DQForm 
AM_PrefixDForm 
AM_XForm 
AM_PCRel 

Definition at line 735 of file PPCISelLowering.h.

◆ BranchHintBit

Enumerator
BR_NO_HINT 
BR_NONTAKEN_HINT 
BR_TAKEN_HINT 
BR_HINT_MASK 

Definition at line 62 of file PPCPredicates.h.

◆ Fixups

Enumerator
fixup_ppc_br24 
fixup_ppc_br24_notoc 
fixup_ppc_brcond14 

14-bit PC relative relocation for conditional branches.

fixup_ppc_br24abs 

24-bit absolute relocation for direct branches like 'ba' and 'bla'.

fixup_ppc_brcond14abs 

14-bit absolute relocation for conditional branches.

fixup_ppc_half16 

A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like 'li' or 'addis'.

fixup_ppc_half16ds 

A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for instrs like 'std'.

fixup_ppc_pcrel34 
fixup_ppc_imm34 
fixup_ppc_nofixup 

Not a true fixup, but ties a symbol to a call to __tls_get_addr for the TLS general and local dynamic models, or inserts the thread-pointer register number.

It can also be used to tie the ref symbol to prevent it from being garbage collected on AIX.

fixup_ppc_half16dq 

A 16-bit fixup corresponding to lo16(_foo) with implied 3 zero bits for instrs like 'lxv'.

Produces the same relocation as fixup_ppc_half16ds.

LastTargetFixupKind 
NumTargetFixupKinds 

Definition at line 18 of file PPCFixupKinds.h.

◆ MemOpFlags

Enumerator
MOF_None 
MOF_SExt 
MOF_ZExt 
MOF_NoExt 
MOF_NotAddNorCst 
MOF_RPlusSImm16 
MOF_RPlusLo 
MOF_RPlusSImm16Mult4 
MOF_RPlusSImm16Mult16 
MOF_RPlusSImm34 
MOF_RPlusR 
MOF_PCRel 
MOF_AddrIsSImm32 
MOF_SubWordInt 
MOF_WordInt 
MOF_DoubleWordInt 
MOF_ScalarFloat 
MOF_Vector 
MOF_Vector256 
MOF_SubtargetBeforeP9 
MOF_SubtargetP9 
MOF_SubtargetP10 
MOF_SubtargetSPE 

Definition at line 700 of file PPCISelLowering.h.

◆ Predicate

Predicate - These are "(BI << 5) | BO" for various predicates.

Enumerator
PRED_LT 
PRED_LE 
PRED_EQ 
PRED_GE 
PRED_GT 
PRED_NE 
PRED_UN 
PRED_NU 
PRED_LT_MINUS 
PRED_LE_MINUS 
PRED_EQ_MINUS 
PRED_GE_MINUS 
PRED_GT_MINUS 
PRED_NE_MINUS 
PRED_UN_MINUS 
PRED_NU_MINUS 
PRED_LT_PLUS 
PRED_LE_PLUS 
PRED_EQ_PLUS 
PRED_GE_PLUS 
PRED_GT_PLUS 
PRED_NE_PLUS 
PRED_UN_PLUS 
PRED_NU_PLUS 
PRED_SPE 
PRED_BIT_SET 
PRED_BIT_UNSET 

Definition at line 26 of file PPCPredicates.h.

Function Documentation

◆ createFastISel()

FastISel * llvm::PPC::createFastISel ( FunctionLoweringInfo FuncInfo,
const TargetLibraryInfo LibInfo 
)

◆ get_VSPLTI_elt()

SDValue llvm::PPC::get_VSPLTI_elt ( SDNode N,
unsigned  ByteSize,
SelectionDAG DAG 
)

get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] instruction of the specified element size, return the constant being splatted.

The ByteSize field indicates the number of bytes of each element [124] -> [bhw].

Definition at line 2529 of file PPCISelLowering.cpp.

References assert(), llvm::SDNode::getAsZExtVal(), llvm::SDValue::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::isAllOnesConstant(), llvm::isNullConstant(), isSplat(), N, and llvm::SignExtend32().

◆ getAltVSXFMAOpcode()

int llvm::PPC::getAltVSXFMAOpcode ( uint16_t  Opcode)

◆ getNonRecordFormOpcode()

int llvm::PPC::getNonRecordFormOpcode ( uint16_t  )

◆ getPredicate()

Predicate llvm::PPC::getPredicate ( unsigned  Condition,
unsigned  Hint 
)
inline

Return predicate consisting of specified condition and hint bits.

Definition at line 87 of file PPCPredicates.h.

References BR_HINT_MASK.

Referenced by llvm::PPCInstrInfo::optimizeCompareInstr().

◆ getPredicateCondition()

unsigned llvm::PPC::getPredicateCondition ( Predicate  Opcode)
inline

Return the condition without hint bits.

Definition at line 77 of file PPCPredicates.h.

Referenced by llvm::PPCInstrInfo::optimizeCompareInstr().

◆ getPredicateHint()

unsigned llvm::PPC::getPredicateHint ( Predicate  Opcode)
inline

Return the hint bits of the predicate.

Definition at line 82 of file PPCPredicates.h.

References BR_HINT_MASK.

Referenced by llvm::PPCInstrInfo::optimizeCompareInstr().

◆ getRegNumForOperand()

unsigned llvm::PPC::getRegNumForOperand ( const MCInstrDesc Desc,
unsigned  Reg,
unsigned  OpNo 
)

getRegNumForOperand - some operands use different numbering schemes for the same registers.

For example, a VSX instruction may have any of vs0-vs63 allocated whereas an Altivec instruction could only have vs32-vs63 allocated (numbered as v0-v31). This function returns the actual register number needed for the opcode/operand number combination. The operand number argument will be useful when we need to extend this to instructions that use both Altivec and VSX numbering (for different operands).

Definition at line 120 of file PPCMCTargetDesc.cpp.

References isVFRegister(), and isVRRegister().

Referenced by llvm::PPCMCCodeEmitter::getMachineOpValue(), and llvm::PPCInstPrinter::printOperand().

◆ getSplatIdxForPPCMnemonics()

unsigned llvm::PPC::getSplatIdxForPPCMnemonics ( SDNode N,
unsigned  EltSize,
SelectionDAG DAG 
)

getSplatIdxForPPCMnemonics - Return the splat index as a value that is appropriate for PPC mnemonics (which have a big endian bias - namely elements are counted from the left of the vector register).

Definition at line 2509 of file PPCISelLowering.cpp.

References assert(), llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getValueType(), llvm::DataLayout::isLittleEndian(), isSplatShuffleMask(), and N.

◆ getSwappedPredicate()

PPC::Predicate llvm::PPC::getSwappedPredicate ( PPC::Predicate  Opcode)

Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions such that condition register is set by MI(b,a).

Definition at line 51 of file PPCPredicates.cpp.

References llvm_unreachable, PRED_BIT_SET, PRED_BIT_UNSET, PRED_EQ, PRED_EQ_MINUS, PRED_EQ_PLUS, PRED_GE, PRED_GE_MINUS, PRED_GE_PLUS, PRED_GT, PRED_GT_MINUS, PRED_GT_PLUS, PRED_LE, PRED_LE_MINUS, PRED_LE_PLUS, PRED_LT, PRED_LT_MINUS, PRED_LT_PLUS, PRED_NE, PRED_NE_MINUS, PRED_NE_PLUS, PRED_NU, PRED_NU_MINUS, PRED_NU_PLUS, PRED_UN, PRED_UN_MINUS, and PRED_UN_PLUS.

Referenced by llvm::PPCInstrInfo::optimizeCompareInstr().

◆ InvertPredicate()

PPC::Predicate llvm::PPC::InvertPredicate ( PPC::Predicate  Opcode)

◆ isSplatShuffleMask()

bool llvm::PPC::isSplatShuffleMask ( ShuffleVectorSDNode N,
unsigned  EltSize 
)

isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a single element that is suitable for input to VSPLTB/VSPLTH/VSPLTW.

isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a single element that is suitable for input to one of the splat operations (VSPLTB/VSPLTH/VSPLTW/XXSPLTW/LXVDSX/etc.).

Definition at line 2207 of file PPCISelLowering.cpp.

References assert(), llvm::isPowerOf2_32(), and N.

Referenced by getSplatIdxForPPCMnemonics().

◆ isVFRegister()

static bool llvm::PPC::isVFRegister ( unsigned  Reg)
inlinestatic

◆ isVMRGEOShuffleMask()

bool llvm::PPC::isVMRGEOShuffleMask ( ShuffleVectorSDNode N,
bool  CheckEven,
unsigned  ShuffleKind,
SelectionDAG DAG 
)

isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instruction

Determine if the specified shuffle mask is suitable for the vmrgew or vmrgow instructions.

Parameters
[in]NThe shuffle vector SD Node to analyze
[in]CheckEvenCheck for an even merge (true) or an odd merge (false)
[in]ShuffleKindIdentify the type of merge:
  • 0 = big-endian merge with two different inputs;
  • 1 = either-endian merge with two identical inputs;
  • 2 = little-endian merge with two different inputs (inputs are swapped for little-endian merges).
[in]DAGThe current SelectionDAG
Returns
true iff this shuffle mask

Definition at line 2134 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::isLittleEndian(), isVMerge(), and N.

◆ isVMRGHShuffleMask()

bool llvm::PPC::isVMRGHShuffleMask ( ShuffleVectorSDNode N,
unsigned  UnitSize,
unsigned  ShuffleKind,
SelectionDAG DAG 
)

isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the specified unit size (1,2 or 4 bytes).

isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).

The ShuffleKind distinguishes between big-endian merges with two different inputs (0), either-endian merges with two identical inputs (1), and little-endian merges with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 2044 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::isLittleEndian(), isVMerge(), and N.

◆ isVMRGLShuffleMask()

bool llvm::PPC::isVMRGLShuffleMask ( ShuffleVectorSDNode N,
unsigned  UnitSize,
unsigned  ShuffleKind,
SelectionDAG DAG 
)

isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the specified unit size (1,2 or 4 bytes).

isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).

The ShuffleKind distinguishes between big-endian merges with two different inputs (0), either-endian merges with two identical inputs (1), and little-endian merges with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 2019 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::isLittleEndian(), isVMerge(), and N.

◆ isVPKUDUMShuffleMask()

bool llvm::PPC::isVPKUDUMShuffleMask ( ShuffleVectorSDNode N,
unsigned  ShuffleKind,
SelectionDAG DAG 
)

isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction.

isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction, AND the VPKUDUM instruction exists for the current subtarget.

The ShuffleKind distinguishes between big-endian operations with two different inputs (0), either-endian operations with two identical inputs (1), and little-endian operations with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 1952 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getSubtarget(), isConstantOrUndef(), llvm::DataLayout::isLittleEndian(), and N.

◆ isVPKUHUMShuffleMask()

bool llvm::PPC::isVPKUHUMShuffleMask ( ShuffleVectorSDNode N,
unsigned  ShuffleKind,
SelectionDAG DAG 
)

isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction.

The ShuffleKind distinguishes between big-endian operations with two different inputs (0), either-endian operations with two identical inputs (1), and little-endian operations with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 1884 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), isConstantOrUndef(), llvm::DataLayout::isLittleEndian(), and N.

◆ isVPKUWUMShuffleMask()

bool llvm::PPC::isVPKUWUMShuffleMask ( ShuffleVectorSDNode N,
unsigned  ShuffleKind,
SelectionDAG DAG 
)

isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction.

The ShuffleKind distinguishes between big-endian operations with two different inputs (0), either-endian operations with two identical inputs (1), and little-endian operations with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 1915 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), isConstantOrUndef(), llvm::DataLayout::isLittleEndian(), and N.

◆ isVRRegister()

static bool llvm::PPC::isVRRegister ( unsigned  Reg)
inlinestatic

Definition at line 292 of file PPCMCTargetDesc.h.

References Reg.

Referenced by getRegNumForOperand().

◆ isVSLDOIShuffleMask()

int llvm::PPC::isVSLDOIShuffleMask ( SDNode N,
unsigned  ShuffleKind,
SelectionDAG DAG 
)

isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1.

The ShuffleKind distinguishes between big-endian operations with two different inputs (0), either-endian operations with two identical inputs (1), and little-endian operations with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 2163 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMaskElt(), isConstantOrUndef(), llvm::DataLayout::isLittleEndian(), and N.

◆ isXXBRDShuffleMask()

bool llvm::PPC::isXXBRDShuffleMask ( ShuffleVectorSDNode N)

isXXBRDShuffleMask - Return true if this is a shuffle mask suitable for a XXBRD instruction.

Definition at line 2437 of file PPCISelLowering.cpp.

References isXXBRShuffleMaskHelper(), and N.

◆ isXXBRHShuffleMask()

bool llvm::PPC::isXXBRHShuffleMask ( ShuffleVectorSDNode N)

isXXBRHShuffleMask - Return true if this is a shuffle mask suitable for a XXBRH instruction.

Definition at line 2429 of file PPCISelLowering.cpp.

References isXXBRShuffleMaskHelper(), and N.

◆ isXXBRQShuffleMask()

bool llvm::PPC::isXXBRQShuffleMask ( ShuffleVectorSDNode N)

isXXBRQShuffleMask - Return true if this is a shuffle mask suitable for a XXBRQ instruction.

Definition at line 2441 of file PPCISelLowering.cpp.

References isXXBRShuffleMaskHelper(), and N.

◆ isXXBRWShuffleMask()

bool llvm::PPC::isXXBRWShuffleMask ( ShuffleVectorSDNode N)

isXXBRWShuffleMask - Return true if this is a shuffle mask suitable for a XXBRW instruction.

Definition at line 2433 of file PPCISelLowering.cpp.

References isXXBRShuffleMaskHelper(), and N.

◆ isXXINSERTWMask()

bool llvm::PPC::isXXINSERTWMask ( ShuffleVectorSDNode N,
unsigned ShiftElts,
unsigned InsertAtByte,
bool Swap,
bool  IsLE 
)

isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by the XXINSERTW instruction introduced in ISA 3.0.

This is essentially any shuffle of v4f32/v4i32 vectors that just inserts one element from one vector into the other. This function will also set a couple of output parameters for how much the source vector needs to be shifted and what byte number needs to be specified for the instruction to put the element in the desired location of the target vector.

Definition at line 2279 of file PPCISelLowering.cpp.

References isNByteElemShuffleMask(), llvm::M0(), llvm::M1(), and N.

◆ isXXPERMDIShuffleMask()

bool llvm::PPC::isXXPERMDIShuffleMask ( ShuffleVectorSDNode N,
unsigned DM,
bool Swap,
bool  IsLE 
)

isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable for a XXPERMDI instruction.

Can node N be lowered to an XXPERMDI instruction? If so, set Swap if the inputs to the instruction should be swapped and set DM to the value for the immediate.

Specifically, set Swap to true only if N can be lowered to XXPERMDI AND element 0 of the result comes from the first input (LE) or second input (BE). Set DM to the calculated result (0-3) only if N can be lowered.

Returns
true iff the given mask of shuffle node N is a XXPERMDI shuffle mask.

Definition at line 2453 of file PPCISelLowering.cpp.

References assert(), DM, isNByteElemShuffleMask(), llvm::M0(), llvm::M1(), and N.

◆ isXXSLDWIShuffleMask()

bool llvm::PPC::isXXSLDWIShuffleMask ( ShuffleVectorSDNode N,
unsigned ShiftElts,
bool Swap,
bool  IsLE 
)

isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable for a XXSLDWI instruction.

Definition at line 2354 of file PPCISelLowering.cpp.

References assert(), isNByteElemShuffleMask(), llvm::M0(), llvm::M1(), and N.

◆ stripRegisterPrefix()

const char * llvm::PPC::stripRegisterPrefix ( const char RegName)

stripRegisterPrefix - This method strips the character prefix from a register name so that only the number is left.

Used by for linux asm.

Definition at line 62 of file PPCMCTargetDesc.cpp.

References RegName.

Referenced by llvm::PPCInstPrinter::printOperand().