LLVM  9.0.0svn
Enumerations | Functions
llvm::X86 Namespace Reference

Define some predicates that are used for node matching. More...

Enumerations

enum  ProcessorVendors : unsigned { VENDOR_DUMMY, VENDOR_OTHER }
 
enum  ProcessorTypes : unsigned { CPU_TYPE_DUMMY, CPU_TYPE_MAX }
 
enum  ProcessorSubtypes : unsigned { CPU_SUBTYPE_DUMMY, CPU_SUBTYPE_MAX }
 
enum  ProcessorFeatures
 
enum  {
  BX_SI = 500, BX_DI = 501, BP_SI = 502, BP_DI = 503,
  sib = 504, sib64 = 505
}
 
enum  {
  AddrBaseReg = 0, AddrScaleAmt = 1, AddrIndexReg = 2, AddrDisp = 3,
  AddrSegmentReg = 4, AddrNumOperands = 5
}
 
enum  STATIC_ROUNDING {
  TO_NEAREST_INT = 0, TO_NEG_INF = 1, TO_POS_INF = 2, TO_ZERO = 3,
  CUR_DIRECTION = 4, NO_EXC = 8
}
 AVX512 static rounding constants. More...
 
enum  IPREFIXES {
  IP_NO_PREFIX = 0, IP_HAS_OP_SIZE = 1, IP_HAS_AD_SIZE = 2, IP_HAS_REPEAT_NE = 4,
  IP_HAS_REPEAT = 8, IP_HAS_LOCK = 16, IP_HAS_NOTRACK = 32, IP_USE_VEX3 = 64
}
 The constants to describe instr prefixes if there are. More...
 
enum  OperandType : unsigned { OPERAND_ROUNDING_CONTROL = MCOI::OPERAND_FIRST_TARGET, OPERAND_COND_CODE }
 
enum  CondCode {
  COND_O = 0, COND_NO = 1, COND_B = 2, COND_AE = 3,
  COND_E = 4, COND_NE = 5, COND_BE = 6, COND_A = 7,
  COND_S = 8, COND_NS = 9, COND_P = 10, COND_NP = 11,
  COND_L = 12, COND_GE = 13, COND_LE = 14, COND_G = 15,
  LAST_VALID_COND = COND_G, COND_NE_OR_P, COND_E_AND_NP, COND_INVALID
}
 
enum  Fixups {
  reloc_riprel_4byte = FirstTargetFixupKind, reloc_riprel_4byte_movq_load, reloc_riprel_4byte_relax, reloc_riprel_4byte_relax_rex,
  reloc_signed_4byte, reloc_signed_4byte_relax, reloc_global_offset_table, reloc_global_offset_table8,
  reloc_branch_4byte_pcrel, LastTargetFixupKind, NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
}
 
enum  AsmComments { AC_EVEX_2_VEX = MachineInstr::TAsmComments }
 

Functions

std::pair< CondCode, boolgetX86ConditionCode (CmpInst::Predicate Predicate)
 Return a pair of condition code for the given predicate and whether the instruction operands should be swaped to match the condition code. More...
 
unsigned getSETOpc (bool HasMemoryOperand=false)
 Return a setcc opcode based on whether it has a memory operand. More...
 
unsigned getCMovOpcode (unsigned RegBytes, bool HasMemoryOperand=false)
 Return a cmov opcode for the given register size in bytes, and operand type. More...
 
CondCode getCondFromBranch (const MachineInstr &MI)
 
CondCode getCondFromSETCC (const MachineInstr &MI)
 Return condition code of a SETCC opcode. More...
 
CondCode getCondFromCMov (const MachineInstr &MI)
 Return condition code of a CMov opcode. More...
 
CondCode GetOppositeBranchCondition (CondCode CC)
 GetOppositeBranchCondition - Return the inverse of the specified cond, e.g. More...
 
unsigned getVPCMPImmForCond (ISD::CondCode CC)
 Get the VPCMP immediate for the given condition. More...
 
unsigned getSwappedVPCMPImm (unsigned Imm)
 Get the VPCMP immediate if the opcodes are swapped. More...
 
unsigned getSwappedVPCOMImm (unsigned Imm)
 Get the VPCOM immediate if the opcodes are swapped. More...
 
bool isZeroNode (SDValue Elt)
 Returns true if Elt is a constant zero or floating point constant +0.0. More...
 
bool isOffsetSuitableForCodeModel (int64_t Offset, CodeModel::Model M, bool hasSymbolicDisplacement=true)
 Returns true of the given offset can be fit into displacement field of the instruction. More...
 
bool isCalleePop (CallingConv::ID CallingConv, bool is64Bit, bool IsVarArg, bool GuaranteeTCO)
 Determines whether the callee is required to pop its own arguments. More...
 
FastISelcreateFastISel (FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
 

Detailed Description

Define some predicates that are used for node matching.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
BX_SI 
BX_DI 
BP_SI 
BP_DI 
sib 
sib64 

Definition at line 114 of file X86Disassembler.cpp.

◆ anonymous enum

anonymous enum
Enumerator
AddrBaseReg 
AddrScaleAmt 
AddrIndexReg 
AddrDisp 
AddrSegmentReg 

AddrSegmentReg - The operand # of the segment in the memory operand.

AddrNumOperands 

AddrNumOperands - Total number of operands in a memory reference.

Definition at line 31 of file X86BaseInfo.h.

◆ AsmComments

Enumerator
AC_EVEX_2_VEX 

Definition at line 33 of file X86InstrInfo.h.

◆ CondCode

Enumerator
COND_O 
COND_NO 
COND_B 
COND_AE 
COND_E 
COND_NE 
COND_BE 
COND_A 
COND_S 
COND_NS 
COND_P 
COND_NP 
COND_L 
COND_GE 
COND_LE 
COND_G 
LAST_VALID_COND 
COND_NE_OR_P 
COND_E_AND_NP 
COND_INVALID 

Definition at line 75 of file X86BaseInfo.h.

◆ Fixups

Enumerator
reloc_riprel_4byte 
reloc_riprel_4byte_movq_load 
reloc_riprel_4byte_relax 
reloc_riprel_4byte_relax_rex 
reloc_signed_4byte 
reloc_signed_4byte_relax 
reloc_global_offset_table 
reloc_global_offset_table8 
reloc_branch_4byte_pcrel 
LastTargetFixupKind 
NumTargetFixupKinds 

Definition at line 16 of file X86FixupKinds.h.

◆ IPREFIXES

The constants to describe instr prefixes if there are.

Enumerator
IP_NO_PREFIX 
IP_HAS_OP_SIZE 
IP_HAS_AD_SIZE 
IP_HAS_REPEAT_NE 
IP_HAS_REPEAT 
IP_HAS_LOCK 
IP_HAS_NOTRACK 
IP_USE_VEX3 

Definition at line 56 of file X86BaseInfo.h.

◆ OperandType

Enumerator
OPERAND_ROUNDING_CONTROL 

AVX512 embedded rounding control. This should only have values 0-3.

OPERAND_COND_CODE 

Definition at line 67 of file X86BaseInfo.h.

◆ ProcessorFeatures

Definition at line 68 of file TargetParser.h.

◆ ProcessorSubtypes

Enumerator
CPU_SUBTYPE_DUMMY 
CPU_SUBTYPE_MAX 

Definition at line 58 of file TargetParser.h.

◆ ProcessorTypes

Enumerator
CPU_TYPE_DUMMY 
CPU_TYPE_MAX 

Definition at line 48 of file TargetParser.h.

◆ ProcessorVendors

Enumerator
VENDOR_DUMMY 
VENDOR_OTHER 

Definition at line 38 of file TargetParser.h.

◆ STATIC_ROUNDING

AVX512 static rounding constants.

These need to match the values in avx512fintrin.h.

Enumerator
TO_NEAREST_INT 
TO_NEG_INF 
TO_POS_INF 
TO_ZERO 
CUR_DIRECTION 
NO_EXC 

Definition at line 46 of file X86BaseInfo.h.

Function Documentation

◆ createFastISel()

FastISel * llvm::X86::createFastISel ( FunctionLoweringInfo funcInfo,
const TargetLibraryInfo libInfo 
)

◆ getCMovOpcode()

unsigned llvm::X86::getCMovOpcode ( unsigned  RegBytes,
bool  HasMemoryOperand = false 
)

Return a cmov opcode for the given register size in bytes, and operand type.

Definition at line 2111 of file X86InstrInfo.cpp.

References llvm_unreachable.

Referenced by getRegClassForUnfoldedLoad(), llvm::X86InstrInfo::insertSelect(), and isEFLAGSLive().

◆ getCondFromBranch()

X86::CondCode llvm::X86::getCondFromBranch ( const MachineInstr MI)

◆ getCondFromCMov()

X86::CondCode llvm::X86::getCondFromCMov ( const MachineInstr MI)

◆ getCondFromSETCC()

X86::CondCode llvm::X86::getCondFromSETCC ( const MachineInstr MI)

◆ GetOppositeBranchCondition()

X86::CondCode llvm::X86::GetOppositeBranchCondition ( X86::CondCode  CC)

GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.

Return the inverse of the specified condition, e.g.

turning COND_E to COND_NE.

Definition at line 2025 of file X86InstrInfo.cpp.

References COND_A, COND_AE, COND_B, COND_BE, COND_E, COND_E_AND_NP, COND_G, COND_GE, COND_L, COND_LE, COND_NE, COND_NE_OR_P, COND_NO, COND_NP, COND_NS, COND_O, COND_P, COND_S, and llvm_unreachable.

Referenced by checkBoolTestSetCCCombine(), llvm::X86InstrInfo::commuteInstructionImpl(), createPHIsForCMOVsInSinkBB(), EmitKORTEST(), foldXor1SetCC(), and packCmovGroup().

◆ getSETOpc()

unsigned llvm::X86::getSETOpc ( bool  HasMemoryOperand = false)

Return a setcc opcode based on whether it has a memory operand.

Return a setcc opcode based on whether it has memory operand.

Definition at line 2106 of file X86InstrInfo.cpp.

◆ getSwappedVPCMPImm()

unsigned llvm::X86::getSwappedVPCMPImm ( unsigned  Imm)

Get the VPCMP immediate if the opcodes are swapped.

Definition at line 2138 of file X86InstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::X86InstrInfo::commuteInstructionImpl().

◆ getSwappedVPCOMImm()

unsigned llvm::X86::getSwappedVPCOMImm ( unsigned  Imm)

Get the VPCOM immediate if the opcodes are swapped.

Definition at line 2156 of file X86InstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::X86InstrInfo::commuteInstructionImpl().

◆ getVPCMPImmForCond()

unsigned llvm::X86::getVPCMPImmForCond ( ISD::CondCode  CC)

◆ getX86ConditionCode()

std::pair< X86::CondCode, bool > llvm::X86::getX86ConditionCode ( CmpInst::Predicate  Predicate)

◆ isCalleePop()

bool llvm::X86::isCalleePop ( CallingConv::ID  CallingConv,
bool  is64Bit,
bool  IsVarArg,
bool  GuaranteeTCO 
)

Determines whether the callee is required to pop its own arguments.

Callee pop is necessary to support tail calls.

Definition at line 4569 of file X86ISelLowering.cpp.

References is64Bit(), shouldGuaranteeTCO(), llvm::CallingConv::X86_FastCall, llvm::CallingConv::X86_StdCall, llvm::CallingConv::X86_ThisCall, and llvm::CallingConv::X86_VectorCall.

Referenced by computeBytesPoppedByCalleeForSRet(), getMOVL(), isSortedByValueNo(), and MatchingStackOffset().

◆ isOffsetSuitableForCodeModel()

bool llvm::X86::isOffsetSuitableForCodeModel ( int64_t  Offset,
CodeModel::Model  M,
bool  hasSymbolicDisplacement = true 
)

Returns true of the given offset can be fit into displacement field of the instruction.

Definition at line 4537 of file X86ISelLowering.cpp.

References llvm::isInt< 32 >(), llvm::CodeModel::Kernel, and llvm::CodeModel::Small.

Referenced by isDispSafeForFrameIndex(), llvm::X86TargetLowering::isLegalAddressingMode(), and LowerEXTRACT_SUBVECTOR().

◆ isZeroNode()

bool llvm::X86::isZeroNode ( SDValue  Elt)

Returns true if Elt is a constant zero or floating point constant +0.0.

Returns true if Elt is a constant zero or a floating point constant +0.0.

Definition at line 5221 of file X86ISelLowering.cpp.

References llvm::isNullConstant(), and llvm::isNullFPConstant().

Referenced by combineADC(), combineAddOrSubToADCOrSBB(), computeZeroableShuffleElements(), EltsFromConsecutiveLoads(), getFauxShuffleMask(), getMaskNode(), InsertBitToMaskVector(), LowerBUILD_VECTORAsVariablePermute(), LowerBuildVectorv4x32(), LowerSCALAR_TO_VECTOR(), and setTargetShuffleZeroElements().