LLVM  9.0.0svn
Classes | Typedefs | Enumerations | Functions | Variables
llvm::mca Namespace Reference


class  Context
struct  CriticalDependency
 A critical data dependency descriptor. More...
class  CycleSegment
 A sequence of cycles. More...
class  DefaultResourceStrategy
 Default resource allocation strategy used by processor resource groups and processor resources with multiple units. More...
class  DefaultSchedulerStrategy
 Default instruction selection strategy used by class Scheduler. More...
class  DispatchStage
class  EntryStage
class  ExecuteStage
class  HardwareUnit
class  HWEventListener
class  HWInstructionDispatchedEvent
class  HWInstructionEvent
class  HWInstructionIssuedEvent
class  HWInstructionRetiredEvent
class  HWPressureEvent
class  HWStallEvent
class  InstrBuilder
 A builder class that knows how to construct Instruction objects. More...
struct  InstrDesc
 An instruction descriptor. More...
class  InstRef
 An InstRef contains both a SourceMgr index and Instruction pair. More...
class  Instruction
 An instruction propagated through the simulated instruction pipeline. More...
class  InstructionBase
 Base class for instructions consumed by the simulation pipeline. More...
class  InstructionError
class  InstructionTables
class  LSUnit
 Default Load/Store Unit (LS Unit) for simulated processors. More...
class  LSUnitBase
 Abstract base interface for LS (load/store) units in llvm-mca. More...
class  MemoryGroup
 A node of a memory dependency graph. More...
class  MicroOpQueueStage
 A stage that simulates a queue of instruction opcodes. More...
class  Pipeline
 A pipeline for a specific subtarget. More...
struct  PipelineOptions
 This is a convenience struct to hold the parameters necessary for creating the pre-built "default" out-of-order pipeline. More...
struct  ReadDescriptor
 A register read descriptor. More...
class  ReadState
 Tracks register operand latency in cycles. More...
class  RegisterFile
 Manages hardware register files, and tracks register definitions for register renaming purposes. More...
class  ResourceCycles
 This class represents the number of cycles per resource (fractions of cycles). More...
class  ResourceManager
 A resource manager for processor resource units and groups. More...
class  ResourceState
 A processor resource descriptor. More...
class  ResourceStrategy
 Resource allocation strategy used by hardware scheduler resources. More...
struct  ResourceUsage
 Helper used by class InstrDesc to describe how hardware resources are used. More...
struct  RetireControlUnit
 This class tracks which instructions are in-flight (i.e., dispatched but not retired) in the OoO backend. More...
class  RetireStage
class  Scheduler
 Class Scheduler is responsible for issuing instructions to pipeline resources. More...
class  SchedulerStrategy
class  SourceMgr
class  Stage
struct  WriteDescriptor
 A register write descriptor. More...
class  WriteRef
 A reference to a register write. More...
class  WriteState
 Tracks uses of a register definition (e.g. More...


typedef std::pair< uint64_t, uint64_t > ResourceRef
 A resource unit identifier. More...
typedef std::pair< unsigned, unsignedBufferUsageEntry
typedef std::pair< unsigned, const Instruction & > SourceRef


 Used to notify the internal state of a processor resource. More...


raw_ostreamoperator<< (raw_ostream &OS, const InstRef &IR)
void computeProcResourceMasks (const MCSchedModel &SM, MutableArrayRef< uint64_t > Masks)
 Populates vector Masks with processor resource masks. More...
unsigned getResourceStateIndex (uint64_t Mask)
double computeBlockRThroughput (const MCSchedModel &SM, unsigned DispatchWidth, unsigned NumMicroOps, ArrayRef< unsigned > ProcResourceUsage)
 Compute the reciprocal block throughput from a set of processor resource cycles. More...
static uint64_t selectImpl (uint64_t CandidateMask, uint64_t &NextInSequenceMask)
static std::unique_ptr< ResourceStrategygetStrategyFor (const ResourceState &RS)
static void initializeUsedResources (InstrDesc &ID, const MCSchedClassDesc &SCDesc, const MCSubtargetInfo &STI, ArrayRef< uint64_t > ProcResourceMasks)
static void computeMaxLatency (InstrDesc &ID, const MCInstrDesc &MCDesc, const MCSchedClassDesc &SCDesc, const MCSubtargetInfo &STI)
static Error verifyOperands (const MCInstrDesc &MCDesc, const MCInst &MCI)
HWStallEvent::GenericEventType toHWStallEventType (Scheduler::Status Status)
static void verifyInstructionEliminated (const InstRef &IR)


constexpr int UNKNOWN_CYCLES = -512

Typedef Documentation

◆ BufferUsageEntry

Definition at line 293 of file ResourceManager.h.

◆ ResourceRef

typedef std::pair<uint64_t, uint64_t> llvm::mca::ResourceRef

A resource unit identifier.

This is used to identify a specific processor resource unit using a pair of indices where the 'first' index is a processor resource mask, and the 'second' index is an index for a "sub-resource" (i.e. unit).

Definition at line 289 of file ResourceManager.h.

◆ SourceRef

Definition at line 23 of file SourceMgr.h.

Enumeration Type Documentation

◆ ResourceStateEvent

Used to notify the internal state of a processor resource.

A processor resource is available if it is not reserved, and there are available slots in the buffer. A processor resource is unavailable if it is either reserved, or the associated buffer is full. A processor resource with a buffer size of -1 is always available if it is not reserved.

Values of type ResourceStateEvent are returned by method ResourceState::isBufferAvailable(), which is used to query the internal state of a resource.

The naming convention for resource state events is:

  • Event names start with prefix RS_
  • Prefix RS_ is followed by a string describing the actual resource state.

Definition at line 42 of file ResourceManager.h.

Function Documentation

◆ computeBlockRThroughput()

double llvm::mca::computeBlockRThroughput ( const MCSchedModel SM,
unsigned  DispatchWidth,
unsigned  NumMicroOps,
ArrayRef< unsigned ProcResourceUsage 

Compute the reciprocal block throughput from a set of processor resource cycles.

The reciprocal block throughput is computed as the MAX between:

  • NumMicroOps / DispatchWidth
  • ProcResourceCycles / #ProcResourceUnits (for every consumed resource).

Definition at line 82 of file Support.cpp.

References E, llvm::MCSchedModel::getNumProcResourceKinds(), llvm::MCSchedModel::getProcResource(), I, llvm::max(), llvm::MCProcResourceDesc::NumUnits, and llvm::mca::ResourceCycles::ResourceCycles().

Referenced by getResourceStateIndex().

◆ computeMaxLatency()

static void llvm::mca::computeMaxLatency ( InstrDesc ID,
const MCInstrDesc MCDesc,
const MCSchedClassDesc SCDesc,
const MCSubtargetInfo STI 

◆ computeProcResourceMasks()

void llvm::mca::computeProcResourceMasks ( const MCSchedModel SM,
MutableArrayRef< uint64_t >  Masks 

Populates vector Masks with processor resource masks.

The number of bits set in a mask depends on the processor resource type. Each processor resource mask has at least one bit set. For groups, the number of bits set in the mask is equal to the cardinality of the group plus one. Excluding the most significant bit, the remaining bits in the mask identify processor resources that are part of the group.


ResourceA – Mask: 0b001 ResourceB – Mask: 0b010 ResourceAB – Mask: 0b100 U (ResourceA::Mask | ResourceB::Mask) == 0b111

ResourceAB is a processor resource group containing ResourceA and ResourceB. Each resource mask uniquely identifies a resource; both ResourceA and ResourceB only have one bit set. ResourceAB is a group; excluding the most significant bit in the mask, the remaining bits identify the composition of the group.

Resource masks are used by the ResourceManager to solve set membership problems with simple bit manipulation operations.

Definition at line 39 of file Support.cpp.

References assert(), llvm::dbgs(), E, llvm::format_decimal(), llvm::format_hex(), llvm::MCSchedModel::getNumProcResourceKinds(), llvm::MCSchedModel::getProcResource(), I, LLVM_DEBUG, llvm::MCProcResourceDesc::Name, llvm::MCProcResourceDesc::NumUnits, llvm::ArrayRef< T >::size(), and llvm::MCProcResourceDesc::SubUnitsIdxBegin.

Referenced by llvm::mca::ResourceCycles::getDenominator(), llvm::mca::InstrBuilder::InstrBuilder(), llvm::mca::InstructionTables::InstructionTables(), and llvm::mca::ResourceManager::ResourceManager().

◆ getResourceStateIndex()

unsigned llvm::mca::getResourceStateIndex ( uint64_t  Mask)

◆ getStrategyFor()

static std::unique_ptr<ResourceStrategy> llvm::mca::getStrategyFor ( const ResourceState RS)

◆ initializeUsedResources()

static void llvm::mca::initializeUsedResources ( InstrDesc ID,
const MCSchedClassDesc SCDesc,
const MCSubtargetInfo STI,
ArrayRef< uint64_t >  ProcResourceMasks 

◆ operator<<()

raw_ostream& llvm::mca::operator<< ( raw_ostream OS,
const InstRef IR 

Definition at line 574 of file Instruction.h.

References llvm::mca::InstRef::print().

◆ selectImpl()

static uint64_t llvm::mca::selectImpl ( uint64_t  CandidateMask,
uint64_t &  NextInSequenceMask 

◆ toHWStallEventType()

HWStallEvent::GenericEventType llvm::mca::toHWStallEventType ( Scheduler::Status  Status)

◆ verifyInstructionEliminated()

static void llvm::mca::verifyInstructionEliminated ( const InstRef IR)

◆ verifyOperands()

static Error llvm::mca::verifyOperands ( const MCInstrDesc MCDesc,
const MCInst MCI 

Definition at line 224 of file InstrBuilder.cpp.

References assert(), llvm::mca::InstrDesc::Buffers, computeMaxLatency(), llvm::MCWriteLatencyEntry::Cycles, llvm::dbgs(), E, llvm::SmallVectorBase::empty(), llvm::MCInstrInfo::get(), llvm::MCInstrDesc::getImplicitDefs(), llvm::MCInstrDesc::getImplicitUses(), llvm::MCInstrInfo::getName(), llvm::MCRegisterInfo::getName(), llvm::MCInstrDesc::getNumDefs(), llvm::MCInstrDesc::getNumImplicitDefs(), llvm::MCInstrDesc::getNumImplicitUses(), llvm::MCInst::getNumOperands(), llvm::MCInstrDesc::getNumOperands(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCSchedModel::getProcessorID(), llvm::MCInstrDesc::getSchedClass(), llvm::MCSchedModel::getSchedClassDesc(), llvm::MCSubtargetInfo::getSchedModel(), llvm::MCSubtargetInfo::getWriteLatencyEntry(), llvm::MCSchedModel::hasInstrSchedModel(), llvm::MCInstrDesc::hasOptionalDef(), llvm::MCInstrDesc::hasUnmodeledSideEffects(), I, initializeUsedResources(), llvm::MCSchedClassDesc::InvalidNumMicroOps, llvm::MCInstrDesc::isCall(), llvm::mca::WriteDescriptor::IsOptionalDef, llvm::MCOperand::isReg(), llvm::MCInstrDesc::isReturn(), llvm::MCSchedClassDesc::isVariant(), llvm::mca::WriteDescriptor::Latency, LLVM_DEBUG, llvm::mca::InstrDesc::MaxLatency, llvm::mca::InstrDesc::MayLoad, llvm::MCInstrDesc::mayLoad(), llvm::mca::InstrDesc::MayStore, llvm::MCInstrDesc::mayStore(), llvm::WithColor::note(), llvm::mca::InstrDesc::NumMicroOps, llvm::MCSchedClassDesc::NumWriteLatencyEntries, llvm::mca::WriteDescriptor::OpIndex, llvm::mca::ReadDescriptor::OpIndex, llvm::mca::InstrDesc::Reads, llvm::mca::WriteDescriptor::RegisterID, llvm::mca::ReadDescriptor::RegisterID, llvm::MCSubtargetInfo::resolveVariantSchedClass(), llvm::mca::InstrDesc::Resources, llvm::mca::ReadDescriptor::SchedClassID, llvm::mca::WriteDescriptor::SClassOrWriteResourceID, llvm::mca::ReadDescriptor::UseIndex, llvm::WithColor::warning(), llvm::MCWriteLatencyEntry::WriteResourceID, and llvm::mca::InstrDesc::Writes.

Variable Documentation


constexpr int llvm::mca::UNKNOWN_CYCLES = -512