Bug Summary

File:lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Warning:line 11348, column 32
1st function call argument is an uninitialized value

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ARMAsmParser.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~svn373517/build-llvm/lib/Target/ARM/AsmParser -I /build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser -I /build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM -I /build/llvm-toolchain-snapshot-10~svn373517/build-llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-10~svn373517/build-llvm/include -I /build/llvm-toolchain-snapshot-10~svn373517/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~svn373517/build-llvm/lib/Target/ARM/AsmParser -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~svn373517=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2019-10-02-234743-9763-1 -x c++ /build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
1//===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "ARMFeatures.h"
10#include "ARMBaseInstrInfo.h"
11#include "Utils/ARMBaseInfo.h"
12#include "MCTargetDesc/ARMAddressingModes.h"
13#include "MCTargetDesc/ARMBaseInfo.h"
14#include "MCTargetDesc/ARMInstPrinter.h"
15#include "MCTargetDesc/ARMMCExpr.h"
16#include "MCTargetDesc/ARMMCTargetDesc.h"
17#include "TargetInfo/ARMTargetInfo.h"
18#include "llvm/ADT/APFloat.h"
19#include "llvm/ADT/APInt.h"
20#include "llvm/ADT/None.h"
21#include "llvm/ADT/STLExtras.h"
22#include "llvm/ADT/SmallSet.h"
23#include "llvm/ADT/SmallVector.h"
24#include "llvm/ADT/StringMap.h"
25#include "llvm/ADT/StringRef.h"
26#include "llvm/ADT/StringSwitch.h"
27#include "llvm/ADT/Triple.h"
28#include "llvm/ADT/Twine.h"
29#include "llvm/MC/MCContext.h"
30#include "llvm/MC/MCExpr.h"
31#include "llvm/MC/MCInst.h"
32#include "llvm/MC/MCInstrDesc.h"
33#include "llvm/MC/MCInstrInfo.h"
34#include "llvm/MC/MCObjectFileInfo.h"
35#include "llvm/MC/MCParser/MCAsmLexer.h"
36#include "llvm/MC/MCParser/MCAsmParser.h"
37#include "llvm/MC/MCParser/MCAsmParserExtension.h"
38#include "llvm/MC/MCParser/MCAsmParserUtils.h"
39#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
40#include "llvm/MC/MCParser/MCTargetAsmParser.h"
41#include "llvm/MC/MCRegisterInfo.h"
42#include "llvm/MC/MCSection.h"
43#include "llvm/MC/MCStreamer.h"
44#include "llvm/MC/MCSubtargetInfo.h"
45#include "llvm/MC/MCSymbol.h"
46#include "llvm/MC/SubtargetFeature.h"
47#include "llvm/Support/ARMBuildAttributes.h"
48#include "llvm/Support/ARMEHABI.h"
49#include "llvm/Support/Casting.h"
50#include "llvm/Support/CommandLine.h"
51#include "llvm/Support/Compiler.h"
52#include "llvm/Support/ErrorHandling.h"
53#include "llvm/Support/MathExtras.h"
54#include "llvm/Support/SMLoc.h"
55#include "llvm/Support/TargetParser.h"
56#include "llvm/Support/TargetRegistry.h"
57#include "llvm/Support/raw_ostream.h"
58#include <algorithm>
59#include <cassert>
60#include <cstddef>
61#include <cstdint>
62#include <iterator>
63#include <limits>
64#include <memory>
65#include <string>
66#include <utility>
67#include <vector>
68
69#define DEBUG_TYPE"asm-parser" "asm-parser"
70
71using namespace llvm;
72
73namespace llvm {
74extern const MCInstrDesc ARMInsts[];
75} // end namespace llvm
76
77namespace {
78
79enum class ImplicitItModeTy { Always, Never, ARMOnly, ThumbOnly };
80
81static cl::opt<ImplicitItModeTy> ImplicitItMode(
82 "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly),
83 cl::desc("Allow conditional instructions outdside of an IT block"),
84 cl::values(clEnumValN(ImplicitItModeTy::Always, "always",llvm::cl::OptionEnumValue { "always", int(ImplicitItModeTy::Always
), "Accept in both ISAs, emit implicit ITs in Thumb" }
85 "Accept in both ISAs, emit implicit ITs in Thumb")llvm::cl::OptionEnumValue { "always", int(ImplicitItModeTy::Always
), "Accept in both ISAs, emit implicit ITs in Thumb" }
,
86 clEnumValN(ImplicitItModeTy::Never, "never",llvm::cl::OptionEnumValue { "never", int(ImplicitItModeTy::Never
), "Warn in ARM, reject in Thumb" }
87 "Warn in ARM, reject in Thumb")llvm::cl::OptionEnumValue { "never", int(ImplicitItModeTy::Never
), "Warn in ARM, reject in Thumb" }
,
88 clEnumValN(ImplicitItModeTy::ARMOnly, "arm",llvm::cl::OptionEnumValue { "arm", int(ImplicitItModeTy::ARMOnly
), "Accept in ARM, reject in Thumb" }
89 "Accept in ARM, reject in Thumb")llvm::cl::OptionEnumValue { "arm", int(ImplicitItModeTy::ARMOnly
), "Accept in ARM, reject in Thumb" }
,
90 clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb",llvm::cl::OptionEnumValue { "thumb", int(ImplicitItModeTy::ThumbOnly
), "Warn in ARM, emit implicit ITs in Thumb" }
91 "Warn in ARM, emit implicit ITs in Thumb")llvm::cl::OptionEnumValue { "thumb", int(ImplicitItModeTy::ThumbOnly
), "Warn in ARM, emit implicit ITs in Thumb" }
));
92
93static cl::opt<bool> AddBuildAttributes("arm-add-build-attributes",
94 cl::init(false));
95
96enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
97
98static inline unsigned extractITMaskBit(unsigned Mask, unsigned Position) {
99 // Position==0 means we're not in an IT block at all. Position==1
100 // means we want the first state bit, which is always 0 (Then).
101 // Position==2 means we want the second state bit, stored at bit 3
102 // of Mask, and so on downwards. So (5 - Position) will shift the
103 // right bit down to bit 0, including the always-0 bit at bit 4 for
104 // the mandatory initial Then.
105 return (Mask >> (5 - Position) & 1);
106}
107
108class UnwindContext {
109 using Locs = SmallVector<SMLoc, 4>;
110
111 MCAsmParser &Parser;
112 Locs FnStartLocs;
113 Locs CantUnwindLocs;
114 Locs PersonalityLocs;
115 Locs PersonalityIndexLocs;
116 Locs HandlerDataLocs;
117 int FPReg;
118
119public:
120 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
121
122 bool hasFnStart() const { return !FnStartLocs.empty(); }
123 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
124 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
125
126 bool hasPersonality() const {
127 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
128 }
129
130 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
131 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
132 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
133 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
134 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
135
136 void saveFPReg(int Reg) { FPReg = Reg; }
137 int getFPReg() const { return FPReg; }
138
139 void emitFnStartLocNotes() const {
140 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
141 FI != FE; ++FI)
142 Parser.Note(*FI, ".fnstart was specified here");
143 }
144
145 void emitCantUnwindLocNotes() const {
146 for (Locs::const_iterator UI = CantUnwindLocs.begin(),
147 UE = CantUnwindLocs.end(); UI != UE; ++UI)
148 Parser.Note(*UI, ".cantunwind was specified here");
149 }
150
151 void emitHandlerDataLocNotes() const {
152 for (Locs::const_iterator HI = HandlerDataLocs.begin(),
153 HE = HandlerDataLocs.end(); HI != HE; ++HI)
154 Parser.Note(*HI, ".handlerdata was specified here");
155 }
156
157 void emitPersonalityLocNotes() const {
158 for (Locs::const_iterator PI = PersonalityLocs.begin(),
159 PE = PersonalityLocs.end(),
160 PII = PersonalityIndexLocs.begin(),
161 PIE = PersonalityIndexLocs.end();
162 PI != PE || PII != PIE;) {
163 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
164 Parser.Note(*PI++, ".personality was specified here");
165 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
166 Parser.Note(*PII++, ".personalityindex was specified here");
167 else
168 llvm_unreachable(".personality and .personalityindex cannot be "::llvm::llvm_unreachable_internal(".personality and .personalityindex cannot be "
"at the same location", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 169)
169 "at the same location")::llvm::llvm_unreachable_internal(".personality and .personalityindex cannot be "
"at the same location", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 169)
;
170 }
171 }
172
173 void reset() {
174 FnStartLocs = Locs();
175 CantUnwindLocs = Locs();
176 PersonalityLocs = Locs();
177 HandlerDataLocs = Locs();
178 PersonalityIndexLocs = Locs();
179 FPReg = ARM::SP;
180 }
181};
182
183
184class ARMAsmParser : public MCTargetAsmParser {
185 const MCRegisterInfo *MRI;
186 UnwindContext UC;
187
188 ARMTargetStreamer &getTargetStreamer() {
189 assert(getParser().getStreamer().getTargetStreamer() &&((getParser().getStreamer().getTargetStreamer() && "do not have a target streamer"
) ? static_cast<void> (0) : __assert_fail ("getParser().getStreamer().getTargetStreamer() && \"do not have a target streamer\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 190, __PRETTY_FUNCTION__))
190 "do not have a target streamer")((getParser().getStreamer().getTargetStreamer() && "do not have a target streamer"
) ? static_cast<void> (0) : __assert_fail ("getParser().getStreamer().getTargetStreamer() && \"do not have a target streamer\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 190, __PRETTY_FUNCTION__))
;
191 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
192 return static_cast<ARMTargetStreamer &>(TS);
193 }
194
195 // Map of register aliases registers via the .req directive.
196 StringMap<unsigned> RegisterReqs;
197
198 bool NextSymbolIsThumb;
199
200 bool useImplicitITThumb() const {
201 return ImplicitItMode == ImplicitItModeTy::Always ||
202 ImplicitItMode == ImplicitItModeTy::ThumbOnly;
203 }
204
205 bool useImplicitITARM() const {
206 return ImplicitItMode == ImplicitItModeTy::Always ||
207 ImplicitItMode == ImplicitItModeTy::ARMOnly;
208 }
209
210 struct {
211 ARMCC::CondCodes Cond; // Condition for IT block.
212 unsigned Mask:4; // Condition mask for instructions.
213 // Starting at first 1 (from lsb).
214 // '1' condition as indicated in IT.
215 // '0' inverse of condition (else).
216 // Count of instructions in IT block is
217 // 4 - trailingzeroes(mask)
218 // Note that this does not have the same encoding
219 // as in the IT instruction, which also depends
220 // on the low bit of the condition code.
221
222 unsigned CurPosition; // Current position in parsing of IT
223 // block. In range [0,4], with 0 being the IT
224 // instruction itself. Initialized according to
225 // count of instructions in block. ~0U if no
226 // active IT block.
227
228 bool IsExplicit; // true - The IT instruction was present in the
229 // input, we should not modify it.
230 // false - The IT instruction was added
231 // implicitly, we can extend it if that
232 // would be legal.
233 } ITState;
234
235 SmallVector<MCInst, 4> PendingConditionalInsts;
236
237 void flushPendingInstructions(MCStreamer &Out) override {
238 if (!inImplicitITBlock()) {
239 assert(PendingConditionalInsts.size() == 0)((PendingConditionalInsts.size() == 0) ? static_cast<void>
(0) : __assert_fail ("PendingConditionalInsts.size() == 0", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 239, __PRETTY_FUNCTION__))
;
240 return;
241 }
242
243 // Emit the IT instruction
244 MCInst ITInst;
245 ITInst.setOpcode(ARM::t2IT);
246 ITInst.addOperand(MCOperand::createImm(ITState.Cond));
247 ITInst.addOperand(MCOperand::createImm(ITState.Mask));
248 Out.EmitInstruction(ITInst, getSTI());
249
250 // Emit the conditonal instructions
251 assert(PendingConditionalInsts.size() <= 4)((PendingConditionalInsts.size() <= 4) ? static_cast<void
> (0) : __assert_fail ("PendingConditionalInsts.size() <= 4"
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 251, __PRETTY_FUNCTION__))
;
252 for (const MCInst &Inst : PendingConditionalInsts) {
253 Out.EmitInstruction(Inst, getSTI());
254 }
255 PendingConditionalInsts.clear();
256
257 // Clear the IT state
258 ITState.Mask = 0;
259 ITState.CurPosition = ~0U;
260 }
261
262 bool inITBlock() { return ITState.CurPosition != ~0U; }
263 bool inExplicitITBlock() { return inITBlock() && ITState.IsExplicit; }
264 bool inImplicitITBlock() { return inITBlock() && !ITState.IsExplicit; }
265
266 bool lastInITBlock() {
267 return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
268 }
269
270 void forwardITPosition() {
271 if (!inITBlock()) return;
272 // Move to the next instruction in the IT block, if there is one. If not,
273 // mark the block as done, except for implicit IT blocks, which we leave
274 // open until we find an instruction that can't be added to it.
275 unsigned TZ = countTrailingZeros(ITState.Mask);
276 if (++ITState.CurPosition == 5 - TZ && ITState.IsExplicit)
277 ITState.CurPosition = ~0U; // Done with the IT block after this.
278 }
279
280 // Rewind the state of the current IT block, removing the last slot from it.
281 void rewindImplicitITPosition() {
282 assert(inImplicitITBlock())((inImplicitITBlock()) ? static_cast<void> (0) : __assert_fail
("inImplicitITBlock()", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 282, __PRETTY_FUNCTION__))
;
283 assert(ITState.CurPosition > 1)((ITState.CurPosition > 1) ? static_cast<void> (0) :
__assert_fail ("ITState.CurPosition > 1", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 283, __PRETTY_FUNCTION__))
;
284 ITState.CurPosition--;
285 unsigned TZ = countTrailingZeros(ITState.Mask);
286 unsigned NewMask = 0;
287 NewMask |= ITState.Mask & (0xC << TZ);
288 NewMask |= 0x2 << TZ;
289 ITState.Mask = NewMask;
290 }
291
292 // Rewind the state of the current IT block, removing the last slot from it.
293 // If we were at the first slot, this closes the IT block.
294 void discardImplicitITBlock() {
295 assert(inImplicitITBlock())((inImplicitITBlock()) ? static_cast<void> (0) : __assert_fail
("inImplicitITBlock()", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 295, __PRETTY_FUNCTION__))
;
296 assert(ITState.CurPosition == 1)((ITState.CurPosition == 1) ? static_cast<void> (0) : __assert_fail
("ITState.CurPosition == 1", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 296, __PRETTY_FUNCTION__))
;
297 ITState.CurPosition = ~0U;
298 }
299
300 // Return the low-subreg of a given Q register.
301 unsigned getDRegFromQReg(unsigned QReg) const {
302 return MRI->getSubReg(QReg, ARM::dsub_0);
303 }
304
305 // Get the condition code corresponding to the current IT block slot.
306 ARMCC::CondCodes currentITCond() {
307 unsigned MaskBit = extractITMaskBit(ITState.Mask, ITState.CurPosition);
308 return MaskBit ? ARMCC::getOppositeCondition(ITState.Cond) : ITState.Cond;
309 }
310
311 // Invert the condition of the current IT block slot without changing any
312 // other slots in the same block.
313 void invertCurrentITCondition() {
314 if (ITState.CurPosition == 1) {
315 ITState.Cond = ARMCC::getOppositeCondition(ITState.Cond);
316 } else {
317 ITState.Mask ^= 1 << (5 - ITState.CurPosition);
318 }
319 }
320
321 // Returns true if the current IT block is full (all 4 slots used).
322 bool isITBlockFull() {
323 return inITBlock() && (ITState.Mask & 1);
324 }
325
326 // Extend the current implicit IT block to have one more slot with the given
327 // condition code.
328 void extendImplicitITBlock(ARMCC::CondCodes Cond) {
329 assert(inImplicitITBlock())((inImplicitITBlock()) ? static_cast<void> (0) : __assert_fail
("inImplicitITBlock()", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 329, __PRETTY_FUNCTION__))
;
330 assert(!isITBlockFull())((!isITBlockFull()) ? static_cast<void> (0) : __assert_fail
("!isITBlockFull()", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 330, __PRETTY_FUNCTION__))
;
331 assert(Cond == ITState.Cond ||((Cond == ITState.Cond || Cond == ARMCC::getOppositeCondition
(ITState.Cond)) ? static_cast<void> (0) : __assert_fail
("Cond == ITState.Cond || Cond == ARMCC::getOppositeCondition(ITState.Cond)"
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 332, __PRETTY_FUNCTION__))
332 Cond == ARMCC::getOppositeCondition(ITState.Cond))((Cond == ITState.Cond || Cond == ARMCC::getOppositeCondition
(ITState.Cond)) ? static_cast<void> (0) : __assert_fail
("Cond == ITState.Cond || Cond == ARMCC::getOppositeCondition(ITState.Cond)"
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 332, __PRETTY_FUNCTION__))
;
333 unsigned TZ = countTrailingZeros(ITState.Mask);
334 unsigned NewMask = 0;
335 // Keep any existing condition bits.
336 NewMask |= ITState.Mask & (0xE << TZ);
337 // Insert the new condition bit.
338 NewMask |= (Cond != ITState.Cond) << TZ;
339 // Move the trailing 1 down one bit.
340 NewMask |= 1 << (TZ - 1);
341 ITState.Mask = NewMask;
342 }
343
344 // Create a new implicit IT block with a dummy condition code.
345 void startImplicitITBlock() {
346 assert(!inITBlock())((!inITBlock()) ? static_cast<void> (0) : __assert_fail
("!inITBlock()", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 346, __PRETTY_FUNCTION__))
;
347 ITState.Cond = ARMCC::AL;
348 ITState.Mask = 8;
349 ITState.CurPosition = 1;
350 ITState.IsExplicit = false;
351 }
352
353 // Create a new explicit IT block with the given condition and mask.
354 // The mask should be in the format used in ARMOperand and
355 // MCOperand, with a 1 implying 'e', regardless of the low bit of
356 // the condition.
357 void startExplicitITBlock(ARMCC::CondCodes Cond, unsigned Mask) {
358 assert(!inITBlock())((!inITBlock()) ? static_cast<void> (0) : __assert_fail
("!inITBlock()", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 358, __PRETTY_FUNCTION__))
;
359 ITState.Cond = Cond;
360 ITState.Mask = Mask;
361 ITState.CurPosition = 0;
362 ITState.IsExplicit = true;
363 }
364
365 struct {
366 unsigned Mask : 4;
367 unsigned CurPosition;
368 } VPTState;
369 bool inVPTBlock() { return VPTState.CurPosition != ~0U; }
370 void forwardVPTPosition() {
371 if (!inVPTBlock()) return;
372 unsigned TZ = countTrailingZeros(VPTState.Mask);
373 if (++VPTState.CurPosition == 5 - TZ)
374 VPTState.CurPosition = ~0U;
375 }
376
377 void Note(SMLoc L, const Twine &Msg, SMRange Range = None) {
378 return getParser().Note(L, Msg, Range);
379 }
380
381 bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) {
382 return getParser().Warning(L, Msg, Range);
383 }
384
385 bool Error(SMLoc L, const Twine &Msg, SMRange Range = None) {
386 return getParser().Error(L, Msg, Range);
387 }
388
389 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
390 unsigned ListNo, bool IsARPop = false);
391 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
392 unsigned ListNo);
393
394 int tryParseRegister();
395 bool tryParseRegisterWithWriteBack(OperandVector &);
396 int tryParseShiftRegister(OperandVector &);
397 bool parseRegisterList(OperandVector &, bool EnforceOrder = true);
398 bool parseMemory(OperandVector &);
399 bool parseOperand(OperandVector &, StringRef Mnemonic);
400 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
401 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
402 unsigned &ShiftAmount);
403 bool parseLiteralValues(unsigned Size, SMLoc L);
404 bool parseDirectiveThumb(SMLoc L);
405 bool parseDirectiveARM(SMLoc L);
406 bool parseDirectiveThumbFunc(SMLoc L);
407 bool parseDirectiveCode(SMLoc L);
408 bool parseDirectiveSyntax(SMLoc L);
409 bool parseDirectiveReq(StringRef Name, SMLoc L);
410 bool parseDirectiveUnreq(SMLoc L);
411 bool parseDirectiveArch(SMLoc L);
412 bool parseDirectiveEabiAttr(SMLoc L);
413 bool parseDirectiveCPU(SMLoc L);
414 bool parseDirectiveFPU(SMLoc L);
415 bool parseDirectiveFnStart(SMLoc L);
416 bool parseDirectiveFnEnd(SMLoc L);
417 bool parseDirectiveCantUnwind(SMLoc L);
418 bool parseDirectivePersonality(SMLoc L);
419 bool parseDirectiveHandlerData(SMLoc L);
420 bool parseDirectiveSetFP(SMLoc L);
421 bool parseDirectivePad(SMLoc L);
422 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
423 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
424 bool parseDirectiveLtorg(SMLoc L);
425 bool parseDirectiveEven(SMLoc L);
426 bool parseDirectivePersonalityIndex(SMLoc L);
427 bool parseDirectiveUnwindRaw(SMLoc L);
428 bool parseDirectiveTLSDescSeq(SMLoc L);
429 bool parseDirectiveMovSP(SMLoc L);
430 bool parseDirectiveObjectArch(SMLoc L);
431 bool parseDirectiveArchExtension(SMLoc L);
432 bool parseDirectiveAlign(SMLoc L);
433 bool parseDirectiveThumbSet(SMLoc L);
434
435 bool isMnemonicVPTPredicable(StringRef Mnemonic, StringRef ExtraToken);
436 StringRef splitMnemonic(StringRef Mnemonic, StringRef ExtraToken,
437 unsigned &PredicationCode,
438 unsigned &VPTPredicationCode, bool &CarrySetting,
439 unsigned &ProcessorIMod, StringRef &ITMask);
440 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef ExtraToken,
441 StringRef FullInst, bool &CanAcceptCarrySet,
442 bool &CanAcceptPredicationCode,
443 bool &CanAcceptVPTPredicationCode);
444
445 void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting,
446 OperandVector &Operands);
447 bool isThumb() const {
448 // FIXME: Can tablegen auto-generate this?
449 return getSTI().getFeatureBits()[ARM::ModeThumb];
450 }
451
452 bool isThumbOne() const {
453 return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2];
454 }
455
456 bool isThumbTwo() const {
457 return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2];
458 }
459
460 bool hasThumb() const {
461 return getSTI().getFeatureBits()[ARM::HasV4TOps];
462 }
463
464 bool hasThumb2() const {
465 return getSTI().getFeatureBits()[ARM::FeatureThumb2];
466 }
467
468 bool hasV6Ops() const {
469 return getSTI().getFeatureBits()[ARM::HasV6Ops];
470 }
471
472 bool hasV6T2Ops() const {
473 return getSTI().getFeatureBits()[ARM::HasV6T2Ops];
474 }
475
476 bool hasV6MOps() const {
477 return getSTI().getFeatureBits()[ARM::HasV6MOps];
478 }
479
480 bool hasV7Ops() const {
481 return getSTI().getFeatureBits()[ARM::HasV7Ops];
482 }
483
484 bool hasV8Ops() const {
485 return getSTI().getFeatureBits()[ARM::HasV8Ops];
486 }
487
488 bool hasV8MBaseline() const {
489 return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps];
490 }
491
492 bool hasV8MMainline() const {
493 return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];
494 }
495 bool hasV8_1MMainline() const {
496 return getSTI().getFeatureBits()[ARM::HasV8_1MMainlineOps];
497 }
498 bool hasMVE() const {
499 return getSTI().getFeatureBits()[ARM::HasMVEIntegerOps];
500 }
501 bool hasMVEFloat() const {
502 return getSTI().getFeatureBits()[ARM::HasMVEFloatOps];
503 }
504 bool has8MSecExt() const {
505 return getSTI().getFeatureBits()[ARM::Feature8MSecExt];
506 }
507
508 bool hasARM() const {
509 return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
510 }
511
512 bool hasDSP() const {
513 return getSTI().getFeatureBits()[ARM::FeatureDSP];
514 }
515
516 bool hasD32() const {
517 return getSTI().getFeatureBits()[ARM::FeatureD32];
518 }
519
520 bool hasV8_1aOps() const {
521 return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
522 }
523
524 bool hasRAS() const {
525 return getSTI().getFeatureBits()[ARM::FeatureRAS];
526 }
527
528 void SwitchMode() {
529 MCSubtargetInfo &STI = copySTI();
530 auto FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
531 setAvailableFeatures(FB);
532 }
533
534 void FixModeAfterArchChange(bool WasThumb, SMLoc Loc);
535
536 bool isMClass() const {
537 return getSTI().getFeatureBits()[ARM::FeatureMClass];
538 }
539
540 /// @name Auto-generated Match Functions
541 /// {
542
543#define GET_ASSEMBLER_HEADER
544#include "ARMGenAsmMatcher.inc"
545
546 /// }
547
548 OperandMatchResultTy parseITCondCode(OperandVector &);
549 OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
550 OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
551 OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
552 OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
553 OperandMatchResultTy parseTraceSyncBarrierOptOperand(OperandVector &);
554 OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
555 OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
556 OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
557 OperandMatchResultTy parseBankedRegOperand(OperandVector &);
558 OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
559 int High);
560 OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
561 return parsePKHImm(O, "lsl", 0, 31);
562 }
563 OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
564 return parsePKHImm(O, "asr", 1, 32);
565 }
566 OperandMatchResultTy parseSetEndImm(OperandVector &);
567 OperandMatchResultTy parseShifterImm(OperandVector &);
568 OperandMatchResultTy parseRotImm(OperandVector &);
569 OperandMatchResultTy parseModImm(OperandVector &);
570 OperandMatchResultTy parseBitfield(OperandVector &);
571 OperandMatchResultTy parsePostIdxReg(OperandVector &);
572 OperandMatchResultTy parseAM3Offset(OperandVector &);
573 OperandMatchResultTy parseFPImm(OperandVector &);
574 OperandMatchResultTy parseVectorList(OperandVector &);
575 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
576 SMLoc &EndLoc);
577
578 // Asm Match Converter Methods
579 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
580 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
581 void cvtMVEVMOVQtoDReg(MCInst &Inst, const OperandVector &);
582
583 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
584 bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
585 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
586 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
587 bool shouldOmitVectorPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
588 bool isITBlockTerminator(MCInst &Inst) const;
589 void fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands);
590 bool validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands,
591 bool Load, bool ARMMode, bool Writeback);
592
593public:
594 enum ARMMatchResultTy {
595 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
596 Match_RequiresNotITBlock,
597 Match_RequiresV6,
598 Match_RequiresThumb2,
599 Match_RequiresV8,
600 Match_RequiresFlagSetting,
601#define GET_OPERAND_DIAGNOSTIC_TYPES
602#include "ARMGenAsmMatcher.inc"
603
604 };
605
606 ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
607 const MCInstrInfo &MII, const MCTargetOptions &Options)
608 : MCTargetAsmParser(Options, STI, MII), UC(Parser) {
609 MCAsmParserExtension::Initialize(Parser);
610
611 // Cache the MCRegisterInfo.
612 MRI = getContext().getRegisterInfo();
613
614 // Initialize the set of available features.
615 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
616
617 // Add build attributes based on the selected target.
618 if (AddBuildAttributes)
619 getTargetStreamer().emitTargetAttributes(STI);
620
621 // Not in an ITBlock to start with.
622 ITState.CurPosition = ~0U;
623
624 VPTState.CurPosition = ~0U;
625
626 NextSymbolIsThumb = false;
627 }
628
629 // Implementation of the MCTargetAsmParser interface:
630 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
631 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
632 SMLoc NameLoc, OperandVector &Operands) override;
633 bool ParseDirective(AsmToken DirectiveID) override;
634
635 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
636 unsigned Kind) override;
637 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
638
639 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
640 OperandVector &Operands, MCStreamer &Out,
641 uint64_t &ErrorInfo,
642 bool MatchingInlineAsm) override;
643 unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
644 SmallVectorImpl<NearMissInfo> &NearMisses,
645 bool MatchingInlineAsm, bool &EmitInITBlock,
646 MCStreamer &Out);
647
648 struct NearMissMessage {
649 SMLoc Loc;
650 SmallString<128> Message;
651 };
652
653 const char *getCustomOperandDiag(ARMMatchResultTy MatchError);
654
655 void FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
656 SmallVectorImpl<NearMissMessage> &NearMissesOut,
657 SMLoc IDLoc, OperandVector &Operands);
658 void ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses, SMLoc IDLoc,
659 OperandVector &Operands);
660
661 void doBeforeLabelEmit(MCSymbol *Symbol) override;
662
663 void onLabelParsed(MCSymbol *Symbol) override;
664};
665
666/// ARMOperand - Instances of this class represent a parsed ARM machine
667/// operand.
668class ARMOperand : public MCParsedAsmOperand {
669 enum KindTy {
670 k_CondCode,
671 k_VPTPred,
672 k_CCOut,
673 k_ITCondMask,
674 k_CoprocNum,
675 k_CoprocReg,
676 k_CoprocOption,
677 k_Immediate,
678 k_MemBarrierOpt,
679 k_InstSyncBarrierOpt,
680 k_TraceSyncBarrierOpt,
681 k_Memory,
682 k_PostIndexRegister,
683 k_MSRMask,
684 k_BankedReg,
685 k_ProcIFlags,
686 k_VectorIndex,
687 k_Register,
688 k_RegisterList,
689 k_RegisterListWithAPSR,
690 k_DPRRegisterList,
691 k_SPRRegisterList,
692 k_FPSRegisterListWithVPR,
693 k_FPDRegisterListWithVPR,
694 k_VectorList,
695 k_VectorListAllLanes,
696 k_VectorListIndexed,
697 k_ShiftedRegister,
698 k_ShiftedImmediate,
699 k_ShifterImmediate,
700 k_RotateImmediate,
701 k_ModifiedImmediate,
702 k_ConstantPoolImmediate,
703 k_BitfieldDescriptor,
704 k_Token,
705 } Kind;
706
707 SMLoc StartLoc, EndLoc, AlignmentLoc;
708 SmallVector<unsigned, 8> Registers;
709
710 struct CCOp {
711 ARMCC::CondCodes Val;
712 };
713
714 struct VCCOp {
715 ARMVCC::VPTCodes Val;
716 };
717
718 struct CopOp {
719 unsigned Val;
720 };
721
722 struct CoprocOptionOp {
723 unsigned Val;
724 };
725
726 struct ITMaskOp {
727 unsigned Mask:4;
728 };
729
730 struct MBOptOp {
731 ARM_MB::MemBOpt Val;
732 };
733
734 struct ISBOptOp {
735 ARM_ISB::InstSyncBOpt Val;
736 };
737
738 struct TSBOptOp {
739 ARM_TSB::TraceSyncBOpt Val;
740 };
741
742 struct IFlagsOp {
743 ARM_PROC::IFlags Val;
744 };
745
746 struct MMaskOp {
747 unsigned Val;
748 };
749
750 struct BankedRegOp {
751 unsigned Val;
752 };
753
754 struct TokOp {
755 const char *Data;
756 unsigned Length;
757 };
758
759 struct RegOp {
760 unsigned RegNum;
761 };
762
763 // A vector register list is a sequential list of 1 to 4 registers.
764 struct VectorListOp {
765 unsigned RegNum;
766 unsigned Count;
767 unsigned LaneIndex;
768 bool isDoubleSpaced;
769 };
770
771 struct VectorIndexOp {
772 unsigned Val;
773 };
774
775 struct ImmOp {
776 const MCExpr *Val;
777 };
778
779 /// Combined record for all forms of ARM address expressions.
780 struct MemoryOp {
781 unsigned BaseRegNum;
782 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
783 // was specified.
784 const MCConstantExpr *OffsetImm; // Offset immediate value
785 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
786 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
787 unsigned ShiftImm; // shift for OffsetReg.
788 unsigned Alignment; // 0 = no alignment specified
789 // n = alignment in bytes (2, 4, 8, 16, or 32)
790 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
791 };
792
793 struct PostIdxRegOp {
794 unsigned RegNum;
795 bool isAdd;
796 ARM_AM::ShiftOpc ShiftTy;
797 unsigned ShiftImm;
798 };
799
800 struct ShifterImmOp {
801 bool isASR;
802 unsigned Imm;
803 };
804
805 struct RegShiftedRegOp {
806 ARM_AM::ShiftOpc ShiftTy;
807 unsigned SrcReg;
808 unsigned ShiftReg;
809 unsigned ShiftImm;
810 };
811
812 struct RegShiftedImmOp {
813 ARM_AM::ShiftOpc ShiftTy;
814 unsigned SrcReg;
815 unsigned ShiftImm;
816 };
817
818 struct RotImmOp {
819 unsigned Imm;
820 };
821
822 struct ModImmOp {
823 unsigned Bits;
824 unsigned Rot;
825 };
826
827 struct BitfieldOp {
828 unsigned LSB;
829 unsigned Width;
830 };
831
832 union {
833 struct CCOp CC;
834 struct VCCOp VCC;
835 struct CopOp Cop;
836 struct CoprocOptionOp CoprocOption;
837 struct MBOptOp MBOpt;
838 struct ISBOptOp ISBOpt;
839 struct TSBOptOp TSBOpt;
840 struct ITMaskOp ITMask;
841 struct IFlagsOp IFlags;
842 struct MMaskOp MMask;
843 struct BankedRegOp BankedReg;
844 struct TokOp Tok;
845 struct RegOp Reg;
846 struct VectorListOp VectorList;
847 struct VectorIndexOp VectorIndex;
848 struct ImmOp Imm;
849 struct MemoryOp Memory;
850 struct PostIdxRegOp PostIdxReg;
851 struct ShifterImmOp ShifterImm;
852 struct RegShiftedRegOp RegShiftedReg;
853 struct RegShiftedImmOp RegShiftedImm;
854 struct RotImmOp RotImm;
855 struct ModImmOp ModImm;
856 struct BitfieldOp Bitfield;
857 };
858
859public:
860 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
861
862 /// getStartLoc - Get the location of the first token of this operand.
863 SMLoc getStartLoc() const override { return StartLoc; }
864
865 /// getEndLoc - Get the location of the last token of this operand.
866 SMLoc getEndLoc() const override { return EndLoc; }
867
868 /// getLocRange - Get the range between the first and last token of this
869 /// operand.
870 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
871
872 /// getAlignmentLoc - Get the location of the Alignment token of this operand.
873 SMLoc getAlignmentLoc() const {
874 assert(Kind == k_Memory && "Invalid access!")((Kind == k_Memory && "Invalid access!") ? static_cast
<void> (0) : __assert_fail ("Kind == k_Memory && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 874, __PRETTY_FUNCTION__))
;
875 return AlignmentLoc;
876 }
877
878 ARMCC::CondCodes getCondCode() const {
879 assert(Kind == k_CondCode && "Invalid access!")((Kind == k_CondCode && "Invalid access!") ? static_cast
<void> (0) : __assert_fail ("Kind == k_CondCode && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 879, __PRETTY_FUNCTION__))
;
880 return CC.Val;
881 }
882
883 ARMVCC::VPTCodes getVPTPred() const {
884 assert(isVPTPred() && "Invalid access!")((isVPTPred() && "Invalid access!") ? static_cast<
void> (0) : __assert_fail ("isVPTPred() && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 884, __PRETTY_FUNCTION__))
;
885 return VCC.Val;
886 }
887
888 unsigned getCoproc() const {
889 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!")(((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"
) ? static_cast<void> (0) : __assert_fail ("(Kind == k_CoprocNum || Kind == k_CoprocReg) && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 889, __PRETTY_FUNCTION__))
;
890 return Cop.Val;
891 }
892
893 StringRef getToken() const {
894 assert(Kind == k_Token && "Invalid access!")((Kind == k_Token && "Invalid access!") ? static_cast
<void> (0) : __assert_fail ("Kind == k_Token && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 894, __PRETTY_FUNCTION__))
;
895 return StringRef(Tok.Data, Tok.Length);
896 }
897
898 unsigned getReg() const override {
899 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!")(((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"
) ? static_cast<void> (0) : __assert_fail ("(Kind == k_Register || Kind == k_CCOut) && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 899, __PRETTY_FUNCTION__))
;
900 return Reg.RegNum;
901 }
902
903 const SmallVectorImpl<unsigned> &getRegList() const {
904 assert((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR ||(((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR ||
Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind
== k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR
) && "Invalid access!") ? static_cast<void> (0)
: __assert_fail ("(Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR) && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 908, __PRETTY_FUNCTION__))
905 Kind == k_DPRRegisterList || Kind == k_SPRRegisterList ||(((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR ||
Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind
== k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR
) && "Invalid access!") ? static_cast<void> (0)
: __assert_fail ("(Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR) && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 908, __PRETTY_FUNCTION__))
906 Kind == k_FPSRegisterListWithVPR ||(((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR ||
Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind
== k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR
) && "Invalid access!") ? static_cast<void> (0)
: __assert_fail ("(Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR) && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 908, __PRETTY_FUNCTION__))
907 Kind == k_FPDRegisterListWithVPR) &&(((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR ||
Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind
== k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR
) && "Invalid access!") ? static_cast<void> (0)
: __assert_fail ("(Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR) && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 908, __PRETTY_FUNCTION__))
908 "Invalid access!")(((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR ||
Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind
== k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR
) && "Invalid access!") ? static_cast<void> (0)
: __assert_fail ("(Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR) && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 908, __PRETTY_FUNCTION__))
;
909 return Registers;
910 }
911
912 const MCExpr *getImm() const {
913 assert(isImm() && "Invalid access!")((isImm() && "Invalid access!") ? static_cast<void
> (0) : __assert_fail ("isImm() && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 913, __PRETTY_FUNCTION__))
;
914 return Imm.Val;
915 }
916
917 const MCExpr *getConstantPoolImm() const {
918 assert(isConstantPoolImm() && "Invalid access!")((isConstantPoolImm() && "Invalid access!") ? static_cast
<void> (0) : __assert_fail ("isConstantPoolImm() && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 918, __PRETTY_FUNCTION__))
;
919 return Imm.Val;
920 }
921
922 unsigned getVectorIndex() const {
923 assert(Kind == k_VectorIndex && "Invalid access!")((Kind == k_VectorIndex && "Invalid access!") ? static_cast
<void> (0) : __assert_fail ("Kind == k_VectorIndex && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 923, __PRETTY_FUNCTION__))
;
924 return VectorIndex.Val;
925 }
926
927 ARM_MB::MemBOpt getMemBarrierOpt() const {
928 assert(Kind == k_MemBarrierOpt && "Invalid access!")((Kind == k_MemBarrierOpt && "Invalid access!") ? static_cast
<void> (0) : __assert_fail ("Kind == k_MemBarrierOpt && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 928, __PRETTY_FUNCTION__))
;
929 return MBOpt.Val;
930 }
931
932 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
933 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!")((Kind == k_InstSyncBarrierOpt && "Invalid access!") ?
static_cast<void> (0) : __assert_fail ("Kind == k_InstSyncBarrierOpt && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 933, __PRETTY_FUNCTION__))
;
934 return ISBOpt.Val;
935 }
936
937 ARM_TSB::TraceSyncBOpt getTraceSyncBarrierOpt() const {
938 assert(Kind == k_TraceSyncBarrierOpt && "Invalid access!")((Kind == k_TraceSyncBarrierOpt && "Invalid access!")
? static_cast<void> (0) : __assert_fail ("Kind == k_TraceSyncBarrierOpt && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 938, __PRETTY_FUNCTION__))
;
939 return TSBOpt.Val;
940 }
941
942 ARM_PROC::IFlags getProcIFlags() const {
943 assert(Kind == k_ProcIFlags && "Invalid access!")((Kind == k_ProcIFlags && "Invalid access!") ? static_cast
<void> (0) : __assert_fail ("Kind == k_ProcIFlags && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 943, __PRETTY_FUNCTION__))
;
944 return IFlags.Val;
945 }
946
947 unsigned getMSRMask() const {
948 assert(Kind == k_MSRMask && "Invalid access!")((Kind == k_MSRMask && "Invalid access!") ? static_cast
<void> (0) : __assert_fail ("Kind == k_MSRMask && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 948, __PRETTY_FUNCTION__))
;
949 return MMask.Val;
950 }
951
952 unsigned getBankedReg() const {
953 assert(Kind == k_BankedReg && "Invalid access!")((Kind == k_BankedReg && "Invalid access!") ? static_cast
<void> (0) : __assert_fail ("Kind == k_BankedReg && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 953, __PRETTY_FUNCTION__))
;
954 return BankedReg.Val;
955 }
956
957 bool isCoprocNum() const { return Kind == k_CoprocNum; }
958 bool isCoprocReg() const { return Kind == k_CoprocReg; }
959 bool isCoprocOption() const { return Kind == k_CoprocOption; }
960 bool isCondCode() const { return Kind == k_CondCode; }
961 bool isVPTPred() const { return Kind == k_VPTPred; }
962 bool isCCOut() const { return Kind == k_CCOut; }
963 bool isITMask() const { return Kind == k_ITCondMask; }
964 bool isITCondCode() const { return Kind == k_CondCode; }
965 bool isImm() const override {
966 return Kind == k_Immediate;
967 }
968
969 bool isARMBranchTarget() const {
970 if (!isImm()) return false;
971
972 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
973 return CE->getValue() % 4 == 0;
974 return true;
975 }
976
977
978 bool isThumbBranchTarget() const {
979 if (!isImm()) return false;
980
981 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
982 return CE->getValue() % 2 == 0;
983 return true;
984 }
985
986 // checks whether this operand is an unsigned offset which fits is a field
987 // of specified width and scaled by a specific number of bits
988 template<unsigned width, unsigned scale>
989 bool isUnsignedOffset() const {
990 if (!isImm()) return false;
991 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
992 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
993 int64_t Val = CE->getValue();
994 int64_t Align = 1LL << scale;
995 int64_t Max = Align * ((1LL << width) - 1);
996 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
997 }
998 return false;
999 }
1000
1001 // checks whether this operand is an signed offset which fits is a field
1002 // of specified width and scaled by a specific number of bits
1003 template<unsigned width, unsigned scale>
1004 bool isSignedOffset() const {
1005 if (!isImm()) return false;
1006 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1007 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1008 int64_t Val = CE->getValue();
1009 int64_t Align = 1LL << scale;
1010 int64_t Max = Align * ((1LL << (width-1)) - 1);
1011 int64_t Min = -Align * (1LL << (width-1));
1012 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
1013 }
1014 return false;
1015 }
1016
1017 // checks whether this operand is an offset suitable for the LE /
1018 // LETP instructions in Arm v8.1M
1019 bool isLEOffset() const {
1020 if (!isImm()) return false;
1021 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1022 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1023 int64_t Val = CE->getValue();
1024 return Val < 0 && Val >= -4094 && (Val & 1) == 0;
1025 }
1026 return false;
1027 }
1028
1029 // checks whether this operand is a memory operand computed as an offset
1030 // applied to PC. the offset may have 8 bits of magnitude and is represented
1031 // with two bits of shift. textually it may be either [pc, #imm], #imm or
1032 // relocable expression...
1033 bool isThumbMemPC() const {
1034 int64_t Val = 0;
1035 if (isImm()) {
1036 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1037 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
1038 if (!CE) return false;
1039 Val = CE->getValue();
1040 }
1041 else if (isGPRMem()) {
1042 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
1043 if(Memory.BaseRegNum != ARM::PC) return false;
1044 Val = Memory.OffsetImm->getValue();
1045 }
1046 else return false;
1047 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
1048 }
1049
1050 bool isFPImm() const {
1051 if (!isImm()) return false;
1052 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1053 if (!CE) return false;
1054 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1055 return Val != -1;
1056 }
1057
1058 template<int64_t N, int64_t M>
1059 bool isImmediate() const {
1060 if (!isImm()) return false;
1061 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1062 if (!CE) return false;
1063 int64_t Value = CE->getValue();
1064 return Value >= N && Value <= M;
1065 }
1066
1067 template<int64_t N, int64_t M>
1068 bool isImmediateS4() const {
1069 if (!isImm()) return false;
1070 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1071 if (!CE) return false;
1072 int64_t Value = CE->getValue();
1073 return ((Value & 3) == 0) && Value >= N && Value <= M;
1074 }
1075 template<int64_t N, int64_t M>
1076 bool isImmediateS2() const {
1077 if (!isImm()) return false;
1078 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1079 if (!CE) return false;
1080 int64_t Value = CE->getValue();
1081 return ((Value & 1) == 0) && Value >= N && Value <= M;
1082 }
1083 bool isFBits16() const {
1084 return isImmediate<0, 17>();
1085 }
1086 bool isFBits32() const {
1087 return isImmediate<1, 33>();
1088 }
1089 bool isImm8s4() const {
1090 return isImmediateS4<-1020, 1020>();
1091 }
1092 bool isImm7s4() const {
1093 return isImmediateS4<-508, 508>();
1094 }
1095 bool isImm7Shift0() const {
1096 return isImmediate<-127, 127>();
1097 }
1098 bool isImm7Shift1() const {
1099 return isImmediateS2<-255, 255>();
1100 }
1101 bool isImm7Shift2() const {
1102 return isImmediateS4<-511, 511>();
1103 }
1104 bool isImm7() const {
1105 return isImmediate<-127, 127>();
1106 }
1107 bool isImm0_1020s4() const {
1108 return isImmediateS4<0, 1020>();
1109 }
1110 bool isImm0_508s4() const {
1111 return isImmediateS4<0, 508>();
1112 }
1113 bool isImm0_508s4Neg() const {
1114 if (!isImm()) return false;
1115 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1116 if (!CE) return false;
1117 int64_t Value = -CE->getValue();
1118 // explicitly exclude zero. we want that to use the normal 0_508 version.
1119 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
1120 }
1121
1122 bool isImm0_4095Neg() const {
1123 if (!isImm()) return false;
1124 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1125 if (!CE) return false;
1126 // isImm0_4095Neg is used with 32-bit immediates only.
1127 // 32-bit immediates are zero extended to 64-bit when parsed,
1128 // thus simple -CE->getValue() results in a big negative number,
1129 // not a small positive number as intended
1130 if ((CE->getValue() >> 32) > 0) return false;
1131 uint32_t Value = -static_cast<uint32_t>(CE->getValue());
1132 return Value > 0 && Value < 4096;
1133 }
1134
1135 bool isImm0_7() const {
1136 return isImmediate<0, 7>();
1137 }
1138
1139 bool isImm1_16() const {
1140 return isImmediate<1, 16>();
1141 }
1142
1143 bool isImm1_32() const {
1144 return isImmediate<1, 32>();
1145 }
1146
1147 bool isImm8_255() const {
1148 return isImmediate<8, 255>();
1149 }
1150
1151 bool isImm256_65535Expr() const {
1152 if (!isImm()) return false;
1153 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1154 // If it's not a constant expression, it'll generate a fixup and be
1155 // handled later.
1156 if (!CE) return true;
1157 int64_t Value = CE->getValue();
1158 return Value >= 256 && Value < 65536;
1159 }
1160
1161 bool isImm0_65535Expr() const {
1162 if (!isImm()) return false;
1163 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1164 // If it's not a constant expression, it'll generate a fixup and be
1165 // handled later.
1166 if (!CE) return true;
1167 int64_t Value = CE->getValue();
1168 return Value >= 0 && Value < 65536;
1169 }
1170
1171 bool isImm24bit() const {
1172 return isImmediate<0, 0xffffff + 1>();
1173 }
1174
1175 bool isImmThumbSR() const {
1176 return isImmediate<1, 33>();
1177 }
1178
1179 template<int shift>
1180 bool isExpImmValue(uint64_t Value) const {
1181 uint64_t mask = (1 << shift) - 1;
1182 if ((Value & mask) != 0 || (Value >> shift) > 0xff)
1183 return false;
1184 return true;
1185 }
1186
1187 template<int shift>
1188 bool isExpImm() const {
1189 if (!isImm()) return false;
1190 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1191 if (!CE) return false;
1192
1193 return isExpImmValue<shift>(CE->getValue());
1194 }
1195
1196 template<int shift, int size>
1197 bool isInvertedExpImm() const {
1198 if (!isImm()) return false;
1199 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1200 if (!CE) return false;
1201
1202 uint64_t OriginalValue = CE->getValue();
1203 uint64_t InvertedValue = OriginalValue ^ (((uint64_t)1 << size) - 1);
1204 return isExpImmValue<shift>(InvertedValue);
1205 }
1206
1207 bool isPKHLSLImm() const {
1208 return isImmediate<0, 32>();
1209 }
1210
1211 bool isPKHASRImm() const {
1212 return isImmediate<0, 33>();
1213 }
1214
1215 bool isAdrLabel() const {
1216 // If we have an immediate that's not a constant, treat it as a label
1217 // reference needing a fixup.
1218 if (isImm() && !isa<MCConstantExpr>(getImm()))
1219 return true;
1220
1221 // If it is a constant, it must fit into a modified immediate encoding.
1222 if (!isImm()) return false;
1223 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1224 if (!CE) return false;
1225 int64_t Value = CE->getValue();
1226 return (ARM_AM::getSOImmVal(Value) != -1 ||
1227 ARM_AM::getSOImmVal(-Value) != -1);
1228 }
1229
1230 bool isT2SOImm() const {
1231 // If we have an immediate that's not a constant, treat it as an expression
1232 // needing a fixup.
1233 if (isImm() && !isa<MCConstantExpr>(getImm())) {
1234 // We want to avoid matching :upper16: and :lower16: as we want these
1235 // expressions to match in isImm0_65535Expr()
1236 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(getImm());
1237 return (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
1238 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16));
1239 }
1240 if (!isImm()) return false;
1241 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1242 if (!CE) return false;
1243 int64_t Value = CE->getValue();
1244 return ARM_AM::getT2SOImmVal(Value) != -1;
1245 }
1246
1247 bool isT2SOImmNot() const {
1248 if (!isImm()) return false;
1249 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1250 if (!CE) return false;
1251 int64_t Value = CE->getValue();
1252 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1253 ARM_AM::getT2SOImmVal(~Value) != -1;
1254 }
1255
1256 bool isT2SOImmNeg() const {
1257 if (!isImm()) return false;
1258 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1259 if (!CE) return false;
1260 int64_t Value = CE->getValue();
1261 // Only use this when not representable as a plain so_imm.
1262 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1263 ARM_AM::getT2SOImmVal(-Value) != -1;
1264 }
1265
1266 bool isSetEndImm() const {
1267 if (!isImm()) return false;
1268 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1269 if (!CE) return false;
1270 int64_t Value = CE->getValue();
1271 return Value == 1 || Value == 0;
1272 }
1273
1274 bool isReg() const override { return Kind == k_Register; }
1275 bool isRegList() const { return Kind == k_RegisterList; }
1276 bool isRegListWithAPSR() const {
1277 return Kind == k_RegisterListWithAPSR || Kind == k_RegisterList;
1278 }
1279 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1280 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1281 bool isFPSRegListWithVPR() const { return Kind == k_FPSRegisterListWithVPR; }
1282 bool isFPDRegListWithVPR() const { return Kind == k_FPDRegisterListWithVPR; }
1283 bool isToken() const override { return Kind == k_Token; }
1284 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1285 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1286 bool isTraceSyncBarrierOpt() const { return Kind == k_TraceSyncBarrierOpt; }
1287 bool isMem() const override {
1288 return isGPRMem() || isMVEMem();
1289 }
1290 bool isMVEMem() const {
1291 if (Kind != k_Memory)
1292 return false;
1293 if (Memory.BaseRegNum &&
1294 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum) &&
1295 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Memory.BaseRegNum))
1296 return false;
1297 if (Memory.OffsetRegNum &&
1298 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1299 Memory.OffsetRegNum))
1300 return false;
1301 return true;
1302 }
1303 bool isGPRMem() const {
1304 if (Kind != k_Memory)
1305 return false;
1306 if (Memory.BaseRegNum &&
1307 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum))
1308 return false;
1309 if (Memory.OffsetRegNum &&
1310 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.OffsetRegNum))
1311 return false;
1312 return true;
1313 }
1314 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1315 bool isRegShiftedReg() const {
1316 return Kind == k_ShiftedRegister &&
1317 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1318 RegShiftedReg.SrcReg) &&
1319 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1320 RegShiftedReg.ShiftReg);
1321 }
1322 bool isRegShiftedImm() const {
1323 return Kind == k_ShiftedImmediate &&
1324 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1325 RegShiftedImm.SrcReg);
1326 }
1327 bool isRotImm() const { return Kind == k_RotateImmediate; }
1328
1329 template<unsigned Min, unsigned Max>
1330 bool isPowerTwoInRange() const {
1331 if (!isImm()) return false;
1332 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1333 if (!CE) return false;
1334 int64_t Value = CE->getValue();
1335 return Value > 0 && countPopulation((uint64_t)Value) == 1 &&
1336 Value >= Min && Value <= Max;
1337 }
1338 bool isModImm() const { return Kind == k_ModifiedImmediate; }
1339
1340 bool isModImmNot() const {
1341 if (!isImm()) return false;
1342 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1343 if (!CE) return false;
1344 int64_t Value = CE->getValue();
1345 return ARM_AM::getSOImmVal(~Value) != -1;
1346 }
1347
1348 bool isModImmNeg() const {
1349 if (!isImm()) return false;
1350 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1351 if (!CE) return false;
1352 int64_t Value = CE->getValue();
1353 return ARM_AM::getSOImmVal(Value) == -1 &&
1354 ARM_AM::getSOImmVal(-Value) != -1;
1355 }
1356
1357 bool isThumbModImmNeg1_7() const {
1358 if (!isImm()) return false;
1359 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1360 if (!CE) return false;
1361 int32_t Value = -(int32_t)CE->getValue();
1362 return 0 < Value && Value < 8;
1363 }
1364
1365 bool isThumbModImmNeg8_255() const {
1366 if (!isImm()) return false;
1367 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1368 if (!CE) return false;
1369 int32_t Value = -(int32_t)CE->getValue();
1370 return 7 < Value && Value < 256;
1371 }
1372
1373 bool isConstantPoolImm() const { return Kind == k_ConstantPoolImmediate; }
1374 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1375 bool isPostIdxRegShifted() const {
1376 return Kind == k_PostIndexRegister &&
1377 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum);
1378 }
1379 bool isPostIdxReg() const {
1380 return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;
1381 }
1382 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1383 if (!isGPRMem())
1384 return false;
1385 // No offset of any kind.
1386 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1387 (alignOK || Memory.Alignment == Alignment);
1388 }
1389 bool isMemNoOffsetT2(bool alignOK = false, unsigned Alignment = 0) const {
1390 if (!isGPRMem())
1391 return false;
1392
1393 if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1394 Memory.BaseRegNum))
1395 return false;
1396
1397 // No offset of any kind.
1398 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1399 (alignOK || Memory.Alignment == Alignment);
1400 }
1401 bool isMemNoOffsetT2NoSp(bool alignOK = false, unsigned Alignment = 0) const {
1402 if (!isGPRMem())
1403 return false;
1404
1405 if (!ARMMCRegisterClasses[ARM::rGPRRegClassID].contains(
1406 Memory.BaseRegNum))
1407 return false;
1408
1409 // No offset of any kind.
1410 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1411 (alignOK || Memory.Alignment == Alignment);
1412 }
1413 bool isMemNoOffsetT(bool alignOK = false, unsigned Alignment = 0) const {
1414 if (!isGPRMem())
1415 return false;
1416
1417 if (!ARMMCRegisterClasses[ARM::tGPRRegClassID].contains(
1418 Memory.BaseRegNum))
1419 return false;
1420
1421 // No offset of any kind.
1422 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1423 (alignOK || Memory.Alignment == Alignment);
1424 }
1425 bool isMemPCRelImm12() const {
1426 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1427 return false;
1428 // Base register must be PC.
1429 if (Memory.BaseRegNum != ARM::PC)
1430 return false;
1431 // Immediate offset in range [-4095, 4095].
1432 if (!Memory.OffsetImm) return true;
1433 int64_t Val = Memory.OffsetImm->getValue();
1434 return (Val > -4096 && Val < 4096) ||
1435 (Val == std::numeric_limits<int32_t>::min());
1436 }
1437
1438 bool isAlignedMemory() const {
1439 return isMemNoOffset(true);
1440 }
1441
1442 bool isAlignedMemoryNone() const {
1443 return isMemNoOffset(false, 0);
1444 }
1445
1446 bool isDupAlignedMemoryNone() const {
1447 return isMemNoOffset(false, 0);
1448 }
1449
1450 bool isAlignedMemory16() const {
1451 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1452 return true;
1453 return isMemNoOffset(false, 0);
1454 }
1455
1456 bool isDupAlignedMemory16() const {
1457 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1458 return true;
1459 return isMemNoOffset(false, 0);
1460 }
1461
1462 bool isAlignedMemory32() const {
1463 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1464 return true;
1465 return isMemNoOffset(false, 0);
1466 }
1467
1468 bool isDupAlignedMemory32() const {
1469 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1470 return true;
1471 return isMemNoOffset(false, 0);
1472 }
1473
1474 bool isAlignedMemory64() const {
1475 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1476 return true;
1477 return isMemNoOffset(false, 0);
1478 }
1479
1480 bool isDupAlignedMemory64() const {
1481 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1482 return true;
1483 return isMemNoOffset(false, 0);
1484 }
1485
1486 bool isAlignedMemory64or128() const {
1487 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1488 return true;
1489 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1490 return true;
1491 return isMemNoOffset(false, 0);
1492 }
1493
1494 bool isDupAlignedMemory64or128() const {
1495 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1496 return true;
1497 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1498 return true;
1499 return isMemNoOffset(false, 0);
1500 }
1501
1502 bool isAlignedMemory64or128or256() const {
1503 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1504 return true;
1505 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1506 return true;
1507 if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1508 return true;
1509 return isMemNoOffset(false, 0);
1510 }
1511
1512 bool isAddrMode2() const {
1513 if (!isGPRMem() || Memory.Alignment != 0) return false;
1514 // Check for register offset.
1515 if (Memory.OffsetRegNum) return true;
1516 // Immediate offset in range [-4095, 4095].
1517 if (!Memory.OffsetImm) return true;
1518 int64_t Val = Memory.OffsetImm->getValue();
1519 return Val > -4096 && Val < 4096;
1520 }
1521
1522 bool isAM2OffsetImm() const {
1523 if (!isImm()) return false;
1524 // Immediate offset in range [-4095, 4095].
1525 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1526 if (!CE) return false;
1527 int64_t Val = CE->getValue();
1528 return (Val == std::numeric_limits<int32_t>::min()) ||
1529 (Val > -4096 && Val < 4096);
1530 }
1531
1532 bool isAddrMode3() const {
1533 // If we have an immediate that's not a constant, treat it as a label
1534 // reference needing a fixup. If it is a constant, it's something else
1535 // and we reject it.
1536 if (isImm() && !isa<MCConstantExpr>(getImm()))
1537 return true;
1538 if (!isGPRMem() || Memory.Alignment != 0) return false;
1539 // No shifts are legal for AM3.
1540 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1541 // Check for register offset.
1542 if (Memory.OffsetRegNum) return true;
1543 // Immediate offset in range [-255, 255].
1544 if (!Memory.OffsetImm) return true;
1545 int64_t Val = Memory.OffsetImm->getValue();
1546 // The #-0 offset is encoded as std::numeric_limits<int32_t>::min(), and we
1547 // have to check for this too.
1548 return (Val > -256 && Val < 256) ||
1549 Val == std::numeric_limits<int32_t>::min();
1550 }
1551
1552 bool isAM3Offset() const {
1553 if (isPostIdxReg())
1554 return true;
1555 if (!isImm())
1556 return false;
1557 // Immediate offset in range [-255, 255].
1558 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1559 if (!CE) return false;
1560 int64_t Val = CE->getValue();
1561 // Special case, #-0 is std::numeric_limits<int32_t>::min().
1562 return (Val > -256 && Val < 256) ||
1563 Val == std::numeric_limits<int32_t>::min();
1564 }
1565
1566 bool isAddrMode5() const {
1567 // If we have an immediate that's not a constant, treat it as a label
1568 // reference needing a fixup. If it is a constant, it's something else
1569 // and we reject it.
1570 if (isImm() && !isa<MCConstantExpr>(getImm()))
1571 return true;
1572 if (!isGPRMem() || Memory.Alignment != 0) return false;
1573 // Check for register offset.
1574 if (Memory.OffsetRegNum) return false;
1575 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1576 if (!Memory.OffsetImm) return true;
1577 int64_t Val = Memory.OffsetImm->getValue();
1578 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1579 Val == std::numeric_limits<int32_t>::min();
1580 }
1581
1582 bool isAddrMode5FP16() const {
1583 // If we have an immediate that's not a constant, treat it as a label
1584 // reference needing a fixup. If it is a constant, it's something else
1585 // and we reject it.
1586 if (isImm() && !isa<MCConstantExpr>(getImm()))
1587 return true;
1588 if (!isGPRMem() || Memory.Alignment != 0) return false;
1589 // Check for register offset.
1590 if (Memory.OffsetRegNum) return false;
1591 // Immediate offset in range [-510, 510] and a multiple of 2.
1592 if (!Memory.OffsetImm) return true;
1593 int64_t Val = Memory.OffsetImm->getValue();
1594 return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) ||
1595 Val == std::numeric_limits<int32_t>::min();
1596 }
1597
1598 bool isMemTBB() const {
1599 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1600 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1601 return false;
1602 return true;
1603 }
1604
1605 bool isMemTBH() const {
1606 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1607 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1608 Memory.Alignment != 0 )
1609 return false;
1610 return true;
1611 }
1612
1613 bool isMemRegOffset() const {
1614 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1615 return false;
1616 return true;
1617 }
1618
1619 bool isT2MemRegOffset() const {
1620 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1621 Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)
1622 return false;
1623 // Only lsl #{0, 1, 2, 3} allowed.
1624 if (Memory.ShiftType == ARM_AM::no_shift)
1625 return true;
1626 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1627 return false;
1628 return true;
1629 }
1630
1631 bool isMemThumbRR() const {
1632 // Thumb reg+reg addressing is simple. Just two registers, a base and
1633 // an offset. No shifts, negations or any other complicating factors.
1634 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1635 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1636 return false;
1637 return isARMLowRegister(Memory.BaseRegNum) &&
1638 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1639 }
1640
1641 bool isMemThumbRIs4() const {
1642 if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1643 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1644 return false;
1645 // Immediate offset, multiple of 4 in range [0, 124].
1646 if (!Memory.OffsetImm) return true;
1647 int64_t Val = Memory.OffsetImm->getValue();
1648 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1649 }
1650
1651 bool isMemThumbRIs2() const {
1652 if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1653 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1654 return false;
1655 // Immediate offset, multiple of 4 in range [0, 62].
1656 if (!Memory.OffsetImm) return true;
1657 int64_t Val = Memory.OffsetImm->getValue();
1658 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1659 }
1660
1661 bool isMemThumbRIs1() const {
1662 if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1663 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1664 return false;
1665 // Immediate offset in range [0, 31].
1666 if (!Memory.OffsetImm) return true;
1667 int64_t Val = Memory.OffsetImm->getValue();
1668 return Val >= 0 && Val <= 31;
1669 }
1670
1671 bool isMemThumbSPI() const {
1672 if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1673 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1674 return false;
1675 // Immediate offset, multiple of 4 in range [0, 1020].
1676 if (!Memory.OffsetImm) return true;
1677 int64_t Val = Memory.OffsetImm->getValue();
1678 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1679 }
1680
1681 bool isMemImm8s4Offset() const {
1682 // If we have an immediate that's not a constant, treat it as a label
1683 // reference needing a fixup. If it is a constant, it's something else
1684 // and we reject it.
1685 if (isImm() && !isa<MCConstantExpr>(getImm()))
1686 return true;
1687 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1688 return false;
1689 // Immediate offset a multiple of 4 in range [-1020, 1020].
1690 if (!Memory.OffsetImm) return true;
1691 int64_t Val = Memory.OffsetImm->getValue();
1692 // Special case, #-0 is std::numeric_limits<int32_t>::min().
1693 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) ||
1694 Val == std::numeric_limits<int32_t>::min();
1695 }
1696 bool isMemImm7s4Offset() const {
1697 // If we have an immediate that's not a constant, treat it as a label
1698 // reference needing a fixup. If it is a constant, it's something else
1699 // and we reject it.
1700 if (isImm() && !isa<MCConstantExpr>(getImm()))
1701 return true;
1702 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
1703 !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1704 Memory.BaseRegNum))
1705 return false;
1706 // Immediate offset a multiple of 4 in range [-508, 508].
1707 if (!Memory.OffsetImm) return true;
1708 int64_t Val = Memory.OffsetImm->getValue();
1709 // Special case, #-0 is INT32_MIN.
1710 return (Val >= -508 && Val <= 508 && (Val & 3) == 0) || Val == INT32_MIN(-2147483647-1);
1711 }
1712 bool isMemImm0_1020s4Offset() const {
1713 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1714 return false;
1715 // Immediate offset a multiple of 4 in range [0, 1020].
1716 if (!Memory.OffsetImm) return true;
1717 int64_t Val = Memory.OffsetImm->getValue();
1718 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1719 }
1720
1721 bool isMemImm8Offset() const {
1722 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1723 return false;
1724 // Base reg of PC isn't allowed for these encodings.
1725 if (Memory.BaseRegNum == ARM::PC) return false;
1726 // Immediate offset in range [-255, 255].
1727 if (!Memory.OffsetImm) return true;
1728 int64_t Val = Memory.OffsetImm->getValue();
1729 return (Val == std::numeric_limits<int32_t>::min()) ||
1730 (Val > -256 && Val < 256);
1731 }
1732
1733 template<unsigned Bits, unsigned RegClassID>
1734 bool isMemImm7ShiftedOffset() const {
1735 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
1736 !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum))
1737 return false;
1738
1739 // Expect an immediate offset equal to an element of the range
1740 // [-127, 127], shifted left by Bits.
1741
1742 if (!Memory.OffsetImm) return true;
1743 int64_t Val = Memory.OffsetImm->getValue();
1744
1745 // INT32_MIN is a special-case value (indicating the encoding with
1746 // zero offset and the subtract bit set)
1747 if (Val == INT32_MIN(-2147483647-1))
1748 return true;
1749
1750 unsigned Divisor = 1U << Bits;
1751
1752 // Check that the low bits are zero
1753 if (Val % Divisor != 0)
1754 return false;
1755
1756 // Check that the remaining offset is within range.
1757 Val /= Divisor;
1758 return (Val >= -127 && Val <= 127);
1759 }
1760
1761 template <int shift> bool isMemRegRQOffset() const {
1762 if (!isMVEMem() || Memory.OffsetImm != 0 || Memory.Alignment != 0)
1763 return false;
1764
1765 if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1766 Memory.BaseRegNum))
1767 return false;
1768 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1769 Memory.OffsetRegNum))
1770 return false;
1771
1772 if (shift == 0 && Memory.ShiftType != ARM_AM::no_shift)
1773 return false;
1774
1775 if (shift > 0 &&
1776 (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift))
1777 return false;
1778
1779 return true;
1780 }
1781
1782 template <int shift> bool isMemRegQOffset() const {
1783 if (!isMVEMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1784 return false;
1785
1786 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1787 Memory.BaseRegNum))
1788 return false;
1789
1790 if(!Memory.OffsetImm) return true;
1791 static_assert(shift < 56,
1792 "Such that we dont shift by a value higher than 62");
1793 int64_t Val = Memory.OffsetImm->getValue();
1794
1795 // The value must be a multiple of (1 << shift)
1796 if ((Val & ((1U << shift) - 1)) != 0)
1797 return false;
1798
1799 // And be in the right range, depending on the amount that it is shifted
1800 // by. Shift 0, is equal to 7 unsigned bits, the sign bit is set
1801 // separately.
1802 int64_t Range = (1U << (7+shift)) - 1;
1803 return (Val == INT32_MIN(-2147483647-1)) || (Val > -Range && Val < Range);
1804 }
1805
1806 bool isMemPosImm8Offset() const {
1807 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1808 return false;
1809 // Immediate offset in range [0, 255].
1810 if (!Memory.OffsetImm) return true;
1811 int64_t Val = Memory.OffsetImm->getValue();
1812 return Val >= 0 && Val < 256;
1813 }
1814
1815 bool isMemNegImm8Offset() const {
1816 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1817 return false;
1818 // Base reg of PC isn't allowed for these encodings.
1819 if (Memory.BaseRegNum == ARM::PC) return false;
1820 // Immediate offset in range [-255, -1].
1821 if (!Memory.OffsetImm) return false;
1822 int64_t Val = Memory.OffsetImm->getValue();
1823 return (Val == std::numeric_limits<int32_t>::min()) ||
1824 (Val > -256 && Val < 0);
1825 }
1826
1827 bool isMemUImm12Offset() const {
1828 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1829 return false;
1830 // Immediate offset in range [0, 4095].
1831 if (!Memory.OffsetImm) return true;
1832 int64_t Val = Memory.OffsetImm->getValue();
1833 return (Val >= 0 && Val < 4096);
1834 }
1835
1836 bool isMemImm12Offset() const {
1837 // If we have an immediate that's not a constant, treat it as a label
1838 // reference needing a fixup. If it is a constant, it's something else
1839 // and we reject it.
1840
1841 if (isImm() && !isa<MCConstantExpr>(getImm()))
1842 return true;
1843
1844 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1845 return false;
1846 // Immediate offset in range [-4095, 4095].
1847 if (!Memory.OffsetImm) return true;
1848 int64_t Val = Memory.OffsetImm->getValue();
1849 return (Val > -4096 && Val < 4096) ||
1850 (Val == std::numeric_limits<int32_t>::min());
1851 }
1852
1853 bool isConstPoolAsmImm() const {
1854 // Delay processing of Constant Pool Immediate, this will turn into
1855 // a constant. Match no other operand
1856 return (isConstantPoolImm());
1857 }
1858
1859 bool isPostIdxImm8() const {
1860 if (!isImm()) return false;
1861 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1862 if (!CE) return false;
1863 int64_t Val = CE->getValue();
1864 return (Val > -256 && Val < 256) ||
1865 (Val == std::numeric_limits<int32_t>::min());
1866 }
1867
1868 bool isPostIdxImm8s4() const {
1869 if (!isImm()) return false;
1870 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1871 if (!CE) return false;
1872 int64_t Val = CE->getValue();
1873 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1874 (Val == std::numeric_limits<int32_t>::min());
1875 }
1876
1877 bool isMSRMask() const { return Kind == k_MSRMask; }
1878 bool isBankedReg() const { return Kind == k_BankedReg; }
1879 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1880
1881 // NEON operands.
1882 bool isSingleSpacedVectorList() const {
1883 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1884 }
1885
1886 bool isDoubleSpacedVectorList() const {
1887 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1888 }
1889
1890 bool isVecListOneD() const {
1891 if (!isSingleSpacedVectorList()) return false;
1892 return VectorList.Count == 1;
1893 }
1894
1895 bool isVecListTwoMQ() const {
1896 return isSingleSpacedVectorList() && VectorList.Count == 2 &&
1897 ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1898 VectorList.RegNum);
1899 }
1900
1901 bool isVecListDPair() const {
1902 if (!isSingleSpacedVectorList()) return false;
1903 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1904 .contains(VectorList.RegNum));
1905 }
1906
1907 bool isVecListThreeD() const {
1908 if (!isSingleSpacedVectorList()) return false;
1909 return VectorList.Count == 3;
1910 }
1911
1912 bool isVecListFourD() const {
1913 if (!isSingleSpacedVectorList()) return false;
1914 return VectorList.Count == 4;
1915 }
1916
1917 bool isVecListDPairSpaced() const {
1918 if (Kind != k_VectorList) return false;
1919 if (isSingleSpacedVectorList()) return false;
1920 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1921 .contains(VectorList.RegNum));
1922 }
1923
1924 bool isVecListThreeQ() const {
1925 if (!isDoubleSpacedVectorList()) return false;
1926 return VectorList.Count == 3;
1927 }
1928
1929 bool isVecListFourQ() const {
1930 if (!isDoubleSpacedVectorList()) return false;
1931 return VectorList.Count == 4;
1932 }
1933
1934 bool isVecListFourMQ() const {
1935 return isSingleSpacedVectorList() && VectorList.Count == 4 &&
1936 ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1937 VectorList.RegNum);
1938 }
1939
1940 bool isSingleSpacedVectorAllLanes() const {
1941 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1942 }
1943
1944 bool isDoubleSpacedVectorAllLanes() const {
1945 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1946 }
1947
1948 bool isVecListOneDAllLanes() const {
1949 if (!isSingleSpacedVectorAllLanes()) return false;
1950 return VectorList.Count == 1;
1951 }
1952
1953 bool isVecListDPairAllLanes() const {
1954 if (!isSingleSpacedVectorAllLanes()) return false;
1955 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1956 .contains(VectorList.RegNum));
1957 }
1958
1959 bool isVecListDPairSpacedAllLanes() const {
1960 if (!isDoubleSpacedVectorAllLanes()) return false;
1961 return VectorList.Count == 2;
1962 }
1963
1964 bool isVecListThreeDAllLanes() const {
1965 if (!isSingleSpacedVectorAllLanes()) return false;
1966 return VectorList.Count == 3;
1967 }
1968
1969 bool isVecListThreeQAllLanes() const {
1970 if (!isDoubleSpacedVectorAllLanes()) return false;
1971 return VectorList.Count == 3;
1972 }
1973
1974 bool isVecListFourDAllLanes() const {
1975 if (!isSingleSpacedVectorAllLanes()) return false;
1976 return VectorList.Count == 4;
1977 }
1978
1979 bool isVecListFourQAllLanes() const {
1980 if (!isDoubleSpacedVectorAllLanes()) return false;
1981 return VectorList.Count == 4;
1982 }
1983
1984 bool isSingleSpacedVectorIndexed() const {
1985 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1986 }
1987
1988 bool isDoubleSpacedVectorIndexed() const {
1989 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1990 }
1991
1992 bool isVecListOneDByteIndexed() const {
1993 if (!isSingleSpacedVectorIndexed()) return false;
1994 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1995 }
1996
1997 bool isVecListOneDHWordIndexed() const {
1998 if (!isSingleSpacedVectorIndexed()) return false;
1999 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
2000 }
2001
2002 bool isVecListOneDWordIndexed() const {
2003 if (!isSingleSpacedVectorIndexed()) return false;
2004 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
2005 }
2006
2007 bool isVecListTwoDByteIndexed() const {
2008 if (!isSingleSpacedVectorIndexed()) return false;
2009 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
2010 }
2011
2012 bool isVecListTwoDHWordIndexed() const {
2013 if (!isSingleSpacedVectorIndexed()) return false;
2014 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
2015 }
2016
2017 bool isVecListTwoQWordIndexed() const {
2018 if (!isDoubleSpacedVectorIndexed()) return false;
2019 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
2020 }
2021
2022 bool isVecListTwoQHWordIndexed() const {
2023 if (!isDoubleSpacedVectorIndexed()) return false;
2024 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
2025 }
2026
2027 bool isVecListTwoDWordIndexed() const {
2028 if (!isSingleSpacedVectorIndexed()) return false;
2029 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
2030 }
2031
2032 bool isVecListThreeDByteIndexed() const {
2033 if (!isSingleSpacedVectorIndexed()) return false;
2034 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
2035 }
2036
2037 bool isVecListThreeDHWordIndexed() const {
2038 if (!isSingleSpacedVectorIndexed()) return false;
2039 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
2040 }
2041
2042 bool isVecListThreeQWordIndexed() const {
2043 if (!isDoubleSpacedVectorIndexed()) return false;
2044 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
2045 }
2046
2047 bool isVecListThreeQHWordIndexed() const {
2048 if (!isDoubleSpacedVectorIndexed()) return false;
2049 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
2050 }
2051
2052 bool isVecListThreeDWordIndexed() const {
2053 if (!isSingleSpacedVectorIndexed()) return false;
2054 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
2055 }
2056
2057 bool isVecListFourDByteIndexed() const {
2058 if (!isSingleSpacedVectorIndexed()) return false;
2059 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
2060 }
2061
2062 bool isVecListFourDHWordIndexed() const {
2063 if (!isSingleSpacedVectorIndexed()) return false;
2064 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
2065 }
2066
2067 bool isVecListFourQWordIndexed() const {
2068 if (!isDoubleSpacedVectorIndexed()) return false;
2069 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
2070 }
2071
2072 bool isVecListFourQHWordIndexed() const {
2073 if (!isDoubleSpacedVectorIndexed()) return false;
2074 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
2075 }
2076
2077 bool isVecListFourDWordIndexed() const {
2078 if (!isSingleSpacedVectorIndexed()) return false;
2079 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
2080 }
2081
2082 bool isVectorIndex() const { return Kind == k_VectorIndex; }
2083
2084 template <unsigned NumLanes>
2085 bool isVectorIndexInRange() const {
2086 if (Kind != k_VectorIndex) return false;
2087 return VectorIndex.Val < NumLanes;
2088 }
2089
2090 bool isVectorIndex8() const { return isVectorIndexInRange<8>(); }
2091 bool isVectorIndex16() const { return isVectorIndexInRange<4>(); }
2092 bool isVectorIndex32() const { return isVectorIndexInRange<2>(); }
2093 bool isVectorIndex64() const { return isVectorIndexInRange<1>(); }
2094
2095 template<int PermittedValue, int OtherPermittedValue>
2096 bool isMVEPairVectorIndex() const {
2097 if (Kind != k_VectorIndex) return false;
2098 return VectorIndex.Val == PermittedValue ||
2099 VectorIndex.Val == OtherPermittedValue;
2100 }
2101
2102 bool isNEONi8splat() const {
2103 if (!isImm()) return false;
2104 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2105 // Must be a constant.
2106 if (!CE) return false;
2107 int64_t Value = CE->getValue();
2108 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
2109 // value.
2110 return Value >= 0 && Value < 256;
2111 }
2112
2113 bool isNEONi16splat() const {
2114 if (isNEONByteReplicate(2))
2115 return false; // Leave that for bytes replication and forbid by default.
2116 if (!isImm())
2117 return false;
2118 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2119 // Must be a constant.
2120 if (!CE) return false;
2121 unsigned Value = CE->getValue();
2122 return ARM_AM::isNEONi16splat(Value);
2123 }
2124
2125 bool isNEONi16splatNot() const {
2126 if (!isImm())
2127 return false;
2128 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2129 // Must be a constant.
2130 if (!CE) return false;
2131 unsigned Value = CE->getValue();
2132 return ARM_AM::isNEONi16splat(~Value & 0xffff);
2133 }
2134
2135 bool isNEONi32splat() const {
2136 if (isNEONByteReplicate(4))
2137 return false; // Leave that for bytes replication and forbid by default.
2138 if (!isImm())
2139 return false;
2140 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2141 // Must be a constant.
2142 if (!CE) return false;
2143 unsigned Value = CE->getValue();
2144 return ARM_AM::isNEONi32splat(Value);
2145 }
2146
2147 bool isNEONi32splatNot() const {
2148 if (!isImm())
2149 return false;
2150 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2151 // Must be a constant.
2152 if (!CE) return false;
2153 unsigned Value = CE->getValue();
2154 return ARM_AM::isNEONi32splat(~Value);
2155 }
2156
2157 static bool isValidNEONi32vmovImm(int64_t Value) {
2158 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
2159 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
2160 return ((Value & 0xffffffffffffff00) == 0) ||
2161 ((Value & 0xffffffffffff00ff) == 0) ||
2162 ((Value & 0xffffffffff00ffff) == 0) ||
2163 ((Value & 0xffffffff00ffffff) == 0) ||
2164 ((Value & 0xffffffffffff00ff) == 0xff) ||
2165 ((Value & 0xffffffffff00ffff) == 0xffff);
2166 }
2167
2168 bool isNEONReplicate(unsigned Width, unsigned NumElems, bool Inv) const {
2169 assert((Width == 8 || Width == 16 || Width == 32) &&(((Width == 8 || Width == 16 || Width == 32) && "Invalid element width"
) ? static_cast<void> (0) : __assert_fail ("(Width == 8 || Width == 16 || Width == 32) && \"Invalid element width\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2170, __PRETTY_FUNCTION__))
2170 "Invalid element width")(((Width == 8 || Width == 16 || Width == 32) && "Invalid element width"
) ? static_cast<void> (0) : __assert_fail ("(Width == 8 || Width == 16 || Width == 32) && \"Invalid element width\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2170, __PRETTY_FUNCTION__))
;
2171 assert(NumElems * Width <= 64 && "Invalid result width")((NumElems * Width <= 64 && "Invalid result width"
) ? static_cast<void> (0) : __assert_fail ("NumElems * Width <= 64 && \"Invalid result width\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2171, __PRETTY_FUNCTION__))
;
2172
2173 if (!isImm())
2174 return false;
2175 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2176 // Must be a constant.
2177 if (!CE)
2178 return false;
2179 int64_t Value = CE->getValue();
2180 if (!Value)
2181 return false; // Don't bother with zero.
2182 if (Inv)
2183 Value = ~Value;
2184
2185 uint64_t Mask = (1ull << Width) - 1;
2186 uint64_t Elem = Value & Mask;
2187 if (Width == 16 && (Elem & 0x00ff) != 0 && (Elem & 0xff00) != 0)
2188 return false;
2189 if (Width == 32 && !isValidNEONi32vmovImm(Elem))
2190 return false;
2191
2192 for (unsigned i = 1; i < NumElems; ++i) {
2193 Value >>= Width;
2194 if ((Value & Mask) != Elem)
2195 return false;
2196 }
2197 return true;
2198 }
2199
2200 bool isNEONByteReplicate(unsigned NumBytes) const {
2201 return isNEONReplicate(8, NumBytes, false);
2202 }
2203
2204 static void checkNeonReplicateArgs(unsigned FromW, unsigned ToW) {
2205 assert((FromW == 8 || FromW == 16 || FromW == 32) &&(((FromW == 8 || FromW == 16 || FromW == 32) && "Invalid source width"
) ? static_cast<void> (0) : __assert_fail ("(FromW == 8 || FromW == 16 || FromW == 32) && \"Invalid source width\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2206, __PRETTY_FUNCTION__))
2206 "Invalid source width")(((FromW == 8 || FromW == 16 || FromW == 32) && "Invalid source width"
) ? static_cast<void> (0) : __assert_fail ("(FromW == 8 || FromW == 16 || FromW == 32) && \"Invalid source width\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2206, __PRETTY_FUNCTION__))
;
2207 assert((ToW == 16 || ToW == 32 || ToW == 64) &&(((ToW == 16 || ToW == 32 || ToW == 64) && "Invalid destination width"
) ? static_cast<void> (0) : __assert_fail ("(ToW == 16 || ToW == 32 || ToW == 64) && \"Invalid destination width\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2208, __PRETTY_FUNCTION__))
2208 "Invalid destination width")(((ToW == 16 || ToW == 32 || ToW == 64) && "Invalid destination width"
) ? static_cast<void> (0) : __assert_fail ("(ToW == 16 || ToW == 32 || ToW == 64) && \"Invalid destination width\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2208, __PRETTY_FUNCTION__))
;
2209 assert(FromW < ToW && "ToW is not less than FromW")((FromW < ToW && "ToW is not less than FromW") ? static_cast
<void> (0) : __assert_fail ("FromW < ToW && \"ToW is not less than FromW\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2209, __PRETTY_FUNCTION__))
;
2210 }
2211
2212 template<unsigned FromW, unsigned ToW>
2213 bool isNEONmovReplicate() const {
2214 checkNeonReplicateArgs(FromW, ToW);
2215 if (ToW == 64 && isNEONi64splat())
2216 return false;
2217 return isNEONReplicate(FromW, ToW / FromW, false);
2218 }
2219
2220 template<unsigned FromW, unsigned ToW>
2221 bool isNEONinvReplicate() const {
2222 checkNeonReplicateArgs(FromW, ToW);
2223 return isNEONReplicate(FromW, ToW / FromW, true);
2224 }
2225
2226 bool isNEONi32vmov() const {
2227 if (isNEONByteReplicate(4))
2228 return false; // Let it to be classified as byte-replicate case.
2229 if (!isImm())
2230 return false;
2231 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2232 // Must be a constant.
2233 if (!CE)
2234 return false;
2235 return isValidNEONi32vmovImm(CE->getValue());
2236 }
2237
2238 bool isNEONi32vmovNeg() const {
2239 if (!isImm()) return false;
2240 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2241 // Must be a constant.
2242 if (!CE) return false;
2243 return isValidNEONi32vmovImm(~CE->getValue());
2244 }
2245
2246 bool isNEONi64splat() const {
2247 if (!isImm()) return false;
2248 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2249 // Must be a constant.
2250 if (!CE) return false;
2251 uint64_t Value = CE->getValue();
2252 // i64 value with each byte being either 0 or 0xff.
2253 for (unsigned i = 0; i < 8; ++i, Value >>= 8)
2254 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
2255 return true;
2256 }
2257
2258 template<int64_t Angle, int64_t Remainder>
2259 bool isComplexRotation() const {
2260 if (!isImm()) return false;
2261
2262 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2263 if (!CE) return false;
2264 uint64_t Value = CE->getValue();
2265
2266 return (Value % Angle == Remainder && Value <= 270);
2267 }
2268
2269 bool isMVELongShift() const {
2270 if (!isImm()) return false;
2271 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2272 // Must be a constant.
2273 if (!CE) return false;
2274 uint64_t Value = CE->getValue();
2275 return Value >= 1 && Value <= 32;
2276 }
2277
2278 bool isMveSaturateOp() const {
2279 if (!isImm()) return false;
2280 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2281 if (!CE) return false;
2282 uint64_t Value = CE->getValue();
2283 return Value == 48 || Value == 64;
2284 }
2285
2286 bool isITCondCodeNoAL() const {
2287 if (!isITCondCode()) return false;
2288 ARMCC::CondCodes CC = getCondCode();
2289 return CC != ARMCC::AL;
2290 }
2291
2292 bool isITCondCodeRestrictedI() const {
2293 if (!isITCondCode())
2294 return false;
2295 ARMCC::CondCodes CC = getCondCode();
2296 return CC == ARMCC::EQ || CC == ARMCC::NE;
2297 }
2298
2299 bool isITCondCodeRestrictedS() const {
2300 if (!isITCondCode())
2301 return false;
2302 ARMCC::CondCodes CC = getCondCode();
2303 return CC == ARMCC::LT || CC == ARMCC::GT || CC == ARMCC::LE ||
2304 CC == ARMCC::GE;
2305 }
2306
2307 bool isITCondCodeRestrictedU() const {
2308 if (!isITCondCode())
2309 return false;
2310 ARMCC::CondCodes CC = getCondCode();
2311 return CC == ARMCC::HS || CC == ARMCC::HI;
2312 }
2313
2314 bool isITCondCodeRestrictedFP() const {
2315 if (!isITCondCode())
2316 return false;
2317 ARMCC::CondCodes CC = getCondCode();
2318 return CC == ARMCC::EQ || CC == ARMCC::NE || CC == ARMCC::LT ||
2319 CC == ARMCC::GT || CC == ARMCC::LE || CC == ARMCC::GE;
2320 }
2321
2322 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
2323 // Add as immediates when possible. Null MCExpr = 0.
2324 if (!Expr)
2325 Inst.addOperand(MCOperand::createImm(0));
2326 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
2327 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2328 else
2329 Inst.addOperand(MCOperand::createExpr(Expr));
2330 }
2331
2332 void addARMBranchTargetOperands(MCInst &Inst, unsigned N) const {
2333 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2333, __PRETTY_FUNCTION__))
;
2334 addExpr(Inst, getImm());
2335 }
2336
2337 void addThumbBranchTargetOperands(MCInst &Inst, unsigned N) const {
2338 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2338, __PRETTY_FUNCTION__))
;
2339 addExpr(Inst, getImm());
2340 }
2341
2342 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
2343 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2343, __PRETTY_FUNCTION__))
;
2344 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2345 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
2346 Inst.addOperand(MCOperand::createReg(RegNum));
2347 }
2348
2349 void addVPTPredNOperands(MCInst &Inst, unsigned N) const {
2350 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2350, __PRETTY_FUNCTION__))
;
2351 Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred())));
2352 unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0;
2353 Inst.addOperand(MCOperand::createReg(RegNum));
2354 }
2355
2356 void addVPTPredROperands(MCInst &Inst, unsigned N) const {
2357 assert(N == 3 && "Invalid number of operands!")((N == 3 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 3 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2357, __PRETTY_FUNCTION__))
;
2358 addVPTPredNOperands(Inst, N-1);
2359 unsigned RegNum;
2360 if (getVPTPred() == ARMVCC::None) {
2361 RegNum = 0;
2362 } else {
2363 unsigned NextOpIndex = Inst.getNumOperands();
2364 const MCInstrDesc &MCID = ARMInsts[Inst.getOpcode()];
2365 int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO);
2366 assert(TiedOp >= 0 &&((TiedOp >= 0 && "Inactive register in vpred_r is not tied to an output!"
) ? static_cast<void> (0) : __assert_fail ("TiedOp >= 0 && \"Inactive register in vpred_r is not tied to an output!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2367, __PRETTY_FUNCTION__))
2367 "Inactive register in vpred_r is not tied to an output!")((TiedOp >= 0 && "Inactive register in vpred_r is not tied to an output!"
) ? static_cast<void> (0) : __assert_fail ("TiedOp >= 0 && \"Inactive register in vpred_r is not tied to an output!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2367, __PRETTY_FUNCTION__))
;
2368 RegNum = Inst.getOperand(TiedOp).getReg();
2369 }
2370 Inst.addOperand(MCOperand::createReg(RegNum));
2371 }
2372
2373 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
2374 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2374, __PRETTY_FUNCTION__))
;
2375 Inst.addOperand(MCOperand::createImm(getCoproc()));
2376 }
2377
2378 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
2379 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2379, __PRETTY_FUNCTION__))
;
2380 Inst.addOperand(MCOperand::createImm(getCoproc()));
2381 }
2382
2383 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
2384 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2384, __PRETTY_FUNCTION__))
;
2385 Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
2386 }
2387
2388 void addITMaskOperands(MCInst &Inst, unsigned N) const {
2389 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2389, __PRETTY_FUNCTION__))
;
2390 Inst.addOperand(MCOperand::createImm(ITMask.Mask));
2391 }
2392
2393 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
2394 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2394, __PRETTY_FUNCTION__))
;
2395 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2396 }
2397
2398 void addITCondCodeInvOperands(MCInst &Inst, unsigned N) const {
2399 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2399, __PRETTY_FUNCTION__))
;
2400 Inst.addOperand(MCOperand::createImm(unsigned(ARMCC::getOppositeCondition(getCondCode()))));
2401 }
2402
2403 void addCCOutOperands(MCInst &Inst, unsigned N) const {
2404 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2404, __PRETTY_FUNCTION__))
;
2405 Inst.addOperand(MCOperand::createReg(getReg()));
2406 }
2407
2408 void addRegOperands(MCInst &Inst, unsigned N) const {
2409 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2409, __PRETTY_FUNCTION__))
;
2410 Inst.addOperand(MCOperand::createReg(getReg()));
2411 }
2412
2413 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
2414 assert(N == 3 && "Invalid number of operands!")((N == 3 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 3 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2414, __PRETTY_FUNCTION__))
;
2415 assert(isRegShiftedReg() &&((isRegShiftedReg() && "addRegShiftedRegOperands() on non-RegShiftedReg!"
) ? static_cast<void> (0) : __assert_fail ("isRegShiftedReg() && \"addRegShiftedRegOperands() on non-RegShiftedReg!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2416, __PRETTY_FUNCTION__))
2416 "addRegShiftedRegOperands() on non-RegShiftedReg!")((isRegShiftedReg() && "addRegShiftedRegOperands() on non-RegShiftedReg!"
) ? static_cast<void> (0) : __assert_fail ("isRegShiftedReg() && \"addRegShiftedRegOperands() on non-RegShiftedReg!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2416, __PRETTY_FUNCTION__))
;
2417 Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
2418 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
2419 Inst.addOperand(MCOperand::createImm(
2420 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
2421 }
2422
2423 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
2424 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2424, __PRETTY_FUNCTION__))
;
2425 assert(isRegShiftedImm() &&((isRegShiftedImm() && "addRegShiftedImmOperands() on non-RegShiftedImm!"
) ? static_cast<void> (0) : __assert_fail ("isRegShiftedImm() && \"addRegShiftedImmOperands() on non-RegShiftedImm!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2426, __PRETTY_FUNCTION__))
2426 "addRegShiftedImmOperands() on non-RegShiftedImm!")((isRegShiftedImm() && "addRegShiftedImmOperands() on non-RegShiftedImm!"
) ? static_cast<void> (0) : __assert_fail ("isRegShiftedImm() && \"addRegShiftedImmOperands() on non-RegShiftedImm!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2426, __PRETTY_FUNCTION__))
;
2427 Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
2428 // Shift of #32 is encoded as 0 where permitted
2429 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
2430 Inst.addOperand(MCOperand::createImm(
2431 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
2432 }
2433
2434 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
2435 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2435, __PRETTY_FUNCTION__))
;
2436 Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
2437 ShifterImm.Imm));
2438 }
2439
2440 void addRegListOperands(MCInst &Inst, unsigned N) const {
2441 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2441, __PRETTY_FUNCTION__))
;
2442 const SmallVectorImpl<unsigned> &RegList = getRegList();
2443 for (SmallVectorImpl<unsigned>::const_iterator
2444 I = RegList.begin(), E = RegList.end(); I != E; ++I)
2445 Inst.addOperand(MCOperand::createReg(*I));
2446 }
2447
2448 void addRegListWithAPSROperands(MCInst &Inst, unsigned N) const {
2449 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2449, __PRETTY_FUNCTION__))
;
2450 const SmallVectorImpl<unsigned> &RegList = getRegList();
2451 for (SmallVectorImpl<unsigned>::const_iterator
2452 I = RegList.begin(), E = RegList.end(); I != E; ++I)
2453 Inst.addOperand(MCOperand::createReg(*I));
2454 }
2455
2456 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
2457 addRegListOperands(Inst, N);
2458 }
2459
2460 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
2461 addRegListOperands(Inst, N);
2462 }
2463
2464 void addFPSRegListWithVPROperands(MCInst &Inst, unsigned N) const {
2465 addRegListOperands(Inst, N);
2466 }
2467
2468 void addFPDRegListWithVPROperands(MCInst &Inst, unsigned N) const {
2469 addRegListOperands(Inst, N);
2470 }
2471
2472 void addRotImmOperands(MCInst &Inst, unsigned N) const {
2473 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2473, __PRETTY_FUNCTION__))
;
2474 // Encoded as val>>3. The printer handles display as 8, 16, 24.
2475 Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
2476 }
2477
2478 void addModImmOperands(MCInst &Inst, unsigned N) const {
2479 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2479, __PRETTY_FUNCTION__))
;
2480
2481 // Support for fixups (MCFixup)
2482 if (isImm())
2483 return addImmOperands(Inst, N);
2484
2485 Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
2486 }
2487
2488 void addModImmNotOperands(MCInst &Inst, unsigned N) const {
2489 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2489, __PRETTY_FUNCTION__))
;
2490 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2491 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
2492 Inst.addOperand(MCOperand::createImm(Enc));
2493 }
2494
2495 void addModImmNegOperands(MCInst &Inst, unsigned N) const {
2496 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2496, __PRETTY_FUNCTION__))
;
2497 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2498 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
2499 Inst.addOperand(MCOperand::createImm(Enc));
2500 }
2501
2502 void addThumbModImmNeg8_255Operands(MCInst &Inst, unsigned N) const {
2503 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2503, __PRETTY_FUNCTION__))
;
2504 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2505 uint32_t Val = -CE->getValue();
2506 Inst.addOperand(MCOperand::createImm(Val));
2507 }
2508
2509 void addThumbModImmNeg1_7Operands(MCInst &Inst, unsigned N) const {
2510 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2510, __PRETTY_FUNCTION__))
;
2511 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2512 uint32_t Val = -CE->getValue();
2513 Inst.addOperand(MCOperand::createImm(Val));
2514 }
2515
2516 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
2517 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2517, __PRETTY_FUNCTION__))
;
2518 // Munge the lsb/width into a bitfield mask.
2519 unsigned lsb = Bitfield.LSB;
2520 unsigned width = Bitfield.Width;
2521 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
2522 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
2523 (32 - (lsb + width)));
2524 Inst.addOperand(MCOperand::createImm(Mask));
2525 }
2526
2527 void addImmOperands(MCInst &Inst, unsigned N) const {
2528 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2528, __PRETTY_FUNCTION__))
;
2529 addExpr(Inst, getImm());
2530 }
2531
2532 void addFBits16Operands(MCInst &Inst, unsigned N) const {
2533 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2533, __PRETTY_FUNCTION__))
;
2534 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2535 Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
2536 }
2537
2538 void addFBits32Operands(MCInst &Inst, unsigned N) const {
2539 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2539, __PRETTY_FUNCTION__))
;
2540 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2541 Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
2542 }
2543
2544 void addFPImmOperands(MCInst &Inst, unsigned N) const {
2545 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2545, __PRETTY_FUNCTION__))
;
2546 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2547 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
2548 Inst.addOperand(MCOperand::createImm(Val));
2549 }
2550
2551 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
2552 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2552, __PRETTY_FUNCTION__))
;
2553 // FIXME: We really want to scale the value here, but the LDRD/STRD
2554 // instruction don't encode operands that way yet.
2555 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2556 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2557 }
2558
2559 void addImm7s4Operands(MCInst &Inst, unsigned N) const {
2560 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2560, __PRETTY_FUNCTION__))
;
2561 // FIXME: We really want to scale the value here, but the VSTR/VLDR_VSYSR
2562 // instruction don't encode operands that way yet.
2563 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2564 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2565 }
2566
2567 void addImm7Shift0Operands(MCInst &Inst, unsigned N) const {
2568 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2568, __PRETTY_FUNCTION__))
;
2569 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2570 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2571 }
2572
2573 void addImm7Shift1Operands(MCInst &Inst, unsigned N) const {
2574 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2574, __PRETTY_FUNCTION__))
;
2575 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2576 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2577 }
2578
2579 void addImm7Shift2Operands(MCInst &Inst, unsigned N) const {
2580 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2580, __PRETTY_FUNCTION__))
;
2581 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2582 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2583 }
2584
2585 void addImm7Operands(MCInst &Inst, unsigned N) const {
2586 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2586, __PRETTY_FUNCTION__))
;
2587 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2588 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2589 }
2590
2591 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
2592 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2592, __PRETTY_FUNCTION__))
;
2593 // The immediate is scaled by four in the encoding and is stored
2594 // in the MCInst as such. Lop off the low two bits here.
2595 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2596 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2597 }
2598
2599 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
2600 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2600, __PRETTY_FUNCTION__))
;
2601 // The immediate is scaled by four in the encoding and is stored
2602 // in the MCInst as such. Lop off the low two bits here.
2603 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2604 Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
2605 }
2606
2607 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
2608 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2608, __PRETTY_FUNCTION__))
;
2609 // The immediate is scaled by four in the encoding and is stored
2610 // in the MCInst as such. Lop off the low two bits here.
2611 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2612 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2613 }
2614
2615 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
2616 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2616, __PRETTY_FUNCTION__))
;
2617 // The constant encodes as the immediate-1, and we store in the instruction
2618 // the bits as encoded, so subtract off one here.
2619 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2620 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2621 }
2622
2623 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
2624 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2624, __PRETTY_FUNCTION__))
;
2625 // The constant encodes as the immediate-1, and we store in the instruction
2626 // the bits as encoded, so subtract off one here.
2627 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2628 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2629 }
2630
2631 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
2632 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2632, __PRETTY_FUNCTION__))
;
2633 // The constant encodes as the immediate, except for 32, which encodes as
2634 // zero.
2635 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2636 unsigned Imm = CE->getValue();
2637 Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
2638 }
2639
2640 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
2641 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2641, __PRETTY_FUNCTION__))
;
2642 // An ASR value of 32 encodes as 0, so that's how we want to add it to
2643 // the instruction as well.
2644 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2645 int Val = CE->getValue();
2646 Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
2647 }
2648
2649 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
2650 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2650, __PRETTY_FUNCTION__))
;
2651 // The operand is actually a t2_so_imm, but we have its bitwise
2652 // negation in the assembly source, so twiddle it here.
2653 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2654 Inst.addOperand(MCOperand::createImm(~(uint32_t)CE->getValue()));
2655 }
2656
2657 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
2658 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2658, __PRETTY_FUNCTION__))
;
2659 // The operand is actually a t2_so_imm, but we have its
2660 // negation in the assembly source, so twiddle it here.
2661 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2662 Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue()));
2663 }
2664
2665 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
2666 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2666, __PRETTY_FUNCTION__))
;
2667 // The operand is actually an imm0_4095, but we have its
2668 // negation in the assembly source, so twiddle it here.
2669 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2670 Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue()));
2671 }
2672
2673 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
2674 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
2675 Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
2676 return;
2677 }
2678 const MCSymbolRefExpr *SR = cast<MCSymbolRefExpr>(Imm.Val);
2679 Inst.addOperand(MCOperand::createExpr(SR));
2680 }
2681
2682 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
2683 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2683, __PRETTY_FUNCTION__))
;
2684 if (isImm()) {
2685 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2686 if (CE) {
2687 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2688 return;
2689 }
2690 const MCSymbolRefExpr *SR = cast<MCSymbolRefExpr>(Imm.Val);
2691 Inst.addOperand(MCOperand::createExpr(SR));
2692 return;
2693 }
2694
2695 assert(isGPRMem() && "Unknown value type!")((isGPRMem() && "Unknown value type!") ? static_cast<
void> (0) : __assert_fail ("isGPRMem() && \"Unknown value type!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2695, __PRETTY_FUNCTION__))
;
2696 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!")((isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!"
) ? static_cast<void> (0) : __assert_fail ("isa<MCConstantExpr>(Memory.OffsetImm) && \"Unknown value type!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2696, __PRETTY_FUNCTION__))
;
2697 Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
2698 }
2699
2700 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2701 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2701, __PRETTY_FUNCTION__))
;
2702 Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
2703 }
2704
2705 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2706 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2706, __PRETTY_FUNCTION__))
;
2707 Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
2708 }
2709
2710 void addTraceSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2711 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2711, __PRETTY_FUNCTION__))
;
2712 Inst.addOperand(MCOperand::createImm(unsigned(getTraceSyncBarrierOpt())));
2713 }
2714
2715 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2716 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2716, __PRETTY_FUNCTION__))
;
2717 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2718 }
2719
2720 void addMemNoOffsetT2Operands(MCInst &Inst, unsigned N) const {
2721 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2721, __PRETTY_FUNCTION__))
;
2722 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2723 }
2724
2725 void addMemNoOffsetT2NoSpOperands(MCInst &Inst, unsigned N) const {
2726 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2726, __PRETTY_FUNCTION__))
;
2727 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2728 }
2729
2730 void addMemNoOffsetTOperands(MCInst &Inst, unsigned N) const {
2731 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2731, __PRETTY_FUNCTION__))
;
2732 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2733 }
2734
2735 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2736 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2736, __PRETTY_FUNCTION__))
;
2737 int32_t Imm = Memory.OffsetImm->getValue();
2738 Inst.addOperand(MCOperand::createImm(Imm));
2739 }
2740
2741 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2742 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2742, __PRETTY_FUNCTION__))
;
2743 assert(isImm() && "Not an immediate!")((isImm() && "Not an immediate!") ? static_cast<void
> (0) : __assert_fail ("isImm() && \"Not an immediate!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2743, __PRETTY_FUNCTION__))
;
2744
2745 // If we have an immediate that's not a constant, treat it as a label
2746 // reference needing a fixup.
2747 if (!isa<MCConstantExpr>(getImm())) {
2748 Inst.addOperand(MCOperand::createExpr(getImm()));
2749 return;
2750 }
2751
2752 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2753 int Val = CE->getValue();
2754 Inst.addOperand(MCOperand::createImm(Val));
2755 }
2756
2757 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2758 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2758, __PRETTY_FUNCTION__))
;
2759 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2760 Inst.addOperand(MCOperand::createImm(Memory.Alignment));
2761 }
2762
2763 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2764 addAlignedMemoryOperands(Inst, N);
2765 }
2766
2767 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2768 addAlignedMemoryOperands(Inst, N);
2769 }
2770
2771 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2772 addAlignedMemoryOperands(Inst, N);
2773 }
2774
2775 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2776 addAlignedMemoryOperands(Inst, N);
2777 }
2778
2779 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2780 addAlignedMemoryOperands(Inst, N);
2781 }
2782
2783 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2784 addAlignedMemoryOperands(Inst, N);
2785 }
2786
2787 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2788 addAlignedMemoryOperands(Inst, N);
2789 }
2790
2791 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2792 addAlignedMemoryOperands(Inst, N);
2793 }
2794
2795 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2796 addAlignedMemoryOperands(Inst, N);
2797 }
2798
2799 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2800 addAlignedMemoryOperands(Inst, N);
2801 }
2802
2803 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2804 addAlignedMemoryOperands(Inst, N);
2805 }
2806
2807 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2808 assert(N == 3 && "Invalid number of operands!")((N == 3 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 3 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2808, __PRETTY_FUNCTION__))
;
2809 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2810 if (!Memory.OffsetRegNum) {
2811 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2812 // Special case for #-0
2813 if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2814 if (Val < 0) Val = -Val;
2815 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2816 } else {
2817 // For register offset, we encode the shift type and negation flag
2818 // here.
2819 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2820 Memory.ShiftImm, Memory.ShiftType);
2821 }
2822 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2823 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2824 Inst.addOperand(MCOperand::createImm(Val));
2825 }
2826
2827 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2828 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2828, __PRETTY_FUNCTION__))
;
2829 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2830 assert(CE && "non-constant AM2OffsetImm operand!")((CE && "non-constant AM2OffsetImm operand!") ? static_cast
<void> (0) : __assert_fail ("CE && \"non-constant AM2OffsetImm operand!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2830, __PRETTY_FUNCTION__))
;
2831 int32_t Val = CE->getValue();
2832 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2833 // Special case for #-0
2834 if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2835 if (Val < 0) Val = -Val;
2836 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2837 Inst.addOperand(MCOperand::createReg(0));
2838 Inst.addOperand(MCOperand::createImm(Val));
2839 }
2840
2841 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2842 assert(N == 3 && "Invalid number of operands!")((N == 3 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 3 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2842, __PRETTY_FUNCTION__))
;
2843 // If we have an immediate that's not a constant, treat it as a label
2844 // reference needing a fixup. If it is a constant, it's something else
2845 // and we reject it.
2846 if (isImm()) {
2847 Inst.addOperand(MCOperand::createExpr(getImm()));
2848 Inst.addOperand(MCOperand::createReg(0));
2849 Inst.addOperand(MCOperand::createImm(0));
2850 return;
2851 }
2852
2853 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2854 if (!Memory.OffsetRegNum) {
2855 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2856 // Special case for #-0
2857 if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2858 if (Val < 0) Val = -Val;
2859 Val = ARM_AM::getAM3Opc(AddSub, Val);
2860 } else {
2861 // For register offset, we encode the shift type and negation flag
2862 // here.
2863 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2864 }
2865 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2866 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2867 Inst.addOperand(MCOperand::createImm(Val));
2868 }
2869
2870 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2871 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2871, __PRETTY_FUNCTION__))
;
2872 if (Kind == k_PostIndexRegister) {
2873 int32_t Val =
2874 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2875 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2876 Inst.addOperand(MCOperand::createImm(Val));
2877 return;
2878 }
2879
2880 // Constant offset.
2881 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2882 int32_t Val = CE->getValue();
2883 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2884 // Special case for #-0
2885 if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2886 if (Val < 0) Val = -Val;
2887 Val = ARM_AM::getAM3Opc(AddSub, Val);
2888 Inst.addOperand(MCOperand::createReg(0));
2889 Inst.addOperand(MCOperand::createImm(Val));
2890 }
2891
2892 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2893 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2893, __PRETTY_FUNCTION__))
;
2894 // If we have an immediate that's not a constant, treat it as a label
2895 // reference needing a fixup. If it is a constant, it's something else
2896 // and we reject it.
2897 if (isImm()) {
2898 Inst.addOperand(MCOperand::createExpr(getImm()));
2899 Inst.addOperand(MCOperand::createImm(0));
2900 return;
2901 }
2902
2903 // The lower two bits are always zero and as such are not encoded.
2904 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2905 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2906 // Special case for #-0
2907 if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2908 if (Val < 0) Val = -Val;
2909 Val = ARM_AM::getAM5Opc(AddSub, Val);
2910 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2911 Inst.addOperand(MCOperand::createImm(Val));
2912 }
2913
2914 void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {
2915 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2915, __PRETTY_FUNCTION__))
;
2916 // If we have an immediate that's not a constant, treat it as a label
2917 // reference needing a fixup. If it is a constant, it's something else
2918 // and we reject it.
2919 if (isImm()) {
2920 Inst.addOperand(MCOperand::createExpr(getImm()));
2921 Inst.addOperand(MCOperand::createImm(0));
2922 return;
2923 }
2924
2925 // The lower bit is always zero and as such is not encoded.
2926 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 2 : 0;
2927 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2928 // Special case for #-0
2929 if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2930 if (Val < 0) Val = -Val;
2931 Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
2932 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2933 Inst.addOperand(MCOperand::createImm(Val));
2934 }
2935
2936 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2937 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2937, __PRETTY_FUNCTION__))
;
2938 // If we have an immediate that's not a constant, treat it as a label
2939 // reference needing a fixup. If it is a constant, it's something else
2940 // and we reject it.
2941 if (isImm()) {
2942 Inst.addOperand(MCOperand::createExpr(getImm()));
2943 Inst.addOperand(MCOperand::createImm(0));
2944 return;
2945 }
2946
2947 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2948 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2949 Inst.addOperand(MCOperand::createImm(Val));
2950 }
2951
2952 void addMemImm7s4OffsetOperands(MCInst &Inst, unsigned N) const {
2953 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2953, __PRETTY_FUNCTION__))
;
2954 // If we have an immediate that's not a constant, treat it as a label
2955 // reference needing a fixup. If it is a constant, it's something else
2956 // and we reject it.
2957 if (isImm()) {
2958 Inst.addOperand(MCOperand::createExpr(getImm()));
2959 Inst.addOperand(MCOperand::createImm(0));
2960 return;
2961 }
2962
2963 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2964 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2965 Inst.addOperand(MCOperand::createImm(Val));
2966 }
2967
2968 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2969 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2969, __PRETTY_FUNCTION__))
;
2970 // The lower two bits are always zero and as such are not encoded.
2971 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2972 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2973 Inst.addOperand(MCOperand::createImm(Val));
2974 }
2975
2976 void addMemImmOffsetOperands(MCInst &Inst, unsigned N) const {
2977 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2977, __PRETTY_FUNCTION__))
;
2978 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2979 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2980 Inst.addOperand(MCOperand::createImm(Val));
2981 }
2982
2983 void addMemRegRQOffsetOperands(MCInst &Inst, unsigned N) const {
2984 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2984, __PRETTY_FUNCTION__))
;
2985 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2986 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2987 }
2988
2989 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2990 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 2990, __PRETTY_FUNCTION__))
;
2991 // If this is an immediate, it's a label reference.
2992 if (isImm()) {
2993 addExpr(Inst, getImm());
2994 Inst.addOperand(MCOperand::createImm(0));
2995 return;
2996 }
2997
2998 // Otherwise, it's a normal memory reg+offset.
2999 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
3000 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3001 Inst.addOperand(MCOperand::createImm(Val));
3002 }
3003
3004 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
3005 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3005, __PRETTY_FUNCTION__))
;
3006 // If this is an immediate, it's a label reference.
3007 if (isImm()) {
3008 addExpr(Inst, getImm());
3009 Inst.addOperand(MCOperand::createImm(0));
3010 return;
3011 }
3012
3013 // Otherwise, it's a normal memory reg+offset.
3014 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
3015 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3016 Inst.addOperand(MCOperand::createImm(Val));
3017 }
3018
3019 void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const {
3020 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3020, __PRETTY_FUNCTION__))
;
3021 // This is container for the immediate that we will create the constant
3022 // pool from
3023 addExpr(Inst, getConstantPoolImm());
3024 return;
3025 }
3026
3027 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
3028 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3028, __PRETTY_FUNCTION__))
;
3029 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3030 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3031 }
3032
3033 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
3034 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3034, __PRETTY_FUNCTION__))
;
3035 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3036 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3037 }
3038
3039 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
3040 assert(N == 3 && "Invalid number of operands!")((N == 3 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 3 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3040, __PRETTY_FUNCTION__))
;
3041 unsigned Val =
3042 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
3043 Memory.ShiftImm, Memory.ShiftType);
3044 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3045 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3046 Inst.addOperand(MCOperand::createImm(Val));
3047 }
3048
3049 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
3050 assert(N == 3 && "Invalid number of operands!")((N == 3 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 3 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3050, __PRETTY_FUNCTION__))
;
3051 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3052 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3053 Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
3054 }
3055
3056 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
3057 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3057, __PRETTY_FUNCTION__))
;
3058 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3059 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3060 }
3061
3062 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
3063 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3063, __PRETTY_FUNCTION__))
;
3064 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
3065 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3066 Inst.addOperand(MCOperand::createImm(Val));
3067 }
3068
3069 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
3070 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3070, __PRETTY_FUNCTION__))
;
3071 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
3072 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3073 Inst.addOperand(MCOperand::createImm(Val));
3074 }
3075
3076 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
3077 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3077, __PRETTY_FUNCTION__))
;
3078 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
3079 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3080 Inst.addOperand(MCOperand::createImm(Val));
3081 }
3082
3083 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
3084 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3084, __PRETTY_FUNCTION__))
;
3085 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
3086 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3087 Inst.addOperand(MCOperand::createImm(Val));
3088 }
3089
3090 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
3091 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3091, __PRETTY_FUNCTION__))
;
3092 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3093 assert(CE && "non-constant post-idx-imm8 operand!")((CE && "non-constant post-idx-imm8 operand!") ? static_cast
<void> (0) : __assert_fail ("CE && \"non-constant post-idx-imm8 operand!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3093, __PRETTY_FUNCTION__))
;
3094 int Imm = CE->getValue();
3095 bool isAdd = Imm >= 0;
3096 if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
3097 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
3098 Inst.addOperand(MCOperand::createImm(Imm));
3099 }
3100
3101 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
3102 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3102, __PRETTY_FUNCTION__))
;
3103 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3104 assert(CE && "non-constant post-idx-imm8s4 operand!")((CE && "non-constant post-idx-imm8s4 operand!") ? static_cast
<void> (0) : __assert_fail ("CE && \"non-constant post-idx-imm8s4 operand!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3104, __PRETTY_FUNCTION__))
;
3105 int Imm = CE->getValue();
3106 bool isAdd = Imm >= 0;
3107 if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
3108 // Immediate is scaled by 4.
3109 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
3110 Inst.addOperand(MCOperand::createImm(Imm));
3111 }
3112
3113 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
3114 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3114, __PRETTY_FUNCTION__))
;
3115 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
3116 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
3117 }
3118
3119 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
3120 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3120, __PRETTY_FUNCTION__))
;
3121 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
3122 // The sign, shift type, and shift amount are encoded in a single operand
3123 // using the AM2 encoding helpers.
3124 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
3125 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
3126 PostIdxReg.ShiftTy);
3127 Inst.addOperand(MCOperand::createImm(Imm));
3128 }
3129
3130 void addPowerTwoOperands(MCInst &Inst, unsigned N) const {
3131 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3131, __PRETTY_FUNCTION__))
;
3132 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3133 Inst.addOperand(MCOperand::createImm(CE->getValue()));
3134 }
3135
3136 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
3137 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3137, __PRETTY_FUNCTION__))
;
3138 Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
3139 }
3140
3141 void addBankedRegOperands(MCInst &Inst, unsigned N) const {
3142 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3142, __PRETTY_FUNCTION__))
;
3143 Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
3144 }
3145
3146 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
3147 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3147, __PRETTY_FUNCTION__))
;
3148 Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
3149 }
3150
3151 void addVecListOperands(MCInst &Inst, unsigned N) const {
3152 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3152, __PRETTY_FUNCTION__))
;
3153 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
3154 }
3155
3156 void addMVEVecListOperands(MCInst &Inst, unsigned N) const {
3157 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3157, __PRETTY_FUNCTION__))
;
3158
3159 // When we come here, the VectorList field will identify a range
3160 // of q-registers by its base register and length, and it will
3161 // have already been error-checked to be the expected length of
3162 // range and contain only q-regs in the range q0-q7. So we can
3163 // count on the base register being in the range q0-q6 (for 2
3164 // regs) or q0-q4 (for 4)
3165 //
3166 // The MVE instructions taking a register range of this kind will
3167 // need an operand in the QQPR or QQQQPR class, representing the
3168 // entire range as a unit. So we must translate into that class,
3169 // by finding the index of the base register in the MQPR reg
3170 // class, and returning the super-register at the corresponding
3171 // index in the target class.
3172
3173 const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID];
3174 const MCRegisterClass *RC_out = (VectorList.Count == 2) ?
3175 &ARMMCRegisterClasses[ARM::QQPRRegClassID] :
3176 &ARMMCRegisterClasses[ARM::QQQQPRRegClassID];
3177
3178 unsigned I, E = RC_out->getNumRegs();
3179 for (I = 0; I < E; I++)
3180 if (RC_in->getRegister(I) == VectorList.RegNum)
3181 break;
3182 assert(I < E && "Invalid vector list start register!")((I < E && "Invalid vector list start register!") ?
static_cast<void> (0) : __assert_fail ("I < E && \"Invalid vector list start register!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3182, __PRETTY_FUNCTION__))
;
3183
3184 Inst.addOperand(MCOperand::createReg(RC_out->getRegister(I)));
3185 }
3186
3187 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
3188 assert(N == 2 && "Invalid number of operands!")((N == 2 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3188, __PRETTY_FUNCTION__))
;
3189 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
3190 Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
3191 }
3192
3193 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
3194 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3194, __PRETTY_FUNCTION__))
;
3195 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3196 }
3197
3198 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
3199 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3199, __PRETTY_FUNCTION__))
;
3200 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3201 }
3202
3203 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
3204 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3204, __PRETTY_FUNCTION__))
;
3205 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3206 }
3207
3208 void addVectorIndex64Operands(MCInst &Inst, unsigned N) const {
3209 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3209, __PRETTY_FUNCTION__))
;
3210 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3211 }
3212
3213 void addMVEVectorIndexOperands(MCInst &Inst, unsigned N) const {
3214 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3214, __PRETTY_FUNCTION__))
;
3215 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3216 }
3217
3218 void addMVEPairVectorIndexOperands(MCInst &Inst, unsigned N) const {
3219 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3219, __PRETTY_FUNCTION__))
;
3220 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3221 }
3222
3223 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
3224 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3224, __PRETTY_FUNCTION__))
;
3225 // The immediate encodes the type of constant as well as the value.
3226 // Mask in that this is an i8 splat.
3227 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3228 Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
3229 }
3230
3231 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
3232 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3232, __PRETTY_FUNCTION__))
;
3233 // The immediate encodes the type of constant as well as the value.
3234 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3235 unsigned Value = CE->getValue();
3236 Value = ARM_AM::encodeNEONi16splat(Value);
3237 Inst.addOperand(MCOperand::createImm(Value));
3238 }
3239
3240 void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
3241 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3241, __PRETTY_FUNCTION__))
;
3242 // The immediate encodes the type of constant as well as the value.
3243 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3244 unsigned Value = CE->getValue();
3245 Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
3246 Inst.addOperand(MCOperand::createImm(Value));
3247 }
3248
3249 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
3250 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3250, __PRETTY_FUNCTION__))
;
3251 // The immediate encodes the type of constant as well as the value.
3252 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3253 unsigned Value = CE->getValue();
3254 Value = ARM_AM::encodeNEONi32splat(Value);
3255 Inst.addOperand(MCOperand::createImm(Value));
3256 }
3257
3258 void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
3259 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3259, __PRETTY_FUNCTION__))
;
3260 // The immediate encodes the type of constant as well as the value.
3261 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3262 unsigned Value = CE->getValue();
3263 Value = ARM_AM::encodeNEONi32splat(~Value);
3264 Inst.addOperand(MCOperand::createImm(Value));
3265 }
3266
3267 void addNEONi8ReplicateOperands(MCInst &Inst, bool Inv) const {
3268 // The immediate encodes the type of constant as well as the value.
3269 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3270 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||(((Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM
::VMOVv16i8) && "All instructions that wants to replicate non-zero byte "
"always must be replaced with VMOVv8i8 or VMOVv16i8.") ? static_cast
<void> (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM::VMOVv16i8) && \"All instructions that wants to replicate non-zero byte \" \"always must be replaced with VMOVv8i8 or VMOVv16i8.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3273, __PRETTY_FUNCTION__))
3271 Inst.getOpcode() == ARM::VMOVv16i8) &&(((Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM
::VMOVv16i8) && "All instructions that wants to replicate non-zero byte "
"always must be replaced with VMOVv8i8 or VMOVv16i8.") ? static_cast
<void> (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM::VMOVv16i8) && \"All instructions that wants to replicate non-zero byte \" \"always must be replaced with VMOVv8i8 or VMOVv16i8.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3273, __PRETTY_FUNCTION__))
3272 "All instructions that wants to replicate non-zero byte "(((Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM
::VMOVv16i8) && "All instructions that wants to replicate non-zero byte "
"always must be replaced with VMOVv8i8 or VMOVv16i8.") ? static_cast
<void> (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM::VMOVv16i8) && \"All instructions that wants to replicate non-zero byte \" \"always must be replaced with VMOVv8i8 or VMOVv16i8.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3273, __PRETTY_FUNCTION__))
3273 "always must be replaced with VMOVv8i8 or VMOVv16i8.")(((Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM
::VMOVv16i8) && "All instructions that wants to replicate non-zero byte "
"always must be replaced with VMOVv8i8 or VMOVv16i8.") ? static_cast
<void> (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM::VMOVv16i8) && \"All instructions that wants to replicate non-zero byte \" \"always must be replaced with VMOVv8i8 or VMOVv16i8.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3273, __PRETTY_FUNCTION__))
;
3274 unsigned Value = CE->getValue();
3275 if (Inv)
3276 Value = ~Value;
3277 unsigned B = Value & 0xff;
3278 B |= 0xe00; // cmode = 0b1110
3279 Inst.addOperand(MCOperand::createImm(B));
3280 }
3281
3282 void addNEONinvi8ReplicateOperands(MCInst &Inst, unsigned N) const {
3283 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3283, __PRETTY_FUNCTION__))
;
3284 addNEONi8ReplicateOperands(Inst, true);
3285 }
3286
3287 static unsigned encodeNeonVMOVImmediate(unsigned Value) {
3288 if (Value >= 256 && Value <= 0xffff)
3289 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
3290 else if (Value > 0xffff && Value <= 0xffffff)
3291 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
3292 else if (Value > 0xffffff)
3293 Value = (Value >> 24) | 0x600;
3294 return Value;
3295 }
3296
3297 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
3298 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3298, __PRETTY_FUNCTION__))
;
3299 // The immediate encodes the type of constant as well as the value.
3300 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3301 unsigned Value = encodeNeonVMOVImmediate(CE->getValue());
3302 Inst.addOperand(MCOperand::createImm(Value));
3303 }
3304
3305 void addNEONvmovi8ReplicateOperands(MCInst &Inst, unsigned N) const {
3306 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3306, __PRETTY_FUNCTION__))
;
3307 addNEONi8ReplicateOperands(Inst, false);
3308 }
3309
3310 void addNEONvmovi16ReplicateOperands(MCInst &Inst, unsigned N) const {
3311 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3311, __PRETTY_FUNCTION__))
;
3312 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3313 assert((Inst.getOpcode() == ARM::VMOVv4i16 ||(((Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM
::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode
() == ARM::VMVNv8i16) && "All instructions that want to replicate non-zero half-word "
"always must be replaced with V{MOV,MVN}v{4,8}i16.") ? static_cast
<void> (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && \"All instructions that want to replicate non-zero half-word \" \"always must be replaced with V{MOV,MVN}v{4,8}i16.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3318, __PRETTY_FUNCTION__))
3314 Inst.getOpcode() == ARM::VMOVv8i16 ||(((Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM
::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode
() == ARM::VMVNv8i16) && "All instructions that want to replicate non-zero half-word "
"always must be replaced with V{MOV,MVN}v{4,8}i16.") ? static_cast
<void> (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && \"All instructions that want to replicate non-zero half-word \" \"always must be replaced with V{MOV,MVN}v{4,8}i16.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3318, __PRETTY_FUNCTION__))
3315 Inst.getOpcode() == ARM::VMVNv4i16 ||(((Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM
::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode
() == ARM::VMVNv8i16) && "All instructions that want to replicate non-zero half-word "
"always must be replaced with V{MOV,MVN}v{4,8}i16.") ? static_cast
<void> (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && \"All instructions that want to replicate non-zero half-word \" \"always must be replaced with V{MOV,MVN}v{4,8}i16.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3318, __PRETTY_FUNCTION__))
3316 Inst.getOpcode() == ARM::VMVNv8i16) &&(((Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM
::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode
() == ARM::VMVNv8i16) && "All instructions that want to replicate non-zero half-word "
"always must be replaced with V{MOV,MVN}v{4,8}i16.") ? static_cast
<void> (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && \"All instructions that want to replicate non-zero half-word \" \"always must be replaced with V{MOV,MVN}v{4,8}i16.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3318, __PRETTY_FUNCTION__))
3317 "All instructions that want to replicate non-zero half-word "(((Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM
::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode
() == ARM::VMVNv8i16) && "All instructions that want to replicate non-zero half-word "
"always must be replaced with V{MOV,MVN}v{4,8}i16.") ? static_cast
<void> (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && \"All instructions that want to replicate non-zero half-word \" \"always must be replaced with V{MOV,MVN}v{4,8}i16.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3318, __PRETTY_FUNCTION__))
3318 "always must be replaced with V{MOV,MVN}v{4,8}i16.")(((Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM
::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode
() == ARM::VMVNv8i16) && "All instructions that want to replicate non-zero half-word "
"always must be replaced with V{MOV,MVN}v{4,8}i16.") ? static_cast
<void> (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && \"All instructions that want to replicate non-zero half-word \" \"always must be replaced with V{MOV,MVN}v{4,8}i16.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3318, __PRETTY_FUNCTION__))
;
3319 uint64_t Value = CE->getValue();
3320 unsigned Elem = Value & 0xffff;
3321 if (Elem >= 256)
3322 Elem = (Elem >> 8) | 0x200;
3323 Inst.addOperand(MCOperand::createImm(Elem));
3324 }
3325
3326 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
3327 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3327, __PRETTY_FUNCTION__))
;
3328 // The immediate encodes the type of constant as well as the value.
3329 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3330 unsigned Value = encodeNeonVMOVImmediate(~CE->getValue());
3331 Inst.addOperand(MCOperand::createImm(Value));
3332 }
3333
3334 void addNEONvmovi32ReplicateOperands(MCInst &Inst, unsigned N) const {
3335 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3335, __PRETTY_FUNCTION__))
;
3336 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3337 assert((Inst.getOpcode() == ARM::VMOVv2i32 ||(((Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM
::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode
() == ARM::VMVNv4i32) && "All instructions that want to replicate non-zero word "
"always must be replaced with V{MOV,MVN}v{2,4}i32.") ? static_cast
<void> (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && \"All instructions that want to replicate non-zero word \" \"always must be replaced with V{MOV,MVN}v{2,4}i32.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3342, __PRETTY_FUNCTION__))
3338 Inst.getOpcode() == ARM::VMOVv4i32 ||(((Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM
::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode
() == ARM::VMVNv4i32) && "All instructions that want to replicate non-zero word "
"always must be replaced with V{MOV,MVN}v{2,4}i32.") ? static_cast
<void> (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && \"All instructions that want to replicate non-zero word \" \"always must be replaced with V{MOV,MVN}v{2,4}i32.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3342, __PRETTY_FUNCTION__))
3339 Inst.getOpcode() == ARM::VMVNv2i32 ||(((Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM
::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode
() == ARM::VMVNv4i32) && "All instructions that want to replicate non-zero word "
"always must be replaced with V{MOV,MVN}v{2,4}i32.") ? static_cast
<void> (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && \"All instructions that want to replicate non-zero word \" \"always must be replaced with V{MOV,MVN}v{2,4}i32.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3342, __PRETTY_FUNCTION__))
3340 Inst.getOpcode() == ARM::VMVNv4i32) &&(((Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM
::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode
() == ARM::VMVNv4i32) && "All instructions that want to replicate non-zero word "
"always must be replaced with V{MOV,MVN}v{2,4}i32.") ? static_cast
<void> (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && \"All instructions that want to replicate non-zero word \" \"always must be replaced with V{MOV,MVN}v{2,4}i32.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3342, __PRETTY_FUNCTION__))
3341 "All instructions that want to replicate non-zero word "(((Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM
::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode
() == ARM::VMVNv4i32) && "All instructions that want to replicate non-zero word "
"always must be replaced with V{MOV,MVN}v{2,4}i32.") ? static_cast
<void> (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && \"All instructions that want to replicate non-zero word \" \"always must be replaced with V{MOV,MVN}v{2,4}i32.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3342, __PRETTY_FUNCTION__))
3342 "always must be replaced with V{MOV,MVN}v{2,4}i32.")(((Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM
::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode
() == ARM::VMVNv4i32) && "All instructions that want to replicate non-zero word "
"always must be replaced with V{MOV,MVN}v{2,4}i32.") ? static_cast
<void> (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && \"All instructions that want to replicate non-zero word \" \"always must be replaced with V{MOV,MVN}v{2,4}i32.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3342, __PRETTY_FUNCTION__))
;
3343 uint64_t Value = CE->getValue();
3344 unsigned Elem = encodeNeonVMOVImmediate(Value & 0xffffffff);
3345 Inst.addOperand(MCOperand::createImm(Elem));
3346 }
3347
3348 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
3349 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3349, __PRETTY_FUNCTION__))
;
3350 // The immediate encodes the type of constant as well as the value.
3351 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3352 uint64_t Value = CE->getValue();
3353 unsigned Imm = 0;
3354 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
3355 Imm |= (Value & 1) << i;
3356 }
3357 Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
3358 }
3359
3360 void addComplexRotationEvenOperands(MCInst &Inst, unsigned N) const {
3361 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3361, __PRETTY_FUNCTION__))
;
3362 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3363 Inst.addOperand(MCOperand::createImm(CE->getValue() / 90));
3364 }
3365
3366 void addComplexRotationOddOperands(MCInst &Inst, unsigned N) const {
3367 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3367, __PRETTY_FUNCTION__))
;
3368 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3369 Inst.addOperand(MCOperand::createImm((CE->getValue() - 90) / 180));
3370 }
3371
3372 void addMveSaturateOperands(MCInst &Inst, unsigned N) const {
3373 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3373, __PRETTY_FUNCTION__))
;
3374 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3375 unsigned Imm = CE->getValue();
3376 assert((Imm == 48 || Imm == 64) && "Invalid saturate operand")(((Imm == 48 || Imm == 64) && "Invalid saturate operand"
) ? static_cast<void> (0) : __assert_fail ("(Imm == 48 || Imm == 64) && \"Invalid saturate operand\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3376, __PRETTY_FUNCTION__))
;
3377 Inst.addOperand(MCOperand::createImm(Imm == 48 ? 1 : 0));
3378 }
3379
3380 void print(raw_ostream &OS) const override;
3381
3382 static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
3383 auto Op = std::make_unique<ARMOperand>(k_ITCondMask);
3384 Op->ITMask.Mask = Mask;
3385 Op->StartLoc = S;
3386 Op->EndLoc = S;
3387 return Op;
3388 }
3389
3390 static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
3391 SMLoc S) {
3392 auto Op = std::make_unique<ARMOperand>(k_CondCode);
3393 Op->CC.Val = CC;
3394 Op->StartLoc = S;
3395 Op->EndLoc = S;
3396 return Op;
3397 }
3398
3399 static std::unique_ptr<ARMOperand> CreateVPTPred(ARMVCC::VPTCodes CC,
3400 SMLoc S) {
3401 auto Op = std::make_unique<ARMOperand>(k_VPTPred);
3402 Op->VCC.Val = CC;
3403 Op->StartLoc = S;
3404 Op->EndLoc = S;
3405 return Op;
3406 }
3407
3408 static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
3409 auto Op = std::make_unique<ARMOperand>(k_CoprocNum);
3410 Op->Cop.Val = CopVal;
3411 Op->StartLoc = S;
3412 Op->EndLoc = S;
3413 return Op;
3414 }
3415
3416 static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
3417 auto Op = std::make_unique<ARMOperand>(k_CoprocReg);
3418 Op->Cop.Val = CopVal;
3419 Op->StartLoc = S;
3420 Op->EndLoc = S;
3421 return Op;
3422 }
3423
3424 static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
3425 SMLoc E) {
3426 auto Op = std::make_unique<ARMOperand>(k_CoprocOption);
3427 Op->Cop.Val = Val;
3428 Op->StartLoc = S;
3429 Op->EndLoc = E;
3430 return Op;
3431 }
3432
3433 static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
3434 auto Op = std::make_unique<ARMOperand>(k_CCOut);
3435 Op->Reg.RegNum = RegNum;
3436 Op->StartLoc = S;
3437 Op->EndLoc = S;
3438 return Op;
3439 }
3440
3441 static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
3442 auto Op = std::make_unique<ARMOperand>(k_Token);
3443 Op->Tok.Data = Str.data();
3444 Op->Tok.Length = Str.size();
3445 Op->StartLoc = S;
3446 Op->EndLoc = S;
3447 return Op;
3448 }
3449
3450 static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
3451 SMLoc E) {
3452 auto Op = std::make_unique<ARMOperand>(k_Register);
3453 Op->Reg.RegNum = RegNum;
3454 Op->StartLoc = S;
3455 Op->EndLoc = E;
3456 return Op;
3457 }
3458
3459 static std::unique_ptr<ARMOperand>
3460 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
3461 unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
3462 SMLoc E) {
3463 auto Op = std::make_unique<ARMOperand>(k_ShiftedRegister);
3464 Op->RegShiftedReg.ShiftTy = ShTy;
3465 Op->RegShiftedReg.SrcReg = SrcReg;
3466 Op->RegShiftedReg.ShiftReg = ShiftReg;
3467 Op->RegShiftedReg.ShiftImm = ShiftImm;
3468 Op->StartLoc = S;
3469 Op->EndLoc = E;
3470 return Op;
3471 }
3472
3473 static std::unique_ptr<ARMOperand>
3474 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
3475 unsigned ShiftImm, SMLoc S, SMLoc E) {
3476 auto Op = std::make_unique<ARMOperand>(k_ShiftedImmediate);
3477 Op->RegShiftedImm.ShiftTy = ShTy;
3478 Op->RegShiftedImm.SrcReg = SrcReg;
3479 Op->RegShiftedImm.ShiftImm = ShiftImm;
3480 Op->StartLoc = S;
3481 Op->EndLoc = E;
3482 return Op;
3483 }
3484
3485 static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
3486 SMLoc S, SMLoc E) {
3487 auto Op = std::make_unique<ARMOperand>(k_ShifterImmediate);
3488 Op->ShifterImm.isASR = isASR;
3489 Op->ShifterImm.Imm = Imm;
3490 Op->StartLoc = S;
3491 Op->EndLoc = E;
3492 return Op;
3493 }
3494
3495 static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
3496 SMLoc E) {
3497 auto Op = std::make_unique<ARMOperand>(k_RotateImmediate);
3498 Op->RotImm.Imm = Imm;
3499 Op->StartLoc = S;
3500 Op->EndLoc = E;
3501 return Op;
3502 }
3503
3504 static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
3505 SMLoc S, SMLoc E) {
3506 auto Op = std::make_unique<ARMOperand>(k_ModifiedImmediate);
3507 Op->ModImm.Bits = Bits;
3508 Op->ModImm.Rot = Rot;
3509 Op->StartLoc = S;
3510 Op->EndLoc = E;
3511 return Op;
3512 }
3513
3514 static std::unique_ptr<ARMOperand>
3515 CreateConstantPoolImm(const MCExpr *Val, SMLoc S, SMLoc E) {
3516 auto Op = std::make_unique<ARMOperand>(k_ConstantPoolImmediate);
3517 Op->Imm.Val = Val;
3518 Op->StartLoc = S;
3519 Op->EndLoc = E;
3520 return Op;
3521 }
3522
3523 static std::unique_ptr<ARMOperand>
3524 CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
3525 auto Op = std::make_unique<ARMOperand>(k_BitfieldDescriptor);
3526 Op->Bitfield.LSB = LSB;
3527 Op->Bitfield.Width = Width;
3528 Op->StartLoc = S;
3529 Op->EndLoc = E;
3530 return Op;
3531 }
3532
3533 static std::unique_ptr<ARMOperand>
3534 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
3535 SMLoc StartLoc, SMLoc EndLoc) {
3536 assert(Regs.size() > 0 && "RegList contains no registers?")((Regs.size() > 0 && "RegList contains no registers?"
) ? static_cast<void> (0) : __assert_fail ("Regs.size() > 0 && \"RegList contains no registers?\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3536, __PRETTY_FUNCTION__))
;
3537 KindTy Kind = k_RegisterList;
3538
3539 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
3540 Regs.front().second)) {
3541 if (Regs.back().second == ARM::VPR)
3542 Kind = k_FPDRegisterListWithVPR;
3543 else
3544 Kind = k_DPRRegisterList;
3545 } else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(
3546 Regs.front().second)) {
3547 if (Regs.back().second == ARM::VPR)
3548 Kind = k_FPSRegisterListWithVPR;
3549 else
3550 Kind = k_SPRRegisterList;
3551 }
3552
3553 if (Kind == k_RegisterList && Regs.back().second == ARM::APSR)
3554 Kind = k_RegisterListWithAPSR;
3555
3556 assert(std::is_sorted(Regs.begin(), Regs.end()) &&((std::is_sorted(Regs.begin(), Regs.end()) && "Register list must be sorted by encoding"
) ? static_cast<void> (0) : __assert_fail ("std::is_sorted(Regs.begin(), Regs.end()) && \"Register list must be sorted by encoding\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3557, __PRETTY_FUNCTION__))
3557 "Register list must be sorted by encoding")((std::is_sorted(Regs.begin(), Regs.end()) && "Register list must be sorted by encoding"
) ? static_cast<void> (0) : __assert_fail ("std::is_sorted(Regs.begin(), Regs.end()) && \"Register list must be sorted by encoding\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3557, __PRETTY_FUNCTION__))
;
3558
3559 auto Op = std::make_unique<ARMOperand>(Kind);
3560 for (const auto &P : Regs)
3561 Op->Registers.push_back(P.second);
3562
3563 Op->StartLoc = StartLoc;
3564 Op->EndLoc = EndLoc;
3565 return Op;
3566 }
3567
3568 static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
3569 unsigned Count,
3570 bool isDoubleSpaced,
3571 SMLoc S, SMLoc E) {
3572 auto Op = std::make_unique<ARMOperand>(k_VectorList);
3573 Op->VectorList.RegNum = RegNum;
3574 Op->VectorList.Count = Count;
3575 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3576 Op->StartLoc = S;
3577 Op->EndLoc = E;
3578 return Op;
3579 }
3580
3581 static std::unique_ptr<ARMOperand>
3582 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
3583 SMLoc S, SMLoc E) {
3584 auto Op = std::make_unique<ARMOperand>(k_VectorListAllLanes);
3585 Op->VectorList.RegNum = RegNum;
3586 Op->VectorList.Count = Count;
3587 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3588 Op->StartLoc = S;
3589 Op->EndLoc = E;
3590 return Op;
3591 }
3592
3593 static std::unique_ptr<ARMOperand>
3594 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
3595 bool isDoubleSpaced, SMLoc S, SMLoc E) {
3596 auto Op = std::make_unique<ARMOperand>(k_VectorListIndexed);
3597 Op->VectorList.RegNum = RegNum;
3598 Op->VectorList.Count = Count;
3599 Op->VectorList.LaneIndex = Index;
3600 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3601 Op->StartLoc = S;
3602 Op->EndLoc = E;
3603 return Op;
3604 }
3605
3606 static std::unique_ptr<ARMOperand>
3607 CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
3608 auto Op = std::make_unique<ARMOperand>(k_VectorIndex);
3609 Op->VectorIndex.Val = Idx;
3610 Op->StartLoc = S;
3611 Op->EndLoc = E;
3612 return Op;
3613 }
3614
3615 static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
3616 SMLoc E) {
3617 auto Op = std::make_unique<ARMOperand>(k_Immediate);
3618 Op->Imm.Val = Val;
3619 Op->StartLoc = S;
3620 Op->EndLoc = E;
3621 return Op;
3622 }
3623
3624 static std::unique_ptr<ARMOperand>
3625 CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
3626 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
3627 unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
3628 SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
3629 auto Op = std::make_unique<ARMOperand>(k_Memory);
3630 Op->Memory.BaseRegNum = BaseRegNum;
3631 Op->Memory.OffsetImm = OffsetImm;
3632 Op->Memory.OffsetRegNum = OffsetRegNum;
3633 Op->Memory.ShiftType = ShiftType;
3634 Op->Memory.ShiftImm = ShiftImm;
3635 Op->Memory.Alignment = Alignment;
3636 Op->Memory.isNegative = isNegative;
3637 Op->StartLoc = S;
3638 Op->EndLoc = E;
3639 Op->AlignmentLoc = AlignmentLoc;
3640 return Op;
3641 }
3642
3643 static std::unique_ptr<ARMOperand>
3644 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
3645 unsigned ShiftImm, SMLoc S, SMLoc E) {
3646 auto Op = std::make_unique<ARMOperand>(k_PostIndexRegister);
3647 Op->PostIdxReg.RegNum = RegNum;
3648 Op->PostIdxReg.isAdd = isAdd;
3649 Op->PostIdxReg.ShiftTy = ShiftTy;
3650 Op->PostIdxReg.ShiftImm = ShiftImm;
3651 Op->StartLoc = S;
3652 Op->EndLoc = E;
3653 return Op;
3654 }
3655
3656 static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
3657 SMLoc S) {
3658 auto Op = std::make_unique<ARMOperand>(k_MemBarrierOpt);
3659 Op->MBOpt.Val = Opt;
3660 Op->StartLoc = S;
3661 Op->EndLoc = S;
3662 return Op;
3663 }
3664
3665 static std::unique_ptr<ARMOperand>
3666 CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
3667 auto Op = std::make_unique<ARMOperand>(k_InstSyncBarrierOpt);
3668 Op->ISBOpt.Val = Opt;
3669 Op->StartLoc = S;
3670 Op->EndLoc = S;
3671 return Op;
3672 }
3673
3674 static std::unique_ptr<ARMOperand>
3675 CreateTraceSyncBarrierOpt(ARM_TSB::TraceSyncBOpt Opt, SMLoc S) {
3676 auto Op = std::make_unique<ARMOperand>(k_TraceSyncBarrierOpt);
3677 Op->TSBOpt.Val = Opt;
3678 Op->StartLoc = S;
3679 Op->EndLoc = S;
3680 return Op;
3681 }
3682
3683 static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
3684 SMLoc S) {
3685 auto Op = std::make_unique<ARMOperand>(k_ProcIFlags);
3686 Op->IFlags.Val = IFlags;
3687 Op->StartLoc = S;
3688 Op->EndLoc = S;
3689 return Op;
3690 }
3691
3692 static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
3693 auto Op = std::make_unique<ARMOperand>(k_MSRMask);
3694 Op->MMask.Val = MMask;
3695 Op->StartLoc = S;
3696 Op->EndLoc = S;
3697 return Op;
3698 }
3699
3700 static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
3701 auto Op = std::make_unique<ARMOperand>(k_BankedReg);
3702 Op->BankedReg.Val = Reg;
3703 Op->StartLoc = S;
3704 Op->EndLoc = S;
3705 return Op;
3706 }
3707};
3708
3709} // end anonymous namespace.
3710
3711void ARMOperand::print(raw_ostream &OS) const {
3712 auto RegName = [](unsigned Reg) {
3713 if (Reg)
3714 return ARMInstPrinter::getRegisterName(Reg);
3715 else
3716 return "noreg";
3717 };
3718
3719 switch (Kind) {
3720 case k_CondCode:
3721 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
3722 break;
3723 case k_VPTPred:
3724 OS << "<ARMVCC::" << ARMVPTPredToString(getVPTPred()) << ">";
3725 break;
3726 case k_CCOut:
3727 OS << "<ccout " << RegName(getReg()) << ">";
3728 break;
3729 case k_ITCondMask: {
3730 static const char *const MaskStr[] = {
3731 "(invalid)", "(tttt)", "(ttt)", "(ttte)",
3732 "(tt)", "(ttet)", "(tte)", "(ttee)",
3733 "(t)", "(tett)", "(tet)", "(tete)",
3734 "(te)", "(teet)", "(tee)", "(teee)",
3735 };
3736 assert((ITMask.Mask & 0xf) == ITMask.Mask)(((ITMask.Mask & 0xf) == ITMask.Mask) ? static_cast<void
> (0) : __assert_fail ("(ITMask.Mask & 0xf) == ITMask.Mask"
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 3736, __PRETTY_FUNCTION__))
;
3737 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
3738 break;
3739 }
3740 case k_CoprocNum:
3741 OS << "<coprocessor number: " << getCoproc() << ">";
3742 break;
3743 case k_CoprocReg:
3744 OS << "<coprocessor register: " << getCoproc() << ">";
3745 break;
3746 case k_CoprocOption:
3747 OS << "<coprocessor option: " << CoprocOption.Val << ">";
3748 break;
3749 case k_MSRMask:
3750 OS << "<mask: " << getMSRMask() << ">";
3751 break;
3752 case k_BankedReg:
3753 OS << "<banked reg: " << getBankedReg() << ">";
3754 break;
3755 case k_Immediate:
3756 OS << *getImm();
3757 break;
3758 case k_MemBarrierOpt:
3759 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
3760 break;
3761 case k_InstSyncBarrierOpt:
3762 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
3763 break;
3764 case k_TraceSyncBarrierOpt:
3765 OS << "<ARM_TSB::" << TraceSyncBOptToString(getTraceSyncBarrierOpt()) << ">";
3766 break;
3767 case k_Memory:
3768 OS << "<memory";
3769 if (Memory.BaseRegNum)
3770 OS << " base:" << RegName(Memory.BaseRegNum);
3771 if (Memory.OffsetImm)
3772 OS << " offset-imm:" << *Memory.OffsetImm;
3773 if (Memory.OffsetRegNum)
3774 OS << " offset-reg:" << (Memory.isNegative ? "-" : "")
3775 << RegName(Memory.OffsetRegNum);
3776 if (Memory.ShiftType != ARM_AM::no_shift) {
3777 OS << " shift-type:" << ARM_AM::getShiftOpcStr(Memory.ShiftType);
3778 OS << " shift-imm:" << Memory.ShiftImm;
3779 }
3780 if (Memory.Alignment)
3781 OS << " alignment:" << Memory.Alignment;
3782 OS << ">";
3783 break;
3784 case k_PostIndexRegister:
3785 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
3786 << RegName(PostIdxReg.RegNum);
3787 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
3788 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
3789 << PostIdxReg.ShiftImm;
3790 OS << ">";
3791 break;
3792 case k_ProcIFlags: {
3793 OS << "<ARM_PROC::";
3794 unsigned IFlags = getProcIFlags();
3795 for (int i=2; i >= 0; --i)
3796 if (IFlags & (1 << i))
3797 OS << ARM_PROC::IFlagsToString(1 << i);
3798 OS << ">";
3799 break;
3800 }
3801 case k_Register:
3802 OS << "<register " << RegName(getReg()) << ">";
3803 break;
3804 case k_ShifterImmediate:
3805 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
3806 << " #" << ShifterImm.Imm << ">";
3807 break;
3808 case k_ShiftedRegister:
3809 OS << "<so_reg_reg " << RegName(RegShiftedReg.SrcReg) << " "
3810 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " "
3811 << RegName(RegShiftedReg.ShiftReg) << ">";
3812 break;
3813 case k_ShiftedImmediate:
3814 OS << "<so_reg_imm " << RegName(RegShiftedImm.SrcReg) << " "
3815 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #"
3816 << RegShiftedImm.ShiftImm << ">";
3817 break;
3818 case k_RotateImmediate:
3819 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
3820 break;
3821 case k_ModifiedImmediate:
3822 OS << "<mod_imm #" << ModImm.Bits << ", #"
3823 << ModImm.Rot << ")>";
3824 break;
3825 case k_ConstantPoolImmediate:
3826 OS << "<constant_pool_imm #" << *getConstantPoolImm();
3827 break;
3828 case k_BitfieldDescriptor:
3829 OS << "<bitfield " << "lsb: " << Bitfield.LSB
3830 << ", width: " << Bitfield.Width << ">";
3831 break;
3832 case k_RegisterList:
3833 case k_RegisterListWithAPSR:
3834 case k_DPRRegisterList:
3835 case k_SPRRegisterList:
3836 case k_FPSRegisterListWithVPR:
3837 case k_FPDRegisterListWithVPR: {
3838 OS << "<register_list ";
3839
3840 const SmallVectorImpl<unsigned> &RegList = getRegList();
3841 for (SmallVectorImpl<unsigned>::const_iterator
3842 I = RegList.begin(), E = RegList.end(); I != E; ) {
3843 OS << RegName(*I);
3844 if (++I < E) OS << ", ";
3845 }
3846
3847 OS << ">";
3848 break;
3849 }
3850 case k_VectorList:
3851 OS << "<vector_list " << VectorList.Count << " * "
3852 << RegName(VectorList.RegNum) << ">";
3853 break;
3854 case k_VectorListAllLanes:
3855 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
3856 << RegName(VectorList.RegNum) << ">";
3857 break;
3858 case k_VectorListIndexed:
3859 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
3860 << VectorList.Count << " * " << RegName(VectorList.RegNum) << ">";
3861 break;
3862 case k_Token:
3863 OS << "'" << getToken() << "'";
3864 break;
3865 case k_VectorIndex:
3866 OS << "<vectorindex " << getVectorIndex() << ">";
3867 break;
3868 }
3869}
3870
3871/// @name Auto-generated Match Functions
3872/// {
3873
3874static unsigned MatchRegisterName(StringRef Name);
3875
3876/// }
3877
3878bool ARMAsmParser::ParseRegister(unsigned &RegNo,
3879 SMLoc &StartLoc, SMLoc &EndLoc) {
3880 const AsmToken &Tok = getParser().getTok();
3881 StartLoc = Tok.getLoc();
3882 EndLoc = Tok.getEndLoc();
3883 RegNo = tryParseRegister();
3884
3885 return (RegNo == (unsigned)-1);
3886}
3887
3888/// Try to parse a register name. The token must be an Identifier when called,
3889/// and if it is a register name the token is eaten and the register number is
3890/// returned. Otherwise return -1.
3891int ARMAsmParser::tryParseRegister() {
3892 MCAsmParser &Parser = getParser();
3893 const AsmToken &Tok = Parser.getTok();
3894 if (Tok.isNot(AsmToken::Identifier)) return -1;
3895
3896 std::string lowerCase = Tok.getString().lower();
3897 unsigned RegNum = MatchRegisterName(lowerCase);
3898 if (!RegNum) {
3899 RegNum = StringSwitch<unsigned>(lowerCase)
3900 .Case("r13", ARM::SP)
3901 .Case("r14", ARM::LR)
3902 .Case("r15", ARM::PC)
3903 .Case("ip", ARM::R12)
3904 // Additional register name aliases for 'gas' compatibility.
3905 .Case("a1", ARM::R0)
3906 .Case("a2", ARM::R1)
3907 .Case("a3", ARM::R2)
3908 .Case("a4", ARM::R3)
3909 .Case("v1", ARM::R4)
3910 .Case("v2", ARM::R5)
3911 .Case("v3", ARM::R6)
3912 .Case("v4", ARM::R7)
3913 .Case("v5", ARM::R8)
3914 .Case("v6", ARM::R9)
3915 .Case("v7", ARM::R10)
3916 .Case("v8", ARM::R11)
3917 .Case("sb", ARM::R9)
3918 .Case("sl", ARM::R10)
3919 .Case("fp", ARM::R11)
3920 .Default(0);
3921 }
3922 if (!RegNum) {
3923 // Check for aliases registered via .req. Canonicalize to lower case.
3924 // That's more consistent since register names are case insensitive, and
3925 // it's how the original entry was passed in from MC/MCParser/AsmParser.
3926 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
3927 // If no match, return failure.
3928 if (Entry == RegisterReqs.end())
3929 return -1;
3930 Parser.Lex(); // Eat identifier token.
3931 return Entry->getValue();
3932 }
3933
3934 // Some FPUs only have 16 D registers, so D16-D31 are invalid
3935 if (!hasD32() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
3936 return -1;
3937
3938 Parser.Lex(); // Eat identifier token.
3939
3940 return RegNum;
3941}
3942
3943// Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
3944// If a recoverable error occurs, return 1. If an irrecoverable error
3945// occurs, return -1. An irrecoverable error is one where tokens have been
3946// consumed in the process of trying to parse the shifter (i.e., when it is
3947// indeed a shifter operand, but malformed).
3948int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
3949 MCAsmParser &Parser = getParser();
3950 SMLoc S = Parser.getTok().getLoc();
3951 const AsmToken &Tok = Parser.getTok();
3952 if (Tok.isNot(AsmToken::Identifier))
3953 return -1;
3954
3955 std::string lowerCase = Tok.getString().lower();
3956 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
3957 .Case("asl", ARM_AM::lsl)
3958 .Case("lsl", ARM_AM::lsl)
3959 .Case("lsr", ARM_AM::lsr)
3960 .Case("asr", ARM_AM::asr)
3961 .Case("ror", ARM_AM::ror)
3962 .Case("rrx", ARM_AM::rrx)
3963 .Default(ARM_AM::no_shift);
3964
3965 if (ShiftTy == ARM_AM::no_shift)
3966 return 1;
3967
3968 Parser.Lex(); // Eat the operator.
3969
3970 // The source register for the shift has already been added to the
3971 // operand list, so we need to pop it off and combine it into the shifted
3972 // register operand instead.
3973 std::unique_ptr<ARMOperand> PrevOp(
3974 (ARMOperand *)Operands.pop_back_val().release());
3975 if (!PrevOp->isReg())
3976 return Error(PrevOp->getStartLoc(), "shift must be of a register");
3977 int SrcReg = PrevOp->getReg();
3978
3979 SMLoc EndLoc;
3980 int64_t Imm = 0;
3981 int ShiftReg = 0;
3982 if (ShiftTy == ARM_AM::rrx) {
3983 // RRX Doesn't have an explicit shift amount. The encoder expects
3984 // the shift register to be the same as the source register. Seems odd,
3985 // but OK.
3986 ShiftReg = SrcReg;
3987 } else {
3988 // Figure out if this is shifted by a constant or a register (for non-RRX).
3989 if (Parser.getTok().is(AsmToken::Hash) ||
3990 Parser.getTok().is(AsmToken::Dollar)) {
3991 Parser.Lex(); // Eat hash.
3992 SMLoc ImmLoc = Parser.getTok().getLoc();
3993 const MCExpr *ShiftExpr = nullptr;
3994 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
3995 Error(ImmLoc, "invalid immediate shift value");
3996 return -1;
3997 }
3998 // The expression must be evaluatable as an immediate.
3999 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
4000 if (!CE) {
4001 Error(ImmLoc, "invalid immediate shift value");
4002 return -1;
4003 }
4004 // Range check the immediate.
4005 // lsl, ror: 0 <= imm <= 31
4006 // lsr, asr: 0 <= imm <= 32
4007 Imm = CE->getValue();
4008 if (Imm < 0 ||
4009 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
4010 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
4011 Error(ImmLoc, "immediate shift value out of range");
4012 return -1;
4013 }
4014 // shift by zero is a nop. Always send it through as lsl.
4015 // ('as' compatibility)
4016 if (Imm == 0)
4017 ShiftTy = ARM_AM::lsl;
4018 } else if (Parser.getTok().is(AsmToken::Identifier)) {
4019 SMLoc L = Parser.getTok().getLoc();
4020 EndLoc = Parser.getTok().getEndLoc();
4021 ShiftReg = tryParseRegister();
4022 if (ShiftReg == -1) {
4023 Error(L, "expected immediate or register in shift operand");
4024 return -1;
4025 }
4026 } else {
4027 Error(Parser.getTok().getLoc(),
4028 "expected immediate or register in shift operand");
4029 return -1;
4030 }
4031 }
4032
4033 if (ShiftReg && ShiftTy != ARM_AM::rrx)
4034 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
4035 ShiftReg, Imm,
4036 S, EndLoc));
4037 else
4038 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
4039 S, EndLoc));
4040
4041 return 0;
4042}
4043
4044/// Try to parse a register name. The token must be an Identifier when called.
4045/// If it's a register, an AsmOperand is created. Another AsmOperand is created
4046/// if there is a "writeback". 'true' if it's not a register.
4047///
4048/// TODO this is likely to change to allow different register types and or to
4049/// parse for a specific register type.
4050bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
4051 MCAsmParser &Parser = getParser();
4052 SMLoc RegStartLoc = Parser.getTok().getLoc();
4053 SMLoc RegEndLoc = Parser.getTok().getEndLoc();
4054 int RegNo = tryParseRegister();
4055 if (RegNo == -1)
4056 return true;
4057
4058 Operands.push_back(ARMOperand::CreateReg(RegNo, RegStartLoc, RegEndLoc));
4059
4060 const AsmToken &ExclaimTok = Parser.getTok();
4061 if (ExclaimTok.is(AsmToken::Exclaim)) {
4062 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
4063 ExclaimTok.getLoc()));
4064 Parser.Lex(); // Eat exclaim token
4065 return false;
4066 }
4067
4068 // Also check for an index operand. This is only legal for vector registers,
4069 // but that'll get caught OK in operand matching, so we don't need to
4070 // explicitly filter everything else out here.
4071 if (Parser.getTok().is(AsmToken::LBrac)) {
4072 SMLoc SIdx = Parser.getTok().getLoc();
4073 Parser.Lex(); // Eat left bracket token.
4074
4075 const MCExpr *ImmVal;
4076 if (getParser().parseExpression(ImmVal))
4077 return true;
4078 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
4079 if (!MCE)
4080 return TokError("immediate value expected for vector index");
4081
4082 if (Parser.getTok().isNot(AsmToken::RBrac))
4083 return Error(Parser.getTok().getLoc(), "']' expected");
4084
4085 SMLoc E = Parser.getTok().getEndLoc();
4086 Parser.Lex(); // Eat right bracket token.
4087
4088 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
4089 SIdx, E,
4090 getContext()));
4091 }
4092
4093 return false;
4094}
4095
4096/// MatchCoprocessorOperandName - Try to parse an coprocessor related
4097/// instruction with a symbolic operand name.
4098/// We accept "crN" syntax for GAS compatibility.
4099/// <operand-name> ::= <prefix><number>
4100/// If CoprocOp is 'c', then:
4101/// <prefix> ::= c | cr
4102/// If CoprocOp is 'p', then :
4103/// <prefix> ::= p
4104/// <number> ::= integer in range [0, 15]
4105static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
4106 // Use the same layout as the tablegen'erated register name matcher. Ugly,
4107 // but efficient.
4108 if (Name.size() < 2 || Name[0] != CoprocOp)
4109 return -1;
4110 Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
4111
4112 switch (Name.size()) {
4113 default: return -1;
4114 case 1:
4115 switch (Name[0]) {
4116 default: return -1;
4117 case '0': return 0;
4118 case '1': return 1;
4119 case '2': return 2;
4120 case '3': return 3;
4121 case '4': return 4;
4122 case '5': return 5;
4123 case '6': return 6;
4124 case '7': return 7;
4125 case '8': return 8;
4126 case '9': return 9;
4127 }
4128 case 2:
4129 if (Name[0] != '1')
4130 return -1;
4131 switch (Name[1]) {
4132 default: return -1;
4133 // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
4134 // However, old cores (v5/v6) did use them in that way.
4135 case '0': return 10;
4136 case '1': return 11;
4137 case '2': return 12;
4138 case '3': return 13;
4139 case '4': return 14;
4140 case '5': return 15;
4141 }
4142 }
4143}
4144
4145/// parseITCondCode - Try to parse a condition code for an IT instruction.
4146OperandMatchResultTy
4147ARMAsmParser::parseITCondCode(OperandVector &Operands) {
4148 MCAsmParser &Parser = getParser();
4149 SMLoc S = Parser.getTok().getLoc();
4150 const AsmToken &Tok = Parser.getTok();
4151 if (!Tok.is(AsmToken::Identifier))
4152 return MatchOperand_NoMatch;
4153 unsigned CC = ARMCondCodeFromString(Tok.getString());
4154 if (CC == ~0U)
4155 return MatchOperand_NoMatch;
4156 Parser.Lex(); // Eat the token.
4157
4158 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
4159
4160 return MatchOperand_Success;
4161}
4162
4163/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
4164/// token must be an Identifier when called, and if it is a coprocessor
4165/// number, the token is eaten and the operand is added to the operand list.
4166OperandMatchResultTy
4167ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
4168 MCAsmParser &Parser = getParser();
4169 SMLoc S = Parser.getTok().getLoc();
4170 const AsmToken &Tok = Parser.getTok();
4171 if (Tok.isNot(AsmToken::Identifier))
4172 return MatchOperand_NoMatch;
4173
4174 int Num = MatchCoprocessorOperandName(Tok.getString().lower(), 'p');
4175 if (Num == -1)
4176 return MatchOperand_NoMatch;
4177 if (!isValidCoprocessorNumber(Num, getSTI().getFeatureBits()))
4178 return MatchOperand_NoMatch;
4179
4180 Parser.Lex(); // Eat identifier token.
4181 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
4182 return MatchOperand_Success;
4183}
4184
4185/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
4186/// token must be an Identifier when called, and if it is a coprocessor
4187/// number, the token is eaten and the operand is added to the operand list.
4188OperandMatchResultTy
4189ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
4190 MCAsmParser &Parser = getParser();
4191 SMLoc S = Parser.getTok().getLoc();
4192 const AsmToken &Tok = Parser.getTok();
4193 if (Tok.isNot(AsmToken::Identifier))
4194 return MatchOperand_NoMatch;
4195
4196 int Reg = MatchCoprocessorOperandName(Tok.getString().lower(), 'c');
4197 if (Reg == -1)
4198 return MatchOperand_NoMatch;
4199
4200 Parser.Lex(); // Eat identifier token.
4201 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
4202 return MatchOperand_Success;
4203}
4204
4205/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
4206/// coproc_option : '{' imm0_255 '}'
4207OperandMatchResultTy
4208ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
4209 MCAsmParser &Parser = getParser();
4210 SMLoc S = Parser.getTok().getLoc();
4211
4212 // If this isn't a '{', this isn't a coprocessor immediate operand.
4213 if (Parser.getTok().isNot(AsmToken::LCurly))
4214 return MatchOperand_NoMatch;
4215 Parser.Lex(); // Eat the '{'
4216
4217 const MCExpr *Expr;
4218 SMLoc Loc = Parser.getTok().getLoc();
4219 if (getParser().parseExpression(Expr)) {
4220 Error(Loc, "illegal expression");
4221 return MatchOperand_ParseFail;
4222 }
4223 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4224 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
4225 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
4226 return MatchOperand_ParseFail;
4227 }
4228 int Val = CE->getValue();
4229
4230 // Check for and consume the closing '}'
4231 if (Parser.getTok().isNot(AsmToken::RCurly))
4232 return MatchOperand_ParseFail;
4233 SMLoc E = Parser.getTok().getEndLoc();
4234 Parser.Lex(); // Eat the '}'
4235
4236 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
4237 return MatchOperand_Success;
4238}
4239
4240// For register list parsing, we need to map from raw GPR register numbering
4241// to the enumeration values. The enumeration values aren't sorted by
4242// register number due to our using "sp", "lr" and "pc" as canonical names.
4243static unsigned getNextRegister(unsigned Reg) {
4244 // If this is a GPR, we need to do it manually, otherwise we can rely
4245 // on the sort ordering of the enumeration since the other reg-classes
4246 // are sane.
4247 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
4248 return Reg + 1;
4249 switch(Reg) {
4250 default: llvm_unreachable("Invalid GPR number!")::llvm::llvm_unreachable_internal("Invalid GPR number!", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 4250)
;
4251 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
4252 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
4253 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
4254 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
4255 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
4256 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
4257 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
4258 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
4259 }
4260}
4261
4262// Insert an <Encoding, Register> pair in an ordered vector. Return true on
4263// success, or false, if duplicate encoding found.
4264static bool
4265insertNoDuplicates(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
4266 unsigned Enc, unsigned Reg) {
4267 Regs.emplace_back(Enc, Reg);
4268 for (auto I = Regs.rbegin(), J = I + 1, E = Regs.rend(); J != E; ++I, ++J) {
4269 if (J->first == Enc) {
4270 Regs.erase(J.base());
4271 return false;
4272 }
4273 if (J->first < Enc)
4274 break;
4275 std::swap(*I, *J);
4276 }
4277 return true;
4278}
4279
4280/// Parse a register list.
4281bool ARMAsmParser::parseRegisterList(OperandVector &Operands,
4282 bool EnforceOrder) {
4283 MCAsmParser &Parser = getParser();
4284 if (Parser.getTok().isNot(AsmToken::LCurly))
4285 return TokError("Token is not a Left Curly Brace");
4286 SMLoc S = Parser.getTok().getLoc();
4287 Parser.Lex(); // Eat '{' token.
4288 SMLoc RegLoc = Parser.getTok().getLoc();
4289
4290 // Check the first register in the list to see what register class
4291 // this is a list of.
4292 int Reg = tryParseRegister();
4293 if (Reg == -1)
4294 return Error(RegLoc, "register expected");
4295
4296 // The reglist instructions have at most 16 registers, so reserve
4297 // space for that many.
4298 int EReg = 0;
4299 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
4300
4301 // Allow Q regs and just interpret them as the two D sub-registers.
4302 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4303 Reg = getDRegFromQReg(Reg);
4304 EReg = MRI->getEncodingValue(Reg);
4305 Registers.emplace_back(EReg, Reg);
4306 ++Reg;
4307 }
4308 const MCRegisterClass *RC;
4309 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
4310 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
4311 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
4312 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
4313 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
4314 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
4315 else if (ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg))
4316 RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID];
4317 else
4318 return Error(RegLoc, "invalid register in register list");
4319
4320 // Store the register.
4321 EReg = MRI->getEncodingValue(Reg);
4322 Registers.emplace_back(EReg, Reg);
4323
4324 // This starts immediately after the first register token in the list,
4325 // so we can see either a comma or a minus (range separator) as a legal
4326 // next token.
4327 while (Parser.getTok().is(AsmToken::Comma) ||
4328 Parser.getTok().is(AsmToken::Minus)) {
4329 if (Parser.getTok().is(AsmToken::Minus)) {
4330 Parser.Lex(); // Eat the minus.
4331 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
4332 int EndReg = tryParseRegister();
4333 if (EndReg == -1)
4334 return Error(AfterMinusLoc, "register expected");
4335 // Allow Q regs and just interpret them as the two D sub-registers.
4336 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
4337 EndReg = getDRegFromQReg(EndReg) + 1;
4338 // If the register is the same as the start reg, there's nothing
4339 // more to do.
4340 if (Reg == EndReg)
4341 continue;
4342 // The register must be in the same register class as the first.
4343 if (!RC->contains(EndReg))
4344 return Error(AfterMinusLoc, "invalid register in register list");
4345 // Ranges must go from low to high.
4346 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
4347 return Error(AfterMinusLoc, "bad range in register list");
4348
4349 // Add all the registers in the range to the register list.
4350 while (Reg != EndReg) {
4351 Reg = getNextRegister(Reg);
4352 EReg = MRI->getEncodingValue(Reg);
4353 if (!insertNoDuplicates(Registers, EReg, Reg)) {
4354 Warning(AfterMinusLoc, StringRef("duplicated register (") +
4355 ARMInstPrinter::getRegisterName(Reg) +
4356 ") in register list");
4357 }
4358 }
4359 continue;
4360 }
4361 Parser.Lex(); // Eat the comma.
4362 RegLoc = Parser.getTok().getLoc();
4363 int OldReg = Reg;
4364 const AsmToken RegTok = Parser.getTok();
4365 Reg = tryParseRegister();
4366 if (Reg == -1)
4367 return Error(RegLoc, "register expected");
4368 // Allow Q regs and just interpret them as the two D sub-registers.
4369 bool isQReg = false;
4370 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4371 Reg = getDRegFromQReg(Reg);
4372 isQReg = true;
4373 }
4374 if (!RC->contains(Reg) &&
4375 RC->getID() == ARMMCRegisterClasses[ARM::GPRRegClassID].getID() &&
4376 ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) {
4377 // switch the register classes, as GPRwithAPSRnospRegClassID is a partial
4378 // subset of GPRRegClassId except it contains APSR as well.
4379 RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID];
4380 }
4381 if (Reg == ARM::VPR &&
4382 (RC == &ARMMCRegisterClasses[ARM::SPRRegClassID] ||
4383 RC == &ARMMCRegisterClasses[ARM::DPRRegClassID] ||
4384 RC == &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID])) {
4385 RC = &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID];
4386 EReg = MRI->getEncodingValue(Reg);
4387 if (!insertNoDuplicates(Registers, EReg, Reg)) {
4388 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
4389 ") in register list");
4390 }
4391 continue;
4392 }
4393 // The register must be in the same register class as the first.
4394 if (!RC->contains(Reg))
4395 return Error(RegLoc, "invalid register in register list");
4396 // In most cases, the list must be monotonically increasing. An
4397 // exception is CLRM, which is order-independent anyway, so
4398 // there's no potential for confusion if you write clrm {r2,r1}
4399 // instead of clrm {r1,r2}.
4400 if (EnforceOrder &&
4401 MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
4402 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
4403 Warning(RegLoc, "register list not in ascending order");
4404 else if (!ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg))
4405 return Error(RegLoc, "register list not in ascending order");
4406 }
4407 // VFP register lists must also be contiguous.
4408 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
4409 RC != &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID] &&
4410 Reg != OldReg + 1)
4411 return Error(RegLoc, "non-contiguous register range");
4412 EReg = MRI->getEncodingValue(Reg);
4413 if (!insertNoDuplicates(Registers, EReg, Reg)) {
4414 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
4415 ") in register list");
4416 }
4417 if (isQReg) {
4418 EReg = MRI->getEncodingValue(++Reg);
4419 Registers.emplace_back(EReg, Reg);
4420 }
4421 }
4422
4423 if (Parser.getTok().isNot(AsmToken::RCurly))
4424 return Error(Parser.getTok().getLoc(), "'}' expected");
4425 SMLoc E = Parser.getTok().getEndLoc();
4426 Parser.Lex(); // Eat '}' token.
4427
4428 // Push the register list operand.
4429 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
4430
4431 // The ARM system instruction variants for LDM/STM have a '^' token here.
4432 if (Parser.getTok().is(AsmToken::Caret)) {
4433 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
4434 Parser.Lex(); // Eat '^' token.
4435 }
4436
4437 return false;
4438}
4439
4440// Helper function to parse the lane index for vector lists.
4441OperandMatchResultTy ARMAsmParser::
4442parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
4443 MCAsmParser &Parser = getParser();
4444 Index = 0; // Always return a defined index value.
4445 if (Parser.getTok().is(AsmToken::LBrac)) {
4446 Parser.Lex(); // Eat the '['.
4447 if (Parser.getTok().is(AsmToken::RBrac)) {
4448 // "Dn[]" is the 'all lanes' syntax.
4449 LaneKind = AllLanes;
4450 EndLoc = Parser.getTok().getEndLoc();
4451 Parser.Lex(); // Eat the ']'.
4452 return MatchOperand_Success;
4453 }
4454
4455 // There's an optional '#' token here. Normally there wouldn't be, but
4456 // inline assemble puts one in, and it's friendly to accept that.
4457 if (Parser.getTok().is(AsmToken::Hash))
4458 Parser.Lex(); // Eat '#' or '$'.
4459
4460 const MCExpr *LaneIndex;
4461 SMLoc Loc = Parser.getTok().getLoc();
4462 if (getParser().parseExpression(LaneIndex)) {
4463 Error(Loc, "illegal expression");
4464 return MatchOperand_ParseFail;
4465 }
4466 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
4467 if (!CE) {
4468 Error(Loc, "lane index must be empty or an integer");
4469 return MatchOperand_ParseFail;
4470 }
4471 if (Parser.getTok().isNot(AsmToken::RBrac)) {
4472 Error(Parser.getTok().getLoc(), "']' expected");
4473 return MatchOperand_ParseFail;
4474 }
4475 EndLoc = Parser.getTok().getEndLoc();
4476 Parser.Lex(); // Eat the ']'.
4477 int64_t Val = CE->getValue();
4478
4479 // FIXME: Make this range check context sensitive for .8, .16, .32.
4480 if (Val < 0 || Val > 7) {
4481 Error(Parser.getTok().getLoc(), "lane index out of range");
4482 return MatchOperand_ParseFail;
4483 }
4484 Index = Val;
4485 LaneKind = IndexedLane;
4486 return MatchOperand_Success;
4487 }
4488 LaneKind = NoLanes;
4489 return MatchOperand_Success;
4490}
4491
4492// parse a vector register list
4493OperandMatchResultTy
4494ARMAsmParser::parseVectorList(OperandVector &Operands) {
4495 MCAsmParser &Parser = getParser();
4496 VectorLaneTy LaneKind;
4497 unsigned LaneIndex;
4498 SMLoc S = Parser.getTok().getLoc();
4499 // As an extension (to match gas), support a plain D register or Q register
4500 // (without encosing curly braces) as a single or double entry list,
4501 // respectively.
4502 if (!hasMVE() && Parser.getTok().is(AsmToken::Identifier)) {
4503 SMLoc E = Parser.getTok().getEndLoc();
4504 int Reg = tryParseRegister();
4505 if (Reg == -1)
4506 return MatchOperand_NoMatch;
4507 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
4508 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
4509 if (Res != MatchOperand_Success)
4510 return Res;
4511 switch (LaneKind) {
4512 case NoLanes:
4513 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
4514 break;
4515 case AllLanes:
4516 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
4517 S, E));
4518 break;
4519 case IndexedLane:
4520 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
4521 LaneIndex,
4522 false, S, E));
4523 break;
4524 }
4525 return MatchOperand_Success;
4526 }
4527 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4528 Reg = getDRegFromQReg(Reg);
4529 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
4530 if (Res != MatchOperand_Success)
4531 return Res;
4532 switch (LaneKind) {
4533 case NoLanes:
4534 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
4535 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
4536 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
4537 break;
4538 case AllLanes:
4539 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
4540 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
4541 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
4542 S, E));
4543 break;
4544 case IndexedLane:
4545 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
4546 LaneIndex,
4547 false, S, E));
4548 break;
4549 }
4550 return MatchOperand_Success;
4551 }
4552 Error(S, "vector register expected");
4553 return MatchOperand_ParseFail;
4554 }
4555
4556 if (Parser.getTok().isNot(AsmToken::LCurly))
4557 return MatchOperand_NoMatch;
4558
4559 Parser.Lex(); // Eat '{' token.
4560 SMLoc RegLoc = Parser.getTok().getLoc();
4561
4562 int Reg = tryParseRegister();
4563 if (Reg == -1) {
4564 Error(RegLoc, "register expected");
4565 return MatchOperand_ParseFail;
4566 }
4567 unsigned Count = 1;
4568 int Spacing = 0;
4569 unsigned FirstReg = Reg;
4570
4571 if (hasMVE() && !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) {
4572 Error(Parser.getTok().getLoc(), "vector register in range Q0-Q7 expected");
4573 return MatchOperand_ParseFail;
4574 }
4575 // The list is of D registers, but we also allow Q regs and just interpret
4576 // them as the two D sub-registers.
4577 else if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4578 FirstReg = Reg = getDRegFromQReg(Reg);
4579 Spacing = 1; // double-spacing requires explicit D registers, otherwise
4580 // it's ambiguous with four-register single spaced.
4581 ++Reg;
4582 ++Count;
4583 }
4584
4585 SMLoc E;
4586 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
4587 return MatchOperand_ParseFail;
4588
4589 while (Parser.getTok().is(AsmToken::Comma) ||
4590 Parser.getTok().is(AsmToken::Minus)) {
4591 if (Parser.getTok().is(AsmToken::Minus)) {
4592 if (!Spacing)
4593 Spacing = 1; // Register range implies a single spaced list.
4594 else if (Spacing == 2) {
4595 Error(Parser.getTok().getLoc(),
4596 "sequential registers in double spaced list");
4597 return MatchOperand_ParseFail;
4598 }
4599 Parser.Lex(); // Eat the minus.
4600 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
4601 int EndReg = tryParseRegister();
4602 if (EndReg == -1) {
4603 Error(AfterMinusLoc, "register expected");
4604 return MatchOperand_ParseFail;
4605 }
4606 // Allow Q regs and just interpret them as the two D sub-registers.
4607 if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
4608 EndReg = getDRegFromQReg(EndReg) + 1;
4609 // If the register is the same as the start reg, there's nothing
4610 // more to do.
4611 if (Reg == EndReg)
4612 continue;
4613 // The register must be in the same register class as the first.
4614 if ((hasMVE() &&
4615 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(EndReg)) ||
4616 (!hasMVE() &&
4617 !ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg))) {
4618 Error(AfterMinusLoc, "invalid register in register list");
4619 return MatchOperand_ParseFail;
4620 }
4621 // Ranges must go from low to high.
4622 if (Reg > EndReg) {
4623 Error(AfterMinusLoc, "bad range in register list");
4624 return MatchOperand_ParseFail;
4625 }
4626 // Parse the lane specifier if present.
4627 VectorLaneTy NextLaneKind;
4628 unsigned NextLaneIndex;
4629 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
4630 MatchOperand_Success)
4631 return MatchOperand_ParseFail;
4632 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4633 Error(AfterMinusLoc, "mismatched lane index in register list");
4634 return MatchOperand_ParseFail;
4635 }
4636
4637 // Add all the registers in the range to the register list.
4638 Count += EndReg - Reg;
4639 Reg = EndReg;
4640 continue;
4641 }
4642 Parser.Lex(); // Eat the comma.
4643 RegLoc = Parser.getTok().getLoc();
4644 int OldReg = Reg;
4645 Reg = tryParseRegister();
4646 if (Reg == -1) {
4647 Error(RegLoc, "register expected");
4648 return MatchOperand_ParseFail;
4649 }
4650
4651 if (hasMVE()) {
4652 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) {
4653 Error(RegLoc, "vector register in range Q0-Q7 expected");
4654 return MatchOperand_ParseFail;
4655 }
4656 Spacing = 1;
4657 }
4658 // vector register lists must be contiguous.
4659 // It's OK to use the enumeration values directly here rather, as the
4660 // VFP register classes have the enum sorted properly.
4661 //
4662 // The list is of D registers, but we also allow Q regs and just interpret
4663 // them as the two D sub-registers.
4664 else if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4665 if (!Spacing)
4666 Spacing = 1; // Register range implies a single spaced list.
4667 else if (Spacing == 2) {
4668 Error(RegLoc,
4669 "invalid register in double-spaced list (must be 'D' register')");
4670 return MatchOperand_ParseFail;
4671 }
4672 Reg = getDRegFromQReg(Reg);
4673 if (Reg != OldReg + 1) {
4674 Error(RegLoc, "non-contiguous register range");
4675 return MatchOperand_ParseFail;
4676 }
4677 ++Reg;
4678 Count += 2;
4679 // Parse the lane specifier if present.
4680 VectorLaneTy NextLaneKind;
4681 unsigned NextLaneIndex;
4682 SMLoc LaneLoc = Parser.getTok().getLoc();
4683 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
4684 MatchOperand_Success)
4685 return MatchOperand_ParseFail;
4686 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4687 Error(LaneLoc, "mismatched lane index in register list");
4688 return MatchOperand_ParseFail;
4689 }
4690 continue;
4691 }
4692 // Normal D register.
4693 // Figure out the register spacing (single or double) of the list if
4694 // we don't know it already.
4695 if (!Spacing)
4696 Spacing = 1 + (Reg == OldReg + 2);
4697
4698 // Just check that it's contiguous and keep going.
4699 if (Reg != OldReg + Spacing) {
4700 Error(RegLoc, "non-contiguous register range");
4701 return MatchOperand_ParseFail;
4702 }
4703 ++Count;
4704 // Parse the lane specifier if present.
4705 VectorLaneTy NextLaneKind;
4706 unsigned NextLaneIndex;
4707 SMLoc EndLoc = Parser.getTok().getLoc();
4708 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
4709 return MatchOperand_ParseFail;
4710 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4711 Error(EndLoc, "mismatched lane index in register list");
4712 return MatchOperand_ParseFail;
4713 }
4714 }
4715
4716 if (Parser.getTok().isNot(AsmToken::RCurly)) {
4717 Error(Parser.getTok().getLoc(), "'}' expected");
4718 return MatchOperand_ParseFail;
4719 }
4720 E = Parser.getTok().getEndLoc();
4721 Parser.Lex(); // Eat '}' token.
4722
4723 switch (LaneKind) {
4724 case NoLanes:
4725 case AllLanes: {
4726 // Two-register operands have been converted to the
4727 // composite register classes.
4728 if (Count == 2 && !hasMVE()) {
4729 const MCRegisterClass *RC = (Spacing == 1) ?
4730 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
4731 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
4732 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
4733 }
4734 auto Create = (LaneKind == NoLanes ? ARMOperand::CreateVectorList :
4735 ARMOperand::CreateVectorListAllLanes);
4736 Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E));
4737 break;
4738 }
4739 case IndexedLane:
4740 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
4741 LaneIndex,
4742 (Spacing == 2),
4743 S, E));
4744 break;
4745 }
4746 return MatchOperand_Success;
4747}
4748
4749/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
4750OperandMatchResultTy
4751ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
4752 MCAsmParser &Parser = getParser();
4753 SMLoc S = Parser.getTok().getLoc();
4754 const AsmToken &Tok = Parser.getTok();
4755 unsigned Opt;
4756
4757 if (Tok.is(AsmToken::Identifier)) {
4758 StringRef OptStr = Tok.getString();
4759
4760 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
4761 .Case("sy", ARM_MB::SY)
4762 .Case("st", ARM_MB::ST)
4763 .Case("ld", ARM_MB::LD)
4764 .Case("sh", ARM_MB::ISH)
4765 .Case("ish", ARM_MB::ISH)
4766 .Case("shst", ARM_MB::ISHST)
4767 .Case("ishst", ARM_MB::ISHST)
4768 .Case("ishld", ARM_MB::ISHLD)
4769 .Case("nsh", ARM_MB::NSH)
4770 .Case("un", ARM_MB::NSH)
4771 .Case("nshst", ARM_MB::NSHST)
4772 .Case("nshld", ARM_MB::NSHLD)
4773 .Case("unst", ARM_MB::NSHST)
4774 .Case("osh", ARM_MB::OSH)
4775 .Case("oshst", ARM_MB::OSHST)
4776 .Case("oshld", ARM_MB::OSHLD)
4777 .Default(~0U);
4778
4779 // ishld, oshld, nshld and ld are only available from ARMv8.
4780 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
4781 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
4782 Opt = ~0U;
4783
4784 if (Opt == ~0U)
4785 return MatchOperand_NoMatch;
4786
4787 Parser.Lex(); // Eat identifier token.
4788 } else if (Tok.is(AsmToken::Hash) ||
4789 Tok.is(AsmToken::Dollar) ||
4790 Tok.is(AsmToken::Integer)) {
4791 if (Parser.getTok().isNot(AsmToken::Integer))
4792 Parser.Lex(); // Eat '#' or '$'.
4793 SMLoc Loc = Parser.getTok().getLoc();
4794
4795 const MCExpr *MemBarrierID;
4796 if (getParser().parseExpression(MemBarrierID)) {
4797 Error(Loc, "illegal expression");
4798 return MatchOperand_ParseFail;
4799 }
4800
4801 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
4802 if (!CE) {
4803 Error(Loc, "constant expression expected");
4804 return MatchOperand_ParseFail;
4805 }
4806
4807 int Val = CE->getValue();
4808 if (Val & ~0xf) {
4809 Error(Loc, "immediate value out of range");
4810 return MatchOperand_ParseFail;
4811 }
4812
4813 Opt = ARM_MB::RESERVED_0 + Val;
4814 } else
4815 return MatchOperand_ParseFail;
4816
4817 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
4818 return MatchOperand_Success;
4819}
4820
4821OperandMatchResultTy
4822ARMAsmParser::parseTraceSyncBarrierOptOperand(OperandVector &Operands) {
4823 MCAsmParser &Parser = getParser();
4824 SMLoc S = Parser.getTok().getLoc();
4825 const AsmToken &Tok = Parser.getTok();
4826
4827 if (Tok.isNot(AsmToken::Identifier))
4828 return MatchOperand_NoMatch;
4829
4830 if (!Tok.getString().equals_lower("csync"))
4831 return MatchOperand_NoMatch;
4832
4833 Parser.Lex(); // Eat identifier token.
4834
4835 Operands.push_back(ARMOperand::CreateTraceSyncBarrierOpt(ARM_TSB::CSYNC, S));
4836 return MatchOperand_Success;
4837}
4838
4839/// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
4840OperandMatchResultTy
4841ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
4842 MCAsmParser &Parser = getParser();
4843 SMLoc S = Parser.getTok().getLoc();
4844 const AsmToken &Tok = Parser.getTok();
4845 unsigned Opt;
4846
4847 if (Tok.is(AsmToken::Identifier)) {
4848 StringRef OptStr = Tok.getString();
4849
4850 if (OptStr.equals_lower("sy"))
4851 Opt = ARM_ISB::SY;
4852 else
4853 return MatchOperand_NoMatch;
4854
4855 Parser.Lex(); // Eat identifier token.
4856 } else if (Tok.is(AsmToken::Hash) ||
4857 Tok.is(AsmToken::Dollar) ||
4858 Tok.is(AsmToken::Integer)) {
4859 if (Parser.getTok().isNot(AsmToken::Integer))
4860 Parser.Lex(); // Eat '#' or '$'.
4861 SMLoc Loc = Parser.getTok().getLoc();
4862
4863 const MCExpr *ISBarrierID;
4864 if (getParser().parseExpression(ISBarrierID)) {
4865 Error(Loc, "illegal expression");
4866 return MatchOperand_ParseFail;
4867 }
4868
4869 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
4870 if (!CE) {
4871 Error(Loc, "constant expression expected");
4872 return MatchOperand_ParseFail;
4873 }
4874
4875 int Val = CE->getValue();
4876 if (Val & ~0xf) {
4877 Error(Loc, "immediate value out of range");
4878 return MatchOperand_ParseFail;
4879 }
4880
4881 Opt = ARM_ISB::RESERVED_0 + Val;
4882 } else
4883 return MatchOperand_ParseFail;
4884
4885 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
4886 (ARM_ISB::InstSyncBOpt)Opt, S));
4887 return MatchOperand_Success;
4888}
4889
4890
4891/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
4892OperandMatchResultTy
4893ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
4894 MCAsmParser &Parser = getParser();
4895 SMLoc S = Parser.getTok().getLoc();
4896 const AsmToken &Tok = Parser.getTok();
4897 if (!Tok.is(AsmToken::Identifier))
4898 return MatchOperand_NoMatch;
4899 StringRef IFlagsStr = Tok.getString();
4900
4901 // An iflags string of "none" is interpreted to mean that none of the AIF
4902 // bits are set. Not a terribly useful instruction, but a valid encoding.
4903 unsigned IFlags = 0;
4904 if (IFlagsStr != "none") {
4905 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
4906 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1).lower())
4907 .Case("a", ARM_PROC::A)
4908 .Case("i", ARM_PROC::I)
4909 .Case("f", ARM_PROC::F)
4910 .Default(~0U);
4911
4912 // If some specific iflag is already set, it means that some letter is
4913 // present more than once, this is not acceptable.
4914 if (Flag == ~0U || (IFlags & Flag))
4915 return MatchOperand_NoMatch;
4916
4917 IFlags |= Flag;
4918 }
4919 }
4920
4921 Parser.Lex(); // Eat identifier token.
4922 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
4923 return MatchOperand_Success;
4924}
4925
4926/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
4927OperandMatchResultTy
4928ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
4929 MCAsmParser &Parser = getParser();
4930 SMLoc S = Parser.getTok().getLoc();
4931 const AsmToken &Tok = Parser.getTok();
4932
4933 if (Tok.is(AsmToken::Integer)) {
4934 int64_t Val = Tok.getIntVal();
4935 if (Val > 255 || Val < 0) {
4936 return MatchOperand_NoMatch;
4937 }
4938 unsigned SYSmvalue = Val & 0xFF;
4939 Parser.Lex();
4940 Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
4941 return MatchOperand_Success;
4942 }
4943
4944 if (!Tok.is(AsmToken::Identifier))
4945 return MatchOperand_NoMatch;
4946 StringRef Mask = Tok.getString();
4947
4948 if (isMClass()) {
4949 auto TheReg = ARMSysReg::lookupMClassSysRegByName(Mask.lower());
4950 if (!TheReg || !TheReg->hasRequiredFeatures(getSTI().getFeatureBits()))
4951 return MatchOperand_NoMatch;
4952
4953 unsigned SYSmvalue = TheReg->Encoding & 0xFFF;
4954
4955 Parser.Lex(); // Eat identifier token.
4956 Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
4957 return MatchOperand_Success;
4958 }
4959
4960 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
4961 size_t Start = 0, Next = Mask.find('_');
4962 StringRef Flags = "";
4963 std::string SpecReg = Mask.slice(Start, Next).lower();
4964 if (Next != StringRef::npos)
4965 Flags = Mask.slice(Next+1, Mask.size());
4966
4967 // FlagsVal contains the complete mask:
4968 // 3-0: Mask
4969 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4970 unsigned FlagsVal = 0;
4971
4972 if (SpecReg == "apsr") {
4973 FlagsVal = StringSwitch<unsigned>(Flags)
4974 .Case("nzcvq", 0x8) // same as CPSR_f
4975 .Case("g", 0x4) // same as CPSR_s
4976 .Case("nzcvqg", 0xc) // same as CPSR_fs
4977 .Default(~0U);
4978
4979 if (FlagsVal == ~0U) {
4980 if (!Flags.empty())
4981 return MatchOperand_NoMatch;
4982 else
4983 FlagsVal = 8; // No flag
4984 }
4985 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
4986 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
4987 if (Flags == "all" || Flags == "")
4988 Flags = "fc";
4989 for (int i = 0, e = Flags.size(); i != e; ++i) {
4990 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
4991 .Case("c", 1)
4992 .Case("x", 2)
4993 .Case("s", 4)
4994 .Case("f", 8)
4995 .Default(~0U);
4996
4997 // If some specific flag is already set, it means that some letter is
4998 // present more than once, this is not acceptable.
4999 if (Flag == ~0U || (FlagsVal & Flag))
5000 return MatchOperand_NoMatch;
5001 FlagsVal |= Flag;
5002 }
5003 } else // No match for special register.
5004 return MatchOperand_NoMatch;
5005
5006 // Special register without flags is NOT equivalent to "fc" flags.
5007 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
5008 // two lines would enable gas compatibility at the expense of breaking
5009 // round-tripping.
5010 //
5011 // if (!FlagsVal)
5012 // FlagsVal = 0x9;
5013
5014 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
5015 if (SpecReg == "spsr")
5016 FlagsVal |= 16;
5017
5018 Parser.Lex(); // Eat identifier token.
5019 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
5020 return MatchOperand_Success;
5021}
5022
5023/// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
5024/// use in the MRS/MSR instructions added to support virtualization.
5025OperandMatchResultTy
5026ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
5027 MCAsmParser &Parser = getParser();
5028 SMLoc S = Parser.getTok().getLoc();
5029 const AsmToken &Tok = Parser.getTok();
5030 if (!Tok.is(AsmToken::Identifier))
5031 return MatchOperand_NoMatch;
5032 StringRef RegName = Tok.getString();
5033
5034 auto TheReg = ARMBankedReg::lookupBankedRegByName(RegName.lower());
5035 if (!TheReg)
5036 return MatchOperand_NoMatch;
5037 unsigned Encoding = TheReg->Encoding;
5038
5039 Parser.Lex(); // Eat identifier token.
5040 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
5041 return MatchOperand_Success;
5042}
5043
5044OperandMatchResultTy
5045ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
5046 int High) {
5047 MCAsmParser &Parser = getParser();
5048 const AsmToken &Tok = Parser.getTok();
5049 if (Tok.isNot(AsmToken::Identifier)) {
5050 Error(Parser.getTok().getLoc(), Op + " operand expected.");
5051 return MatchOperand_ParseFail;
5052 }
5053 StringRef ShiftName = Tok.getString();
5054 std::string LowerOp = Op.lower();
5055 std::string UpperOp = Op.upper();
5056 if (ShiftName != LowerOp && ShiftName != UpperOp) {
5057 Error(Parser.getTok().getLoc(), Op + " operand expected.");
5058 return MatchOperand_ParseFail;
5059 }
5060 Parser.Lex(); // Eat shift type token.
5061
5062 // There must be a '#' and a shift amount.
5063 if (Parser.getTok().isNot(AsmToken::Hash) &&
5064 Parser.getTok().isNot(AsmToken::Dollar)) {
5065 Error(Parser.getTok().getLoc(), "'#' expected");
5066 return MatchOperand_ParseFail;
5067 }
5068 Parser.Lex(); // Eat hash token.
5069
5070 const MCExpr *ShiftAmount;
5071 SMLoc Loc = Parser.getTok().getLoc();
5072 SMLoc EndLoc;
5073 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5074 Error(Loc, "illegal expression");
5075 return MatchOperand_ParseFail;
5076 }
5077 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5078 if (!CE) {
5079 Error(Loc, "constant expression expected");
5080 return MatchOperand_ParseFail;
5081 }
5082 int Val = CE->getValue();
5083 if (Val < Low || Val > High) {
5084 Error(Loc, "immediate value out of range");
5085 return MatchOperand_ParseFail;
5086 }
5087
5088 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
5089
5090 return MatchOperand_Success;
5091}
5092
5093OperandMatchResultTy
5094ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
5095 MCAsmParser &Parser = getParser();
5096 const AsmToken &Tok = Parser.getTok();
5097 SMLoc S = Tok.getLoc();
5098 if (Tok.isNot(AsmToken::Identifier)) {
5099 Error(S, "'be' or 'le' operand expected");
5100 return MatchOperand_ParseFail;
5101 }
5102 int Val = StringSwitch<int>(Tok.getString().lower())
5103 .Case("be", 1)
5104 .Case("le", 0)
5105 .Default(-1);
5106 Parser.Lex(); // Eat the token.
5107
5108 if (Val == -1) {
5109 Error(S, "'be' or 'le' operand expected");
5110 return MatchOperand_ParseFail;
5111 }
5112 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val,
5113 getContext()),
5114 S, Tok.getEndLoc()));
5115 return MatchOperand_Success;
5116}
5117
5118/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
5119/// instructions. Legal values are:
5120/// lsl #n 'n' in [0,31]
5121/// asr #n 'n' in [1,32]
5122/// n == 32 encoded as n == 0.
5123OperandMatchResultTy
5124ARMAsmParser::parseShifterImm(OperandVector &Operands) {
5125 MCAsmParser &Parser = getParser();
5126 const AsmToken &Tok = Parser.getTok();
5127 SMLoc S = Tok.getLoc();
5128 if (Tok.isNot(AsmToken::Identifier)) {
5129 Error(S, "shift operator 'asr' or 'lsl' expected");
5130 return MatchOperand_ParseFail;
5131 }
5132 StringRef ShiftName = Tok.getString();
5133 bool isASR;
5134 if (ShiftName == "lsl" || ShiftName == "LSL")
5135 isASR = false;
5136 else if (ShiftName == "asr" || ShiftName == "ASR")
5137 isASR = true;
5138 else {
5139 Error(S, "shift operator 'asr' or 'lsl' expected");
5140 return MatchOperand_ParseFail;
5141 }
5142 Parser.Lex(); // Eat the operator.
5143
5144 // A '#' and a shift amount.
5145 if (Parser.getTok().isNot(AsmToken::Hash) &&
5146 Parser.getTok().isNot(AsmToken::Dollar)) {
5147 Error(Parser.getTok().getLoc(), "'#' expected");
5148 return MatchOperand_ParseFail;
5149 }
5150 Parser.Lex(); // Eat hash token.
5151 SMLoc ExLoc = Parser.getTok().getLoc();
5152
5153 const MCExpr *ShiftAmount;
5154 SMLoc EndLoc;
5155 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5156 Error(ExLoc, "malformed shift expression");
5157 return MatchOperand_ParseFail;
5158 }
5159 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5160 if (!CE) {
5161 Error(ExLoc, "shift amount must be an immediate");
5162 return MatchOperand_ParseFail;
5163 }
5164
5165 int64_t Val = CE->getValue();
5166 if (isASR) {
5167 // Shift amount must be in [1,32]
5168 if (Val < 1 || Val > 32) {
5169 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
5170 return MatchOperand_ParseFail;
5171 }
5172 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
5173 if (isThumb() && Val == 32) {
5174 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
5175 return MatchOperand_ParseFail;
5176 }
5177 if (Val == 32) Val = 0;
5178 } else {
5179 // Shift amount must be in [1,32]
5180 if (Val < 0 || Val > 31) {
5181 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
5182 return MatchOperand_ParseFail;
5183 }
5184 }
5185
5186 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
5187
5188 return MatchOperand_Success;
5189}
5190
5191/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
5192/// of instructions. Legal values are:
5193/// ror #n 'n' in {0, 8, 16, 24}
5194OperandMatchResultTy
5195ARMAsmParser::parseRotImm(OperandVector &Operands) {
5196 MCAsmParser &Parser = getParser();
5197 const AsmToken &Tok = Parser.getTok();
5198 SMLoc S = Tok.getLoc();
5199 if (Tok.isNot(AsmToken::Identifier))
5200 return MatchOperand_NoMatch;
5201 StringRef ShiftName = Tok.getString();
5202 if (ShiftName != "ror" && ShiftName != "ROR")
5203 return MatchOperand_NoMatch;
5204 Parser.Lex(); // Eat the operator.
5205
5206 // A '#' and a rotate amount.
5207 if (Parser.getTok().isNot(AsmToken::Hash) &&
5208 Parser.getTok().isNot(AsmToken::Dollar)) {
5209 Error(Parser.getTok().getLoc(), "'#' expected");
5210 return MatchOperand_ParseFail;
5211 }
5212 Parser.Lex(); // Eat hash token.
5213 SMLoc ExLoc = Parser.getTok().getLoc();
5214
5215 const MCExpr *ShiftAmount;
5216 SMLoc EndLoc;
5217 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5218 Error(ExLoc, "malformed rotate expression");
5219 return MatchOperand_ParseFail;
5220 }
5221 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5222 if (!CE) {
5223 Error(ExLoc, "rotate amount must be an immediate");
5224 return MatchOperand_ParseFail;
5225 }
5226
5227 int64_t Val = CE->getValue();
5228 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
5229 // normally, zero is represented in asm by omitting the rotate operand
5230 // entirely.
5231 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
5232 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
5233 return MatchOperand_ParseFail;
5234 }
5235
5236 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
5237
5238 return MatchOperand_Success;
5239}
5240
5241OperandMatchResultTy
5242ARMAsmParser::parseModImm(OperandVector &Operands) {
5243 MCAsmParser &Parser = getParser();
5244 MCAsmLexer &Lexer = getLexer();
5245 int64_t Imm1, Imm2;
5246
5247 SMLoc S = Parser.getTok().getLoc();
5248
5249 // 1) A mod_imm operand can appear in the place of a register name:
5250 // add r0, #mod_imm
5251 // add r0, r0, #mod_imm
5252 // to correctly handle the latter, we bail out as soon as we see an
5253 // identifier.
5254 //
5255 // 2) Similarly, we do not want to parse into complex operands:
5256 // mov r0, #mod_imm
5257 // mov r0, :lower16:(_foo)
5258 if (Parser.getTok().is(AsmToken::Identifier) ||
5259 Parser.getTok().is(AsmToken::Colon))
5260 return MatchOperand_NoMatch;
5261
5262 // Hash (dollar) is optional as per the ARMARM
5263 if (Parser.getTok().is(AsmToken::Hash) ||
5264 Parser.getTok().is(AsmToken::Dollar)) {
5265 // Avoid parsing into complex operands (#:)
5266 if (Lexer.peekTok().is(AsmToken::Colon))
5267 return MatchOperand_NoMatch;
5268
5269 // Eat the hash (dollar)
5270 Parser.Lex();
5271 }
5272
5273 SMLoc Sx1, Ex1;
5274 Sx1 = Parser.getTok().getLoc();
5275 const MCExpr *Imm1Exp;
5276 if (getParser().parseExpression(Imm1Exp, Ex1)) {
5277 Error(Sx1, "malformed expression");
5278 return MatchOperand_ParseFail;
5279 }
5280
5281 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
5282
5283 if (CE) {
5284 // Immediate must fit within 32-bits
5285 Imm1 = CE->getValue();
5286 int Enc = ARM_AM::getSOImmVal(Imm1);
5287 if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
5288 // We have a match!
5289 Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
5290 (Enc & 0xF00) >> 7,
5291 Sx1, Ex1));
5292 return MatchOperand_Success;
5293 }
5294
5295 // We have parsed an immediate which is not for us, fallback to a plain
5296 // immediate. This can happen for instruction aliases. For an example,
5297 // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform
5298 // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite
5299 // instruction with a mod_imm operand. The alias is defined such that the
5300 // parser method is shared, that's why we have to do this here.
5301 if (Parser.getTok().is(AsmToken::EndOfStatement)) {
5302 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
5303 return MatchOperand_Success;
5304 }
5305 } else {
5306 // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
5307 // MCFixup). Fallback to a plain immediate.
5308 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
5309 return MatchOperand_Success;
5310 }
5311
5312 // From this point onward, we expect the input to be a (#bits, #rot) pair
5313 if (Parser.getTok().isNot(AsmToken::Comma)) {
5314 Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]");
5315 return MatchOperand_ParseFail;
5316 }
5317
5318 if (Imm1 & ~0xFF) {
5319 Error(Sx1, "immediate operand must a number in the range [0, 255]");
5320 return MatchOperand_ParseFail;
5321 }
5322
5323 // Eat the comma
5324 Parser.Lex();
5325
5326 // Repeat for #rot
5327 SMLoc Sx2, Ex2;
5328 Sx2 = Parser.getTok().getLoc();
5329
5330 // Eat the optional hash (dollar)
5331 if (Parser.getTok().is(AsmToken::Hash) ||
5332 Parser.getTok().is(AsmToken::Dollar))
5333 Parser.Lex();
5334
5335 const MCExpr *Imm2Exp;
5336 if (getParser().parseExpression(Imm2Exp, Ex2)) {
5337 Error(Sx2, "malformed expression");
5338 return MatchOperand_ParseFail;
5339 }
5340
5341 CE = dyn_cast<MCConstantExpr>(Imm2Exp);
5342
5343 if (CE) {
5344 Imm2 = CE->getValue();
5345 if (!(Imm2 & ~0x1E)) {
5346 // We have a match!
5347 Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
5348 return MatchOperand_Success;
5349 }
5350 Error(Sx2, "immediate operand must an even number in the range [0, 30]");
5351 return MatchOperand_ParseFail;
5352 } else {
5353 Error(Sx2, "constant expression expected");
5354 return MatchOperand_ParseFail;
5355 }
5356}
5357
5358OperandMatchResultTy
5359ARMAsmParser::parseBitfield(OperandVector &Operands) {
5360 MCAsmParser &Parser = getParser();
5361 SMLoc S = Parser.getTok().getLoc();
5362 // The bitfield descriptor is really two operands, the LSB and the width.
5363 if (Parser.getTok().isNot(AsmToken::Hash) &&
5364 Parser.getTok().isNot(AsmToken::Dollar)) {
5365 Error(Parser.getTok().getLoc(), "'#' expected");
5366 return MatchOperand_ParseFail;
5367 }
5368 Parser.Lex(); // Eat hash token.
5369
5370 const MCExpr *LSBExpr;
5371 SMLoc E = Parser.getTok().getLoc();
5372 if (getParser().parseExpression(LSBExpr)) {
5373 Error(E, "malformed immediate expression");
5374 return MatchOperand_ParseFail;
5375 }
5376 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
5377 if (!CE) {
5378 Error(E, "'lsb' operand must be an immediate");
5379 return MatchOperand_ParseFail;
5380 }
5381
5382 int64_t LSB = CE->getValue();
5383 // The LSB must be in the range [0,31]
5384 if (LSB < 0 || LSB > 31) {
5385 Error(E, "'lsb' operand must be in the range [0,31]");
5386 return MatchOperand_ParseFail;
5387 }
5388 E = Parser.getTok().getLoc();
5389
5390 // Expect another immediate operand.
5391 if (Parser.getTok().isNot(AsmToken::Comma)) {
5392 Error(Parser.getTok().getLoc(), "too few operands");
5393 return MatchOperand_ParseFail;
5394 }
5395 Parser.Lex(); // Eat hash token.
5396 if (Parser.getTok().isNot(AsmToken::Hash) &&
5397 Parser.getTok().isNot(AsmToken::Dollar)) {
5398 Error(Parser.getTok().getLoc(), "'#' expected");
5399 return MatchOperand_ParseFail;
5400 }
5401 Parser.Lex(); // Eat hash token.
5402
5403 const MCExpr *WidthExpr;
5404 SMLoc EndLoc;
5405 if (getParser().parseExpression(WidthExpr, EndLoc)) {
5406 Error(E, "malformed immediate expression");
5407 return MatchOperand_ParseFail;
5408 }
5409 CE = dyn_cast<MCConstantExpr>(WidthExpr);
5410 if (!CE) {
5411 Error(E, "'width' operand must be an immediate");
5412 return MatchOperand_ParseFail;
5413 }
5414
5415 int64_t Width = CE->getValue();
5416 // The LSB must be in the range [1,32-lsb]
5417 if (Width < 1 || Width > 32 - LSB) {
5418 Error(E, "'width' operand must be in the range [1,32-lsb]");
5419 return MatchOperand_ParseFail;
5420 }
5421
5422 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
5423
5424 return MatchOperand_Success;
5425}
5426
5427OperandMatchResultTy
5428ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
5429 // Check for a post-index addressing register operand. Specifically:
5430 // postidx_reg := '+' register {, shift}
5431 // | '-' register {, shift}
5432 // | register {, shift}
5433
5434 // This method must return MatchOperand_NoMatch without consuming any tokens
5435 // in the case where there is no match, as other alternatives take other
5436 // parse methods.
5437 MCAsmParser &Parser = getParser();
5438 AsmToken Tok = Parser.getTok();
5439 SMLoc S = Tok.getLoc();
5440 bool haveEaten = false;
5441 bool isAdd = true;
5442 if (Tok.is(AsmToken::Plus)) {
5443 Parser.Lex(); // Eat the '+' token.
5444 haveEaten = true;
5445 } else if (Tok.is(AsmToken::Minus)) {
5446 Parser.Lex(); // Eat the '-' token.
5447 isAdd = false;
5448 haveEaten = true;
5449 }
5450
5451 SMLoc E = Parser.getTok().getEndLoc();
5452 int Reg = tryParseRegister();
5453 if (Reg == -1) {
5454 if (!haveEaten)
5455 return MatchOperand_NoMatch;
5456 Error(Parser.getTok().getLoc(), "register expected");
5457 return MatchOperand_ParseFail;
5458 }
5459
5460 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
5461 unsigned ShiftImm = 0;
5462 if (Parser.getTok().is(AsmToken::Comma)) {
5463 Parser.Lex(); // Eat the ','.
5464 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
5465 return MatchOperand_ParseFail;
5466
5467 // FIXME: Only approximates end...may include intervening whitespace.
5468 E = Parser.getTok().getLoc();
5469 }
5470
5471 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
5472 ShiftImm, S, E));
5473
5474 return MatchOperand_Success;
5475}
5476
5477OperandMatchResultTy
5478ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
5479 // Check for a post-index addressing register operand. Specifically:
5480 // am3offset := '+' register
5481 // | '-' register
5482 // | register
5483 // | # imm
5484 // | # + imm
5485 // | # - imm
5486
5487 // This method must return MatchOperand_NoMatch without consuming any tokens
5488 // in the case where there is no match, as other alternatives take other
5489 // parse methods.
5490 MCAsmParser &Parser = getParser();
5491 AsmToken Tok = Parser.getTok();
5492 SMLoc S = Tok.getLoc();
5493
5494 // Do immediates first, as we always parse those if we have a '#'.
5495 if (Parser.getTok().is(AsmToken::Hash) ||
5496 Parser.getTok().is(AsmToken::Dollar)) {
5497 Parser.Lex(); // Eat '#' or '$'.
5498 // Explicitly look for a '-', as we need to encode negative zero
5499 // differently.
5500 bool isNegative = Parser.getTok().is(AsmToken::Minus);
5501 const MCExpr *Offset;
5502 SMLoc E;
5503 if (getParser().parseExpression(Offset, E))
5504 return MatchOperand_ParseFail;
5505 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
5506 if (!CE) {
5507 Error(S, "constant expression expected");
5508 return MatchOperand_ParseFail;
5509 }
5510 // Negative zero is encoded as the flag value
5511 // std::numeric_limits<int32_t>::min().
5512 int32_t Val = CE->getValue();
5513 if (isNegative && Val == 0)
5514 Val = std::numeric_limits<int32_t>::min();
5515
5516 Operands.push_back(
5517 ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E));
5518
5519 return MatchOperand_Success;
5520 }
5521
5522 bool haveEaten = false;
5523 bool isAdd = true;
5524 if (Tok.is(AsmToken::Plus)) {
5525 Parser.Lex(); // Eat the '+' token.
5526 haveEaten = true;
5527 } else if (Tok.is(AsmToken::Minus)) {
5528 Parser.Lex(); // Eat the '-' token.
5529 isAdd = false;
5530 haveEaten = true;
5531 }
5532
5533 Tok = Parser.getTok();
5534 int Reg = tryParseRegister();
5535 if (Reg == -1) {
5536 if (!haveEaten)
5537 return MatchOperand_NoMatch;
5538 Error(Tok.getLoc(), "register expected");
5539 return MatchOperand_ParseFail;
5540 }
5541
5542 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
5543 0, S, Tok.getEndLoc()));
5544
5545 return MatchOperand_Success;
5546}
5547
5548/// Convert parsed operands to MCInst. Needed here because this instruction
5549/// only has two register operands, but multiplication is commutative so
5550/// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
5551void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
5552 const OperandVector &Operands) {
5553 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
5554 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
5555 // If we have a three-operand form, make sure to set Rn to be the operand
5556 // that isn't the same as Rd.
5557 unsigned RegOp = 4;
5558 if (Operands.size() == 6 &&
5559 ((ARMOperand &)*Operands[4]).getReg() ==
5560 ((ARMOperand &)*Operands[3]).getReg())
5561 RegOp = 5;
5562 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
5563 Inst.addOperand(Inst.getOperand(0));
5564 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
5565}
5566
5567void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
5568 const OperandVector &Operands) {
5569 int CondOp = -1, ImmOp = -1;
5570 switch(Inst.getOpcode()) {
5571 case ARM::tB:
5572 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
5573
5574 case ARM::t2B:
5575 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
5576
5577 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches")::llvm::llvm_unreachable_internal("Unexpected instruction in cvtThumbBranches"
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 5577)
;
5578 }
5579 // first decide whether or not the branch should be conditional
5580 // by looking at it's location relative to an IT block
5581 if(inITBlock()) {
5582 // inside an IT block we cannot have any conditional branches. any
5583 // such instructions needs to be converted to unconditional form
5584 switch(Inst.getOpcode()) {
5585 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
5586 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
5587 }
5588 } else {
5589 // outside IT blocks we can only have unconditional branches with AL
5590 // condition code or conditional branches with non-AL condition code
5591 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
5592 switch(Inst.getOpcode()) {
5593 case ARM::tB:
5594 case ARM::tBcc:
5595 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
5596 break;
5597 case ARM::t2B:
5598 case ARM::t2Bcc:
5599 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
5600 break;
5601 }
5602 }
5603
5604 // now decide on encoding size based on branch target range
5605 switch(Inst.getOpcode()) {
5606 // classify tB as either t2B or t1B based on range of immediate operand
5607 case ARM::tB: {
5608 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
5609 if (!op.isSignedOffset<11, 1>() && isThumb() && hasV8MBaseline())
5610 Inst.setOpcode(ARM::t2B);
5611 break;
5612 }
5613 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
5614 case ARM::tBcc: {
5615 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
5616 if (!op.isSignedOffset<8, 1>() && isThumb() && hasV8MBaseline())
5617 Inst.setOpcode(ARM::t2Bcc);
5618 break;
5619 }
5620 }
5621 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
5622 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
5623}
5624
5625void ARMAsmParser::cvtMVEVMOVQtoDReg(
5626 MCInst &Inst, const OperandVector &Operands) {
5627
5628 // mnemonic, condition code, Rt, Rt2, Qd, idx, Qd again, idx2
5629 assert(Operands.size() == 8)((Operands.size() == 8) ? static_cast<void> (0) : __assert_fail
("Operands.size() == 8", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 5629, __PRETTY_FUNCTION__))
;
5630
5631 ((ARMOperand &)*Operands[2]).addRegOperands(Inst, 1); // Rt
5632 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); // Rt2
5633 ((ARMOperand &)*Operands[4]).addRegOperands(Inst, 1); // Qd
5634 ((ARMOperand &)*Operands[5]).addMVEPairVectorIndexOperands(Inst, 1); // idx
5635 // skip second copy of Qd in Operands[6]
5636 ((ARMOperand &)*Operands[7]).addMVEPairVectorIndexOperands(Inst, 1); // idx2
5637 ((ARMOperand &)*Operands[1]).addCondCodeOperands(Inst, 2); // condition code
5638}
5639
5640/// Parse an ARM memory expression, return false if successful else return true
5641/// or an error. The first token must be a '[' when called.
5642bool ARMAsmParser::parseMemory(OperandVector &Operands) {
5643 MCAsmParser &Parser = getParser();
5644 SMLoc S, E;
5645 if (Parser.getTok().isNot(AsmToken::LBrac))
5646 return TokError("Token is not a Left Bracket");
5647 S = Parser.getTok().getLoc();
5648 Parser.Lex(); // Eat left bracket token.
5649
5650 const AsmToken &BaseRegTok = Parser.getTok();
5651 int BaseRegNum = tryParseRegister();
5652 if (BaseRegNum == -1)
5653 return Error(BaseRegTok.getLoc(), "register expected");
5654
5655 // The next token must either be a comma, a colon or a closing bracket.
5656 const AsmToken &Tok = Parser.getTok();
5657 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
5658 !Tok.is(AsmToken::RBrac))
5659 return Error(Tok.getLoc(), "malformed memory operand");
5660
5661 if (Tok.is(AsmToken::RBrac)) {
5662 E = Tok.getEndLoc();
5663 Parser.Lex(); // Eat right bracket token.
5664
5665 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
5666 ARM_AM::no_shift, 0, 0, false,
5667 S, E));
5668
5669 // If there's a pre-indexing writeback marker, '!', just add it as a token
5670 // operand. It's rather odd, but syntactically valid.
5671 if (Parser.getTok().is(AsmToken::Exclaim)) {
5672 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5673 Parser.Lex(); // Eat the '!'.
5674 }
5675
5676 return false;
5677 }
5678
5679 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&(((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
"Lost colon or comma in memory operand?!") ? static_cast<
void> (0) : __assert_fail ("(Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) && \"Lost colon or comma in memory operand?!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 5680, __PRETTY_FUNCTION__))
5680 "Lost colon or comma in memory operand?!")(((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
"Lost colon or comma in memory operand?!") ? static_cast<
void> (0) : __assert_fail ("(Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) && \"Lost colon or comma in memory operand?!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 5680, __PRETTY_FUNCTION__))
;
5681 if (Tok.is(AsmToken::Comma)) {
5682 Parser.Lex(); // Eat the comma.
5683 }
5684
5685 // If we have a ':', it's an alignment specifier.
5686 if (Parser.getTok().is(AsmToken::Colon)) {
5687 Parser.Lex(); // Eat the ':'.
5688 E = Parser.getTok().getLoc();
5689 SMLoc AlignmentLoc = Tok.getLoc();
5690
5691 const MCExpr *Expr;
5692 if (getParser().parseExpression(Expr))
5693 return true;
5694
5695 // The expression has to be a constant. Memory references with relocations
5696 // don't come through here, as they use the <label> forms of the relevant
5697 // instructions.
5698 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5699 if (!CE)
5700 return Error (E, "constant expression expected");
5701
5702 unsigned Align = 0;
5703 switch (CE->getValue()) {
5704 default:
5705 return Error(E,
5706 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
5707 case 16: Align = 2; break;
5708 case 32: Align = 4; break;
5709 case 64: Align = 8; break;
5710 case 128: Align = 16; break;
5711 case 256: Align = 32; break;
5712 }
5713
5714 // Now we should have the closing ']'
5715 if (Parser.getTok().isNot(AsmToken::RBrac))
5716 return Error(Parser.getTok().getLoc(), "']' expected");
5717 E = Parser.getTok().getEndLoc();
5718 Parser.Lex(); // Eat right bracket token.
5719
5720 // Don't worry about range checking the value here. That's handled by
5721 // the is*() predicates.
5722 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
5723 ARM_AM::no_shift, 0, Align,
5724 false, S, E, AlignmentLoc));
5725
5726 // If there's a pre-indexing writeback marker, '!', just add it as a token
5727 // operand.
5728 if (Parser.getTok().is(AsmToken::Exclaim)) {
5729 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5730 Parser.Lex(); // Eat the '!'.
5731 }
5732
5733 return false;
5734 }
5735
5736 // If we have a '#', it's an immediate offset, else assume it's a register
5737 // offset. Be friendly and also accept a plain integer (without a leading
5738 // hash) for gas compatibility.
5739 if (Parser.getTok().is(AsmToken::Hash) ||
5740 Parser.getTok().is(AsmToken::Dollar) ||
5741 Parser.getTok().is(AsmToken::Integer)) {
5742 if (Parser.getTok().isNot(AsmToken::Integer))
5743 Parser.Lex(); // Eat '#' or '$'.
5744 E = Parser.getTok().getLoc();
5745
5746 bool isNegative = getParser().getTok().is(AsmToken::Minus);
5747 const MCExpr *Offset;
5748 if (getParser().parseExpression(Offset))
5749 return true;
5750
5751 // The expression has to be a constant. Memory references with relocations
5752 // don't come through here, as they use the <label> forms of the relevant
5753 // instructions.
5754 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
5755 if (!CE)
5756 return Error (E, "constant expression expected");
5757
5758 // If the constant was #-0, represent it as
5759 // std::numeric_limits<int32_t>::min().
5760 int32_t Val = CE->getValue();
5761 if (isNegative && Val == 0)
5762 CE = MCConstantExpr::create(std::numeric_limits<int32_t>::min(),
5763 getContext());
5764
5765 // Now we should have the closing ']'
5766 if (Parser.getTok().isNot(AsmToken::RBrac))
5767 return Error(Parser.getTok().getLoc(), "']' expected");
5768 E = Parser.getTok().getEndLoc();
5769 Parser.Lex(); // Eat right bracket token.
5770
5771 // Don't worry about range checking the value here. That's handled by
5772 // the is*() predicates.
5773 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
5774 ARM_AM::no_shift, 0, 0,
5775 false, S, E));
5776
5777 // If there's a pre-indexing writeback marker, '!', just add it as a token
5778 // operand.
5779 if (Parser.getTok().is(AsmToken::Exclaim)) {
5780 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5781 Parser.Lex(); // Eat the '!'.
5782 }
5783
5784 return false;
5785 }
5786
5787 // The register offset is optionally preceded by a '+' or '-'
5788 bool isNegative = false;
5789 if (Parser.getTok().is(AsmToken::Minus)) {
5790 isNegative = true;
5791 Parser.Lex(); // Eat the '-'.
5792 } else if (Parser.getTok().is(AsmToken::Plus)) {
5793 // Nothing to do.
5794 Parser.Lex(); // Eat the '+'.
5795 }
5796
5797 E = Parser.getTok().getLoc();
5798 int OffsetRegNum = tryParseRegister();
5799 if (OffsetRegNum == -1)
5800 return Error(E, "register expected");
5801
5802 // If there's a shift operator, handle it.
5803 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
5804 unsigned ShiftImm = 0;
5805 if (Parser.getTok().is(AsmToken::Comma)) {
5806 Parser.Lex(); // Eat the ','.
5807 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
5808 return true;
5809 }
5810
5811 // Now we should have the closing ']'
5812 if (Parser.getTok().isNot(AsmToken::RBrac))
5813 return Error(Parser.getTok().getLoc(), "']' expected");
5814 E = Parser.getTok().getEndLoc();
5815 Parser.Lex(); // Eat right bracket token.
5816
5817 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
5818 ShiftType, ShiftImm, 0, isNegative,
5819 S, E));
5820
5821 // If there's a pre-indexing writeback marker, '!', just add it as a token
5822 // operand.
5823 if (Parser.getTok().is(AsmToken::Exclaim)) {
5824 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5825 Parser.Lex(); // Eat the '!'.
5826 }
5827
5828 return false;
5829}
5830
5831/// parseMemRegOffsetShift - one of these two:
5832/// ( lsl | lsr | asr | ror ) , # shift_amount
5833/// rrx
5834/// return true if it parses a shift otherwise it returns false.
5835bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
5836 unsigned &Amount) {
5837 MCAsmParser &Parser = getParser();
5838 SMLoc Loc = Parser.getTok().getLoc();
5839 const AsmToken &Tok = Parser.getTok();
5840 if (Tok.isNot(AsmToken::Identifier))
5841 return Error(Loc, "illegal shift operator");
5842 StringRef ShiftName = Tok.getString();
5843 if (ShiftName == "lsl" || ShiftName == "LSL" ||
5844 ShiftName == "asl" || ShiftName == "ASL")
5845 St = ARM_AM::lsl;
5846 else if (ShiftName == "lsr" || ShiftName == "LSR")
5847 St = ARM_AM::lsr;
5848 else if (ShiftName == "asr" || ShiftName == "ASR")
5849 St = ARM_AM::asr;
5850 else if (ShiftName == "ror" || ShiftName == "ROR")
5851 St = ARM_AM::ror;
5852 else if (ShiftName == "rrx" || ShiftName == "RRX")
5853 St = ARM_AM::rrx;
5854 else if (ShiftName == "uxtw" || ShiftName == "UXTW")
5855 St = ARM_AM::uxtw;
5856 else
5857 return Error(Loc, "illegal shift operator");
5858 Parser.Lex(); // Eat shift type token.
5859
5860 // rrx stands alone.
5861 Amount = 0;
5862 if (St != ARM_AM::rrx) {
5863 Loc = Parser.getTok().getLoc();
5864 // A '#' and a shift amount.
5865 const AsmToken &HashTok = Parser.getTok();
5866 if (HashTok.isNot(AsmToken::Hash) &&
5867 HashTok.isNot(AsmToken::Dollar))
5868 return Error(HashTok.getLoc(), "'#' expected");
5869 Parser.Lex(); // Eat hash token.
5870
5871 const MCExpr *Expr;
5872 if (getParser().parseExpression(Expr))
5873 return true;
5874 // Range check the immediate.
5875 // lsl, ror: 0 <= imm <= 31
5876 // lsr, asr: 0 <= imm <= 32
5877 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5878 if (!CE)
5879 return Error(Loc, "shift amount must be an immediate");
5880 int64_t Imm = CE->getValue();
5881 if (Imm < 0 ||
5882 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
5883 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
5884 return Error(Loc, "immediate shift value out of range");
5885 // If <ShiftTy> #0, turn it into a no_shift.
5886 if (Imm == 0)
5887 St = ARM_AM::lsl;
5888 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
5889 if (Imm == 32)
5890 Imm = 0;
5891 Amount = Imm;
5892 }
5893
5894 return false;
5895}
5896
5897/// parseFPImm - A floating point immediate expression operand.
5898OperandMatchResultTy
5899ARMAsmParser::parseFPImm(OperandVector &Operands) {
5900 MCAsmParser &Parser = getParser();
5901 // Anything that can accept a floating point constant as an operand
5902 // needs to go through here, as the regular parseExpression is
5903 // integer only.
5904 //
5905 // This routine still creates a generic Immediate operand, containing
5906 // a bitcast of the 64-bit floating point value. The various operands
5907 // that accept floats can check whether the value is valid for them
5908 // via the standard is*() predicates.
5909
5910 SMLoc S = Parser.getTok().getLoc();
5911
5912 if (Parser.getTok().isNot(AsmToken::Hash) &&
5913 Parser.getTok().isNot(AsmToken::Dollar))
5914 return MatchOperand_NoMatch;
5915
5916 // Disambiguate the VMOV forms that can accept an FP immediate.
5917 // vmov.f32 <sreg>, #imm
5918 // vmov.f64 <dreg>, #imm
5919 // vmov.f32 <dreg>, #imm @ vector f32x2
5920 // vmov.f32 <qreg>, #imm @ vector f32x4
5921 //
5922 // There are also the NEON VMOV instructions which expect an
5923 // integer constant. Make sure we don't try to parse an FPImm
5924 // for these:
5925 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
5926 ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
5927 bool isVmovf = TyOp.isToken() &&
5928 (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64" ||
5929 TyOp.getToken() == ".f16");
5930 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
5931 bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
5932 Mnemonic.getToken() == "fconsts");
5933 if (!(isVmovf || isFconst))
5934 return MatchOperand_NoMatch;
5935
5936 Parser.Lex(); // Eat '#' or '$'.
5937
5938 // Handle negation, as that still comes through as a separate token.
5939 bool isNegative = false;
5940 if (Parser.getTok().is(AsmToken::Minus)) {
5941 isNegative = true;
5942 Parser.Lex();
5943 }
5944 const AsmToken &Tok = Parser.getTok();
5945 SMLoc Loc = Tok.getLoc();
5946 if (Tok.is(AsmToken::Real) && isVmovf) {
5947 APFloat RealVal(APFloat::IEEEsingle(), Tok.getString());
5948 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
5949 // If we had a '-' in front, toggle the sign bit.
5950 IntVal ^= (uint64_t)isNegative << 31;
5951 Parser.Lex(); // Eat the token.
5952 Operands.push_back(ARMOperand::CreateImm(
5953 MCConstantExpr::create(IntVal, getContext()),
5954 S, Parser.getTok().getLoc()));
5955 return MatchOperand_Success;
5956 }
5957 // Also handle plain integers. Instructions which allow floating point
5958 // immediates also allow a raw encoded 8-bit value.
5959 if (Tok.is(AsmToken::Integer) && isFconst) {
5960 int64_t Val = Tok.getIntVal();
5961 Parser.Lex(); // Eat the token.
5962 if (Val > 255 || Val < 0) {
5963 Error(Loc, "encoded floating point value out of range");
5964 return MatchOperand_ParseFail;
5965 }
5966 float RealVal = ARM_AM::getFPImmFloat(Val);
5967 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
5968
5969 Operands.push_back(ARMOperand::CreateImm(
5970 MCConstantExpr::create(Val, getContext()), S,
5971 Parser.getTok().getLoc()));
5972 return MatchOperand_Success;
5973 }
5974
5975 Error(Loc, "invalid floating point immediate");
5976 return MatchOperand_ParseFail;
5977}
5978
5979/// Parse a arm instruction operand. For now this parses the operand regardless
5980/// of the mnemonic.
5981bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
5982 MCAsmParser &Parser = getParser();
5983 SMLoc S, E;
5984
5985 // Check if the current operand has a custom associated parser, if so, try to
5986 // custom parse the operand, or fallback to the general approach.
5987 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
5988 if (ResTy == MatchOperand_Success)
5989 return false;
5990 // If there wasn't a custom match, try the generic matcher below. Otherwise,
5991 // there was a match, but an error occurred, in which case, just return that
5992 // the operand parsing failed.
5993 if (ResTy == MatchOperand_ParseFail)
5994 return true;
5995
5996 switch (getLexer().getKind()) {
5997 default:
5998 Error(Parser.getTok().getLoc(), "unexpected token in operand");
5999 return true;
6000 case AsmToken::Identifier: {
6001 // If we've seen a branch mnemonic, the next operand must be a label. This
6002 // is true even if the label is a register name. So "br r1" means branch to
6003 // label "r1".
6004 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
6005 if (!ExpectLabel) {
6006 if (!tryParseRegisterWithWriteBack(Operands))
6007 return false;
6008 int Res = tryParseShiftRegister(Operands);
6009 if (Res == 0) // success
6010 return false;
6011 else if (Res == -1) // irrecoverable error
6012 return true;
6013 // If this is VMRS, check for the apsr_nzcv operand.
6014 if (Mnemonic == "vmrs" &&
6015 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
6016 S = Parser.getTok().getLoc();
6017 Parser.Lex();
6018 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
6019 return false;
6020 }
6021 }
6022
6023 // Fall though for the Identifier case that is not a register or a
6024 // special name.
6025 LLVM_FALLTHROUGH[[gnu::fallthrough]];
6026 }
6027 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
6028 case AsmToken::Integer: // things like 1f and 2b as a branch targets
6029 case AsmToken::String: // quoted label names.
6030 case AsmToken::Dot: { // . as a branch target
6031 // This was not a register so parse other operands that start with an
6032 // identifier (like labels) as expressions and create them as immediates.
6033 const MCExpr *IdVal;
6034 S = Parser.getTok().getLoc();
6035 if (getParser().parseExpression(IdVal))
6036 return true;
6037 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6038 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
6039 return false;
6040 }
6041 case AsmToken::LBrac:
6042 return parseMemory(Operands);
6043 case AsmToken::LCurly:
6044 return parseRegisterList(Operands, !Mnemonic.startswith("clr"));
6045 case AsmToken::Dollar:
6046 case AsmToken::Hash:
6047 // #42 -> immediate.
6048 S = Parser.getTok().getLoc();
6049 Parser.Lex();
6050
6051 if (Parser.getTok().isNot(AsmToken::Colon)) {
6052 bool isNegative = Parser.getTok().is(AsmToken::Minus);
6053 const MCExpr *ImmVal;
6054 if (getParser().parseExpression(ImmVal))
6055 return true;
6056 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
6057 if (CE) {
6058 int32_t Val = CE->getValue();
6059 if (isNegative && Val == 0)
6060 ImmVal = MCConstantExpr::create(std::numeric_limits<int32_t>::min(),
6061 getContext());
6062 }
6063 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6064 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
6065
6066 // There can be a trailing '!' on operands that we want as a separate
6067 // '!' Token operand. Handle that here. For example, the compatibility
6068 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
6069 if (Parser.getTok().is(AsmToken::Exclaim)) {
6070 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
6071 Parser.getTok().getLoc()));
6072 Parser.Lex(); // Eat exclaim token
6073 }
6074 return false;
6075 }
6076 // w/ a ':' after the '#', it's just like a plain ':'.
6077 LLVM_FALLTHROUGH[[gnu::fallthrough]];
6078
6079 case AsmToken::Colon: {
6080 S = Parser.getTok().getLoc();
6081 // ":lower16:" and ":upper16:" expression prefixes
6082 // FIXME: Check it's an expression prefix,
6083 // e.g. (FOO - :lower16:BAR) isn't legal.
6084 ARMMCExpr::VariantKind RefKind;
6085 if (parsePrefix(RefKind))
6086 return true;
6087
6088 const MCExpr *SubExprVal;
6089 if (getParser().parseExpression(SubExprVal))
6090 return true;
6091
6092 const MCExpr *ExprVal = ARMMCExpr::create(RefKind, SubExprVal,
6093 getContext());
6094 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6095 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
6096 return false;
6097 }
6098 case AsmToken::Equal: {
6099 S = Parser.getTok().getLoc();
6100 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
6101 return Error(S, "unexpected token in operand");
6102 Parser.Lex(); // Eat '='
6103 const MCExpr *SubExprVal;
6104 if (getParser().parseExpression(SubExprVal))
6105 return true;
6106 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6107
6108 // execute-only: we assume that assembly programmers know what they are
6109 // doing and allow literal pool creation here
6110 Operands.push_back(ARMOperand::CreateConstantPoolImm(SubExprVal, S, E));
6111 return false;
6112 }
6113 }
6114}
6115
6116// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
6117// :lower16: and :upper16:.
6118bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
6119 MCAsmParser &Parser = getParser();
6120 RefKind = ARMMCExpr::VK_ARM_None;
6121
6122 // consume an optional '#' (GNU compatibility)
6123 if (getLexer().is(AsmToken::Hash))
6124 Parser.Lex();
6125
6126 // :lower16: and :upper16: modifiers
6127 assert(getLexer().is(AsmToken::Colon) && "expected a :")((getLexer().is(AsmToken::Colon) && "expected a :") ?
static_cast<void> (0) : __assert_fail ("getLexer().is(AsmToken::Colon) && \"expected a :\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 6127, __PRETTY_FUNCTION__))
;
6128 Parser.Lex(); // Eat ':'
6129
6130 if (getLexer().isNot(AsmToken::Identifier)) {
6131 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
6132 return true;
6133 }
6134
6135 enum {
6136 COFF = (1 << MCObjectFileInfo::IsCOFF),
6137 ELF = (1 << MCObjectFileInfo::IsELF),
6138 MACHO = (1 << MCObjectFileInfo::IsMachO),
6139 WASM = (1 << MCObjectFileInfo::IsWasm),
6140 };
6141 static const struct PrefixEntry {
6142 const char *Spelling;
6143 ARMMCExpr::VariantKind VariantKind;
6144 uint8_t SupportedFormats;
6145 } PrefixEntries[] = {
6146 { "lower16", ARMMCExpr::VK_ARM_LO16, COFF | ELF | MACHO },
6147 { "upper16", ARMMCExpr::VK_ARM_HI16, COFF | ELF | MACHO },
6148 };
6149
6150 StringRef IDVal = Parser.getTok().getIdentifier();
6151
6152 const auto &Prefix =
6153 std::find_if(std::begin(PrefixEntries), std::end(PrefixEntries),
6154 [&IDVal](const PrefixEntry &PE) {
6155 return PE.Spelling == IDVal;
6156 });
6157 if (Prefix == std::end(PrefixEntries)) {
6158 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
6159 return true;
6160 }
6161
6162 uint8_t CurrentFormat;
6163 switch (getContext().getObjectFileInfo()->getObjectFileType()) {
6164 case MCObjectFileInfo::IsMachO:
6165 CurrentFormat = MACHO;
6166 break;
6167 case MCObjectFileInfo::IsELF:
6168 CurrentFormat = ELF;
6169 break;
6170 case MCObjectFileInfo::IsCOFF:
6171 CurrentFormat = COFF;
6172 break;
6173 case MCObjectFileInfo::IsWasm:
6174 CurrentFormat = WASM;
6175 break;
6176 case MCObjectFileInfo::IsXCOFF:
6177 llvm_unreachable("unexpected object format")::llvm::llvm_unreachable_internal("unexpected object format",
"/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 6177)
;
6178 break;
6179 }
6180
6181 if (~Prefix->SupportedFormats & CurrentFormat) {
6182 Error(Parser.getTok().getLoc(),
6183 "cannot represent relocation in the current file format");
6184 return true;
6185 }
6186
6187 RefKind = Prefix->VariantKind;
6188 Parser.Lex();
6189
6190 if (getLexer().isNot(AsmToken::Colon)) {
6191 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
6192 return true;
6193 }
6194 Parser.Lex(); // Eat the last ':'
6195
6196 return false;
6197}
6198
6199/// Given a mnemonic, split out possible predication code and carry
6200/// setting letters to form a canonical mnemonic and flags.
6201//
6202// FIXME: Would be nice to autogen this.
6203// FIXME: This is a bit of a maze of special cases.
6204StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
6205 StringRef ExtraToken,
6206 unsigned &PredicationCode,
6207 unsigned &VPTPredicationCode,
6208 bool &CarrySetting,
6209 unsigned &ProcessorIMod,
6210 StringRef &ITMask) {
6211 PredicationCode = ARMCC::AL;
6212 VPTPredicationCode = ARMVCC::None;
6213 CarrySetting = false;
6214 ProcessorIMod = 0;
6215
6216 // Ignore some mnemonics we know aren't predicated forms.
6217 //
6218 // FIXME: Would be nice to autogen this.
6219 if ((Mnemonic == "movs" && isThumb()) ||
6220 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
6221 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
6222 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
6223 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
6224 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
6225 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
6226 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
6227 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
6228 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
6229 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
6230 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
6231 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
6232 Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx" ||
6233 Mnemonic == "bxns" || Mnemonic == "blxns" ||
6234 Mnemonic == "vudot" || Mnemonic == "vsdot" ||
6235 Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
6236 Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
6237 Mnemonic == "wls" || Mnemonic == "le" || Mnemonic == "dls" ||
6238 Mnemonic == "csel" || Mnemonic == "csinc" ||
6239 Mnemonic == "csinv" || Mnemonic == "csneg" || Mnemonic == "cinc" ||
6240 Mnemonic == "cinv" || Mnemonic == "cneg" || Mnemonic == "cset" ||
6241 Mnemonic == "csetm")
6242 return Mnemonic;
6243
6244 // First, split out any predication code. Ignore mnemonics we know aren't
6245 // predicated but do have a carry-set and so weren't caught above.
6246 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
6247 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
6248 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
6249 Mnemonic != "sbcs" && Mnemonic != "rscs" &&
6250 !(hasMVE() &&
6251 (Mnemonic == "vmine" ||
6252 Mnemonic == "vshle" || Mnemonic == "vshlt" || Mnemonic == "vshllt" ||
6253 Mnemonic == "vrshle" || Mnemonic == "vrshlt" ||
6254 Mnemonic == "vmvne" || Mnemonic == "vorne" ||
6255 Mnemonic == "vnege" || Mnemonic == "vnegt" ||
6256 Mnemonic == "vmule" || Mnemonic == "vmult" ||
6257 Mnemonic == "vrintne" ||
6258 Mnemonic == "vcmult" || Mnemonic == "vcmule" ||
6259 Mnemonic == "vpsele" || Mnemonic == "vpselt" ||
6260 Mnemonic.startswith("vq")))) {
6261 unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
6262 if (CC != ~0U) {
6263 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
6264 PredicationCode = CC;
6265 }
6266 }
6267
6268 // Next, determine if we have a carry setting bit. We explicitly ignore all
6269 // the instructions we know end in 's'.
6270 if (Mnemonic.endswith("s") &&
6271 !(Mnemonic == "cps" || Mnemonic == "mls" ||
6272 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
6273 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
6274 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
6275 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
6276 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
6277 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
6278 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
6279 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
6280 Mnemonic == "bxns" || Mnemonic == "blxns" || Mnemonic == "vfmas" ||
6281 Mnemonic == "vmlas" ||
6282 (Mnemonic == "movs" && isThumb()))) {
6283 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
6284 CarrySetting = true;
6285 }
6286
6287 // The "cps" instruction can have a interrupt mode operand which is glued into
6288 // the mnemonic. Check if this is the case, split it and parse the imod op
6289 if (Mnemonic.startswith("cps")) {
6290 // Split out any imod code.
6291 unsigned IMod =
6292 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
6293 .Case("ie", ARM_PROC::IE)
6294 .Case("id", ARM_PROC::ID)
6295 .Default(~0U);
6296 if (IMod != ~0U) {
6297 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
6298 ProcessorIMod = IMod;
6299 }
6300 }
6301
6302 if (isMnemonicVPTPredicable(Mnemonic, ExtraToken) && Mnemonic != "vmovlt" &&
6303 Mnemonic != "vshllt" && Mnemonic != "vrshrnt" && Mnemonic != "vshrnt" &&
6304 Mnemonic != "vqrshrunt" && Mnemonic != "vqshrunt" &&
6305 Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt" && Mnemonic != "vmullt" &&
6306 Mnemonic != "vqmovnt" && Mnemonic != "vqmovunt" &&
6307 Mnemonic != "vqmovnt" && Mnemonic != "vmovnt" && Mnemonic != "vqdmullt" &&
6308 Mnemonic != "vpnot" && Mnemonic != "vcvtt" && Mnemonic != "vcvt") {
6309 unsigned CC = ARMVectorCondCodeFromString(Mnemonic.substr(Mnemonic.size()-1));
6310 if (CC != ~0U) {
6311 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-1);
6312 VPTPredicationCode = CC;
6313 }
6314 return Mnemonic;
6315 }
6316
6317 // The "it" instruction has the condition mask on the end of the mnemonic.
6318 if (Mnemonic.startswith("it")) {
6319 ITMask = Mnemonic.slice(2, Mnemonic.size());
6320 Mnemonic = Mnemonic.slice(0, 2);
6321 }
6322
6323 if (Mnemonic.startswith("vpst")) {
6324 ITMask = Mnemonic.slice(4, Mnemonic.size());
6325 Mnemonic = Mnemonic.slice(0, 4);
6326 }
6327 else if (Mnemonic.startswith("vpt")) {
6328 ITMask = Mnemonic.slice(3, Mnemonic.size());
6329 Mnemonic = Mnemonic.slice(0, 3);
6330 }
6331
6332 return Mnemonic;
6333}
6334
6335/// Given a canonical mnemonic, determine if the instruction ever allows
6336/// inclusion of carry set or predication code operands.
6337//
6338// FIXME: It would be nice to autogen this.
6339void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic,
6340 StringRef ExtraToken,
6341 StringRef FullInst,
6342 bool &CanAcceptCarrySet,
6343 bool &CanAcceptPredicationCode,
6344 bool &CanAcceptVPTPredicationCode) {
6345 CanAcceptVPTPredicationCode = isMnemonicVPTPredicable(Mnemonic, ExtraToken);
6346
6347 CanAcceptCarrySet =
6348 Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
6349 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
6350 Mnemonic == "add" || Mnemonic == "adc" || Mnemonic == "mul" ||
6351 Mnemonic == "bic" || Mnemonic == "asr" || Mnemonic == "orr" ||
6352 Mnemonic == "mvn" || Mnemonic == "rsb" || Mnemonic == "rsc" ||
6353 Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "eor" ||
6354 Mnemonic == "neg" || Mnemonic == "vfm" || Mnemonic == "vfnm" ||
6355 (!isThumb() &&
6356 (Mnemonic == "smull" || Mnemonic == "mov" || Mnemonic == "mla" ||
6357 Mnemonic == "smlal" || Mnemonic == "umlal" || Mnemonic == "umull"));
6358
6359 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
6360 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
6361 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
6362 Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
6363 Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" ||
6364 Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" ||
6365 Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" ||
6366 Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
6367 Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
6368 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
6369 (FullInst.startswith("vmull") && FullInst.endswith(".p64")) ||
6370 Mnemonic == "vmovx" || Mnemonic == "vins" ||
6371 Mnemonic == "vudot" || Mnemonic == "vsdot" ||
6372 Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
6373 Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
6374 Mnemonic == "sb" || Mnemonic == "ssbb" ||
6375 Mnemonic == "pssbb" ||
6376 Mnemonic == "bfcsel" || Mnemonic == "wls" ||
6377 Mnemonic == "dls" || Mnemonic == "le" || Mnemonic == "csel" ||
6378 Mnemonic == "csinc" || Mnemonic == "csinv" || Mnemonic == "csneg" ||
6379 Mnemonic == "cinc" || Mnemonic == "cinv" || Mnemonic == "cneg" ||
6380 Mnemonic == "cset" || Mnemonic == "csetm" ||
6381 Mnemonic.startswith("vpt") || Mnemonic.startswith("vpst") ||
6382 (hasMVE() &&
6383 (Mnemonic.startswith("vst2") || Mnemonic.startswith("vld2") ||
6384 Mnemonic.startswith("vst4") || Mnemonic.startswith("vld4") ||
6385 Mnemonic.startswith("wlstp") || Mnemonic.startswith("dlstp") ||
6386 Mnemonic.startswith("letp")))) {
6387 // These mnemonics are never predicable
6388 CanAcceptPredicationCode = false;
6389 } else if (!isThumb()) {
6390 // Some instructions are only predicable in Thumb mode
6391 CanAcceptPredicationCode =
6392 Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
6393 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
6394 Mnemonic != "dmb" && Mnemonic != "dfb" && Mnemonic != "dsb" &&
6395 Mnemonic != "isb" && Mnemonic != "pld" && Mnemonic != "pli" &&
6396 Mnemonic != "pldw" && Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
6397 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
6398 Mnemonic != "tsb" &&
6399 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
6400 } else if (isThumbOne()) {
6401 if (hasV6MOps())
6402 CanAcceptPredicationCode = Mnemonic != "movs";
6403 else
6404 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
6405 } else
6406 CanAcceptPredicationCode = true;
6407}
6408
6409// Some Thumb instructions have two operand forms that are not
6410// available as three operand, convert to two operand form if possible.
6411//
6412// FIXME: We would really like to be able to tablegen'erate this.
6413void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
6414 bool CarrySetting,
6415 OperandVector &Operands) {
6416 if (Operands.size() != 6)
6417 return;
6418
6419 const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]);
6420 auto &Op4 = static_cast<ARMOperand &>(*Operands[4]);
6421 if (!Op3.isReg() || !Op4.isReg())
6422 return;
6423
6424 auto Op3Reg = Op3.getReg();
6425 auto Op4Reg = Op4.getReg();
6426
6427 // For most Thumb2 cases we just generate the 3 operand form and reduce
6428 // it in processInstruction(), but the 3 operand form of ADD (t2ADDrr)
6429 // won't accept SP or PC so we do the transformation here taking care
6430 // with immediate range in the 'add sp, sp #imm' case.
6431 auto &Op5 = static_cast<ARMOperand &>(*Operands[5]);
6432 if (isThumbTwo()) {
6433 if (Mnemonic != "add")
6434 return;
6435 bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC ||
6436 (Op5.isReg() && Op5.getReg() == ARM::PC);
6437 if (!TryTransform) {
6438 TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP ||
6439 (Op5.isReg() && Op5.getReg() == ARM::SP)) &&
6440 !(Op3Reg == ARM::SP && Op4Reg == ARM::SP &&
6441 Op5.isImm() && !Op5.isImm0_508s4());
6442 }
6443 if (!TryTransform)
6444 return;
6445 } else if (!isThumbOne())
6446 return;
6447
6448 if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
6449 Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
6450 Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" ||
6451 Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic"))
6452 return;
6453
6454 // If first 2 operands of a 3 operand instruction are the same
6455 // then transform to 2 operand version of the same instruction
6456 // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
6457 bool Transform = Op3Reg == Op4Reg;
6458
6459 // For communtative operations, we might be able to transform if we swap
6460 // Op4 and Op5. The 'ADD Rdm, SP, Rdm' form is already handled specially
6461 // as tADDrsp.
6462 const ARMOperand *LastOp = &Op5;
6463 bool Swap = false;
6464 if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() &&
6465 ((Mnemonic == "add" && Op4Reg != ARM::SP) ||
6466 Mnemonic == "and" || Mnemonic == "eor" ||
6467 Mnemonic == "adc" || Mnemonic == "orr")) {
6468 Swap = true;
6469 LastOp = &Op4;
6470 Transform = true;
6471 }
6472
6473 // If both registers are the same then remove one of them from
6474 // the operand list, with certain exceptions.
6475 if (Transform) {
6476 // Don't transform 'adds Rd, Rd, Rm' or 'sub{s} Rd, Rd, Rm' because the
6477 // 2 operand forms don't exist.
6478 if (((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub") &&
6479 LastOp->isReg())
6480 Transform = false;
6481
6482 // Don't transform 'add/sub{s} Rd, Rd, #imm' if the immediate fits into
6483 // 3-bits because the ARMARM says not to.
6484 if ((Mnemonic == "add" || Mnemonic == "sub") && LastOp->isImm0_7())
6485 Transform = false;
6486 }
6487
6488 if (Transform) {
6489 if (Swap)
6490 std::swap(Op4, Op5);
6491 Operands.erase(Operands.begin() + 3);
6492 }
6493}
6494
6495bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
6496 OperandVector &Operands) {
6497 // FIXME: This is all horribly hacky. We really need a better way to deal
6498 // with optional operands like this in the matcher table.
6499
6500 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
6501 // another does not. Specifically, the MOVW instruction does not. So we
6502 // special case it here and remove the defaulted (non-setting) cc_out
6503 // operand if that's the instruction we're trying to match.
6504 //
6505 // We do this as post-processing of the explicit operands rather than just
6506 // conditionally adding the cc_out in the first place because we need
6507 // to check the type of the parsed immediate operand.
6508 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
6509 !static_cast<ARMOperand &>(*Operands[4]).isModImm() &&
6510 static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
6511 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
6512 return true;
6513
6514 // Register-register 'add' for thumb does not have a cc_out operand
6515 // when there are only two register operands.
6516 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
6517 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6518 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6519 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
6520 return true;
6521 // Register-register 'add' for thumb does not have a cc_out operand
6522 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
6523 // have to check the immediate range here since Thumb2 has a variant
6524 // that can handle a different range and has a cc_out operand.
6525 if (((isThumb() && Mnemonic == "add") ||
6526 (isThumbTwo() && Mnemonic == "sub")) &&
6527 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6528 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6529 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
6530 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6531 ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
6532 static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
6533 return true;
6534 // For Thumb2, add/sub immediate does not have a cc_out operand for the
6535 // imm0_4095 variant. That's the least-preferred variant when
6536 // selecting via the generic "add" mnemonic, so to know that we
6537 // should remove the cc_out operand, we have to explicitly check that
6538 // it's not one of the other variants. Ugh.
6539 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
6540 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6541 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6542 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
6543 // Nest conditions rather than one big 'if' statement for readability.
6544 //
6545 // If both registers are low, we're in an IT block, and the immediate is
6546 // in range, we should use encoding T1 instead, which has a cc_out.
6547 if (inITBlock() &&
6548 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
6549 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
6550 static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
6551 return false;
6552 // Check against T3. If the second register is the PC, this is an
6553 // alternate form of ADR, which uses encoding T4, so check for that too.
6554 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
6555 static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
6556 return false;
6557
6558 // Otherwise, we use encoding T4, which does not have a cc_out
6559 // operand.
6560 return true;
6561 }
6562
6563 // The thumb2 multiply instruction doesn't have a CCOut register, so
6564 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
6565 // use the 16-bit encoding or not.
6566 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
6567 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6568 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6569 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6570 static_cast<ARMOperand &>(*Operands[5]).isReg() &&
6571 // If the registers aren't low regs, the destination reg isn't the
6572 // same as one of the source regs, or the cc_out operand is zero
6573 // outside of an IT block, we have to use the 32-bit encoding, so
6574 // remove the cc_out operand.
6575 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
6576 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
6577 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
6578 !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
6579 static_cast<ARMOperand &>(*Operands[5]).getReg() &&
6580 static_cast<ARMOperand &>(*Operands[3]).getReg() !=
6581 static_cast<ARMOperand &>(*Operands[4]).getReg())))
6582 return true;
6583
6584 // Also check the 'mul' syntax variant that doesn't specify an explicit
6585 // destination register.
6586 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
6587 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6588 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6589 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6590 // If the registers aren't low regs or the cc_out operand is zero
6591 // outside of an IT block, we have to use the 32-bit encoding, so
6592 // remove the cc_out operand.
6593 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
6594 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
6595 !inITBlock()))
6596 return true;
6597
6598 // Register-register 'add/sub' for thumb does not have a cc_out operand
6599 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
6600 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
6601 // right, this will result in better diagnostics (which operand is off)
6602 // anyway.
6603 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
6604 (Operands.size() == 5 || Operands.size() == 6) &&
6605 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6606 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
6607 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6608 (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
6609 (Operands.size() == 6 &&
6610 static_cast<ARMOperand &>(*Operands[5]).isImm())))
6611 return true;
6612
6613 return false;
6614}
6615
6616bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
6617 OperandVector &Operands) {
6618 // VRINT{Z, X} have a predicate operand in VFP, but not in NEON
6619 unsigned RegIdx = 3;
6620 if ((((Mnemonic == "vrintz" || Mnemonic == "vrintx") && !hasMVE()) ||
6621 Mnemonic == "vrintr") &&
6622 (static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32" ||
6623 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f16")) {
6624 if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
6625 (static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32" ||
6626 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f16"))
6627 RegIdx = 4;
6628
6629 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
6630 (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
6631 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
6632 ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
6633 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
6634 return true;
6635 }
6636 return false;
6637}
6638
6639bool ARMAsmParser::shouldOmitVectorPredicateOperand(StringRef Mnemonic,
6640 OperandVector &Operands) {
6641 if (!hasMVE() || Operands.size() < 3)
6642 return true;
6643
6644 if (Mnemonic.startswith("vld2") || Mnemonic.startswith("vld4") ||
6645 Mnemonic.startswith("vst2") || Mnemonic.startswith("vst4"))
6646 return true;
6647
6648 if (Mnemonic.startswith("vctp") || Mnemonic.startswith("vpnot"))
6649 return false;
6650
6651 if (Mnemonic.startswith("vmov") &&
6652 !(Mnemonic.startswith("vmovl") || Mnemonic.startswith("vmovn") ||
6653 Mnemonic.startswith("vmovx"))) {
6654 for (auto &Operand : Operands) {
6655 if (static_cast<ARMOperand &>(*Operand).isVectorIndex() ||
6656 ((*Operand).isReg() &&
6657 (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(
6658 (*Operand).getReg()) ||
6659 ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
6660 (*Operand).getReg())))) {
6661 return true;
6662 }
6663 }
6664 return false;
6665 } else {
6666 for (auto &Operand : Operands) {
6667 // We check the larger class QPR instead of just the legal class
6668 // MQPR, to more accurately report errors when using Q registers
6669 // outside of the allowed range.
6670 if (static_cast<ARMOperand &>(*Operand).isVectorIndex() ||
6671 (Operand->isReg() &&
6672 (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
6673 Operand->getReg()))))
6674 return false;
6675 }
6676 return true;
6677 }
6678}
6679
6680static bool isDataTypeToken(StringRef Tok) {
6681 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
6682 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
6683 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
6684 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
6685 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
6686 Tok == ".f" || Tok == ".d";
6687}
6688
6689// FIXME: This bit should probably be handled via an explicit match class
6690// in the .td files that matches the suffix instead of having it be
6691// a literal string token the way it is now.
6692static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
6693 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
6694}
6695
6696static void applyMnemonicAliases(StringRef &Mnemonic,
6697 const FeatureBitset &Features,
6698 unsigned VariantID);
6699
6700// The GNU assembler has aliases of ldrd and strd with the second register
6701// omitted. We don't have a way to do that in tablegen, so fix it up here.
6702//
6703// We have to be careful to not emit an invalid Rt2 here, because the rest of
6704// the assmebly parser could then generate confusing diagnostics refering to
6705// it. If we do find anything that prevents us from doing the transformation we
6706// bail out, and let the assembly parser report an error on the instruction as
6707// it is written.
6708void ARMAsmParser::fixupGNULDRDAlias(StringRef Mnemonic,
6709 OperandVector &Operands) {
6710 if (Mnemonic != "ldrd" && Mnemonic != "strd")
6711 return;
6712 if (Operands.size() < 4)
6713 return;
6714
6715 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
6716 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
6717
6718 if (!Op2.isReg())
6719 return;
6720 if (!Op3.isGPRMem())
6721 return;
6722
6723 const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID);
6724 if (!GPR.contains(Op2.getReg()))
6725 return;
6726
6727 unsigned RtEncoding = MRI->getEncodingValue(Op2.getReg());
6728 if (!isThumb() && (RtEncoding & 1)) {
6729 // In ARM mode, the registers must be from an aligned pair, this
6730 // restriction does not apply in Thumb mode.
6731 return;
6732 }
6733 if (Op2.getReg() == ARM::PC)
6734 return;
6735 unsigned PairedReg = GPR.getRegister(RtEncoding + 1);
6736 if (!PairedReg || PairedReg == ARM::PC ||
6737 (PairedReg == ARM::SP && !hasV8Ops()))
6738 return;
6739
6740 Operands.insert(
6741 Operands.begin() + 3,
6742 ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
6743}
6744
6745/// Parse an arm instruction mnemonic followed by its operands.
6746bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
6747 SMLoc NameLoc, OperandVector &Operands) {
6748 MCAsmParser &Parser = getParser();
6749
6750 // Apply mnemonic aliases before doing anything else, as the destination
6751 // mnemonic may include suffices and we want to handle them normally.
6752 // The generic tblgen'erated code does this later, at the start of
6753 // MatchInstructionImpl(), but that's too late for aliases that include
6754 // any sort of suffix.
6755 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
6756 unsigned AssemblerDialect = getParser().getAssemblerDialect();
6757 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
6758
6759 // First check for the ARM-specific .req directive.
6760 if (Parser.getTok().is(AsmToken::Identifier) &&
6761 Parser.getTok().getIdentifier() == ".req") {
6762 parseDirectiveReq(Name, NameLoc);
6763 // We always return 'error' for this, as we're done with this
6764 // statement and don't need to match the 'instruction."
6765 return true;
6766 }
6767
6768 // Create the leading tokens for the mnemonic, split by '.' characters.
6769 size_t Start = 0, Next = Name.find('.');
6770 StringRef Mnemonic = Name.slice(Start, Next);
6771 StringRef ExtraToken = Name.slice(Next, Name.find(' ', Next + 1));
6772
6773 // Split out the predication code and carry setting flag from the mnemonic.
6774 unsigned PredicationCode;
6775 unsigned VPTPredicationCode;
6776 unsigned ProcessorIMod;
6777 bool CarrySetting;
6778 StringRef ITMask;
6779 Mnemonic = splitMnemonic(Mnemonic, ExtraToken, PredicationCode, VPTPredicationCode,
6780 CarrySetting, ProcessorIMod, ITMask);
6781
6782 // In Thumb1, only the branch (B) instruction can be predicated.
6783 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
6784 return Error(NameLoc, "conditional execution not supported in Thumb1");
6785 }
6786
6787 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
6788
6789 // Handle the mask for IT and VPT instructions. In ARMOperand and
6790 // MCOperand, this is stored in a format independent of the
6791 // condition code: the lowest set bit indicates the end of the
6792 // encoding, and above that, a 1 bit indicates 'else', and an 0
6793 // indicates 'then'. E.g.
6794 // IT -> 1000
6795 // ITx -> x100 (ITT -> 0100, ITE -> 1100)
6796 // ITxy -> xy10 (e.g. ITET -> 1010)
6797 // ITxyz -> xyz1 (e.g. ITEET -> 1101)
6798 if (Mnemonic == "it" || Mnemonic.startswith("vpt") ||
6799 Mnemonic.startswith("vpst")) {
6800 SMLoc Loc = Mnemonic == "it" ? SMLoc::getFromPointer(NameLoc.getPointer() + 2) :
6801 Mnemonic == "vpt" ? SMLoc::getFromPointer(NameLoc.getPointer() + 3) :
6802 SMLoc::getFromPointer(NameLoc.getPointer() + 4);
6803 if (ITMask.size() > 3) {
6804 if (Mnemonic == "it")
6805 return Error(Loc, "too many conditions on IT instruction");
6806 return Error(Loc, "too many conditions on VPT instruction");
6807 }
6808 unsigned Mask = 8;
6809 for (unsigned i = ITMask.size(); i != 0; --i) {
6810 char pos = ITMask[i - 1];
6811 if (pos != 't' && pos != 'e') {
6812 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
6813 }
6814 Mask >>= 1;
6815 if (ITMask[i - 1] == 'e')
6816 Mask |= 8;
6817 }
6818 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
6819 }
6820
6821 // FIXME: This is all a pretty gross hack. We should automatically handle
6822 // optional operands like this via tblgen.
6823
6824 // Next, add the CCOut and ConditionCode operands, if needed.
6825 //
6826 // For mnemonics which can ever incorporate a carry setting bit or predication
6827 // code, our matching model involves us always generating CCOut and
6828 // ConditionCode operands to match the mnemonic "as written" and then we let
6829 // the matcher deal with finding the right instruction or generating an
6830 // appropriate error.
6831 bool CanAcceptCarrySet, CanAcceptPredicationCode, CanAcceptVPTPredicationCode;
6832 getMnemonicAcceptInfo(Mnemonic, ExtraToken, Name, CanAcceptCarrySet,
6833 CanAcceptPredicationCode, CanAcceptVPTPredicationCode);
6834
6835 // If we had a carry-set on an instruction that can't do that, issue an
6836 // error.
6837 if (!CanAcceptCarrySet && CarrySetting) {
6838 return Error(NameLoc, "instruction '" + Mnemonic +
6839 "' can not set flags, but 's' suffix specified");
6840 }
6841 // If we had a predication code on an instruction that can't do that, issue an
6842 // error.
6843 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
6844 return Error(NameLoc, "instruction '" + Mnemonic +
6845 "' is not predicable, but condition code specified");
6846 }
6847
6848 // If we had a VPT predication code on an instruction that can't do that, issue an
6849 // error.
6850 if (!CanAcceptVPTPredicationCode && VPTPredicationCode != ARMVCC::None) {
6851 return Error(NameLoc, "instruction '" + Mnemonic +
6852 "' is not VPT predicable, but VPT code T/E is specified");
6853 }
6854
6855 // Add the carry setting operand, if necessary.
6856 if (CanAcceptCarrySet) {
6857 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
6858 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
6859 Loc));
6860 }
6861
6862 // Add the predication code operand, if necessary.
6863 if (CanAcceptPredicationCode) {
6864 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
6865 CarrySetting);
6866 Operands.push_back(ARMOperand::CreateCondCode(
6867 ARMCC::CondCodes(PredicationCode), Loc));
6868 }
6869
6870 // Add the VPT predication code operand, if necessary.
6871 // FIXME: We don't add them for the instructions filtered below as these can
6872 // have custom operands which need special parsing. This parsing requires
6873 // the operand to be in the same place in the OperandVector as their
6874 // definition in tblgen. Since these instructions may also have the
6875 // scalar predication operand we do not add the vector one and leave until
6876 // now to fix it up.
6877 if (CanAcceptVPTPredicationCode && Mnemonic != "vmov" &&
6878 !Mnemonic.startswith("vcmp") &&
6879 !(Mnemonic.startswith("vcvt") && Mnemonic != "vcvta" &&
6880 Mnemonic != "vcvtn" && Mnemonic != "vcvtp" && Mnemonic != "vcvtm")) {
6881 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
6882 CarrySetting);
6883 Operands.push_back(ARMOperand::CreateVPTPred(
6884 ARMVCC::VPTCodes(VPTPredicationCode), Loc));
6885 }
6886
6887 // Add the processor imod operand, if necessary.
6888 if (ProcessorIMod) {
6889 Operands.push_back(ARMOperand::CreateImm(
6890 MCConstantExpr::create(ProcessorIMod, getContext()),
6891 NameLoc, NameLoc));
6892 } else if (Mnemonic == "cps" && isMClass()) {
6893 return Error(NameLoc, "instruction 'cps' requires effect for M-class");
6894 }
6895
6896 // Add the remaining tokens in the mnemonic.
6897 while (Next != StringRef::npos) {
6898 Start = Next;
6899 Next = Name.find('.', Start + 1);
6900 ExtraToken = Name.slice(Start, Next);
6901
6902 // Some NEON instructions have an optional datatype suffix that is
6903 // completely ignored. Check for that.
6904 if (isDataTypeToken(ExtraToken) &&
6905 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
6906 continue;
6907
6908 // For for ARM mode generate an error if the .n qualifier is used.
6909 if (ExtraToken == ".n" && !isThumb()) {
6910 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
6911 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
6912 "arm mode");
6913 }
6914
6915 // The .n qualifier is always discarded as that is what the tables
6916 // and matcher expect. In ARM mode the .w qualifier has no effect,
6917 // so discard it to avoid errors that can be caused by the matcher.
6918 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
6919 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
6920 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
6921 }
6922 }
6923
6924 // Read the remaining operands.
6925 if (getLexer().isNot(AsmToken::EndOfStatement)) {
6926 // Read the first operand.
6927 if (parseOperand(Operands, Mnemonic)) {
6928 return true;
6929 }
6930
6931 while (parseOptionalToken(AsmToken::Comma)) {
6932 // Parse and remember the operand.
6933 if (parseOperand(Operands, Mnemonic)) {
6934 return true;
6935 }
6936 }
6937 }
6938
6939 if (parseToken(AsmToken::EndOfStatement, "unexpected token in argument list"))
6940 return true;
6941
6942 tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands);
6943
6944 // Some instructions, mostly Thumb, have forms for the same mnemonic that
6945 // do and don't have a cc_out optional-def operand. With some spot-checks
6946 // of the operand list, we can figure out which variant we're trying to
6947 // parse and adjust accordingly before actually matching. We shouldn't ever
6948 // try to remove a cc_out operand that was explicitly set on the
6949 // mnemonic, of course (CarrySetting == true). Reason number #317 the
6950 // table driven matcher doesn't fit well with the ARM instruction set.
6951 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
6952 Operands.erase(Operands.begin() + 1);
6953
6954 // Some instructions have the same mnemonic, but don't always
6955 // have a predicate. Distinguish them here and delete the
6956 // appropriate predicate if needed. This could be either the scalar
6957 // predication code or the vector predication code.
6958 if (PredicationCode == ARMCC::AL &&
6959 shouldOmitPredicateOperand(Mnemonic, Operands))
6960 Operands.erase(Operands.begin() + 1);
6961
6962
6963 if (hasMVE()) {
6964 if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands) &&
6965 Mnemonic == "vmov" && PredicationCode == ARMCC::LT) {
6966 // Very nasty hack to deal with the vector predicated variant of vmovlt
6967 // the scalar predicated vmov with condition 'lt'. We can not tell them
6968 // apart until we have parsed their operands.
6969 Operands.erase(Operands.begin() + 1);
6970 Operands.erase(Operands.begin());
6971 SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
6972 SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
6973 Mnemonic.size() - 1 + CarrySetting);
6974 Operands.insert(Operands.begin(),
6975 ARMOperand::CreateVPTPred(ARMVCC::None, PLoc));
6976 Operands.insert(Operands.begin(),
6977 ARMOperand::CreateToken(StringRef("vmovlt"), MLoc));
6978 } else if (Mnemonic == "vcvt" && PredicationCode == ARMCC::NE &&
6979 !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
6980 // Another nasty hack to deal with the ambiguity between vcvt with scalar
6981 // predication 'ne' and vcvtn with vector predication 'e'. As above we
6982 // can only distinguish between the two after we have parsed their
6983 // operands.
6984 Operands.erase(Operands.begin() + 1);
6985 Operands.erase(Operands.begin());
6986 SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
6987 SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
6988 Mnemonic.size() - 1 + CarrySetting);
6989 Operands.insert(Operands.begin(),
6990 ARMOperand::CreateVPTPred(ARMVCC::Else, PLoc));
6991 Operands.insert(Operands.begin(),
6992 ARMOperand::CreateToken(StringRef("vcvtn"), MLoc));
6993 } else if (Mnemonic == "vmul" && PredicationCode == ARMCC::LT &&
6994 !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
6995 // Another hack, this time to distinguish between scalar predicated vmul
6996 // with 'lt' predication code and the vector instruction vmullt with
6997 // vector predication code "none"
6998 Operands.erase(Operands.begin() + 1);
6999 Operands.erase(Operands.begin());
7000 SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
7001 Operands.insert(Operands.begin(),
7002 ARMOperand::CreateToken(StringRef("vmullt"), MLoc));
7003 }
7004 // For vmov and vcmp, as mentioned earlier, we did not add the vector
7005 // predication code, since these may contain operands that require
7006 // special parsing. So now we have to see if they require vector
7007 // predication and replace the scalar one with the vector predication
7008 // operand if that is the case.
7009 else if (Mnemonic == "vmov" || Mnemonic.startswith("vcmp") ||
7010 (Mnemonic.startswith("vcvt") && !Mnemonic.startswith("vcvta") &&
7011 !Mnemonic.startswith("vcvtn") && !Mnemonic.startswith("vcvtp") &&
7012 !Mnemonic.startswith("vcvtm"))) {
7013 if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
7014 // We could not split the vector predicate off vcvt because it might
7015 // have been the scalar vcvtt instruction. Now we know its a vector
7016 // instruction, we still need to check whether its the vector
7017 // predicated vcvt with 'Then' predication or the vector vcvtt. We can
7018 // distinguish the two based on the suffixes, if it is any of
7019 // ".f16.f32", ".f32.f16", ".f16.f64" or ".f64.f16" then it is the vcvtt.
7020 if (Mnemonic.startswith("vcvtt") && Operands.size() >= 4) {
7021 auto Sz1 = static_cast<ARMOperand &>(*Operands[2]);
7022 auto Sz2 = static_cast<ARMOperand &>(*Operands[3]);
7023 if (!(Sz1.isToken() && Sz1.getToken().startswith(".f") &&
7024 Sz2.isToken() && Sz2.getToken().startswith(".f"))) {
7025 Operands.erase(Operands.begin());
7026 SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
7027 VPTPredicationCode = ARMVCC::Then;
7028
7029 Mnemonic = Mnemonic.substr(0, 4);
7030 Operands.insert(Operands.begin(),
7031 ARMOperand::CreateToken(Mnemonic, MLoc));
7032 }
7033 }
7034 Operands.erase(Operands.begin() + 1);
7035 SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
7036 Mnemonic.size() + CarrySetting);
7037 Operands.insert(Operands.begin() + 1,
7038 ARMOperand::CreateVPTPred(
7039 ARMVCC::VPTCodes(VPTPredicationCode), PLoc));
7040 }
7041 } else if (CanAcceptVPTPredicationCode) {
7042 // For all other instructions, make sure only one of the two
7043 // predication operands is left behind, depending on whether we should
7044 // use the vector predication.
7045 if (shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
7046 if (CanAcceptPredicationCode)
7047 Operands.erase(Operands.begin() + 2);
7048 else
7049 Operands.erase(Operands.begin() + 1);
7050 } else if (CanAcceptPredicationCode && PredicationCode == ARMCC::AL) {
7051 Operands.erase(Operands.begin() + 1);
7052 }
7053 }
7054 }
7055
7056 if (VPTPredicationCode != ARMVCC::None) {
7057 bool usedVPTPredicationCode = false;
7058 for (unsigned I = 1; I < Operands.size(); ++I)
7059 if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred())
7060 usedVPTPredicationCode = true;
7061 if (!usedVPTPredicationCode) {
7062 // If we have a VPT predication code and we haven't just turned it
7063 // into an operand, then it was a mistake for splitMnemonic to
7064 // separate it from the rest of the mnemonic in the first place,
7065 // and this may lead to wrong disassembly (e.g. scalar floating
7066 // point VCMPE is actually a different instruction from VCMP, so
7067 // we mustn't treat them the same). In that situation, glue it
7068 // back on.
7069 Mnemonic = Name.slice(0, Mnemonic.size() + 1);
7070 Operands.erase(Operands.begin());
7071 Operands.insert(Operands.begin(),
7072 ARMOperand::CreateToken(Mnemonic, NameLoc));
7073 }
7074 }
7075
7076 // ARM mode 'blx' need special handling, as the register operand version
7077 // is predicable, but the label operand version is not. So, we can't rely
7078 // on the Mnemonic based checking to correctly figure out when to put
7079 // a k_CondCode operand in the list. If we're trying to match the label
7080 // version, remove the k_CondCode operand here.
7081 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
7082 static_cast<ARMOperand &>(*Operands[2]).isImm())
7083 Operands.erase(Operands.begin() + 1);
7084
7085 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
7086 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
7087 // a single GPRPair reg operand is used in the .td file to replace the two
7088 // GPRs. However, when parsing from asm, the two GRPs cannot be
7089 // automatically
7090 // expressed as a GPRPair, so we have to manually merge them.
7091 // FIXME: We would really like to be able to tablegen'erate this.
7092 if (!isThumb() && Operands.size() > 4 &&
7093 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
7094 Mnemonic == "stlexd")) {
7095 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
7096 unsigned Idx = isLoad ? 2 : 3;
7097 ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
7098 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
7099
7100 const MCRegisterClass &MRC = MRI->getRegClass(ARM::GPRRegClassID);
7101 // Adjust only if Op1 and Op2 are GPRs.
7102 if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
7103 MRC.contains(Op2.getReg())) {
7104 unsigned Reg1 = Op1.getReg();
7105 unsigned Reg2 = Op2.getReg();
7106 unsigned Rt = MRI->getEncodingValue(Reg1);
7107 unsigned Rt2 = MRI->getEncodingValue(Reg2);
7108
7109 // Rt2 must be Rt + 1 and Rt must be even.
7110 if (Rt + 1 != Rt2 || (Rt & 1)) {
7111 return Error(Op2.getStartLoc(),
7112 isLoad ? "destination operands must be sequential"
7113 : "source operands must be sequential");
7114 }
7115 unsigned NewReg = MRI->getMatchingSuperReg(
7116 Reg1, ARM::gsub_0, &(MRI->getRegClass(ARM::GPRPairRegClassID)));
7117 Operands[Idx] =
7118 ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
7119 Operands.erase(Operands.begin() + Idx + 1);
7120 }
7121 }
7122
7123 // GNU Assembler extension (compatibility).
7124 fixupGNULDRDAlias(Mnemonic, Operands);
7125
7126 // FIXME: As said above, this is all a pretty gross hack. This instruction
7127 // does not fit with other "subs" and tblgen.
7128 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
7129 // so the Mnemonic is the original name "subs" and delete the predicate
7130 // operand so it will match the table entry.
7131 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
7132 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
7133 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
7134 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
7135 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
7136 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
7137 Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
7138 Operands.erase(Operands.begin() + 1);
7139 }
7140 return false;
7141}
7142
7143// Validate context-sensitive operand constraints.
7144
7145// return 'true' if register list contains non-low GPR registers,
7146// 'false' otherwise. If Reg is in the register list or is HiReg, set
7147// 'containsReg' to true.
7148static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo,
7149 unsigned Reg, unsigned HiReg,
7150 bool &containsReg) {
7151 containsReg = false;
7152 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
7153 unsigned OpReg = Inst.getOperand(i).getReg();
7154 if (OpReg == Reg)
7155 containsReg = true;
7156 // Anything other than a low register isn't legal here.
7157 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
7158 return true;
7159 }
7160 return false;
7161}
7162
7163// Check if the specified regisgter is in the register list of the inst,
7164// starting at the indicated operand number.
7165static bool listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) {
7166 for (unsigned i = OpNo, e = Inst.getNumOperands(); i < e; ++i) {
7167 unsigned OpReg = Inst.getOperand(i).getReg();
7168 if (OpReg == Reg)
7169 return true;
7170 }
7171 return false;
7172}
7173
7174// Return true if instruction has the interesting property of being
7175// allowed in IT blocks, but not being predicable.
7176static bool instIsBreakpoint(const MCInst &Inst) {
7177 return Inst.getOpcode() == ARM::tBKPT ||
7178 Inst.getOpcode() == ARM::BKPT ||
7179 Inst.getOpcode() == ARM::tHLT ||
7180 Inst.getOpcode() == ARM::HLT;
7181}
7182
7183bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst,
7184 const OperandVector &Operands,
7185 unsigned ListNo, bool IsARPop) {
7186 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
7187 bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
7188
7189 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
7190 bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR);
7191 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
7192
7193 if (!IsARPop && ListContainsSP)
7194 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7195 "SP may not be in the register list");
7196 else if (ListContainsPC && ListContainsLR)
7197 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7198 "PC and LR may not be in the register list simultaneously");
7199 return false;
7200}
7201
7202bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst,
7203 const OperandVector &Operands,
7204 unsigned ListNo) {
7205 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
7206 bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
7207
7208 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
7209 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
7210
7211 if (ListContainsSP && ListContainsPC)
7212 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7213 "SP and PC may not be in the register list");
7214 else if (ListContainsSP)
7215 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7216 "SP may not be in the register list");
7217 else if (ListContainsPC)
7218 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7219 "PC may not be in the register list");
7220 return false;
7221}
7222
7223bool ARMAsmParser::validateLDRDSTRD(MCInst &Inst,
7224 const OperandVector &Operands,
7225 bool Load, bool ARMMode, bool Writeback) {
7226 unsigned RtIndex = Load || !Writeback ? 0 : 1;
7227 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(RtIndex).getReg());
7228 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(RtIndex + 1).getReg());
7229
7230 if (ARMMode) {
7231 // Rt can't be R14.
7232 if (Rt == 14)
7233 return Error(Operands[3]->getStartLoc(),
7234 "Rt can't be R14");
7235
7236 // Rt must be even-numbered.
7237 if ((Rt & 1) == 1)
7238 return Error(Operands[3]->getStartLoc(),
7239 "Rt must be even-numbered");
7240
7241 // Rt2 must be Rt + 1.
7242 if (Rt2 != Rt + 1) {
7243 if (Load)
7244 return Error(Operands[3]->getStartLoc(),
7245 "destination operands must be sequential");
7246 else
7247 return Error(Operands[3]->getStartLoc(),
7248 "source operands must be sequential");
7249 }
7250
7251 // FIXME: Diagnose m == 15
7252 // FIXME: Diagnose ldrd with m == t || m == t2.
7253 }
7254
7255 if (!ARMMode && Load) {
7256 if (Rt2 == Rt)
7257 return Error(Operands[3]->getStartLoc(),
7258 "destination operands can't be identical");
7259 }
7260
7261 if (Writeback) {
7262 unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
7263
7264 if (Rn == Rt || Rn == Rt2) {
7265 if (Load)
7266 return Error(Operands[3]->getStartLoc(),
7267 "base register needs to be different from destination "
7268 "registers");
7269 else
7270 return Error(Operands[3]->getStartLoc(),
7271 "source register and base register can't be identical");
7272 }
7273
7274 // FIXME: Diagnose ldrd/strd with writeback and n == 15.
7275 // (Except the immediate form of ldrd?)
7276 }
7277
7278 return false;
7279}
7280
7281static int findFirstVectorPredOperandIdx(const MCInstrDesc &MCID) {
7282 for (unsigned i = 0; i < MCID.NumOperands; ++i) {
7283 if (ARM::isVpred(MCID.OpInfo[i].OperandType))
7284 return i;
7285 }
7286 return -1;
7287}
7288
7289static bool isVectorPredicable(const MCInstrDesc &MCID) {
7290 return findFirstVectorPredOperandIdx(MCID) != -1;
7291}
7292
7293// FIXME: We would really like to be able to tablegen'erate this.
7294bool ARMAsmParser::validateInstruction(MCInst &Inst,
7295 const OperandVector &Operands) {
7296 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
7297 SMLoc Loc = Operands[0]->getStartLoc();
7298
7299 // Check the IT block state first.
7300 // NOTE: BKPT and HLT instructions have the interesting property of being
7301 // allowed in IT blocks, but not being predicable. They just always execute.
7302 if (inITBlock() && !instIsBreakpoint(Inst)) {
7303 // The instruction must be predicable.
7304 if (!MCID.isPredicable())
7305 return Error(Loc, "instructions in IT block must be predicable");
7306 ARMCC::CondCodes Cond = ARMCC::CondCodes(
7307 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm());
7308 if (Cond != currentITCond()) {
7309 // Find the condition code Operand to get its SMLoc information.
7310 SMLoc CondLoc;
7311 for (unsigned I = 1; I < Operands.size(); ++I)
7312 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
7313 CondLoc = Operands[I]->getStartLoc();
7314 return Error(CondLoc, "incorrect condition in IT block; got '" +
7315 StringRef(ARMCondCodeToString(Cond)) +
7316 "', but expected '" +
7317 ARMCondCodeToString(currentITCond()) + "'");
7318 }
7319 // Check for non-'al' condition codes outside of the IT block.
7320 } else if (isThumbTwo() && MCID.isPredicable() &&
7321 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
7322 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
7323 Inst.getOpcode() != ARM::t2Bcc &&
7324 Inst.getOpcode() != ARM::t2BFic) {
7325 return Error(Loc, "predicated instructions must be in IT block");
7326 } else if (!isThumb() && !useImplicitITARM() && MCID.isPredicable() &&
7327 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
7328 ARMCC::AL) {
7329 return Warning(Loc, "predicated instructions should be in IT block");
7330 } else if (!MCID.isPredicable()) {
7331 // Check the instruction doesn't have a predicate operand anyway
7332 // that it's not allowed to use. Sometimes this happens in order
7333 // to keep instructions the same shape even though one cannot
7334 // legally be predicated, e.g. vmul.f16 vs vmul.f32.
7335 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
7336 if (MCID.OpInfo[i].isPredicate()) {
7337 if (Inst.getOperand(i).getImm() != ARMCC::AL)
7338 return Error(Loc, "instruction is not predicable");
7339 break;
7340 }
7341 }
7342 }
7343
7344 // PC-setting instructions in an IT block, but not the last instruction of
7345 // the block, are UNPREDICTABLE.
7346 if (inExplicitITBlock() && !lastInITBlock() && isITBlockTerminator(Inst)) {
7347 return Error(Loc, "instruction must be outside of IT block or the last instruction in an IT block");
7348 }
7349
7350 if (inVPTBlock() && !instIsBreakpoint(Inst)) {
7351 unsigned Bit = extractITMaskBit(VPTState.Mask, VPTState.CurPosition);
7352 if (!isVectorPredicable(MCID))
7353 return Error(Loc, "instruction in VPT block must be predicable");
7354 unsigned Pred = Inst.getOperand(findFirstVectorPredOperandIdx(MCID)).getImm();
7355 unsigned VPTPred = Bit ? ARMVCC::Else : ARMVCC::Then;
7356 if (Pred != VPTPred) {
7357 SMLoc PredLoc;
7358 for (unsigned I = 1; I < Operands.size(); ++I)
7359 if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred())
7360 PredLoc = Operands[I]->getStartLoc();
7361 return Error(PredLoc, "incorrect predication in VPT block; got '" +
7362 StringRef(ARMVPTPredToString(ARMVCC::VPTCodes(Pred))) +
7363 "', but expected '" +
7364 ARMVPTPredToString(ARMVCC::VPTCodes(VPTPred)) + "'");
7365 }
7366 }
7367 else if (isVectorPredicable(MCID) &&
7368 Inst.getOperand(findFirstVectorPredOperandIdx(MCID)).getImm() !=
7369 ARMVCC::None)
7370 return Error(Loc, "VPT predicated instructions must be in VPT block");
7371
7372 const unsigned Opcode = Inst.getOpcode();
7373 switch (Opcode) {
7374 case ARM::t2IT: {
7375 // Encoding is unpredictable if it ever results in a notional 'NV'
7376 // predicate. Since we don't parse 'NV' directly this means an 'AL'
7377 // predicate with an "else" mask bit.
7378 unsigned Cond = Inst.getOperand(0).getImm();
7379 unsigned Mask = Inst.getOperand(1).getImm();
7380
7381 // Conditions only allowing a 't' are those with no set bit except
7382 // the lowest-order one that indicates the end of the sequence. In
7383 // other words, powers of 2.
7384 if (Cond == ARMCC::AL && countPopulation(Mask) != 1)
7385 return Error(Loc, "unpredictable IT predicate sequence");
7386 break;
7387 }
7388 case ARM::LDRD:
7389 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true,
7390 /*Writeback*/false))
7391 return true;
7392 break;
7393 case ARM::LDRD_PRE:
7394 case ARM::LDRD_POST:
7395 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true,
7396 /*Writeback*/true))
7397 return true;
7398 break;
7399 case ARM::t2LDRDi8:
7400 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false,
7401 /*Writeback*/false))
7402 return true;
7403 break;
7404 case ARM::t2LDRD_PRE:
7405 case ARM::t2LDRD_POST:
7406 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false,
7407 /*Writeback*/true))
7408 return true;
7409 break;
7410 case ARM::t2BXJ: {
7411 const unsigned RmReg = Inst.getOperand(0).getReg();
7412 // Rm = SP is no longer unpredictable in v8-A
7413 if (RmReg == ARM::SP && !hasV8Ops())
7414 return Error(Operands[2]->getStartLoc(),
7415 "r13 (SP) is an unpredictable operand to BXJ");
7416 return false;
7417 }
7418 case ARM::STRD:
7419 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true,
7420 /*Writeback*/false))
7421 return true;
7422 break;
7423 case ARM::STRD_PRE:
7424 case ARM::STRD_POST:
7425 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true,
7426 /*Writeback*/true))
7427 return true;
7428 break;
7429 case ARM::t2STRD_PRE:
7430 case ARM::t2STRD_POST:
7431 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/false,
7432 /*Writeback*/true))
7433 return true;
7434 break;
7435 case ARM::STR_PRE_IMM:
7436 case ARM::STR_PRE_REG:
7437 case ARM::t2STR_PRE:
7438 case ARM::STR_POST_IMM:
7439 case ARM::STR_POST_REG:
7440 case ARM::t2STR_POST:
7441 case ARM::STRH_PRE:
7442 case ARM::t2STRH_PRE:
7443 case ARM::STRH_POST:
7444 case ARM::t2STRH_POST:
7445 case ARM::STRB_PRE_IMM:
7446 case ARM::STRB_PRE_REG:
7447 case ARM::t2STRB_PRE:
7448 case ARM::STRB_POST_IMM:
7449 case ARM::STRB_POST_REG:
7450 case ARM::t2STRB_POST: {
7451 // Rt must be different from Rn.
7452 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
7453 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
7454
7455 if (Rt == Rn)
7456 return Error(Operands[3]->getStartLoc(),
7457 "source register and base register can't be identical");
7458 return false;
7459 }
7460 case ARM::LDR_PRE_IMM:
7461 case ARM::LDR_PRE_REG:
7462 case ARM::t2LDR_PRE:
7463 case ARM::LDR_POST_IMM:
7464 case ARM::LDR_POST_REG:
7465 case ARM::t2LDR_POST:
7466 case ARM::LDRH_PRE:
7467 case ARM::t2LDRH_PRE:
7468 case ARM::LDRH_POST:
7469 case ARM::t2LDRH_POST:
7470 case ARM::LDRSH_PRE:
7471 case ARM::t2LDRSH_PRE:
7472 case ARM::LDRSH_POST:
7473 case ARM::t2LDRSH_POST:
7474 case ARM::LDRB_PRE_IMM:
7475 case ARM::LDRB_PRE_REG:
7476 case ARM::t2LDRB_PRE:
7477 case ARM::LDRB_POST_IMM:
7478 case ARM::LDRB_POST_REG:
7479 case ARM::t2LDRB_POST:
7480 case ARM::LDRSB_PRE:
7481 case ARM::t2LDRSB_PRE:
7482 case ARM::LDRSB_POST:
7483 case ARM::t2LDRSB_POST: {
7484 // Rt must be different from Rn.
7485 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
7486 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
7487
7488 if (Rt == Rn)
7489 return Error(Operands[3]->getStartLoc(),
7490 "destination register and base register can't be identical");
7491 return false;
7492 }
7493
7494 case ARM::MVE_VLDRBU8_rq:
7495 case ARM::MVE_VLDRBU16_rq:
7496 case ARM::MVE_VLDRBS16_rq:
7497 case ARM::MVE_VLDRBU32_rq:
7498 case ARM::MVE_VLDRBS32_rq:
7499 case ARM::MVE_VLDRHU16_rq:
7500 case ARM::MVE_VLDRHU16_rq_u:
7501 case ARM::MVE_VLDRHU32_rq:
7502 case ARM::MVE_VLDRHU32_rq_u:
7503 case ARM::MVE_VLDRHS32_rq:
7504 case ARM::MVE_VLDRHS32_rq_u:
7505 case ARM::MVE_VLDRWU32_rq:
7506 case ARM::MVE_VLDRWU32_rq_u:
7507 case ARM::MVE_VLDRDU64_rq:
7508 case ARM::MVE_VLDRDU64_rq_u:
7509 case ARM::MVE_VLDRWU32_qi:
7510 case ARM::MVE_VLDRWU32_qi_pre:
7511 case ARM::MVE_VLDRDU64_qi:
7512 case ARM::MVE_VLDRDU64_qi_pre: {
7513 // Qd must be different from Qm.
7514 unsigned QdIdx = 0, QmIdx = 2;
7515 bool QmIsPointer = false;
7516 switch (Opcode) {
7517 case ARM::MVE_VLDRWU32_qi:
7518 case ARM::MVE_VLDRDU64_qi:
7519 QmIdx = 1;
7520 QmIsPointer = true;
7521 break;
7522 case ARM::MVE_VLDRWU32_qi_pre:
7523 case ARM::MVE_VLDRDU64_qi_pre:
7524 QdIdx = 1;
7525 QmIsPointer = true;
7526 break;
7527 }
7528
7529 const unsigned Qd = MRI->getEncodingValue(Inst.getOperand(QdIdx).getReg());
7530 const unsigned Qm = MRI->getEncodingValue(Inst.getOperand(QmIdx).getReg());
7531
7532 if (Qd == Qm) {
7533 return Error(Operands[3]->getStartLoc(),
7534 Twine("destination vector register and vector ") +
7535 (QmIsPointer ? "pointer" : "offset") +
7536 " register can't be identical");
7537 }
7538 return false;
7539 }
7540
7541 case ARM::SBFX:
7542 case ARM::t2SBFX:
7543 case ARM::UBFX:
7544 case ARM::t2UBFX: {
7545 // Width must be in range [1, 32-lsb].
7546 unsigned LSB = Inst.getOperand(2).getImm();
7547 unsigned Widthm1 = Inst.getOperand(3).getImm();
7548 if (Widthm1 >= 32 - LSB)
7549 return Error(Operands[5]->getStartLoc(),
7550 "bitfield width must be in range [1,32-lsb]");
7551 return false;
7552 }
7553 // Notionally handles ARM::tLDMIA_UPD too.
7554 case ARM::tLDMIA: {
7555 // If we're parsing Thumb2, the .w variant is available and handles
7556 // most cases that are normally illegal for a Thumb1 LDM instruction.
7557 // We'll make the transformation in processInstruction() if necessary.
7558 //
7559 // Thumb LDM instructions are writeback iff the base register is not
7560 // in the register list.
7561 unsigned Rn = Inst.getOperand(0).getReg();
7562 bool HasWritebackToken =
7563 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7564 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
7565 bool ListContainsBase;
7566 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
7567 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
7568 "registers must be in range r0-r7");
7569 // If we should have writeback, then there should be a '!' token.
7570 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
7571 return Error(Operands[2]->getStartLoc(),
7572 "writeback operator '!' expected");
7573 // If we should not have writeback, there must not be a '!'. This is
7574 // true even for the 32-bit wide encodings.
7575 if (ListContainsBase && HasWritebackToken)
7576 return Error(Operands[3]->getStartLoc(),
7577 "writeback operator '!' not allowed when base register "
7578 "in register list");
7579
7580 if (validatetLDMRegList(Inst, Operands, 3))
7581 return true;
7582 break;
7583 }
7584 case ARM::LDMIA_UPD:
7585 case ARM::LDMDB_UPD:
7586 case ARM::LDMIB_UPD:
7587 case ARM::LDMDA_UPD:
7588 // ARM variants loading and updating the same register are only officially
7589 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
7590 if (!hasV7Ops())
7591 break;
7592 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
7593 return Error(Operands.back()->getStartLoc(),
7594 "writeback register not allowed in register list");
7595 break;
7596 case ARM::t2LDMIA:
7597 case ARM::t2LDMDB:
7598 if (validatetLDMRegList(Inst, Operands, 3))
7599 return true;
7600 break;
7601 case ARM::t2STMIA:
7602 case ARM::t2STMDB:
7603 if (validatetSTMRegList(Inst, Operands, 3))
7604 return true;
7605 break;
7606 case ARM::t2LDMIA_UPD:
7607 case ARM::t2LDMDB_UPD:
7608 case ARM::t2STMIA_UPD:
7609 case ARM::t2STMDB_UPD:
7610 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
7611 return Error(Operands.back()->getStartLoc(),
7612 "writeback register not allowed in register list");
7613
7614 if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
7615 if (validatetLDMRegList(Inst, Operands, 3))
7616 return true;
7617 } else {
7618 if (validatetSTMRegList(Inst, Operands, 3))
7619 return true;
7620 }
7621 break;
7622
7623 case ARM::sysLDMIA_UPD:
7624 case ARM::sysLDMDA_UPD:
7625 case ARM::sysLDMDB_UPD:
7626 case ARM::sysLDMIB_UPD:
7627 if (!listContainsReg(Inst, 3, ARM::PC))
7628 return Error(Operands[4]->getStartLoc(),
7629 "writeback register only allowed on system LDM "
7630 "if PC in register-list");
7631 break;
7632 case ARM::sysSTMIA_UPD:
7633 case ARM::sysSTMDA_UPD:
7634 case ARM::sysSTMDB_UPD:
7635 case ARM::sysSTMIB_UPD:
7636 return Error(Operands[2]->getStartLoc(),
7637 "system STM cannot have writeback register");
7638 case ARM::tMUL:
7639 // The second source operand must be the same register as the destination
7640 // operand.
7641 //
7642 // In this case, we must directly check the parsed operands because the
7643 // cvtThumbMultiply() function is written in such a way that it guarantees
7644 // this first statement is always true for the new Inst. Essentially, the
7645 // destination is unconditionally copied into the second source operand
7646 // without checking to see if it matches what we actually parsed.
7647 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
7648 ((ARMOperand &)*Operands[5]).getReg()) &&
7649 (((ARMOperand &)*Operands[3]).getReg() !=
7650 ((ARMOperand &)*Operands[4]).getReg())) {
7651 return Error(Operands[3]->getStartLoc(),
7652 "destination register must match source register");
7653 }
7654 break;
7655
7656 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
7657 // so only issue a diagnostic for thumb1. The instructions will be
7658 // switched to the t2 encodings in processInstruction() if necessary.
7659 case ARM::tPOP: {
7660 bool ListContainsBase;
7661 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
7662 !isThumbTwo())
7663 return Error(Operands[2]->getStartLoc(),
7664 "registers must be in range r0-r7 or pc");
7665 if (validatetLDMRegList(Inst, Operands, 2, !isMClass()))
7666 return true;
7667 break;
7668 }
7669 case ARM::tPUSH: {
7670 bool ListContainsBase;
7671 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
7672 !isThumbTwo())
7673 return Error(Operands[2]->getStartLoc(),
7674 "registers must be in range r0-r7 or lr");
7675 if (validatetSTMRegList(Inst, Operands, 2))
7676 return true;
7677 break;
7678 }
7679 case ARM::tSTMIA_UPD: {
7680 bool ListContainsBase, InvalidLowList;
7681 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
7682 0, ListContainsBase);
7683 if (InvalidLowList && !isThumbTwo())
7684 return Error(Operands[4]->getStartLoc(),
7685 "registers must be in range r0-r7");
7686
7687 // This would be converted to a 32-bit stm, but that's not valid if the
7688 // writeback register is in the list.
7689 if (InvalidLowList && ListContainsBase)
7690 return Error(Operands[4]->getStartLoc(),
7691 "writeback operator '!' not allowed when base register "
7692 "in register list");
7693
7694 if (validatetSTMRegList(Inst, Operands, 4))
7695 return true;
7696 break;
7697 }
7698 case ARM::tADDrSP:
7699 // If the non-SP source operand and the destination operand are not the
7700 // same, we need thumb2 (for the wide encoding), or we have an error.
7701 if (!isThumbTwo() &&
7702 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7703 return Error(Operands[4]->getStartLoc(),
7704 "source register must be the same as destination");
7705 }
7706 break;
7707
7708 case ARM::t2ADDri:
7709 case ARM::t2ADDri12:
7710 case ARM::t2ADDrr:
7711 case ARM::t2ADDrs:
7712 case ARM::t2SUBri:
7713 case ARM::t2SUBri12:
7714 case ARM::t2SUBrr:
7715 case ARM::t2SUBrs:
7716 if (Inst.getOperand(0).getReg() == ARM::SP &&
7717 Inst.getOperand(1).getReg() != ARM::SP)
7718 return Error(Operands[4]->getStartLoc(),
7719 "source register must be sp if destination is sp");
7720 break;
7721
7722 // Final range checking for Thumb unconditional branch instructions.
7723 case ARM::tB:
7724 if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
7725 return Error(Operands[2]->getStartLoc(), "branch target out of range");
7726 break;
7727 case ARM::t2B: {
7728 int op = (Operands[2]->isImm()) ? 2 : 3;
7729 if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
7730 return Error(Operands[op]->getStartLoc(), "branch target out of range");
7731 break;
7732 }
7733 // Final range checking for Thumb conditional branch instructions.
7734 case ARM::tBcc:
7735 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
7736 return Error(Operands[2]->getStartLoc(), "branch target out of range");
7737 break;
7738 case ARM::t2Bcc: {
7739 int Op = (Operands[2]->isImm()) ? 2 : 3;
7740 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
7741 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
7742 break;
7743 }
7744 case ARM::tCBZ:
7745 case ARM::tCBNZ: {
7746 if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<6, 1>())
7747 return Error(Operands[2]->getStartLoc(), "branch target out of range");
7748 break;
7749 }
7750 case ARM::MOVi16:
7751 case ARM::MOVTi16:
7752 case ARM::t2MOVi16:
7753 case ARM::t2MOVTi16:
7754 {
7755 // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
7756 // especially when we turn it into a movw and the expression <symbol> does
7757 // not have a :lower16: or :upper16 as part of the expression. We don't
7758 // want the behavior of silently truncating, which can be unexpected and
7759 // lead to bugs that are difficult to find since this is an easy mistake
7760 // to make.
7761 int i = (Operands[3]->isImm()) ? 3 : 4;
7762 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
7763 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
7764 if (CE) break;
7765 const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
7766 if (!E) break;
7767 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
7768 if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
7769 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
7770 return Error(
7771 Op.getStartLoc(),
7772 "immediate expression for mov requires :lower16: or :upper16");
7773 break;
7774 }
7775 case ARM::HINT:
7776 case ARM::t2HINT: {
7777 unsigned Imm8 = Inst.getOperand(0).getImm();
7778 unsigned Pred = Inst.getOperand(1).getImm();
7779 // ESB is not predicable (pred must be AL). Without the RAS extension, this
7780 // behaves as any other unallocated hint.
7781 if (Imm8 == 0x10 && Pred != ARMCC::AL && hasRAS())
7782 return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not "
7783 "predicable, but condition "
7784 "code specified");
7785 if (Imm8 == 0x14 && Pred != ARMCC::AL)
7786 return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not "
7787 "predicable, but condition "
7788 "code specified");
7789 break;
7790 }
7791 case ARM::t2BFi:
7792 case ARM::t2BFr:
7793 case ARM::t2BFLi:
7794 case ARM::t2BFLr: {
7795 if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<4, 1>() ||
7796 (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0))
7797 return Error(Operands[2]->getStartLoc(),
7798 "branch location out of range or not a multiple of 2");
7799
7800 if (Opcode == ARM::t2BFi) {
7801 if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<16, 1>())
7802 return Error(Operands[3]->getStartLoc(),
7803 "branch target out of range or not a multiple of 2");
7804 } else if (Opcode == ARM::t2BFLi) {
7805 if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<18, 1>())
7806 return Error(Operands[3]->getStartLoc(),
7807 "branch target out of range or not a multiple of 2");
7808 }
7809 break;
7810 }
7811 case ARM::t2BFic: {
7812 if (!static_cast<ARMOperand &>(*Operands[1]).isUnsignedOffset<4, 1>() ||
7813 (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0))
7814 return Error(Operands[1]->getStartLoc(),
7815 "branch location out of range or not a multiple of 2");
7816
7817 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<16, 1>())
7818 return Error(Operands[2]->getStartLoc(),
7819 "branch target out of range or not a multiple of 2");
7820
7821 assert(Inst.getOperand(0).isImm() == Inst.getOperand(2).isImm() &&((Inst.getOperand(0).isImm() == Inst.getOperand(2).isImm() &&
"branch location and else branch target should either both be "
"immediates or both labels") ? static_cast<void> (0) :
__assert_fail ("Inst.getOperand(0).isImm() == Inst.getOperand(2).isImm() && \"branch location and else branch target should either both be \" \"immediates or both labels\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 7823, __PRETTY_FUNCTION__))
7822 "branch location and else branch target should either both be "((Inst.getOperand(0).isImm() == Inst.getOperand(2).isImm() &&
"branch location and else branch target should either both be "
"immediates or both labels") ? static_cast<void> (0) :
__assert_fail ("Inst.getOperand(0).isImm() == Inst.getOperand(2).isImm() && \"branch location and else branch target should either both be \" \"immediates or both labels\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 7823, __PRETTY_FUNCTION__))
7823 "immediates or both labels")((Inst.getOperand(0).isImm() == Inst.getOperand(2).isImm() &&
"branch location and else branch target should either both be "
"immediates or both labels") ? static_cast<void> (0) :
__assert_fail ("Inst.getOperand(0).isImm() == Inst.getOperand(2).isImm() && \"branch location and else branch target should either both be \" \"immediates or both labels\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 7823, __PRETTY_FUNCTION__))
;
7824
7825 if (Inst.getOperand(0).isImm() && Inst.getOperand(2).isImm()) {
7826 int Diff = Inst.getOperand(2).getImm() - Inst.getOperand(0).getImm();
7827 if (Diff != 4 && Diff != 2)
7828 return Error(
7829 Operands[3]->getStartLoc(),
7830 "else branch target must be 2 or 4 greater than the branch location");
7831 }
7832 break;
7833 }
7834 case ARM::t2CLRM: {
7835 for (unsigned i = 2; i < Inst.getNumOperands(); i++) {
7836 if (Inst.getOperand(i).isReg() &&
7837 !ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(
7838 Inst.getOperand(i).getReg())) {
7839 return Error(Operands[2]->getStartLoc(),
7840 "invalid register in register list. Valid registers are "
7841 "r0-r12, lr/r14 and APSR.");
7842 }
7843 }
7844 break;
7845 }
7846 case ARM::DSB:
7847 case ARM::t2DSB: {
7848
7849 if (Inst.getNumOperands() < 2)
7850 break;
7851
7852 unsigned Option = Inst.getOperand(0).getImm();
7853 unsigned Pred = Inst.getOperand(1).getImm();
7854
7855 // SSBB and PSSBB (DSB #0|#4) are not predicable (pred must be AL).
7856 if (Option == 0 && Pred != ARMCC::AL)
7857 return Error(Operands[1]->getStartLoc(),
7858 "instruction 'ssbb' is not predicable, but condition code "
7859 "specified");
7860 if (Option == 4 && Pred != ARMCC::AL)
7861 return Error(Operands[1]->getStartLoc(),
7862 "instruction 'pssbb' is not predicable, but condition code "
7863 "specified");
7864 break;
7865 }
7866 case ARM::VMOVRRS: {
7867 // Source registers must be sequential.
7868 const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(2).getReg());
7869 const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(3).getReg());
7870 if (Sm1 != Sm + 1)
7871 return Error(Operands[5]->getStartLoc(),
7872 "source operands must be sequential");
7873 break;
7874 }
7875 case ARM::VMOVSRR: {
7876 // Destination registers must be sequential.
7877 const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(0).getReg());
7878 const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
7879 if (Sm1 != Sm + 1)
7880 return Error(Operands[3]->getStartLoc(),
7881 "destination operands must be sequential");
7882 break;
7883 }
7884 case ARM::VLDMDIA:
7885 case ARM::VSTMDIA: {
7886 ARMOperand &Op = static_cast<ARMOperand&>(*Operands[3]);
7887 auto &RegList = Op.getRegList();
7888 if (RegList.size() < 1 || RegList.size() > 16)
7889 return Error(Operands[3]->getStartLoc(),
7890 "list of registers must be at least 1 and at most 16");
7891 break;
7892 }
7893 case ARM::MVE_VQDMULLs32bh:
7894 case ARM::MVE_VQDMULLs32th:
7895 case ARM::MVE_VCMULf32:
7896 case ARM::MVE_VMULLs32bh:
7897 case ARM::MVE_VMULLs32th:
7898 case ARM::MVE_VMULLu32bh:
7899 case ARM::MVE_VMULLu32th: {
7900 if (Operands[3]->getReg() == Operands[4]->getReg()) {
7901 return Error (Operands[3]->getStartLoc(),
7902 "Qd register and Qn register can't be identical");
7903 }
7904 if (Operands[3]->getReg() == Operands[5]->getReg()) {
7905 return Error (Operands[3]->getStartLoc(),
7906 "Qd register and Qm register can't be identical");
7907 }
7908 break;
7909 }
7910 case ARM::MVE_VMOV_rr_q: {
7911 if (Operands[4]->getReg() != Operands[6]->getReg())
7912 return Error (Operands[4]->getStartLoc(), "Q-registers must be the same");
7913 if (static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() !=
7914 static_cast<ARMOperand &>(*Operands[7]).getVectorIndex() + 2)
7915 return Error (Operands[5]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1");
7916 break;
7917 }
7918 case ARM::MVE_VMOV_q_rr: {
7919 if (Operands[2]->getReg() != Operands[4]->getReg())
7920 return Error (Operands[2]->getStartLoc(), "Q-registers must be the same");
7921 if (static_cast<ARMOperand &>(*Operands[3]).getVectorIndex() !=
7922 static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() + 2)
7923 return Error (Operands[3]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1");
7924 break;
7925 }
7926 }
7927
7928 return false;
7929}
7930
7931static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
7932 switch(Opc) {
7933 default: llvm_unreachable("unexpected opcode!")::llvm::llvm_unreachable_internal("unexpected opcode!", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 7933)
;
7934 // VST1LN
7935 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
7936 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
7937 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
7938 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
7939 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
7940 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
7941 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
7942 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
7943 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
7944
7945 // VST2LN
7946 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
7947 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
7948 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
7949 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
7950 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
7951
7952 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
7953 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
7954 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
7955 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
7956 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
7957
7958 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
7959 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
7960 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
7961 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
7962 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
7963
7964 // VST3LN
7965 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
7966 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
7967 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
7968 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
7969 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
7970 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
7971 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
7972 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
7973 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
7974 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
7975 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
7976 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
7977 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
7978 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
7979 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
7980
7981 // VST3
7982 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
7983 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
7984 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
7985 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
7986 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
7987 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
7988 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
7989 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
7990 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
7991 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
7992 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
7993 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
7994 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
7995 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
7996 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
7997 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
7998 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
7999 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
8000
8001 // VST4LN
8002 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
8003 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
8004 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
8005 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
8006 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
8007 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
8008 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
8009 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
8010 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
8011 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
8012 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
8013 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
8014 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
8015 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
8016 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
8017
8018 // VST4
8019 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
8020 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
8021 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
8022 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
8023 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
8024 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
8025 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
8026 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
8027 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
8028 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
8029 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
8030 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
8031 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
8032 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
8033 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
8034 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
8035 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
8036 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
8037 }
8038}
8039
8040static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
8041 switch(Opc) {
8042 default: llvm_unreachable("unexpected opcode!")::llvm::llvm_unreachable_internal("unexpected opcode!", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 8042)
;
8043 // VLD1LN
8044 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
8045 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
8046 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
8047 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
8048 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
8049 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
8050 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
8051 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
8052 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
8053
8054 // VLD2LN
8055 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
8056 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
8057 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
8058 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
8059 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
8060 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
8061 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
8062 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
8063 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
8064 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
8065 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
8066 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
8067 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
8068 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
8069 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
8070
8071 // VLD3DUP
8072 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
8073 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
8074 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
8075 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
8076 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
8077 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
8078 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
8079 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
8080 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
8081 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
8082 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
8083 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
8084 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
8085 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
8086 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
8087 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
8088 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
8089 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
8090
8091 // VLD3LN
8092 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
8093 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
8094 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
8095 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
8096 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
8097 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
8098 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
8099 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
8100 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
8101 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
8102 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
8103 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
8104 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
8105 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
8106 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
8107
8108 // VLD3
8109 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
8110 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
8111 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
8112 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
8113 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
8114 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
8115 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
8116 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
8117 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
8118 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
8119 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
8120 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
8121 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
8122 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
8123 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
8124 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
8125 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
8126 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
8127
8128 // VLD4LN
8129 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
8130 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
8131 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
8132 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
8133 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
8134 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
8135 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
8136 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
8137 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
8138 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
8139 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
8140 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
8141 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
8142 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
8143 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
8144
8145 // VLD4DUP
8146 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
8147 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
8148 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
8149 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
8150 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
8151 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
8152 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
8153 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
8154 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
8155 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
8156 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
8157 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
8158 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
8159 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
8160 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
8161 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
8162 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
8163 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
8164
8165 // VLD4
8166 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
8167 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
8168 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
8169 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
8170 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
8171 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
8172 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
8173 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
8174 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
8175 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
8176 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
8177 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
8178 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
8179 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
8180 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
8181 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
8182 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
8183 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
8184 }
8185}
8186
8187bool ARMAsmParser::processInstruction(MCInst &Inst,
8188 const OperandVector &Operands,
8189 MCStreamer &Out) {
8190 // Check if we have the wide qualifier, because if it's present we
8191 // must avoid selecting a 16-bit thumb instruction.
8192 bool HasWideQualifier = false;
8193 for (auto &Op : Operands) {
8194 ARMOperand &ARMOp = static_cast<ARMOperand&>(*Op);
8195 if (ARMOp.isToken() && ARMOp.getToken() == ".w") {
8196 HasWideQualifier = true;
8197 break;
8198 }
8199 }
8200
8201 switch (Inst.getOpcode()) {
8202 case ARM::MVE_VORNIZ0v4i32:
8203 case ARM::MVE_VORNIZ0v8i16:
8204 case ARM::MVE_VORNIZ8v4i32:
8205 case ARM::MVE_VORNIZ8v8i16:
8206 case ARM::MVE_VORNIZ16v4i32:
8207 case ARM::MVE_VORNIZ24v4i32:
8208 case ARM::MVE_VANDIZ0v4i32:
8209 case ARM::MVE_VANDIZ0v8i16:
8210 case ARM::MVE_VANDIZ8v4i32:
8211 case ARM::MVE_VANDIZ8v8i16:
8212 case ARM::MVE_VANDIZ16v4i32:
8213 case ARM::MVE_VANDIZ24v4i32: {
8214 unsigned Opcode;
8215 bool imm16 = false;
8216 switch(Inst.getOpcode()) {
8217 case ARM::MVE_VORNIZ0v4i32: Opcode = ARM::MVE_VORRIZ0v4i32; break;
8218 case ARM::MVE_VORNIZ0v8i16: Opcode = ARM::MVE_VORRIZ0v8i16; imm16 = true; break;
8219 case ARM::MVE_VORNIZ8v4i32: Opcode = ARM::MVE_VORRIZ8v4i32; break;
8220 case ARM::MVE_VORNIZ8v8i16: Opcode = ARM::MVE_VORRIZ8v8i16; imm16 = true; break;
8221 case ARM::MVE_VORNIZ16v4i32: Opcode = ARM::MVE_VORRIZ16v4i32; break;
8222 case ARM::MVE_VORNIZ24v4i32: Opcode = ARM::MVE_VORRIZ24v4i32; break;
8223 case ARM::MVE_VANDIZ0v4i32: Opcode = ARM::MVE_VBICIZ0v4i32; break;
8224 case ARM::MVE_VANDIZ0v8i16: Opcode = ARM::MVE_VBICIZ0v8i16; imm16 = true; break;
8225 case ARM::MVE_VANDIZ8v4i32: Opcode = ARM::MVE_VBICIZ8v4i32; break;
8226 case ARM::MVE_VANDIZ8v8i16: Opcode = ARM::MVE_VBICIZ8v8i16; imm16 = true; break;
8227 case ARM::MVE_VANDIZ16v4i32: Opcode = ARM::MVE_VBICIZ16v4i32; break;
8228 case ARM::MVE_VANDIZ24v4i32: Opcode = ARM::MVE_VBICIZ24v4i32; break;
8229 default: llvm_unreachable("unexpected opcode")::llvm::llvm_unreachable_internal("unexpected opcode", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 8229)
;
8230 }
8231
8232 MCInst TmpInst;
8233 TmpInst.setOpcode(Opcode);
8234 TmpInst.addOperand(Inst.getOperand(0));
8235 TmpInst.addOperand(Inst.getOperand(1));
8236
8237 // invert immediate
8238 unsigned imm = ~Inst.getOperand(2).getImm() & (imm16 ? 0xffff : 0xffffffff);
8239 TmpInst.addOperand(MCOperand::createImm(imm));
8240
8241 TmpInst.addOperand(Inst.getOperand(3));
8242 TmpInst.addOperand(Inst.getOperand(4));
8243 Inst = TmpInst;
8244 return true;
8245 }
8246 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
8247 case ARM::LDRT_POST:
8248 case ARM::LDRBT_POST: {
8249 const unsigned Opcode =
8250 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
8251 : ARM::LDRBT_POST_IMM;
8252 MCInst TmpInst;
8253 TmpInst.setOpcode(Opcode);
8254 TmpInst.addOperand(Inst.getOperand(0));
8255 TmpInst.addOperand(Inst.getOperand(1));
8256 TmpInst.addOperand(Inst.getOperand(1));
8257 TmpInst.addOperand(MCOperand::createReg(0));
8258 TmpInst.addOperand(MCOperand::createImm(0));
8259 TmpInst.addOperand(Inst.getOperand(2));
8260 TmpInst.addOperand(Inst.getOperand(3));
8261 Inst = TmpInst;
8262 return true;
8263 }
8264 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
8265 case ARM::STRT_POST:
8266 case ARM::STRBT_POST: {
8267 const unsigned Opcode =
8268 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
8269 : ARM::STRBT_POST_IMM;
8270 MCInst TmpInst;
8271 TmpInst.setOpcode(Opcode);
8272 TmpInst.addOperand(Inst.getOperand(1));
8273 TmpInst.addOperand(Inst.getOperand(0));
8274 TmpInst.addOperand(Inst.getOperand(1));
8275 TmpInst.addOperand(MCOperand::createReg(0));
8276 TmpInst.addOperand(MCOperand::createImm(0));
8277 TmpInst.addOperand(Inst.getOperand(2));
8278 TmpInst.addOperand(Inst.getOperand(3));
8279 Inst = TmpInst;
8280 return true;
8281 }
8282 // Alias for alternate form of 'ADR Rd, #imm' instruction.
8283 case ARM::ADDri: {
8284 if (Inst.getOperand(1).getReg() != ARM::PC ||
8285 Inst.getOperand(5).getReg() != 0 ||
8286 !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
8287 return false;
8288 MCInst TmpInst;
8289 TmpInst.setOpcode(ARM::ADR);
8290 TmpInst.addOperand(Inst.getOperand(0));
8291 if (Inst.getOperand(2).isImm()) {
8292 // Immediate (mod_imm) will be in its encoded form, we must unencode it
8293 // before passing it to the ADR instruction.
8294 unsigned Enc = Inst.getOperand(2).getImm();
8295 TmpInst.addOperand(MCOperand::createImm(
8296 ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
8297 } else {
8298 // Turn PC-relative expression into absolute expression.
8299 // Reading PC provides the start of the current instruction + 8 and
8300 // the transform to adr is biased by that.
8301 MCSymbol *Dot = getContext().createTempSymbol();
8302 Out.EmitLabel(Dot);
8303 const MCExpr *OpExpr = Inst.getOperand(2).getExpr();
8304 const MCExpr *InstPC = MCSymbolRefExpr::create(Dot,
8305 MCSymbolRefExpr::VK_None,
8306 getContext());
8307 const MCExpr *Const8 = MCConstantExpr::create(8, getContext());
8308 const MCExpr *ReadPC = MCBinaryExpr::createAdd(InstPC, Const8,
8309 getContext());
8310 const MCExpr *FixupAddr = MCBinaryExpr::createAdd(ReadPC, OpExpr,
8311 getContext());
8312 TmpInst.addOperand(MCOperand::createExpr(FixupAddr));
8313 }
8314 TmpInst.addOperand(Inst.getOperand(3));
8315 TmpInst.addOperand(Inst.getOperand(4));
8316 Inst = TmpInst;
8317 return true;
8318 }
8319 // Aliases for alternate PC+imm syntax of LDR instructions.
8320 case ARM::t2LDRpcrel:
8321 // Select the narrow version if the immediate will fit.
8322 if (Inst.getOperand(1).getImm() > 0 &&
8323 Inst.getOperand(1).getImm() <= 0xff &&
8324 !HasWideQualifier)
8325 Inst.setOpcode(ARM::tLDRpci);
8326 else
8327 Inst.setOpcode(ARM::t2LDRpci);
8328 return true;
8329 case ARM::t2LDRBpcrel:
8330 Inst.setOpcode(ARM::t2LDRBpci);
8331 return true;
8332 case ARM::t2LDRHpcrel:
8333 Inst.setOpcode(ARM::t2LDRHpci);
8334 return true;
8335 case ARM::t2LDRSBpcrel:
8336 Inst.setOpcode(ARM::t2LDRSBpci);
8337 return true;
8338 case ARM::t2LDRSHpcrel:
8339 Inst.setOpcode(ARM::t2LDRSHpci);
8340 return true;
8341 case ARM::LDRConstPool:
8342 case ARM::tLDRConstPool:
8343 case ARM::t2LDRConstPool: {
8344 // Pseudo instruction ldr rt, =immediate is converted to a
8345 // MOV rt, immediate if immediate is known and representable
8346 // otherwise we create a constant pool entry that we load from.
8347 MCInst TmpInst;
8348 if (Inst.getOpcode() == ARM::LDRConstPool)
8349 TmpInst.setOpcode(ARM::LDRi12);
8350 else if (Inst.getOpcode() == ARM::tLDRConstPool)
8351 TmpInst.setOpcode(ARM::tLDRpci);
8352 else if (Inst.getOpcode() == ARM::t2LDRConstPool)
8353 TmpInst.setOpcode(ARM::t2LDRpci);
8354 const ARMOperand &PoolOperand =
8355 (HasWideQualifier ?
8356 static_cast<ARMOperand &>(*Operands[4]) :
8357 static_cast<ARMOperand &>(*Operands[3]));
8358 const MCExpr *SubExprVal = PoolOperand.getConstantPoolImm();
8359 // If SubExprVal is a constant we may be able to use a MOV
8360 if (isa<MCConstantExpr>(SubExprVal) &&
8361 Inst.getOperand(0).getReg() != ARM::PC &&
8362 Inst.getOperand(0).getReg() != ARM::SP) {
8363 int64_t Value =
8364 (int64_t) (cast<MCConstantExpr>(SubExprVal))->getValue();
8365 bool UseMov = true;
8366 bool MovHasS = true;
8367 if (Inst.getOpcode() == ARM::LDRConstPool) {
8368 // ARM Constant
8369 if (ARM_AM::getSOImmVal(Value) != -1) {
8370 Value = ARM_AM::getSOImmVal(Value);
8371 TmpInst.setOpcode(ARM::MOVi);
8372 }
8373 else if (ARM_AM::getSOImmVal(~Value) != -1) {
8374 Value = ARM_AM::getSOImmVal(~Value);
8375 TmpInst.setOpcode(ARM::MVNi);
8376 }
8377 else if (hasV6T2Ops() &&
8378 Value >=0 && Value < 65536) {
8379 TmpInst.setOpcode(ARM::MOVi16);
8380 MovHasS = false;
8381 }
8382 else
8383 UseMov = false;
8384 }
8385 else {
8386 // Thumb/Thumb2 Constant
8387 if (hasThumb2() &&
8388 ARM_AM::getT2SOImmVal(Value) != -1)
8389 TmpInst.setOpcode(ARM::t2MOVi);
8390 else if (hasThumb2() &&
8391 ARM_AM::getT2SOImmVal(~Value) != -1) {
8392 TmpInst.setOpcode(ARM::t2MVNi);
8393 Value = ~Value;
8394 }
8395 else if (hasV8MBaseline() &&
8396 Value >=0 && Value < 65536) {
8397 TmpInst.setOpcode(ARM::t2MOVi16);
8398 MovHasS = false;
8399 }
8400 else
8401 UseMov = false;
8402 }
8403 if (UseMov) {
8404 TmpInst.addOperand(Inst.getOperand(0)); // Rt
8405 TmpInst.addOperand(MCOperand::createImm(Value)); // Immediate
8406 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8407 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8408 if (MovHasS)
8409 TmpInst.addOperand(MCOperand::createReg(0)); // S
8410 Inst = TmpInst;
8411 return true;
8412 }
8413 }
8414 // No opportunity to use MOV/MVN create constant pool
8415 const MCExpr *CPLoc =
8416 getTargetStreamer().addConstantPoolEntry(SubExprVal,
8417 PoolOperand.getStartLoc());
8418 TmpInst.addOperand(Inst.getOperand(0)); // Rt
8419 TmpInst.addOperand(MCOperand::createExpr(CPLoc)); // offset to constpool
8420 if (TmpInst.getOpcode() == ARM::LDRi12)
8421 TmpInst.addOperand(MCOperand::createImm(0)); // unused offset
8422 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8423 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8424 Inst = TmpInst;
8425 return true;
8426 }
8427 // Handle NEON VST complex aliases.
8428 case ARM::VST1LNdWB_register_Asm_8:
8429 case ARM::VST1LNdWB_register_Asm_16:
8430 case ARM::VST1LNdWB_register_Asm_32: {
8431 MCInst TmpInst;
8432 // Shuffle the operands around so the lane index operand is in the
8433 // right place.
8434 unsigned Spacing;
8435 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8436 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8437 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8438 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8439 TmpInst.addOperand(Inst.getOperand(4)); // Rm
8440 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8441 TmpInst.addOperand(Inst.getOperand(1)); // lane
8442 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8443 TmpInst.addOperand(Inst.getOperand(6));
8444 Inst = TmpInst;
8445 return true;
8446 }
8447
8448 case ARM::VST2LNdWB_register_Asm_8:
8449 case ARM::VST2LNdWB_register_Asm_16:
8450 case ARM::VST2LNdWB_register_Asm_32:
8451 case ARM::VST2LNqWB_register_Asm_16:
8452 case ARM::VST2LNqWB_register_Asm_32: {
8453 MCInst TmpInst;
8454 // Shuffle the operands around so the lane index operand is in the
8455 // right place.
8456 unsigned Spacing;
8457 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8458 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8459 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8460 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8461 TmpInst.addOperand(Inst.getOperand(4)); // Rm
8462 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8463 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8464 Spacing));
8465 TmpInst.addOperand(Inst.getOperand(1)); // lane
8466 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8467 TmpInst.addOperand(Inst.getOperand(6));
8468 Inst = TmpInst;
8469 return true;
8470 }
8471
8472 case ARM::VST3LNdWB_register_Asm_8:
8473 case ARM::VST3LNdWB_register_Asm_16:
8474 case ARM::VST3LNdWB_register_Asm_32:
8475 case ARM::VST3LNqWB_register_Asm_16:
8476 case ARM::VST3LNqWB_register_Asm_32: {
8477 MCInst TmpInst;
8478 // Shuffle the operands around so the lane index operand is in the
8479 // right place.
8480 unsigned Spacing;
8481 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8482 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8483 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8484 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8485 TmpInst.addOperand(Inst.getOperand(4)); // Rm
8486 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8487 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8488 Spacing));
8489 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8490 Spacing * 2));
8491 TmpInst.addOperand(Inst.getOperand(1)); // lane
8492 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8493 TmpInst.addOperand(Inst.getOperand(6));
8494 Inst = TmpInst;
8495 return true;
8496 }
8497
8498 case ARM::VST4LNdWB_register_Asm_8:
8499 case ARM::VST4LNdWB_register_Asm_16:
8500 case ARM::VST4LNdWB_register_Asm_32:
8501 case ARM::VST4LNqWB_register_Asm_16:
8502 case ARM::VST4LNqWB_register_Asm_32: {
8503 MCInst TmpInst;
8504 // Shuffle the operands around so the lane index operand is in the
8505 // right place.
8506 unsigned Spacing;
8507 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8508 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8509 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8510 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8511 TmpInst.addOperand(Inst.getOperand(4)); // Rm
8512 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8513 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8514 Spacing));
8515 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8516 Spacing * 2));
8517 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8518 Spacing * 3));
8519 TmpInst.addOperand(Inst.getOperand(1)); // lane
8520 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8521 TmpInst.addOperand(Inst.getOperand(6));
8522 Inst = TmpInst;
8523 return true;
8524 }
8525
8526 case ARM::VST1LNdWB_fixed_Asm_8:
8527 case ARM::VST1LNdWB_fixed_Asm_16:
8528 case ARM::VST1LNdWB_fixed_Asm_32: {
8529 MCInst TmpInst;
8530 // Shuffle the operands around so the lane index operand is in the
8531 // right place.
8532 unsigned Spacing;
8533 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8534 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8535 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8536 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8537 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8538 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8539 TmpInst.addOperand(Inst.getOperand(1)); // lane
8540 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8541 TmpInst.addOperand(Inst.getOperand(5));
8542 Inst = TmpInst;
8543 return true;
8544 }
8545
8546 case ARM::VST2LNdWB_fixed_Asm_8:
8547 case ARM::VST2LNdWB_fixed_Asm_16:
8548 case ARM::VST2LNdWB_fixed_Asm_32:
8549 case ARM::VST2LNqWB_fixed_Asm_16:
8550 case ARM::VST2LNqWB_fixed_Asm_32: {
8551 MCInst TmpInst;
8552 // Shuffle the operands around so the lane index operand is in the
8553 // right place.
8554 unsigned Spacing;
8555 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8556 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8557 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8558 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8559 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8560 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8561 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8562 Spacing));
8563 TmpInst.addOperand(Inst.getOperand(1)); // lane
8564 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8565 TmpInst.addOperand(Inst.getOperand(5));
8566 Inst = TmpInst;
8567 return true;
8568 }
8569
8570 case ARM::VST3LNdWB_fixed_Asm_8:
8571 case ARM::VST3LNdWB_fixed_Asm_16:
8572 case ARM::VST3LNdWB_fixed_Asm_32:
8573 case ARM::VST3LNqWB_fixed_Asm_16:
8574 case ARM::VST3LNqWB_fixed_Asm_32: {
8575 MCInst TmpInst;
8576 // Shuffle the operands around so the lane index operand is in the
8577 // right place.
8578 unsigned Spacing;
8579 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8580 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8581 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8582 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8583 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8584 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8585 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8586 Spacing));
8587 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8588 Spacing * 2));
8589 TmpInst.addOperand(Inst.getOperand(1)); // lane
8590 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8591 TmpInst.addOperand(Inst.getOperand(5));
8592 Inst = TmpInst;
8593 return true;
8594 }
8595
8596 case ARM::VST4LNdWB_fixed_Asm_8:
8597 case ARM::VST4LNdWB_fixed_Asm_16:
8598 case ARM::VST4LNdWB_fixed_Asm_32:
8599 case ARM::VST4LNqWB_fixed_Asm_16:
8600 case ARM::VST4LNqWB_fixed_Asm_32: {
8601 MCInst TmpInst;
8602 // Shuffle the operands around so the lane index operand is in the
8603 // right place.
8604 unsigned Spacing;
8605 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8606 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8607 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8608 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8609 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8610 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8611 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8612 Spacing));
8613 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8614 Spacing * 2));
8615 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8616 Spacing * 3));
8617 TmpInst.addOperand(Inst.getOperand(1)); // lane
8618 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8619 TmpInst.addOperand(Inst.getOperand(5));
8620 Inst = TmpInst;
8621 return true;
8622 }
8623
8624 case ARM::VST1LNdAsm_8:
8625 case ARM::VST1LNdAsm_16:
8626 case ARM::VST1LNdAsm_32: {
8627 MCInst TmpInst;
8628 // Shuffle the operands around so the lane index operand is in the
8629 // right place.
8630 unsigned Spacing;
8631 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8632 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8633 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8634 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8635 TmpInst.addOperand(Inst.getOperand(1)); // lane
8636 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8637 TmpInst.addOperand(Inst.getOperand(5));
8638 Inst = TmpInst;
8639 return true;
8640 }
8641
8642 case ARM::VST2LNdAsm_8:
8643 case ARM::VST2LNdAsm_16:
8644 case ARM::VST2LNdAsm_32:
8645 case ARM::VST2LNqAsm_16:
8646 case ARM::VST2LNqAsm_32: {
8647 MCInst TmpInst;
8648 // Shuffle the operands around so the lane index operand is in the
8649 // right place.
8650 unsigned Spacing;
8651 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8652 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8653 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8654 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8655 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8656 Spacing));
8657 TmpInst.addOperand(Inst.getOperand(1)); // lane
8658 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8659 TmpInst.addOperand(Inst.getOperand(5));
8660 Inst = TmpInst;
8661 return true;
8662 }
8663
8664 case ARM::VST3LNdAsm_8:
8665 case ARM::VST3LNdAsm_16:
8666 case ARM::VST3LNdAsm_32:
8667 case ARM::VST3LNqAsm_16:
8668 case ARM::VST3LNqAsm_32: {
8669 MCInst TmpInst;
8670 // Shuffle the operands around so the lane index operand is in the
8671 // right place.
8672 unsigned Spacing;
8673 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8674 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8675 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8676 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8677 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8678 Spacing));
8679 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8680 Spacing * 2));
8681 TmpInst.addOperand(Inst.getOperand(1)); // lane
8682 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8683 TmpInst.addOperand(Inst.getOperand(5));
8684 Inst = TmpInst;
8685 return true;
8686 }
8687
8688 case ARM::VST4LNdAsm_8:
8689 case ARM::VST4LNdAsm_16:
8690 case ARM::VST4LNdAsm_32:
8691 case ARM::VST4LNqAsm_16:
8692 case ARM::VST4LNqAsm_32: {
8693 MCInst TmpInst;
8694 // Shuffle the operands around so the lane index operand is in the
8695 // right place.
8696 unsigned Spacing;
8697 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8698 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8699 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8700 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8701 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8702 Spacing));
8703 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8704 Spacing * 2));
8705 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8706 Spacing * 3));
8707 TmpInst.addOperand(Inst.getOperand(1)); // lane
8708 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8709 TmpInst.addOperand(Inst.getOperand(5));
8710 Inst = TmpInst;
8711 return true;
8712 }
8713
8714 // Handle NEON VLD complex aliases.
8715 case ARM::VLD1LNdWB_register_Asm_8:
8716 case ARM::VLD1LNdWB_register_Asm_16:
8717 case ARM::VLD1LNdWB_register_Asm_32: {
8718 MCInst TmpInst;
8719 // Shuffle the operands around so the lane index operand is in the
8720 // right place.
8721 unsigned Spacing;
8722 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8723 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8724 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8725 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8726 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8727 TmpInst.addOperand(Inst.getOperand(4)); // Rm
8728 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
8729 TmpInst.addOperand(Inst.getOperand(1)); // lane
8730 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8731 TmpInst.addOperand(Inst.getOperand(6));
8732 Inst = TmpInst;
8733 return true;
8734 }
8735
8736 case ARM::VLD2LNdWB_register_Asm_8:
8737 case ARM::VLD2LNdWB_register_Asm_16:
8738 case ARM::VLD2LNdWB_register_Asm_32:
8739 case ARM::VLD2LNqWB_register_Asm_16:
8740 case ARM::VLD2LNqWB_register_Asm_32: {
8741 MCInst TmpInst;
8742 // Shuffle the operands around so the lane index operand is in the
8743 // right place.
8744 unsigned Spacing;
8745 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8746 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8747 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8748 Spacing));
8749 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8750 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8751 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8752 TmpInst.addOperand(Inst.getOperand(4)); // Rm
8753 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
8754 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8755 Spacing));
8756 TmpInst.addOperand(Inst.getOperand(1)); // lane
8757 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8758 TmpInst.addOperand(Inst.getOperand(6));
8759 Inst = TmpInst;
8760 return true;
8761 }
8762
8763 case ARM::VLD3LNdWB_register_Asm_8:
8764 case ARM::VLD3LNdWB_register_Asm_16:
8765 case ARM::VLD3LNdWB_register_Asm_32:
8766 case ARM::VLD3LNqWB_register_Asm_16:
8767 case ARM::VLD3LNqWB_register_Asm_32: {
8768 MCInst TmpInst;
8769 // Shuffle the operands around so the lane index operand is in the
8770 // right place.
8771 unsigned Spacing;
8772 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8773 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8774 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8775 Spacing));
8776 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8777 Spacing * 2));
8778 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8779 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8780 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8781 TmpInst.addOperand(Inst.getOperand(4)); // Rm
8782 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
8783 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8784 Spacing));
8785 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8786 Spacing * 2));
8787 TmpInst.addOperand(Inst.getOperand(1)); // lane
8788 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8789 TmpInst.addOperand(Inst.getOperand(6));
8790 Inst = TmpInst;
8791 return true;
8792 }
8793
8794 case ARM::VLD4LNdWB_register_Asm_8:
8795 case ARM::VLD4LNdWB_register_Asm_16:
8796 case ARM::VLD4LNdWB_register_Asm_32:
8797 case ARM::VLD4LNqWB_register_Asm_16:
8798 case ARM::VLD4LNqWB_register_Asm_32: {
8799 MCInst TmpInst;
8800 // Shuffle the operands around so the lane index operand is in the
8801 // right place.
8802 unsigned Spacing;
8803 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8804 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8805 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8806 Spacing));
8807 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8808 Spacing * 2));
8809 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8810 Spacing * 3));
8811 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8812 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8813 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8814 TmpInst.addOperand(Inst.getOperand(4)); // Rm
8815 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
8816 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8817 Spacing));
8818 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8819 Spacing * 2));
8820 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8821 Spacing * 3));
8822 TmpInst.addOperand(Inst.getOperand(1)); // lane
8823 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8824 TmpInst.addOperand(Inst.getOperand(6));
8825 Inst = TmpInst;
8826 return true;
8827 }
8828
8829 case ARM::VLD1LNdWB_fixed_Asm_8:
8830 case ARM::VLD1LNdWB_fixed_Asm_16:
8831 case ARM::VLD1LNdWB_fixed_Asm_32: {
8832 MCInst TmpInst;
8833 // Shuffle the operands around so the lane index operand is in the
8834 // right place.
8835 unsigned Spacing;
8836 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8837 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8838 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8839 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8840 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8841 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8842 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
8843 TmpInst.addOperand(Inst.getOperand(1)); // lane
8844 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8845 TmpInst.addOperand(Inst.getOperand(5));
8846 Inst = TmpInst;
8847 return true;
8848 }
8849
8850 case ARM::VLD2LNdWB_fixed_Asm_8:
8851 case ARM::VLD2LNdWB_fixed_Asm_16:
8852 case ARM::VLD2LNdWB_fixed_Asm_32:
8853 case ARM::VLD2LNqWB_fixed_Asm_16:
8854 case ARM::VLD2LNqWB_fixed_Asm_32: {
8855 MCInst TmpInst;
8856 // Shuffle the operands around so the lane index operand is in the
8857 // right place.
8858 unsigned Spacing;
8859 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8860 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8861 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8862 Spacing));
8863 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8864 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8865 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8866 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8867 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
8868 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8869 Spacing));
8870 TmpInst.addOperand(Inst.getOperand(1)); // lane
8871 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8872 TmpInst.addOperand(Inst.getOperand(5));
8873 Inst = TmpInst;
8874 return true;
8875 }
8876
8877 case ARM::VLD3LNdWB_fixed_Asm_8:
8878 case ARM::VLD3LNdWB_fixed_Asm_16:
8879 case ARM::VLD3LNdWB_fixed_Asm_32:
8880 case ARM::VLD3LNqWB_fixed_Asm_16:
8881 case ARM::VLD3LNqWB_fixed_Asm_32: {
8882 MCInst TmpInst;
8883 // Shuffle the operands around so the lane index operand is in the
8884 // right place.
8885 unsigned Spacing;
8886 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8887 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8888 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8889 Spacing));
8890 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8891 Spacing * 2));
8892 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8893 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8894 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8895 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8896 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
8897 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8898 Spacing));
8899 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8900 Spacing * 2));
8901 TmpInst.addOperand(Inst.getOperand(1)); // lane
8902 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8903 TmpInst.addOperand(Inst.getOperand(5));
8904 Inst = TmpInst;
8905 return true;
8906 }
8907
8908 case ARM::VLD4LNdWB_fixed_Asm_8:
8909 case ARM::VLD4LNdWB_fixed_Asm_16:
8910 case ARM::VLD4LNdWB_fixed_Asm_32:
8911 case ARM::VLD4LNqWB_fixed_Asm_16:
8912 case ARM::VLD4LNqWB_fixed_Asm_32: {
8913 MCInst TmpInst;
8914 // Shuffle the operands around so the lane index operand is in the
8915 // right place.
8916 unsigned Spacing;
8917 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8918 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8919 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8920 Spacing));
8921 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8922 Spacing * 2));
8923 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8924 Spacing * 3));
8925 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8926 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8927 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8928 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8929 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
8930 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8931 Spacing));
8932 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8933 Spacing * 2));
8934 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8935 Spacing * 3));
8936 TmpInst.addOperand(Inst.getOperand(1)); // lane
8937 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8938 TmpInst.addOperand(Inst.getOperand(5));
8939 Inst = TmpInst;
8940 return true;
8941 }
8942
8943 case ARM::VLD1LNdAsm_8:
8944 case ARM::VLD1LNdAsm_16:
8945 case ARM::VLD1LNdAsm_32: {
8946 MCInst TmpInst;
8947 // Shuffle the operands around so the lane index operand is in the
8948 // right place.
8949 unsigned Spacing;
8950 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8951 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8952 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8953 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8954 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
8955 TmpInst.addOperand(Inst.getOperand(1)); // lane
8956 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8957 TmpInst.addOperand(Inst.getOperand(5));
8958 Inst = TmpInst;
8959 return true;
8960 }
8961
8962 case ARM::VLD2LNdAsm_8:
8963 case ARM::VLD2LNdAsm_16:
8964 case ARM::VLD2LNdAsm_32:
8965 case ARM::VLD2LNqAsm_16:
8966 case ARM::VLD2LNqAsm_32: {
8967 MCInst TmpInst;
8968 // Shuffle the operands around so the lane index operand is in the
8969 // right place.
8970 unsigned Spacing;
8971 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8972 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8973 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8974 Spacing));
8975 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8976 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8977 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
8978 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8979 Spacing));
8980 TmpInst.addOperand(Inst.getOperand(1)); // lane
8981 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8982 TmpInst.addOperand(Inst.getOperand(5));
8983 Inst = TmpInst;
8984 return true;
8985 }
8986
8987 case ARM::VLD3LNdAsm_8:
8988 case ARM::VLD3LNdAsm_16:
8989 case ARM::VLD3LNdAsm_32:
8990 case ARM::VLD3LNqAsm_16:
8991 case ARM::VLD3LNqAsm_32: {
8992 MCInst TmpInst;
8993 // Shuffle the operands around so the lane index operand is in the
8994 // right place.
8995 unsigned Spacing;
8996 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8997 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8998 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8999 Spacing));
9000 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9001 Spacing * 2));
9002 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9003 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9004 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9005 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9006 Spacing));
9007 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9008 Spacing * 2));
9009 TmpInst.addOperand(Inst.getOperand(1)); // lane
9010 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9011 TmpInst.addOperand(Inst.getOperand(5));
9012 Inst = TmpInst;
9013 return true;
9014 }
9015
9016 case ARM::VLD4LNdAsm_8:
9017 case ARM::VLD4LNdAsm_16:
9018 case ARM::VLD4LNdAsm_32:
9019 case ARM::VLD4LNqAsm_16:
9020 case ARM::VLD4LNqAsm_32: {
9021 MCInst TmpInst;
9022 // Shuffle the operands around so the lane index operand is in the
9023 // right place.
9024 unsigned Spacing;
9025 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9026 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9027 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9028 Spacing));
9029 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9030 Spacing * 2));
9031 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9032 Spacing * 3));
9033 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9034 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9035 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9036 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9037 Spacing));
9038 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9039 Spacing * 2));
9040 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9041 Spacing * 3));
9042 TmpInst.addOperand(Inst.getOperand(1)); // lane
9043 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9044 TmpInst.addOperand(Inst.getOperand(5));
9045 Inst = TmpInst;
9046 return true;
9047 }
9048
9049 // VLD3DUP single 3-element structure to all lanes instructions.
9050 case ARM::VLD3DUPdAsm_8:
9051 case ARM::VLD3DUPdAsm_16:
9052 case ARM::VLD3DUPdAsm_32:
9053 case ARM::VLD3DUPqAsm_8:
9054 case ARM::VLD3DUPqAsm_16:
9055 case ARM::VLD3DUPqAsm_32: {
9056 MCInst TmpInst;
9057 unsigned Spacing;
9058 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9059 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9060 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9061 Spacing));
9062 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9063 Spacing * 2));
9064 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9065 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9066 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9067 TmpInst.addOperand(Inst.getOperand(4));
9068 Inst = TmpInst;
9069 return true;
9070 }
9071
9072 case ARM::VLD3DUPdWB_fixed_Asm_8:
9073 case ARM::VLD3DUPdWB_fixed_Asm_16:
9074 case ARM::VLD3DUPdWB_fixed_Asm_32:
9075 case ARM::VLD3DUPqWB_fixed_Asm_8:
9076 case ARM::VLD3DUPqWB_fixed_Asm_16:
9077 case ARM::VLD3DUPqWB_fixed_Asm_32: {
9078 MCInst TmpInst;
9079 unsigned Spacing;
9080 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9081 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9082 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9083 Spacing));
9084 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9085 Spacing * 2));
9086 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9087 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9088 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9089 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9090 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9091 TmpInst.addOperand(Inst.getOperand(4));
9092 Inst = TmpInst;
9093 return true;
9094 }
9095
9096 case ARM::VLD3DUPdWB_register_Asm_8:
9097 case ARM::VLD3DUPdWB_register_Asm_16:
9098 case ARM::VLD3DUPdWB_register_Asm_32:
9099 case ARM::VLD3DUPqWB_register_Asm_8:
9100 case ARM::VLD3DUPqWB_register_Asm_16:
9101 case ARM::VLD3DUPqWB_register_Asm_32: {
9102 MCInst TmpInst;
9103 unsigned Spacing;
9104 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9105 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9106 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9107 Spacing));
9108 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9109 Spacing * 2));
9110 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9111 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9112 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9113 TmpInst.addOperand(Inst.getOperand(3)); // Rm
9114 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9115 TmpInst.addOperand(Inst.getOperand(5));
9116 Inst = TmpInst;
9117 return true;
9118 }
9119
9120 // VLD3 multiple 3-element structure instructions.
9121 case ARM::VLD3dAsm_8:
9122 case ARM::VLD3dAsm_16:
9123 case ARM::VLD3dAsm_32:
9124 case ARM::VLD3qAsm_8:
9125 case ARM::VLD3qAsm_16:
9126 case ARM::VLD3qAsm_32: {
9127 MCInst TmpInst;
9128 unsigned Spacing;
9129 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9130 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9131 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9132 Spacing));
9133 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9134 Spacing * 2));
9135 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9136 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9137 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9138 TmpInst.addOperand(Inst.getOperand(4));
9139 Inst = TmpInst;
9140 return true;
9141 }
9142
9143 case ARM::VLD3dWB_fixed_Asm_8:
9144 case ARM::VLD3dWB_fixed_Asm_16:
9145 case ARM::VLD3dWB_fixed_Asm_32:
9146 case ARM::VLD3qWB_fixed_Asm_8:
9147 case ARM::VLD3qWB_fixed_Asm_16:
9148 case ARM::VLD3qWB_fixed_Asm_32: {
9149 MCInst TmpInst;
9150 unsigned Spacing;
9151 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9152 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9153 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9154 Spacing));
9155 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9156 Spacing * 2));
9157 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9158 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9159 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9160 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9161 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9162 TmpInst.addOperand(Inst.getOperand(4));
9163 Inst = TmpInst;
9164 return true;
9165 }
9166
9167 case ARM::VLD3dWB_register_Asm_8:
9168 case ARM::VLD3dWB_register_Asm_16:
9169 case ARM::VLD3dWB_register_Asm_32:
9170 case ARM::VLD3qWB_register_Asm_8:
9171 case ARM::VLD3qWB_register_Asm_16:
9172 case ARM::VLD3qWB_register_Asm_32: {
9173 MCInst TmpInst;
9174 unsigned Spacing;
9175 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9176 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9177 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9178 Spacing));
9179 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9180 Spacing * 2));
9181 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9182 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9183 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9184 TmpInst.addOperand(Inst.getOperand(3)); // Rm
9185 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9186 TmpInst.addOperand(Inst.getOperand(5));
9187 Inst = TmpInst;
9188 return true;
9189 }
9190
9191 // VLD4DUP single 3-element structure to all lanes instructions.
9192 case ARM::VLD4DUPdAsm_8:
9193 case ARM::VLD4DUPdAsm_16:
9194 case ARM::VLD4DUPdAsm_32:
9195 case ARM::VLD4DUPqAsm_8:
9196 case ARM::VLD4DUPqAsm_16:
9197 case ARM::VLD4DUPqAsm_32: {
9198 MCInst TmpInst;
9199 unsigned Spacing;
9200 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9201 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9202 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9203 Spacing));
9204 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9205 Spacing * 2));
9206 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9207 Spacing * 3));
9208 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9209 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9210 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9211 TmpInst.addOperand(Inst.getOperand(4));
9212 Inst = TmpInst;
9213 return true;
9214 }
9215
9216 case ARM::VLD4DUPdWB_fixed_Asm_8:
9217 case ARM::VLD4DUPdWB_fixed_Asm_16:
9218 case ARM::VLD4DUPdWB_fixed_Asm_32:
9219 case ARM::VLD4DUPqWB_fixed_Asm_8:
9220 case ARM::VLD4DUPqWB_fixed_Asm_16:
9221 case ARM::VLD4DUPqWB_fixed_Asm_32: {
9222 MCInst TmpInst;
9223 unsigned Spacing;
9224 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9225 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9226 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9227 Spacing));
9228 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9229 Spacing * 2));
9230 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9231 Spacing * 3));
9232 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9233 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9234 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9235 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9236 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9237 TmpInst.addOperand(Inst.getOperand(4));
9238 Inst = TmpInst;
9239 return true;
9240 }
9241
9242 case ARM::VLD4DUPdWB_register_Asm_8:
9243 case ARM::VLD4DUPdWB_register_Asm_16:
9244 case ARM::VLD4DUPdWB_register_Asm_32:
9245 case ARM::VLD4DUPqWB_register_Asm_8:
9246 case ARM::VLD4DUPqWB_register_Asm_16:
9247 case ARM::VLD4DUPqWB_register_Asm_32: {
9248 MCInst TmpInst;
9249 unsigned Spacing;
9250 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9251 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9252 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9253 Spacing));
9254 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9255 Spacing * 2));
9256 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9257 Spacing * 3));
9258 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9259 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9260 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9261 TmpInst.addOperand(Inst.getOperand(3)); // Rm
9262 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9263 TmpInst.addOperand(Inst.getOperand(5));
9264 Inst = TmpInst;
9265 return true;
9266 }
9267
9268 // VLD4 multiple 4-element structure instructions.
9269 case ARM::VLD4dAsm_8:
9270 case ARM::VLD4dAsm_16:
9271 case ARM::VLD4dAsm_32:
9272 case ARM::VLD4qAsm_8:
9273 case ARM::VLD4qAsm_16:
9274 case ARM::VLD4qAsm_32: {
9275 MCInst TmpInst;
9276 unsigned Spacing;
9277 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9278 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9279 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9280 Spacing));
9281 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9282 Spacing * 2));
9283 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9284 Spacing * 3));
9285 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9286 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9287 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9288 TmpInst.addOperand(Inst.getOperand(4));
9289 Inst = TmpInst;
9290 return true;
9291 }
9292
9293 case ARM::VLD4dWB_fixed_Asm_8:
9294 case ARM::VLD4dWB_fixed_Asm_16:
9295 case ARM::VLD4dWB_fixed_Asm_32:
9296 case ARM::VLD4qWB_fixed_Asm_8:
9297 case ARM::VLD4qWB_fixed_Asm_16:
9298 case ARM::VLD4qWB_fixed_Asm_32: {
9299 MCInst TmpInst;
9300 unsigned Spacing;
9301 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9302 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9303 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9304 Spacing));
9305 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9306 Spacing * 2));
9307 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9308 Spacing * 3));
9309 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9310 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9311 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9312 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9313 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9314 TmpInst.addOperand(Inst.getOperand(4));
9315 Inst = TmpInst;
9316 return true;
9317 }
9318
9319 case ARM::VLD4dWB_register_Asm_8:
9320 case ARM::VLD4dWB_register_Asm_16:
9321 case ARM::VLD4dWB_register_Asm_32:
9322 case ARM::VLD4qWB_register_Asm_8:
9323 case ARM::VLD4qWB_register_Asm_16:
9324 case ARM::VLD4qWB_register_Asm_32: {
9325 MCInst TmpInst;
9326 unsigned Spacing;
9327 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9328 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9329 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9330 Spacing));
9331 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9332 Spacing * 2));
9333 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9334 Spacing * 3));
9335 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9336 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9337 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9338 TmpInst.addOperand(Inst.getOperand(3)); // Rm
9339 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9340 TmpInst.addOperand(Inst.getOperand(5));
9341 Inst = TmpInst;
9342 return true;
9343 }
9344
9345 // VST3 multiple 3-element structure instructions.
9346 case ARM::VST3dAsm_8:
9347 case ARM::VST3dAsm_16:
9348 case ARM::VST3dAsm_32:
9349 case ARM::VST3qAsm_8:
9350 case ARM::VST3qAsm_16:
9351 case ARM::VST3qAsm_32: {
9352 MCInst TmpInst;
9353 unsigned Spacing;
9354 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9355 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9356 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9357 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9358 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9359 Spacing));
9360 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9361 Spacing * 2));
9362 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9363 TmpInst.addOperand(Inst.getOperand(4));
9364 Inst = TmpInst;
9365 return true;
9366 }
9367
9368 case ARM::VST3dWB_fixed_Asm_8:
9369 case ARM::VST3dWB_fixed_Asm_16:
9370 case ARM::VST3dWB_fixed_Asm_32:
9371 case ARM::VST3qWB_fixed_Asm_8:
9372 case ARM::VST3qWB_fixed_Asm_16:
9373 case ARM::VST3qWB_fixed_Asm_32: {
9374 MCInst TmpInst;
9375 unsigned Spacing;
9376 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9377 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9378 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9379 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9380 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9381 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9382 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9383 Spacing));
9384 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9385 Spacing * 2));
9386 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9387 TmpInst.addOperand(Inst.getOperand(4));
9388 Inst = TmpInst;
9389 return true;
9390 }
9391
9392 case ARM::VST3dWB_register_Asm_8:
9393 case ARM::VST3dWB_register_Asm_16:
9394 case ARM::VST3dWB_register_Asm_32:
9395 case ARM::VST3qWB_register_Asm_8:
9396 case ARM::VST3qWB_register_Asm_16:
9397 case ARM::VST3qWB_register_Asm_32: {
9398 MCInst TmpInst;
9399 unsigned Spacing;
9400 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9401 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9402 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9403 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9404 TmpInst.addOperand(Inst.getOperand(3)); // Rm
9405 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9406 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9407 Spacing));
9408 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9409 Spacing * 2));
9410 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9411 TmpInst.addOperand(Inst.getOperand(5));
9412 Inst = TmpInst;
9413 return true;
9414 }
9415
9416 // VST4 multiple 3-element structure instructions.
9417 case ARM::VST4dAsm_8:
9418 case ARM::VST4dAsm_16:
9419 case ARM::VST4dAsm_32:
9420 case ARM::VST4qAsm_8:
9421 case ARM::VST4qAsm_16:
9422 case ARM::VST4qAsm_32: {
9423 MCInst TmpInst;
9424 unsigned Spacing;
9425 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9426 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9427 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9428 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9429 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9430 Spacing));
9431 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9432 Spacing * 2));
9433 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9434 Spacing * 3));
9435 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9436 TmpInst.addOperand(Inst.getOperand(4));
9437 Inst = TmpInst;
9438 return true;
9439 }
9440
9441 case ARM::VST4dWB_fixed_Asm_8:
9442 case ARM::VST4dWB_fixed_Asm_16:
9443 case ARM::VST4dWB_fixed_Asm_32:
9444 case ARM::VST4qWB_fixed_Asm_8:
9445 case ARM::VST4qWB_fixed_Asm_16:
9446 case ARM::VST4qWB_fixed_Asm_32: {
9447 MCInst TmpInst;
9448 unsigned Spacing;
9449 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9450 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9451 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9452 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9453 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9454 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9455 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9456 Spacing));
9457 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9458 Spacing * 2));
9459 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9460 Spacing * 3));
9461 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9462 TmpInst.addOperand(Inst.getOperand(4));
9463 Inst = TmpInst;
9464 return true;
9465 }
9466
9467 case ARM::VST4dWB_register_Asm_8:
9468 case ARM::VST4dWB_register_Asm_16:
9469 case ARM::VST4dWB_register_Asm_32:
9470 case ARM::VST4qWB_register_Asm_8:
9471 case ARM::VST4qWB_register_Asm_16:
9472 case ARM::VST4qWB_register_Asm_32: {
9473 MCInst TmpInst;
9474 unsigned Spacing;
9475 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9476 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9477 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9478 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9479 TmpInst.addOperand(Inst.getOperand(3)); // Rm
9480 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9481 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9482 Spacing));
9483 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9484 Spacing * 2));
9485 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9486 Spacing * 3));
9487 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9488 TmpInst.addOperand(Inst.getOperand(5));
9489 Inst = TmpInst;
9490 return true;
9491 }
9492
9493 // Handle encoding choice for the shift-immediate instructions.
9494 case ARM::t2LSLri:
9495 case ARM::t2LSRri:
9496 case ARM::t2ASRri:
9497 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
9498 isARMLowRegister(Inst.getOperand(1).getReg()) &&
9499 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
9500 !HasWideQualifier) {
9501 unsigned NewOpc;
9502 switch (Inst.getOpcode()) {
9503 default: llvm_unreachable("unexpected opcode")::llvm::llvm_unreachable_internal("unexpected opcode", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 9503)
;
9504 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
9505 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
9506 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
9507 }
9508 // The Thumb1 operands aren't in the same order. Awesome, eh?
9509 MCInst TmpInst;
9510 TmpInst.setOpcode(NewOpc);
9511 TmpInst.addOperand(Inst.getOperand(0));
9512 TmpInst.addOperand(Inst.getOperand(5));
9513 TmpInst.addOperand(Inst.getOperand(1));
9514 TmpInst.addOperand(Inst.getOperand(2));
9515 TmpInst.addOperand(Inst.getOperand(3));
9516 TmpInst.addOperand(Inst.getOperand(4));
9517 Inst = TmpInst;
9518 return true;
9519 }
9520 return false;
9521
9522 // Handle the Thumb2 mode MOV complex aliases.
9523 case ARM::t2MOVsr:
9524 case ARM::t2MOVSsr: {
9525 // Which instruction to expand to depends on the CCOut operand and
9526 // whether we're in an IT block if the register operands are low
9527 // registers.
9528 bool isNarrow = false;
9529 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
9530 isARMLowRegister(Inst.getOperand(1).getReg()) &&
9531 isARMLowRegister(Inst.getOperand(2).getReg()) &&
9532 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
9533 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr) &&
9534 !HasWideQualifier)
9535 isNarrow = true;
9536 MCInst TmpInst;
9537 unsigned newOpc;
9538 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
9539 default: llvm_unreachable("unexpected opcode!")::llvm::llvm_unreachable_internal("unexpected opcode!", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 9539)
;
9540 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
9541 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
9542 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
9543 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
9544 }
9545 TmpInst.setOpcode(newOpc);
9546 TmpInst.addOperand(Inst.getOperand(0)); // Rd
9547 if (isNarrow)
9548 TmpInst.addOperand(MCOperand::createReg(
9549 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
9550 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9551 TmpInst.addOperand(Inst.getOperand(2)); // Rm
9552 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9553 TmpInst.addOperand(Inst.getOperand(5));
9554 if (!isNarrow)
9555 TmpInst.addOperand(MCOperand::createReg(
9556 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
9557 Inst = TmpInst;
9558 return true;
9559 }
9560 case ARM::t2MOVsi:
9561 case ARM::t2MOVSsi: {
9562 // Which instruction to expand to depends on the CCOut operand and
9563 // whether we're in an IT block if the register operands are low
9564 // registers.
9565 bool isNarrow = false;
9566 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
9567 isARMLowRegister(Inst.getOperand(1).getReg()) &&
9568 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi) &&
9569 !HasWideQualifier)
9570 isNarrow = true;
9571 MCInst TmpInst;
9572 unsigned newOpc;
9573 unsigned Shift = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
9574 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
9575 bool isMov = false;
9576 // MOV rd, rm, LSL #0 is actually a MOV instruction
9577 if (Shift == ARM_AM::lsl && Amount == 0) {
9578 isMov = true;
9579 // The 16-bit encoding of MOV rd, rm, LSL #N is explicitly encoding T2 of
9580 // MOV (register) in the ARMv8-A and ARMv8-M manuals, and immediate 0 is
9581 // unpredictable in an IT block so the 32-bit encoding T3 has to be used
9582 // instead.
9583 if (inITBlock()) {
9584 isNarrow = false;
9585 }
9586 newOpc = isNarrow ? ARM::tMOVSr : ARM::t2MOVr;
9587 } else {
9588 switch(Shift) {
9589 default: llvm_unreachable("unexpected opcode!")::llvm::llvm_unreachable_internal("unexpected opcode!", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 9589)
;
9590 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
9591 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
9592 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
9593 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
9594 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
9595 }
9596 }
9597 if (Amount == 32) Amount = 0;
9598 TmpInst.setOpcode(newOpc);
9599 TmpInst.addOperand(Inst.getOperand(0)); // Rd
9600 if (isNarrow && !isMov)
9601 TmpInst.addOperand(MCOperand::createReg(
9602 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
9603 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9604 if (newOpc != ARM::t2RRX && !isMov)
9605 TmpInst.addOperand(MCOperand::createImm(Amount));
9606 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9607 TmpInst.addOperand(Inst.getOperand(4));
9608 if (!isNarrow)
9609 TmpInst.addOperand(MCOperand::createReg(
9610 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
9611 Inst = TmpInst;
9612 return true;
9613 }
9614 // Handle the ARM mode MOV complex aliases.
9615 case ARM::ASRr:
9616 case ARM::LSRr:
9617 case ARM::LSLr:
9618 case ARM::RORr: {
9619 ARM_AM::ShiftOpc ShiftTy;
9620 switch(Inst.getOpcode()) {
9621 default: llvm_unreachable("unexpected opcode!")::llvm::llvm_unreachable_internal("unexpected opcode!", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 9621)
;
9622 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
9623 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
9624 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
9625 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
9626 }
9627 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
9628 MCInst TmpInst;
9629 TmpInst.setOpcode(ARM::MOVsr);
9630 TmpInst.addOperand(Inst.getOperand(0)); // Rd
9631 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9632 TmpInst.addOperand(Inst.getOperand(2)); // Rm
9633 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
9634 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9635 TmpInst.addOperand(Inst.getOperand(4));
9636 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
9637 Inst = TmpInst;
9638 return true;
9639 }
9640 case ARM::ASRi:
9641 case ARM::LSRi:
9642 case ARM::LSLi:
9643 case ARM::RORi: {
9644 ARM_AM::ShiftOpc ShiftTy;
9645 switch(Inst.getOpcode()) {
9646 default: llvm_unreachable("unexpected opcode!")::llvm::llvm_unreachable_internal("unexpected opcode!", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 9646)
;
9647 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
9648 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
9649 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
9650 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
9651 }
9652 // A shift by zero is a plain MOVr, not a MOVsi.
9653 unsigned Amt = Inst.getOperand(2).getImm();
9654 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
9655 // A shift by 32 should be encoded as 0 when permitted
9656 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
9657 Amt = 0;
9658 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
9659 MCInst TmpInst;
9660 TmpInst.setOpcode(Opc);
9661 TmpInst.addOperand(Inst.getOperand(0)); // Rd
9662 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9663 if (Opc == ARM::MOVsi)
9664 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
9665 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9666 TmpInst.addOperand(Inst.getOperand(4));
9667 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
9668 Inst = TmpInst;
9669 return true;
9670 }
9671 case ARM::RRXi: {
9672 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
9673 MCInst TmpInst;
9674 TmpInst.setOpcode(ARM::MOVsi);
9675 TmpInst.addOperand(Inst.getOperand(0)); // Rd
9676 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9677 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
9678 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
9679 TmpInst.addOperand(Inst.getOperand(3));
9680 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
9681 Inst = TmpInst;
9682 return true;
9683 }
9684 case ARM::t2LDMIA_UPD: {
9685 // If this is a load of a single register, then we should use
9686 // a post-indexed LDR instruction instead, per the ARM ARM.
9687 if (Inst.getNumOperands() != 5)
9688 return false;
9689 MCInst TmpInst;
9690 TmpInst.setOpcode(ARM::t2LDR_POST);
9691 TmpInst.addOperand(Inst.getOperand(4)); // Rt
9692 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
9693 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9694 TmpInst.addOperand(MCOperand::createImm(4));
9695 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
9696 TmpInst.addOperand(Inst.getOperand(3));
9697 Inst = TmpInst;
9698 return true;
9699 }
9700 case ARM::t2STMDB_UPD: {
9701 // If this is a store of a single register, then we should use
9702 // a pre-indexed STR instruction instead, per the ARM ARM.
9703 if (Inst.getNumOperands() != 5)
9704 return false;
9705 MCInst TmpInst;
9706 TmpInst.setOpcode(ARM::t2STR_PRE);
9707 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
9708 TmpInst.addOperand(Inst.getOperand(4)); // Rt
9709 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9710 TmpInst.addOperand(MCOperand::createImm(-4));
9711 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
9712 TmpInst.addOperand(Inst.getOperand(3));
9713 Inst = TmpInst;
9714 return true;
9715 }
9716 case ARM::LDMIA_UPD:
9717 // If this is a load of a single register via a 'pop', then we should use
9718 // a post-indexed LDR instruction instead, per the ARM ARM.
9719 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
9720 Inst.getNumOperands() == 5) {
9721 MCInst TmpInst;
9722 TmpInst.setOpcode(ARM::LDR_POST_IMM);
9723 TmpInst.addOperand(Inst.getOperand(4)); // Rt
9724 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
9725 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9726 TmpInst.addOperand(MCOperand::createReg(0)); // am2offset
9727 TmpInst.addOperand(MCOperand::createImm(4));
9728 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
9729 TmpInst.addOperand(Inst.getOperand(3));
9730 Inst = TmpInst;
9731 return true;
9732 }
9733 break;
9734 case ARM::STMDB_UPD:
9735 // If this is a store of a single register via a 'push', then we should use
9736 // a pre-indexed STR instruction instead, per the ARM ARM.
9737 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
9738 Inst.getNumOperands() == 5) {
9739 MCInst TmpInst;
9740 TmpInst.setOpcode(ARM::STR_PRE_IMM);
9741 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
9742 TmpInst.addOperand(Inst.getOperand(4)); // Rt
9743 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
9744 TmpInst.addOperand(MCOperand::createImm(-4));
9745 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
9746 TmpInst.addOperand(Inst.getOperand(3));
9747 Inst = TmpInst;
9748 }
9749 break;
9750 case ARM::t2ADDri12:
9751 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
9752 // mnemonic was used (not "addw"), encoding T3 is preferred.
9753 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
9754 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
9755 break;
9756 Inst.setOpcode(ARM::t2ADDri);
9757 Inst.addOperand(MCOperand::createReg(0)); // cc_out
9758 break;
9759 case ARM::t2SUBri12:
9760 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
9761 // mnemonic was used (not "subw"), encoding T3 is preferred.
9762 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
9763 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
9764 break;
9765 Inst.setOpcode(ARM::t2SUBri);
9766 Inst.addOperand(MCOperand::createReg(0)); // cc_out
9767 break;
9768 case ARM::tADDi8:
9769 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
9770 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
9771 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
9772 // to encoding T1 if <Rd> is omitted."
9773 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
9774 Inst.setOpcode(ARM::tADDi3);
9775 return true;
9776 }
9777 break;
9778 case ARM::tSUBi8:
9779 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
9780 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
9781 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
9782 // to encoding T1 if <Rd> is omitted."
9783 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
9784 Inst.setOpcode(ARM::tSUBi3);
9785 return true;
9786 }
9787 break;
9788 case ARM::t2ADDri:
9789 case ARM::t2SUBri: {
9790 // If the destination and first source operand are the same, and
9791 // the flags are compatible with the current IT status, use encoding T2
9792 // instead of T3. For compatibility with the system 'as'. Make sure the
9793 // wide encoding wasn't explicit.
9794 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
9795 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
9796 (Inst.getOperand(2).isImm() &&
9797 (unsigned)Inst.getOperand(2).getImm() > 255) ||
9798 Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) ||
9799 HasWideQualifier)
9800 break;
9801 MCInst TmpInst;
9802 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
9803 ARM::tADDi8 : ARM::tSUBi8);
9804 TmpInst.addOperand(Inst.getOperand(0));
9805 TmpInst.addOperand(Inst.getOperand(5));
9806 TmpInst.addOperand(Inst.getOperand(0));
9807 TmpInst.addOperand(Inst.getOperand(2));
9808 TmpInst.addOperand(Inst.getOperand(3));
9809 TmpInst.addOperand(Inst.getOperand(4));
9810 Inst = TmpInst;
9811 return true;
9812 }
9813 case ARM::t2ADDrr: {
9814 // If the destination and first source operand are the same, and
9815 // there's no setting of the flags, use encoding T2 instead of T3.
9816 // Note that this is only for ADD, not SUB. This mirrors the system
9817 // 'as' behaviour. Also take advantage of ADD being commutative.
9818 // Make sure the wide encoding wasn't explicit.
9819 bool Swap = false;
9820 auto DestReg = Inst.getOperand(0).getReg();
9821 bool Transform = DestReg == Inst.getOperand(1).getReg();
9822 if (!Transform && DestReg == Inst.getOperand(2).getReg()) {
9823 Transform = true;
9824 Swap = true;
9825 }
9826 if (!Transform ||
9827 Inst.getOperand(5).getReg() != 0 ||
9828 HasWideQualifier)
9829 break;
9830 MCInst TmpInst;
9831 TmpInst.setOpcode(ARM::tADDhirr);
9832 TmpInst.addOperand(Inst.getOperand(0));
9833 TmpInst.addOperand(Inst.getOperand(0));
9834 TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2));
9835 TmpInst.addOperand(Inst.getOperand(3));
9836 TmpInst.addOperand(Inst.getOperand(4));
9837 Inst = TmpInst;
9838 return true;
9839 }
9840 case ARM::tADDrSP:
9841 // If the non-SP source operand and the destination operand are not the
9842 // same, we need to use the 32-bit encoding if it's available.
9843 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
9844 Inst.setOpcode(ARM::t2ADDrr);
9845 Inst.addOperand(MCOperand::createReg(0)); // cc_out
9846 return true;
9847 }
9848 break;
9849 case ARM::tB:
9850 // A Thumb conditional branch outside of an IT block is a tBcc.
9851 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
9852 Inst.setOpcode(ARM::tBcc);
9853 return true;
9854 }
9855 break;
9856 case ARM::t2B:
9857 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
9858 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
9859 Inst.setOpcode(ARM::t2Bcc);
9860 return true;
9861 }
9862 break;
9863 case ARM::t2Bcc:
9864 // If the conditional is AL or we're in an IT block, we really want t2B.
9865 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
9866 Inst.setOpcode(ARM::t2B);
9867 return true;
9868 }
9869 break;
9870 case ARM::tBcc:
9871 // If the conditional is AL, we really want tB.
9872 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
9873 Inst.setOpcode(ARM::tB);
9874 return true;
9875 }
9876 break;
9877 case ARM::tLDMIA: {
9878 // If the register list contains any high registers, or if the writeback
9879 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
9880 // instead if we're in Thumb2. Otherwise, this should have generated
9881 // an error in validateInstruction().
9882 unsigned Rn = Inst.getOperand(0).getReg();
9883 bool hasWritebackToken =
9884 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
9885 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
9886 bool listContainsBase;
9887 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
9888 (!listContainsBase && !hasWritebackToken) ||
9889 (listContainsBase && hasWritebackToken)) {
9890 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
9891 assert(isThumbTwo())((isThumbTwo()) ? static_cast<void> (0) : __assert_fail
("isThumbTwo()", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 9891, __PRETTY_FUNCTION__))
;
9892 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
9893 // If we're switching to the updating version, we need to insert
9894 // the writeback tied operand.
9895 if (hasWritebackToken)
9896 Inst.insert(Inst.begin(),
9897 MCOperand::createReg(Inst.getOperand(0).getReg()));
9898 return true;
9899 }
9900 break;
9901 }
9902 case ARM::tSTMIA_UPD: {
9903 // If the register list contains any high registers, we need to use
9904 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
9905 // should have generated an error in validateInstruction().
9906 unsigned Rn = Inst.getOperand(0).getReg();
9907 bool listContainsBase;
9908 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
9909 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
9910 assert(isThumbTwo())((isThumbTwo()) ? static_cast<void> (0) : __assert_fail
("isThumbTwo()", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 9910, __PRETTY_FUNCTION__))
;
9911 Inst.setOpcode(ARM::t2STMIA_UPD);
9912 return true;
9913 }
9914 break;
9915 }
9916 case ARM::tPOP: {
9917 bool listContainsBase;
9918 // If the register list contains any high registers, we need to use
9919 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
9920 // should have generated an error in validateInstruction().
9921 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
9922 return false;
9923 assert(isThumbTwo())((isThumbTwo()) ? static_cast<void> (0) : __assert_fail
("isThumbTwo()", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 9923, __PRETTY_FUNCTION__))
;
9924 Inst.setOpcode(ARM::t2LDMIA_UPD);
9925 // Add the base register and writeback operands.
9926 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
9927 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
9928 return true;
9929 }
9930 case ARM::tPUSH: {
9931 bool listContainsBase;
9932 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
9933 return false;
9934 assert(isThumbTwo())((isThumbTwo()) ? static_cast<void> (0) : __assert_fail
("isThumbTwo()", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 9934, __PRETTY_FUNCTION__))
;
9935 Inst.setOpcode(ARM::t2STMDB_UPD);
9936 // Add the base register and writeback operands.
9937 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
9938 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
9939 return true;
9940 }
9941 case ARM::t2MOVi:
9942 // If we can use the 16-bit encoding and the user didn't explicitly
9943 // request the 32-bit variant, transform it here.
9944 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
9945 (Inst.getOperand(1).isImm() &&
9946 (unsigned)Inst.getOperand(1).getImm() <= 255) &&
9947 Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
9948 !HasWideQualifier) {
9949 // The operands aren't in the same order for tMOVi8...
9950 MCInst TmpInst;
9951 TmpInst.setOpcode(ARM::tMOVi8);
9952 TmpInst.addOperand(Inst.getOperand(0));
9953 TmpInst.addOperand(Inst.getOperand(4));
9954 TmpInst.addOperand(Inst.getOperand(1));
9955 TmpInst.addOperand(Inst.getOperand(2));
9956 TmpInst.addOperand(Inst.getOperand(3));
9957 Inst = TmpInst;
9958 return true;
9959 }
9960 break;
9961
9962 case ARM::t2MOVr:
9963 // If we can use the 16-bit encoding and the user didn't explicitly
9964 // request the 32-bit variant, transform it here.
9965 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
9966 isARMLowRegister(Inst.getOperand(1).getReg()) &&
9967 Inst.getOperand(2).getImm() == ARMCC::AL &&
9968 Inst.getOperand(4).getReg() == ARM::CPSR &&
9969 !HasWideQualifier) {
9970 // The operands aren't the same for tMOV[S]r... (no cc_out)
9971 MCInst TmpInst;
9972 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
9973 TmpInst.addOperand(Inst.getOperand(0));
9974 TmpInst.addOperand(Inst.getOperand(1));
9975 TmpInst.addOperand(Inst.getOperand(2));
9976 TmpInst.addOperand(Inst.getOperand(3));
9977 Inst = TmpInst;
9978 return true;
9979 }
9980 break;
9981
9982 case ARM::t2SXTH:
9983 case ARM::t2SXTB:
9984 case ARM::t2UXTH:
9985 case ARM::t2UXTB:
9986 // If we can use the 16-bit encoding and the user didn't explicitly
9987 // request the 32-bit variant, transform it here.
9988 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
9989 isARMLowRegister(Inst.getOperand(1).getReg()) &&
9990 Inst.getOperand(2).getImm() == 0 &&
9991 !HasWideQualifier) {
9992 unsigned NewOpc;
9993 switch (Inst.getOpcode()) {
9994 default: llvm_unreachable("Illegal opcode!")::llvm::llvm_unreachable_internal("Illegal opcode!", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 9994)
;
9995 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
9996 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
9997 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
9998 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
9999 }
10000 // The operands aren't the same for thumb1 (no rotate operand).
10001 MCInst TmpInst;
10002 TmpInst.setOpcode(NewOpc);
10003 TmpInst.addOperand(Inst.getOperand(0));
10004 TmpInst.addOperand(Inst.getOperand(1));
10005 TmpInst.addOperand(Inst.getOperand(3));
10006 TmpInst.addOperand(Inst.getOperand(4));
10007 Inst = TmpInst;
10008 return true;
10009 }
10010 break;
10011
10012 case ARM::MOVsi: {
10013 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
10014 // rrx shifts and asr/lsr of #32 is encoded as 0
10015 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
10016 return false;
10017 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
10018 // Shifting by zero is accepted as a vanilla 'MOVr'
10019 MCInst TmpInst;
10020 TmpInst.setOpcode(ARM::MOVr);
10021 TmpInst.addOperand(Inst.getOperand(0));
10022 TmpInst.addOperand(Inst.getOperand(1));
10023 TmpInst.addOperand(Inst.getOperand(3));
10024 TmpInst.addOperand(Inst.getOperand(4));
10025 TmpInst.addOperand(Inst.getOperand(5));
10026 Inst = TmpInst;
10027 return true;
10028 }
10029 return false;
10030 }
10031 case ARM::ANDrsi:
10032 case ARM::ORRrsi:
10033 case ARM::EORrsi:
10034 case ARM::BICrsi:
10035 case ARM::SUBrsi:
10036 case ARM::ADDrsi: {
10037 unsigned newOpc;
10038 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
10039 if (SOpc == ARM_AM::rrx) return false;
10040 switch (Inst.getOpcode()) {
10041 default: llvm_unreachable("unexpected opcode!")::llvm::llvm_unreachable_internal("unexpected opcode!", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10041)
;
10042 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
10043 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
10044 case ARM::EORrsi: newOpc = ARM::EORrr; break;
10045 case ARM::BICrsi: newOpc = ARM::BICrr; break;
10046 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
10047 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
10048 }
10049 // If the shift is by zero, use the non-shifted instruction definition.
10050 // The exception is for right shifts, where 0 == 32
10051 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
10052 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
10053 MCInst TmpInst;
10054 TmpInst.setOpcode(newOpc);
10055 TmpInst.addOperand(Inst.getOperand(0));
10056 TmpInst.addOperand(Inst.getOperand(1));
10057 TmpInst.addOperand(Inst.getOperand(2));
10058 TmpInst.addOperand(Inst.getOperand(4));
10059 TmpInst.addOperand(Inst.getOperand(5));
10060 TmpInst.addOperand(Inst.getOperand(6));
10061 Inst = TmpInst;
10062 return true;
10063 }
10064 return false;
10065 }
10066 case ARM::ITasm:
10067 case ARM::t2IT: {
10068 // Set up the IT block state according to the IT instruction we just
10069 // matched.
10070 assert(!inITBlock() && "nested IT blocks?!")((!inITBlock() && "nested IT blocks?!") ? static_cast
<void> (0) : __assert_fail ("!inITBlock() && \"nested IT blocks?!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10070, __PRETTY_FUNCTION__))
;
10071 startExplicitITBlock(ARMCC::CondCodes(Inst.getOperand(0).getImm()),
10072 Inst.getOperand(1).getImm());
10073 break;
10074 }
10075 case ARM::t2LSLrr:
10076 case ARM::t2LSRrr:
10077 case ARM::t2ASRrr:
10078 case ARM::t2SBCrr:
10079 case ARM::t2RORrr:
10080 case ARM::t2BICrr:
10081 // Assemblers should use the narrow encodings of these instructions when permissible.
10082 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
10083 isARMLowRegister(Inst.getOperand(2).getReg())) &&
10084 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
10085 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
10086 !HasWideQualifier) {
10087 unsigned NewOpc;
10088 switch (Inst.getOpcode()) {
10089 default: llvm_unreachable("unexpected opcode")::llvm::llvm_unreachable_internal("unexpected opcode", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10089)
;
10090 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
10091 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
10092 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
10093 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
10094 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
10095 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
10096 }
10097 MCInst TmpInst;
10098 TmpInst.setOpcode(NewOpc);
10099 TmpInst.addOperand(Inst.getOperand(0));
10100 TmpInst.addOperand(Inst.getOperand(5));
10101 TmpInst.addOperand(Inst.getOperand(1));
10102 TmpInst.addOperand(Inst.getOperand(2));
10103 TmpInst.addOperand(Inst.getOperand(3));
10104 TmpInst.addOperand(Inst.getOperand(4));
10105 Inst = TmpInst;
10106 return true;
10107 }
10108 return false;
10109
10110 case ARM::t2ANDrr:
10111 case ARM::t2EORrr:
10112 case ARM::t2ADCrr:
10113 case ARM::t2ORRrr:
10114 // Assemblers should use the narrow encodings of these instructions when permissible.
10115 // These instructions are special in that they are commutable, so shorter encodings
10116 // are available more often.
10117 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
10118 isARMLowRegister(Inst.getOperand(2).getReg())) &&
10119 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
10120 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
10121 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
10122 !HasWideQualifier) {
10123 unsigned NewOpc;
10124 switch (Inst.getOpcode()) {
10125 default: llvm_unreachable("unexpected opcode")::llvm::llvm_unreachable_internal("unexpected opcode", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10125)
;
10126 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
10127 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
10128 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
10129 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
10130 }
10131 MCInst TmpInst;
10132 TmpInst.setOpcode(NewOpc);
10133 TmpInst.addOperand(Inst.getOperand(0));
10134 TmpInst.addOperand(Inst.getOperand(5));
10135 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
10136 TmpInst.addOperand(Inst.getOperand(1));
10137 TmpInst.addOperand(Inst.getOperand(2));
10138 } else {
10139 TmpInst.addOperand(Inst.getOperand(2));
10140 TmpInst.addOperand(Inst.getOperand(1));
10141 }
10142 TmpInst.addOperand(Inst.getOperand(3));
10143 TmpInst.addOperand(Inst.getOperand(4));
10144 Inst = TmpInst;
10145 return true;
10146 }
10147 return false;
10148 case ARM::MVE_VPST:
10149 case ARM::MVE_VPTv16i8:
10150 case ARM::MVE_VPTv8i16:
10151 case ARM::MVE_VPTv4i32:
10152 case ARM::MVE_VPTv16u8:
10153 case ARM::MVE_VPTv8u16:
10154 case ARM::MVE_VPTv4u32:
10155 case ARM::MVE_VPTv16s8:
10156 case ARM::MVE_VPTv8s16:
10157 case ARM::MVE_VPTv4s32:
10158 case ARM::MVE_VPTv4f32:
10159 case ARM::MVE_VPTv8f16:
10160 case ARM::MVE_VPTv16i8r:
10161 case ARM::MVE_VPTv8i16r:
10162 case ARM::MVE_VPTv4i32r:
10163 case ARM::MVE_VPTv16u8r:
10164 case ARM::MVE_VPTv8u16r:
10165 case ARM::MVE_VPTv4u32r:
10166 case ARM::MVE_VPTv16s8r:
10167 case ARM::MVE_VPTv8s16r:
10168 case ARM::MVE_VPTv4s32r:
10169 case ARM::MVE_VPTv4f32r:
10170 case ARM::MVE_VPTv8f16r: {
10171 assert(!inVPTBlock() && "Nested VPT blocks are not allowed")((!inVPTBlock() && "Nested VPT blocks are not allowed"
) ? static_cast<void> (0) : __assert_fail ("!inVPTBlock() && \"Nested VPT blocks are not allowed\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10171, __PRETTY_FUNCTION__))
;
10172 MCOperand &MO = Inst.getOperand(0);
10173 VPTState.Mask = MO.getImm();
10174 VPTState.CurPosition = 0;
10175 break;
10176 }
10177 }
10178 return false;
10179}
10180
10181unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
10182 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
10183 // suffix depending on whether they're in an IT block or not.
10184 unsigned Opc = Inst.getOpcode();
10185 const MCInstrDesc &MCID = MII.get(Opc);
10186 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
10187 assert(MCID.hasOptionalDef() &&((MCID.hasOptionalDef() && "optionally flag setting instruction missing optional def operand"
) ? static_cast<void> (0) : __assert_fail ("MCID.hasOptionalDef() && \"optionally flag setting instruction missing optional def operand\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10188, __PRETTY_FUNCTION__))
10188 "optionally flag setting instruction missing optional def operand")((MCID.hasOptionalDef() && "optionally flag setting instruction missing optional def operand"
) ? static_cast<void> (0) : __assert_fail ("MCID.hasOptionalDef() && \"optionally flag setting instruction missing optional def operand\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10188, __PRETTY_FUNCTION__))
;
10189 assert(MCID.NumOperands == Inst.getNumOperands() &&((MCID.NumOperands == Inst.getNumOperands() && "operand count mismatch!"
) ? static_cast<void> (0) : __assert_fail ("MCID.NumOperands == Inst.getNumOperands() && \"operand count mismatch!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10190, __PRETTY_FUNCTION__))
10190 "operand count mismatch!")((MCID.NumOperands == Inst.getNumOperands() && "operand count mismatch!"
) ? static_cast<void> (0) : __assert_fail ("MCID.NumOperands == Inst.getNumOperands() && \"operand count mismatch!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10190, __PRETTY_FUNCTION__))
;
10191 // Find the optional-def operand (cc_out).
10192 unsigned OpNo;
10193 for (OpNo = 0;
10194 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
10195 ++OpNo)
10196 ;
10197 // If we're parsing Thumb1, reject it completely.
10198 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
10199 return Match_RequiresFlagSetting;
10200 // If we're parsing Thumb2, which form is legal depends on whether we're
10201 // in an IT block.
10202 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
10203 !inITBlock())
10204 return Match_RequiresITBlock;
10205 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
10206 inITBlock())
10207 return Match_RequiresNotITBlock;
10208 // LSL with zero immediate is not allowed in an IT block
10209 if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock())
10210 return Match_RequiresNotITBlock;
10211 } else if (isThumbOne()) {
10212 // Some high-register supporting Thumb1 encodings only allow both registers
10213 // to be from r0-r7 when in Thumb2.
10214 if (Opc == ARM::tADDhirr && !hasV6MOps() &&
10215 isARMLowRegister(Inst.getOperand(1).getReg()) &&
10216 isARMLowRegister(Inst.getOperand(2).getReg()))
10217 return Match_RequiresThumb2;
10218 // Others only require ARMv6 or later.
10219 else if (Opc == ARM::tMOVr && !hasV6Ops() &&
10220 isARMLowRegister(Inst.getOperand(0).getReg()) &&
10221 isARMLowRegister(Inst.getOperand(1).getReg()))
10222 return Match_RequiresV6;
10223 }
10224
10225 // Before ARMv8 the rules for when SP is allowed in t2MOVr are more complex
10226 // than the loop below can handle, so it uses the GPRnopc register class and
10227 // we do SP handling here.
10228 if (Opc == ARM::t2MOVr && !hasV8Ops())
10229 {
10230 // SP as both source and destination is not allowed
10231 if (Inst.getOperand(0).getReg() == ARM::SP &&
10232 Inst.getOperand(1).getReg() == ARM::SP)
10233 return Match_RequiresV8;
10234 // When flags-setting SP as either source or destination is not allowed
10235 if (Inst.getOperand(4).getReg() == ARM::CPSR &&
10236 (Inst.getOperand(0).getReg() == ARM::SP ||
10237 Inst.getOperand(1).getReg() == ARM::SP))
10238 return Match_RequiresV8;
10239 }
10240
10241 switch (Inst.getOpcode()) {
10242 case ARM::VMRS:
10243 case ARM::VMSR:
10244 case ARM::VMRS_FPCXTS:
10245 case ARM::VMRS_FPCXTNS:
10246 case ARM::VMSR_FPCXTS:
10247 case ARM::VMSR_FPCXTNS:
10248 case ARM::VMRS_FPSCR_NZCVQC:
10249 case ARM::VMSR_FPSCR_NZCVQC:
10250 case ARM::FMSTAT:
10251 case ARM::VMRS_VPR:
10252 case ARM::VMRS_P0:
10253 case ARM::VMSR_VPR:
10254 case ARM::VMSR_P0:
10255 // Use of SP for VMRS/VMSR is only allowed in ARM mode with the exception of
10256 // ARMv8-A.
10257 if (Inst.getOperand(0).isReg() && Inst.getOperand(0).getReg() == ARM::SP &&
10258 (isThumb() && !hasV8Ops()))
10259 return Match_InvalidOperand;
10260 break;
10261 default:
10262 break;
10263 }
10264
10265 for (unsigned I = 0; I < MCID.NumOperands; ++I)
10266 if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
10267 // rGPRRegClass excludes PC, and also excluded SP before ARMv8
10268 const auto &Op = Inst.getOperand(I);
10269 if (!Op.isReg()) {
10270 // This can happen in awkward cases with tied operands, e.g. a
10271 // writeback load/store with a complex addressing mode in
10272 // which there's an output operand corresponding to the
10273 // updated written-back base register: the Tablegen-generated
10274 // AsmMatcher will have written a placeholder operand to that
10275 // slot in the form of an immediate 0, because it can't
10276 // generate the register part of the complex addressing-mode
10277 // operand ahead of time.
10278 continue;
10279 }
10280
10281 unsigned Reg = Op.getReg();
10282 if ((Reg == ARM::SP) && !hasV8Ops())
10283 return Match_RequiresV8;
10284 else if (Reg == ARM::PC)
10285 return Match_InvalidOperand;
10286 }
10287
10288 return Match_Success;
10289}
10290
10291namespace llvm {
10292
10293template <> inline bool IsCPSRDead<MCInst>(const MCInst *Instr) {
10294 return true; // In an assembly source, no need to second-guess
10295}
10296
10297} // end namespace llvm
10298
10299// Returns true if Inst is unpredictable if it is in and IT block, but is not
10300// the last instruction in the block.
10301bool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const {
10302 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10303
10304 // All branch & call instructions terminate IT blocks with the exception of
10305 // SVC.
10306 if (MCID.isTerminator() || (MCID.isCall() && Inst.getOpcode() != ARM::tSVC) ||
10307 MCID.isReturn() || MCID.isBranch() || MCID.isIndirectBranch())
10308 return true;
10309
10310 // Any arithmetic instruction which writes to the PC also terminates the IT
10311 // block.
10312 if (MCID.hasDefOfPhysReg(Inst, ARM::PC, *MRI))
10313 return true;
10314
10315 return false;
10316}
10317
10318unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst,
10319 SmallVectorImpl<NearMissInfo> &NearMisses,
10320 bool MatchingInlineAsm,
10321 bool &EmitInITBlock,
10322 MCStreamer &Out) {
10323 // If we can't use an implicit IT block here, just match as normal.
10324 if (inExplicitITBlock() || !isThumbTwo() || !useImplicitITThumb())
10325 return MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm);
10326
10327 // Try to match the instruction in an extension of the current IT block (if
10328 // there is one).
10329 if (inImplicitITBlock()) {
10330 extendImplicitITBlock(ITState.Cond);
10331 if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) ==
10332 Match_Success) {
10333 // The match succeded, but we still have to check that the instruction is
10334 // valid in this implicit IT block.
10335 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10336 if (MCID.isPredicable()) {
10337 ARMCC::CondCodes InstCond =
10338 (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
10339 .getImm();
10340 ARMCC::CondCodes ITCond = currentITCond();
10341 if (InstCond == ITCond) {
10342 EmitInITBlock = true;
10343 return Match_Success;
10344 } else if (InstCond == ARMCC::getOppositeCondition(ITCond)) {
10345 invertCurrentITCondition();
10346 EmitInITBlock = true;
10347 return Match_Success;
10348 }
10349 }
10350 }
10351 rewindImplicitITPosition();
10352 }
10353
10354 // Finish the current IT block, and try to match outside any IT block.
10355 flushPendingInstructions(Out);
10356 unsigned PlainMatchResult =
10357 MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm);
10358 if (PlainMatchResult == Match_Success) {
10359 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10360 if (MCID.isPredicable()) {
10361 ARMCC::CondCodes InstCond =
10362 (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
10363 .getImm();
10364 // Some forms of the branch instruction have their own condition code
10365 // fields, so can be conditionally executed without an IT block.
10366 if (Inst.getOpcode() == ARM::tBcc || Inst.getOpcode() == ARM::t2Bcc) {
10367 EmitInITBlock = false;
10368 return Match_Success;
10369 }
10370 if (InstCond == ARMCC::AL) {
10371 EmitInITBlock = false;
10372 return Match_Success;
10373 }
10374 } else {
10375 EmitInITBlock = false;
10376 return Match_Success;
10377 }
10378 }
10379
10380 // Try to match in a new IT block. The matcher doesn't check the actual
10381 // condition, so we create an IT block with a dummy condition, and fix it up
10382 // once we know the actual condition.
10383 startImplicitITBlock();
10384 if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) ==
10385 Match_Success) {
10386 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10387 if (MCID.isPredicable()) {
10388 ITState.Cond =
10389 (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
10390 .getImm();
10391 EmitInITBlock = true;
10392 return Match_Success;
10393 }
10394 }
10395 discardImplicitITBlock();
10396
10397 // If none of these succeed, return the error we got when trying to match
10398 // outside any IT blocks.
10399 EmitInITBlock = false;
10400 return PlainMatchResult;
10401}
10402
10403static std::string ARMMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS,
10404 unsigned VariantID = 0);
10405
10406static const char *getSubtargetFeatureName(uint64_t Val);
10407bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
10408 OperandVector &Operands,
10409 MCStreamer &Out, uint64_t &ErrorInfo,
10410 bool MatchingInlineAsm) {
10411 MCInst Inst;
10412 unsigned MatchResult;
10413 bool PendConditionalInstruction = false;
10414
10415 SmallVector<NearMissInfo, 4> NearMisses;
10416 MatchResult = MatchInstruction(Operands, Inst, NearMisses, MatchingInlineAsm,
10417 PendConditionalInstruction, Out);
10418
10419 switch (MatchResult) {
10420 case Match_Success:
10421 LLVM_DEBUG(dbgs() << "Parsed as: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("asm-parser")) { dbgs() << "Parsed as: "; Inst.dump_pretty
(dbgs(), MII.getName(Inst.getOpcode())); dbgs() << "\n"
; } } while (false)
10422 Inst.dump_pretty(dbgs(), MII.getName(Inst.getOpcode()));do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("asm-parser")) { dbgs() << "Parsed as: "; Inst.dump_pretty
(dbgs(), MII.getName(Inst.getOpcode())); dbgs() << "\n"
; } } while (false)
10423 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("asm-parser")) { dbgs() << "Parsed as: "; Inst.dump_pretty
(dbgs(), MII.getName(Inst.getOpcode())); dbgs() << "\n"
; } } while (false)
;
10424
10425 // Context sensitive operand constraints aren't handled by the matcher,
10426 // so check them here.
10427 if (validateInstruction(Inst, Operands)) {
10428 // Still progress the IT block, otherwise one wrong condition causes
10429 // nasty cascading errors.
10430 forwardITPosition();
10431 forwardVPTPosition();
10432 return true;
10433 }
10434
10435 { // processInstruction() updates inITBlock state, we need to save it away
10436 bool wasInITBlock = inITBlock();
10437
10438 // Some instructions need post-processing to, for example, tweak which
10439 // encoding is selected. Loop on it while changes happen so the
10440 // individual transformations can chain off each other. E.g.,
10441 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
10442 while (processInstruction(Inst, Operands, Out))
10443 LLVM_DEBUG(dbgs() << "Changed to: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("asm-parser")) { dbgs() << "Changed to: "; Inst.dump_pretty
(dbgs(), MII.getName(Inst.getOpcode())); dbgs() << "\n"
; } } while (false)
10444 Inst.dump_pretty(dbgs(), MII.getName(Inst.getOpcode()));do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("asm-parser")) { dbgs() << "Changed to: "; Inst.dump_pretty
(dbgs(), MII.getName(Inst.getOpcode())); dbgs() << "\n"
; } } while (false)
10445 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("asm-parser")) { dbgs() << "Changed to: "; Inst.dump_pretty
(dbgs(), MII.getName(Inst.getOpcode())); dbgs() << "\n"
; } } while (false)
;
10446
10447 // Only after the instruction is fully processed, we can validate it
10448 if (wasInITBlock && hasV8Ops() && isThumb() &&
10449 !isV8EligibleForIT(&Inst)) {
10450 Warning(IDLoc, "deprecated instruction in IT block");
10451 }
10452 }
10453
10454 // Only move forward at the very end so that everything in validate
10455 // and process gets a consistent answer about whether we're in an IT
10456 // block.
10457 forwardITPosition();
10458 forwardVPTPosition();
10459
10460 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
10461 // doesn't actually encode.
10462 if (Inst.getOpcode() == ARM::ITasm)
10463 return false;
10464
10465 Inst.setLoc(IDLoc);
10466 if (PendConditionalInstruction) {
10467 PendingConditionalInsts.push_back(Inst);
10468 if (isITBlockFull() || isITBlockTerminator(Inst))
10469 flushPendingInstructions(Out);
10470 } else {
10471 Out.EmitInstruction(Inst, getSTI());
10472 }
10473 return false;
10474 case Match_NearMisses:
10475 ReportNearMisses(NearMisses, IDLoc, Operands);
10476 return true;
10477 case Match_MnemonicFail: {
10478 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
10479 std::string Suggestion = ARMMnemonicSpellCheck(
10480 ((ARMOperand &)*Operands[0]).getToken(), FBS);
10481 return Error(IDLoc, "invalid instruction" + Suggestion,
10482 ((ARMOperand &)*Operands[0]).getLocRange());
10483 }
10484 }
10485
10486 llvm_unreachable("Implement any new match types added!")::llvm::llvm_unreachable_internal("Implement any new match types added!"
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10486)
;
10487}
10488
10489/// parseDirective parses the arm specific directives
10490bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
10491 const MCObjectFileInfo::Environment Format =
10492 getContext().getObjectFileInfo()->getObjectFileType();
10493 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
10494 bool IsCOFF = Format == MCObjectFileInfo::IsCOFF;
10495
10496 StringRef IDVal = DirectiveID.getIdentifier();
10497 if (IDVal == ".word")
10498 parseLiteralValues(4, DirectiveID.getLoc());
10499 else if (IDVal == ".short" || IDVal == ".hword")
10500 parseLiteralValues(2, DirectiveID.getLoc());
10501 else if (IDVal == ".thumb")
10502 parseDirectiveThumb(DirectiveID.getLoc());
10503 else if (IDVal == ".arm")
10504 parseDirectiveARM(DirectiveID.getLoc());
10505 else if (IDVal == ".thumb_func")
10506 parseDirectiveThumbFunc(DirectiveID.getLoc());
10507 else if (IDVal == ".code")
10508 parseDirectiveCode(DirectiveID.getLoc());
10509 else if (IDVal == ".syntax")
10510 parseDirectiveSyntax(DirectiveID.getLoc());
10511 else if (IDVal == ".unreq")
10512 parseDirectiveUnreq(DirectiveID.getLoc());
10513 else if (IDVal == ".fnend")
10514 parseDirectiveFnEnd(DirectiveID.getLoc());
10515 else if (IDVal == ".cantunwind")
10516 parseDirectiveCantUnwind(DirectiveID.getLoc());
10517 else if (IDVal == ".personality")
10518 parseDirectivePersonality(DirectiveID.getLoc());
10519 else if (IDVal == ".handlerdata")
10520 parseDirectiveHandlerData(DirectiveID.getLoc());
10521 else if (IDVal == ".setfp")
10522 parseDirectiveSetFP(DirectiveID.getLoc());
10523 else if (IDVal == ".pad")
10524 parseDirectivePad(DirectiveID.getLoc());
10525 else if (IDVal == ".save")
10526 parseDirectiveRegSave(DirectiveID.getLoc(), false);
10527 else if (IDVal == ".vsave")
10528 parseDirectiveRegSave(DirectiveID.getLoc(), true);
10529 else if (IDVal == ".ltorg" || IDVal == ".pool")
10530 parseDirectiveLtorg(DirectiveID.getLoc());
10531 else if (IDVal == ".even")
10532 parseDirectiveEven(DirectiveID.getLoc());
10533 else if (IDVal == ".personalityindex")
10534 parseDirectivePersonalityIndex(DirectiveID.getLoc());
10535 else if (IDVal == ".unwind_raw")
10536 parseDirectiveUnwindRaw(DirectiveID.getLoc());
10537 else if (IDVal == ".movsp")
10538 parseDirectiveMovSP(DirectiveID.getLoc());
10539 else if (IDVal == ".arch_extension")
10540 parseDirectiveArchExtension(DirectiveID.getLoc());
10541 else if (IDVal == ".align")
10542 return parseDirectiveAlign(DirectiveID.getLoc()); // Use Generic on failure.
10543 else if (IDVal == ".thumb_set")
10544 parseDirectiveThumbSet(DirectiveID.getLoc());
10545 else if (IDVal == ".inst")
10546 parseDirectiveInst(DirectiveID.getLoc());
10547 else if (IDVal == ".inst.n")
10548 parseDirectiveInst(DirectiveID.getLoc(), 'n');
10549 else if (IDVal == ".inst.w")
10550 parseDirectiveInst(DirectiveID.getLoc(), 'w');
10551 else if (!IsMachO && !IsCOFF) {
10552 if (IDVal == ".arch")
10553 parseDirectiveArch(DirectiveID.getLoc());
10554 else if (IDVal == ".cpu")
10555 parseDirectiveCPU(DirectiveID.getLoc());
10556 else if (IDVal == ".eabi_attribute")
10557 parseDirectiveEabiAttr(DirectiveID.getLoc());
10558 else if (IDVal == ".fpu")
10559 parseDirectiveFPU(DirectiveID.getLoc());
10560 else if (IDVal == ".fnstart")
10561 parseDirectiveFnStart(DirectiveID.getLoc());
10562 else if (IDVal == ".object_arch")
10563 parseDirectiveObjectArch(DirectiveID.getLoc());
10564 else if (IDVal == ".tlsdescseq")
10565 parseDirectiveTLSDescSeq(DirectiveID.getLoc());
10566 else
10567 return true;
10568 } else
10569 return true;
10570 return false;
10571}
10572
10573/// parseLiteralValues
10574/// ::= .hword expression [, expression]*
10575/// ::= .short expression [, expression]*
10576/// ::= .word expression [, expression]*
10577bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
10578 auto parseOne = [&]() -> bool {
10579 const MCExpr *Value;
10580 if (getParser().parseExpression(Value))
10581 return true;
10582 getParser().getStreamer().EmitValue(Value, Size, L);
10583 return false;
10584 };
10585 return (parseMany(parseOne));
10586}
10587
10588/// parseDirectiveThumb
10589/// ::= .thumb
10590bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
10591 if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive") ||
10592 check(!hasThumb(), L, "target does not support Thumb mode"))
10593 return true;
10594
10595 if (!isThumb())
10596 SwitchMode();
10597
10598 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
10599 return false;
10600}
10601
10602/// parseDirectiveARM
10603/// ::= .arm
10604bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
10605 if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive") ||
10606 check(!hasARM(), L, "target does not support ARM mode"))
10607 return true;
10608
10609 if (isThumb())
10610 SwitchMode();
10611 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
10612 return false;
10613}
10614
10615void ARMAsmParser::doBeforeLabelEmit(MCSymbol *Symbol) {
10616 // We need to flush the current implicit IT block on a label, because it is
10617 // not legal to branch into an IT block.
10618 flushPendingInstructions(getStreamer());
10619}
10620
10621void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
10622 if (NextSymbolIsThumb) {
10623 getParser().getStreamer().EmitThumbFunc(Symbol);
10624 NextSymbolIsThumb = false;
10625 }
10626}
10627
10628/// parseDirectiveThumbFunc
10629/// ::= .thumbfunc symbol_name
10630bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
10631 MCAsmParser &Parser = getParser();
10632 const auto Format = getContext().getObjectFileInfo()->getObjectFileType();
10633 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
10634
10635 // Darwin asm has (optionally) function name after .thumb_func direction
10636 // ELF doesn't
10637
10638 if (IsMachO) {
10639 if (Parser.getTok().is(AsmToken::Identifier) ||
10640 Parser.getTok().is(AsmToken::String)) {
10641 MCSymbol *Func = getParser().getContext().getOrCreateSymbol(
10642 Parser.getTok().getIdentifier());
10643 getParser().getStreamer().EmitThumbFunc(Func);
10644 Parser.Lex();
10645 if (parseToken(AsmToken::EndOfStatement,
10646 "unexpected token in '.thumb_func' directive"))
10647 return true;
10648 return false;
10649 }
10650 }
10651
10652 if (parseToken(AsmToken::EndOfStatement,
10653 "unexpected token in '.thumb_func' directive"))
10654 return true;
10655
10656 NextSymbolIsThumb = true;
10657 return false;
10658}
10659
10660/// parseDirectiveSyntax
10661/// ::= .syntax unified | divided
10662bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
10663 MCAsmParser &Parser = getParser();
10664 const AsmToken &Tok = Parser.getTok();
10665 if (Tok.isNot(AsmToken::Identifier)) {
10666 Error(L, "unexpected token in .syntax directive");
10667 return false;
10668 }
10669
10670 StringRef Mode = Tok.getString();
10671 Parser.Lex();
10672 if (check(Mode == "divided" || Mode == "DIVIDED", L,
10673 "'.syntax divided' arm assembly not supported") ||
10674 check(Mode != "unified" && Mode != "UNIFIED", L,
10675 "unrecognized syntax mode in .syntax directive") ||
10676 parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
10677 return true;
10678
10679 // TODO tell the MC streamer the mode
10680 // getParser().getStreamer().Emit???();
10681 return false;
10682}
10683
10684/// parseDirectiveCode
10685/// ::= .code 16 | 32
10686bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
10687 MCAsmParser &Parser = getParser();
10688 const AsmToken &Tok = Parser.getTok();
10689 if (Tok.isNot(AsmToken::Integer))
10690 return Error(L, "unexpected token in .code directive");
10691 int64_t Val = Parser.getTok().getIntVal();
10692 if (Val != 16 && Val != 32) {
10693 Error(L, "invalid operand to .code directive");
10694 return false;
10695 }
10696 Parser.Lex();
10697
10698 if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
10699 return true;
10700
10701 if (Val == 16) {
10702 if (!hasThumb())
10703 return Error(L, "target does not support Thumb mode");
10704
10705 if (!isThumb())
10706 SwitchMode();
10707 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
10708 } else {
10709 if (!hasARM())
10710 return Error(L, "target does not support ARM mode");
10711
10712 if (isThumb())
10713 SwitchMode();
10714 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
10715 }
10716
10717 return false;
10718}
10719
10720/// parseDirectiveReq
10721/// ::= name .req registername
10722bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
10723 MCAsmParser &Parser = getParser();
10724 Parser.Lex(); // Eat the '.req' token.
10725 unsigned Reg;
10726 SMLoc SRegLoc, ERegLoc;
10727 if (check(ParseRegister(Reg, SRegLoc, ERegLoc), SRegLoc,
10728 "register name expected") ||
10729 parseToken(AsmToken::EndOfStatement,
10730 "unexpected input in .req directive."))
10731 return true;
10732
10733 if (RegisterReqs.insert(std::make_pair(Name, Reg)).first->second != Reg)
10734 return Error(SRegLoc,
10735 "redefinition of '" + Name + "' does not match original.");
10736
10737 return false;
10738}
10739
10740/// parseDirectiveUneq
10741/// ::= .unreq registername
10742bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
10743 MCAsmParser &Parser = getParser();
10744 if (Parser.getTok().isNot(AsmToken::Identifier))
10745 return Error(L, "unexpected input in .unreq directive.");
10746 RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
10747 Parser.Lex(); // Eat the identifier.
10748 if (parseToken(AsmToken::EndOfStatement,
10749 "unexpected input in '.unreq' directive"))
10750 return true;
10751 return false;
10752}
10753
10754// After changing arch/CPU, try to put the ARM/Thumb mode back to what it was
10755// before, if supported by the new target, or emit mapping symbols for the mode
10756// switch.
10757void ARMAsmParser::FixModeAfterArchChange(bool WasThumb, SMLoc Loc) {
10758 if (WasThumb != isThumb()) {
10759 if (WasThumb && hasThumb()) {
10760 // Stay in Thumb mode
10761 SwitchMode();
10762 } else if (!WasThumb && hasARM()) {
10763 // Stay in ARM mode
10764 SwitchMode();
10765 } else {
10766 // Mode switch forced, because the new arch doesn't support the old mode.
10767 getParser().getStreamer().EmitAssemblerFlag(isThumb() ? MCAF_Code16
10768 : MCAF_Code32);
10769 // Warn about the implcit mode switch. GAS does not switch modes here,
10770 // but instead stays in the old mode, reporting an error on any following
10771 // instructions as the mode does not exist on the target.
10772 Warning(Loc, Twine("new target does not support ") +
10773 (WasThumb ? "thumb" : "arm") + " mode, switching to " +
10774 (!WasThumb ? "thumb" : "arm") + " mode");
10775 }
10776 }
10777}
10778
10779/// parseDirectiveArch
10780/// ::= .arch token
10781bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
10782 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
10783 ARM::ArchKind ID = ARM::parseArch(Arch);
10784
10785 if (ID == ARM::ArchKind::INVALID)
10786 return Error(L, "Unknown arch name");
10787
10788 bool WasThumb = isThumb();
10789 Triple T;
10790 MCSubtargetInfo &STI = copySTI();
10791 STI.setDefaultFeatures("", ("+" + ARM::getArchName(ID)).str());
10792 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
10793 FixModeAfterArchChange(WasThumb, L);
10794
10795 getTargetStreamer().emitArch(ID);
10796 return false;
10797}
10798
10799/// parseDirectiveEabiAttr
10800/// ::= .eabi_attribute int, int [, "str"]
10801/// ::= .eabi_attribute Tag_name, int [, "str"]
10802bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
10803 MCAsmParser &Parser = getParser();
10804 int64_t Tag;
10805 SMLoc TagLoc;
10806 TagLoc = Parser.getTok().getLoc();
10807 if (Parser.getTok().is(AsmToken::Identifier)) {
10808 StringRef Name = Parser.getTok().getIdentifier();
10809 Tag = ARMBuildAttrs::AttrTypeFromString(Name);
10810 if (Tag == -1) {
10811 Error(TagLoc, "attribute name not recognised: " + Name);
10812 return false;
10813 }
10814 Parser.Lex();
10815 } else {
10816 const MCExpr *AttrExpr;
10817
10818 TagLoc = Parser.getTok().getLoc();
10819 if (Parser.parseExpression(AttrExpr))
10820 return true;
10821
10822 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
10823 if (check(!CE, TagLoc, "expected numeric constant"))
10824 return true;
10825
10826 Tag = CE->getValue();
10827 }
10828
10829 if (Parser.parseToken(AsmToken::Comma, "comma expected"))
10830 return true;
10831
10832 StringRef StringValue = "";
10833 bool IsStringValue = false;
10834
10835 int64_t IntegerValue = 0;
10836 bool IsIntegerValue = false;
10837
10838 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
10839 IsStringValue = true;
10840 else if (Tag == ARMBuildAttrs::compatibility) {
10841 IsStringValue = true;
10842 IsIntegerValue = true;
10843 } else if (Tag < 32 || Tag % 2 == 0)
10844 IsIntegerValue = true;
10845 else if (Tag % 2 == 1)
10846 IsStringValue = true;
10847 else
10848 llvm_unreachable("invalid tag type")::llvm::llvm_unreachable_internal("invalid tag type", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10848)
;
10849
10850 if (IsIntegerValue) {
10851 const MCExpr *ValueExpr;
10852 SMLoc ValueExprLoc = Parser.getTok().getLoc();
10853 if (Parser.parseExpression(ValueExpr))
10854 return true;
10855
10856 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
10857 if (!CE)
10858 return Error(ValueExprLoc, "expected numeric constant");
10859 IntegerValue = CE->getValue();
10860 }
10861
10862 if (Tag == ARMBuildAttrs::compatibility) {
10863 if (Parser.parseToken(AsmToken::Comma, "comma expected"))
10864 return true;
10865 }
10866
10867 if (IsStringValue) {
10868 if (Parser.getTok().isNot(AsmToken::String))
10869 return Error(Parser.getTok().getLoc(), "bad string constant");
10870
10871 StringValue = Parser.getTok().getStringContents();
10872 Parser.Lex();
10873 }
10874
10875 if (Parser.parseToken(AsmToken::EndOfStatement,
10876 "unexpected token in '.eabi_attribute' directive"))
10877 return true;
10878
10879 if (IsIntegerValue && IsStringValue) {
10880 assert(Tag == ARMBuildAttrs::compatibility)((Tag == ARMBuildAttrs::compatibility) ? static_cast<void>
(0) : __assert_fail ("Tag == ARMBuildAttrs::compatibility", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10880, __PRETTY_FUNCTION__))
;
10881 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
10882 } else if (IsIntegerValue)
10883 getTargetStreamer().emitAttribute(Tag, IntegerValue);
10884 else if (IsStringValue)
10885 getTargetStreamer().emitTextAttribute(Tag, StringValue);
10886 return false;
10887}
10888
10889/// parseDirectiveCPU
10890/// ::= .cpu str
10891bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
10892 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
10893 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
10894
10895 // FIXME: This is using table-gen data, but should be moved to
10896 // ARMTargetParser once that is table-gen'd.
10897 if (!getSTI().isCPUStringValid(CPU))
10898 return Error(L, "Unknown CPU name");
10899
10900 bool WasThumb = isThumb();
10901 MCSubtargetInfo &STI = copySTI();
10902 STI.setDefaultFeatures(CPU, "");
10903 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
10904 FixModeAfterArchChange(WasThumb, L);
10905
10906 return false;
10907}
10908
10909/// parseDirectiveFPU
10910/// ::= .fpu str
10911bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
10912 SMLoc FPUNameLoc = getTok().getLoc();
10913 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
10914
10915 unsigned ID = ARM::parseFPU(FPU);
10916 std::vector<StringRef> Features;
10917 if (!ARM::getFPUFeatures(ID, Features))
10918 return Error(FPUNameLoc, "Unknown FPU name");
10919
10920 MCSubtargetInfo &STI = copySTI();
10921 for (auto Feature : Features)
10922 STI.ApplyFeatureFlag(Feature);
10923 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
10924
10925 getTargetStreamer().emitFPU(ID);
10926 return false;
10927}
10928
10929/// parseDirectiveFnStart
10930/// ::= .fnstart
10931bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
10932 if (parseToken(AsmToken::EndOfStatement,
10933 "unexpected token in '.fnstart' directive"))
10934 return true;
10935
10936 if (UC.hasFnStart()) {
10937 Error(L, ".fnstart starts before the end of previous one");
10938 UC.emitFnStartLocNotes();
10939 return true;
10940 }
10941
10942 // Reset the unwind directives parser state
10943 UC.reset();
10944
10945 getTargetStreamer().emitFnStart();
10946
10947 UC.recordFnStart(L);
10948 return false;
10949}
10950
10951/// parseDirectiveFnEnd
10952/// ::= .fnend
10953bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
10954 if (parseToken(AsmToken::EndOfStatement,
10955 "unexpected token in '.fnend' directive"))
10956 return true;
10957 // Check the ordering of unwind directives
10958 if (!UC.hasFnStart())
10959 return Error(L, ".fnstart must precede .fnend directive");
10960
10961 // Reset the unwind directives parser state
10962 getTargetStreamer().emitFnEnd();
10963
10964 UC.reset();
10965 return false;
10966}
10967
10968/// parseDirectiveCantUnwind
10969/// ::= .cantunwind
10970bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
10971 if (parseToken(AsmToken::EndOfStatement,
10972 "unexpected token in '.cantunwind' directive"))
10973 return true;
10974
10975 UC.recordCantUnwind(L);
10976 // Check the ordering of unwind directives
10977 if (check(!UC.hasFnStart(), L, ".fnstart must precede .cantunwind directive"))
10978 return true;
10979
10980 if (UC.hasHandlerData()) {
10981 Error(L, ".cantunwind can't be used with .handlerdata directive");
10982 UC.emitHandlerDataLocNotes();
10983 return true;
10984 }
10985 if (UC.hasPersonality()) {
10986 Error(L, ".cantunwind can't be used with .personality directive");
10987 UC.emitPersonalityLocNotes();
10988 return true;
10989 }
10990
10991 getTargetStreamer().emitCantUnwind();
10992 return false;
10993}
10994
10995/// parseDirectivePersonality
10996/// ::= .personality name
10997bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
10998 MCAsmParser &Parser = getParser();
10999 bool HasExistingPersonality = UC.hasPersonality();
11000
11001 // Parse the name of the personality routine
11002 if (Parser.getTok().isNot(AsmToken::Identifier))
11003 return Error(L, "unexpected input in .personality directive.");
11004 StringRef Name(Parser.getTok().getIdentifier());
11005 Parser.Lex();
11006
11007 if (parseToken(AsmToken::EndOfStatement,
11008 "unexpected token in '.personality' directive"))
11009 return true;
11010
11011 UC.recordPersonality(L);
11012
11013 // Check the ordering of unwind directives
11014 if (!UC.hasFnStart())
11015 return Error(L, ".fnstart must precede .personality directive");
11016 if (UC.cantUnwind()) {
11017 Error(L, ".personality can't be used with .cantunwind directive");
11018 UC.emitCantUnwindLocNotes();
11019 return true;
11020 }
11021 if (UC.hasHandlerData()) {
11022 Error(L, ".personality must precede .handlerdata directive");
11023 UC.emitHandlerDataLocNotes();
11024 return true;
11025 }
11026 if (HasExistingPersonality) {
11027 Error(L, "multiple personality directives");
11028 UC.emitPersonalityLocNotes();
11029 return true;
11030 }
11031
11032 MCSymbol *PR = getParser().getContext().getOrCreateSymbol(Name);
11033 getTargetStreamer().emitPersonality(PR);
11034 return false;
11035}
11036
11037/// parseDirectiveHandlerData
11038/// ::= .handlerdata
11039bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
11040 if (parseToken(AsmToken::EndOfStatement,
11041 "unexpected token in '.handlerdata' directive"))
11042 return true;
11043
11044 UC.recordHandlerData(L);
11045 // Check the ordering of unwind directives
11046 if (!UC.hasFnStart())
11047 return Error(L, ".fnstart must precede .personality directive");
11048 if (UC.cantUnwind()) {
11049 Error(L, ".handlerdata can't be used with .cantunwind directive");
11050 UC.emitCantUnwindLocNotes();
11051 return true;
11052 }
11053
11054 getTargetStreamer().emitHandlerData();
11055 return false;
11056}
11057
11058/// parseDirectiveSetFP
11059/// ::= .setfp fpreg, spreg [, offset]
11060bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
11061 MCAsmParser &Parser = getParser();
11062 // Check the ordering of unwind directives
11063 if (check(!UC.hasFnStart(), L, ".fnstart must precede .setfp directive") ||
11064 check(UC.hasHandlerData(), L,
11065 ".setfp must precede .handlerdata directive"))
11066 return true;
11067
11068 // Parse fpreg
11069 SMLoc FPRegLoc = Parser.getTok().getLoc();
11070 int FPReg = tryParseRegister();
11071
11072 if (check(FPReg == -1, FPRegLoc, "frame pointer register expected") ||
11073 Parser.parseToken(AsmToken::Comma, "comma expected"))
11074 return true;
11075
11076 // Parse spreg
11077 SMLoc SPRegLoc = Parser.getTok().getLoc();
11078 int SPReg = tryParseRegister();
11079 if (check(SPReg == -1, SPRegLoc, "stack pointer register expected") ||
11080 check(SPReg != ARM::SP && SPReg != UC.getFPReg(), SPRegLoc,
11081 "register should be either $sp or the latest fp register"))
11082 return true;
11083
11084 // Update the frame pointer register
11085 UC.saveFPReg(FPReg);
11086
11087 // Parse offset
11088 int64_t Offset = 0;
11089 if (Parser.parseOptionalToken(AsmToken::Comma)) {
11090 if (Parser.getTok().isNot(AsmToken::Hash) &&
11091 Parser.getTok().isNot(AsmToken::Dollar))
11092 return Error(Parser.getTok().getLoc(), "'#' expected");
11093 Parser.Lex(); // skip hash token.
11094
11095 const MCExpr *OffsetExpr;
11096 SMLoc ExLoc = Parser.getTok().getLoc();
11097 SMLoc EndLoc;
11098 if (getParser().parseExpression(OffsetExpr, EndLoc))
11099 return Error(ExLoc, "malformed setfp offset");
11100 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
11101 if (check(!CE, ExLoc, "setfp offset must be an immediate"))
11102 return true;
11103 Offset = CE->getValue();
11104 }
11105
11106 if (Parser.parseToken(AsmToken::EndOfStatement))
11107 return true;
11108
11109 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
11110 static_cast<unsigned>(SPReg), Offset);
11111 return false;
11112}
11113
11114/// parseDirective
11115/// ::= .pad offset
11116bool ARMAsmParser::parseDirectivePad(SMLoc L) {
11117 MCAsmParser &Parser = getParser();
11118 // Check the ordering of unwind directives
11119 if (!UC.hasFnStart())
11120 return Error(L, ".fnstart must precede .pad directive");
11121 if (UC.hasHandlerData())
11122 return Error(L, ".pad must precede .handlerdata directive");
11123
11124 // Parse the offset
11125 if (Parser.getTok().isNot(AsmToken::Hash) &&
11126 Parser.getTok().isNot(AsmToken::Dollar))
11127 return Error(Parser.getTok().getLoc(), "'#' expected");
11128 Parser.Lex(); // skip hash token.
11129
11130 const MCExpr *OffsetExpr;
11131 SMLoc ExLoc = Parser.getTok().getLoc();
11132 SMLoc EndLoc;
11133 if (getParser().parseExpression(OffsetExpr, EndLoc))
11134 return Error(ExLoc, "malformed pad offset");
11135 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
11136 if (!CE)
11137 return Error(ExLoc, "pad offset must be an immediate");
11138
11139 if (parseToken(AsmToken::EndOfStatement,
11140 "unexpected token in '.pad' directive"))
11141 return true;
11142
11143 getTargetStreamer().emitPad(CE->getValue());
11144 return false;
11145}
11146
11147/// parseDirectiveRegSave
11148/// ::= .save { registers }
11149/// ::= .vsave { registers }
11150bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
11151 // Check the ordering of unwind directives
11152 if (!UC.hasFnStart())
11153 return Error(L, ".fnstart must precede .save or .vsave directives");
11154 if (UC.hasHandlerData())
11155 return Error(L, ".save or .vsave must precede .handlerdata directive");
11156
11157 // RAII object to make sure parsed operands are deleted.
11158 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
11159
11160 // Parse the register list
11161 if (parseRegisterList(Operands) ||
11162 parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
11163 return true;
11164 ARMOperand &Op = (ARMOperand &)*Operands[0];
11165 if (!IsVector && !Op.isRegList())
11166 return Error(L, ".save expects GPR registers");
11167 if (IsVector && !Op.isDPRRegList())
11168 return Error(L, ".vsave expects DPR registers");
11169
11170 getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
11171 return false;
11172}
11173
11174/// parseDirectiveInst
11175/// ::= .inst opcode [, ...]
11176/// ::= .inst.n opcode [, ...]
11177/// ::= .inst.w opcode [, ...]
11178bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
11179 int Width = 4;
11180
11181 if (isThumb()) {
11182 switch (Suffix) {
11183 case 'n':
11184 Width = 2;
11185 break;
11186 case 'w':
11187 break;
11188 default:
11189 Width = 0;
11190 break;
11191 }
11192 } else {
11193 if (Suffix)
11194 return Error(Loc, "width suffixes are invalid in ARM mode");
11195 }
11196
11197 auto parseOne = [&]() -> bool {
11198 const MCExpr *Expr;
11199 if (getParser().parseExpression(Expr))
11200 return true;
11201 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
11202 if (!Value) {
11203 return Error(Loc, "expected constant expression");
11204 }
11205
11206 char CurSuffix = Suffix;
11207 switch (Width) {
11208 case 2:
11209 if (Value->getValue() > 0xffff)
11210 return Error(Loc, "inst.n operand is too big, use inst.w instead");
11211 break;
11212 case 4:
11213 if (Value->getValue() > 0xffffffff)
11214 return Error(Loc, StringRef(Suffix ? "inst.w" : "inst") +
11215 " operand is too big");
11216 break;
11217 case 0:
11218 // Thumb mode, no width indicated. Guess from the opcode, if possible.
11219 if (Value->getValue() < 0xe800)
11220 CurSuffix = 'n';
11221 else if (Value->getValue() >= 0xe8000000)
11222 CurSuffix = 'w';
11223 else
11224 return Error(Loc, "cannot determine Thumb instruction size, "
11225 "use inst.n/inst.w instead");
11226 break;
11227 default:
11228 llvm_unreachable("only supported widths are 2 and 4")::llvm::llvm_unreachable_internal("only supported widths are 2 and 4"
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 11228)
;
11229 }
11230
11231 getTargetStreamer().emitInst(Value->getValue(), CurSuffix);
11232 return false;
11233 };
11234
11235 if (parseOptionalToken(AsmToken::EndOfStatement))
11236 return Error(Loc, "expected expression following directive");
11237 if (parseMany(parseOne))
11238 return true;
11239 return false;
11240}
11241
11242/// parseDirectiveLtorg
11243/// ::= .ltorg | .pool
11244bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
11245 if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
11246 return true;
11247 getTargetStreamer().emitCurrentConstantPool();
11248 return false;
11249}
11250
11251bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
11252 const MCSection *Section = getStreamer().getCurrentSectionOnly();
11253
11254 if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
11255 return true;
11256
11257 if (!Section) {
11258 getStreamer().InitSections(false);
11259 Section = getStreamer().getCurrentSectionOnly();
11260 }
11261
11262 assert(Section && "must have section to emit alignment")((Section && "must have section to emit alignment") ?
static_cast<void> (0) : __assert_fail ("Section && \"must have section to emit alignment\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 11262, __PRETTY_FUNCTION__))
;
11263 if (Section->UseCodeAlign())
11264 getStreamer().EmitCodeAlignment(2);
11265 else
11266 getStreamer().EmitValueToAlignment(2);
11267
11268 return false;
11269}
11270
11271/// parseDirectivePersonalityIndex
11272/// ::= .personalityindex index
11273bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
11274 MCAsmParser &Parser = getParser();
11275 bool HasExistingPersonality = UC.hasPersonality();
11276
11277 const MCExpr *IndexExpression;
11278 SMLoc IndexLoc = Parser.getTok().getLoc();
11279 if (Parser.parseExpression(IndexExpression) ||
11280 parseToken(AsmToken::EndOfStatement,
11281 "unexpected token in '.personalityindex' directive")) {
11282 return true;
11283 }
11284
11285 UC.recordPersonalityIndex(L);
11286
11287 if (!UC.hasFnStart()) {
11288 return Error(L, ".fnstart must precede .personalityindex directive");
11289 }
11290 if (UC.cantUnwind()) {
11291 Error(L, ".personalityindex cannot be used with .cantunwind");
11292 UC.emitCantUnwindLocNotes();
11293 return true;
11294 }
11295 if (UC.hasHandlerData()) {
11296 Error(L, ".personalityindex must precede .handlerdata directive");
11297 UC.emitHandlerDataLocNotes();
11298 return true;
11299 }
11300 if (HasExistingPersonality) {
11301 Error(L, "multiple personality directives");
11302 UC.emitPersonalityLocNotes();
11303 return true;
11304 }
11305
11306 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
11307 if (!CE)
11308 return Error(IndexLoc, "index must be a constant number");
11309 if (CE->getValue() < 0 || CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX)
11310 return Error(IndexLoc,
11311 "personality routine index should be in range [0-3]");
11312
11313 getTargetStreamer().emitPersonalityIndex(CE->getValue());
11314 return false;
11315}
11316
11317/// parseDirectiveUnwindRaw
11318/// ::= .unwind_raw offset, opcode [, opcode...]
11319bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
11320 MCAsmParser &Parser = getParser();
11321 int64_t StackOffset;
11322 const MCExpr *OffsetExpr;
11323 SMLoc OffsetLoc = getLexer().getLoc();
11324
11325 if (!UC.hasFnStart())
11326 return Error(L, ".fnstart must precede .unwind_raw directives");
11327 if (getParser().parseExpression(OffsetExpr))
11328 return Error(OffsetLoc, "expected expression");
11329
11330 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
11331 if (!CE)
11332 return Error(OffsetLoc, "offset must be a constant");
11333
11334 StackOffset = CE->getValue();
11335
11336 if (Parser.parseToken(AsmToken::Comma, "expected comma"))
11337 return true;
11338
11339 SmallVector<uint8_t, 16> Opcodes;
11340
11341 auto parseOne = [&]() -> bool {
11342 const MCExpr *OE;
1
'OE' declared without an initial value
11343 SMLoc OpcodeLoc = getLexer().getLoc();
11344 if (check(getLexer().is(AsmToken::EndOfStatement) ||
2
Assuming the condition is false
3
Taking false branch
11345 Parser.parseExpression(OE),
11346 OpcodeLoc, "expected opcode expression"))
11347 return true;
11348 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
4
1st function call argument is an uninitialized value
11349 if (!OC)
11350 return Error(OpcodeLoc, "opcode value must be a constant");
11351 const int64_t Opcode = OC->getValue();
11352 if (Opcode & ~0xff)
11353 return Error(OpcodeLoc, "invalid opcode");
11354 Opcodes.push_back(uint8_t(Opcode));
11355 return false;
11356 };
11357
11358 // Must have at least 1 element
11359 SMLoc OpcodeLoc = getLexer().getLoc();
11360 if (parseOptionalToken(AsmToken::EndOfStatement))
11361 return Error(OpcodeLoc, "expected opcode expression");
11362 if (parseMany(parseOne))
11363 return true;
11364
11365 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
11366 return false;
11367}
11368
11369/// parseDirectiveTLSDescSeq
11370/// ::= .tlsdescseq tls-variable
11371bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
11372 MCAsmParser &Parser = getParser();
11373
11374 if (getLexer().isNot(AsmToken::Identifier))
11375 return TokError("expected variable after '.tlsdescseq' directive");
11376
11377 const MCSymbolRefExpr *SRE =
11378 MCSymbolRefExpr::create(Parser.getTok().getIdentifier(),
11379 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
11380 Lex();
11381
11382 if (parseToken(AsmToken::EndOfStatement,
11383 "unexpected token in '.tlsdescseq' directive"))
11384 return true;
11385
11386 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
11387 return false;
11388}
11389
11390/// parseDirectiveMovSP
11391/// ::= .movsp reg [, #offset]
11392bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
11393 MCAsmParser &Parser = getParser();
11394 if (!UC.hasFnStart())
11395 return Error(L, ".fnstart must precede .movsp directives");
11396 if (UC.getFPReg() != ARM::SP)
11397 return Error(L, "unexpected .movsp directive");
11398
11399 SMLoc SPRegLoc = Parser.getTok().getLoc();
11400 int SPReg = tryParseRegister();
11401 if (SPReg == -1)
11402 return Error(SPRegLoc, "register expected");
11403 if (SPReg == ARM::SP || SPReg == ARM::PC)
11404 return Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
11405
11406 int64_t Offset = 0;
11407 if (Parser.parseOptionalToken(AsmToken::Comma)) {
11408 if (Parser.parseToken(AsmToken::Hash, "expected #constant"))
11409 return true;
11410
11411 const MCExpr *OffsetExpr;
11412 SMLoc OffsetLoc = Parser.getTok().getLoc();
11413
11414 if (Parser.parseExpression(OffsetExpr))
11415 return Error(OffsetLoc, "malformed offset expression");
11416
11417 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
11418 if (!CE)
11419 return Error(OffsetLoc, "offset must be an immediate constant");
11420
11421 Offset = CE->getValue();
11422 }
11423
11424 if (parseToken(AsmToken::EndOfStatement,
11425 "unexpected token in '.movsp' directive"))
11426 return true;
11427
11428 getTargetStreamer().emitMovSP(SPReg, Offset);
11429 UC.saveFPReg(SPReg);
11430
11431 return false;
11432}
11433
11434/// parseDirectiveObjectArch
11435/// ::= .object_arch name
11436bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
11437 MCAsmParser &Parser = getParser();
11438 if (getLexer().isNot(AsmToken::Identifier))
11439 return Error(getLexer().getLoc(), "unexpected token");
11440
11441 StringRef Arch = Parser.getTok().getString();
11442 SMLoc ArchLoc = Parser.getTok().getLoc();
11443 Lex();
11444
11445 ARM::ArchKind ID = ARM::parseArch(Arch);
11446
11447 if (ID == ARM::ArchKind::INVALID)
11448 return Error(ArchLoc, "unknown architecture '" + Arch + "'");
11449 if (parseToken(AsmToken::EndOfStatement))
11450 return true;
11451
11452 getTargetStreamer().emitObjectArch(ID);
11453 return false;
11454}
11455
11456/// parseDirectiveAlign
11457/// ::= .align
11458bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
11459 // NOTE: if this is not the end of the statement, fall back to the target
11460 // agnostic handling for this directive which will correctly handle this.
11461 if (parseOptionalToken(AsmToken::EndOfStatement)) {
11462 // '.align' is target specifically handled to mean 2**2 byte alignment.
11463 const MCSection *Section = getStreamer().getCurrentSectionOnly();
11464 assert(Section && "must have section to emit alignment")((Section && "must have section to emit alignment") ?
static_cast<void> (0) : __assert_fail ("Section && \"must have section to emit alignment\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 11464, __PRETTY_FUNCTION__))
;
11465 if (Section->UseCodeAlign())
11466 getStreamer().EmitCodeAlignment(4, 0);
11467 else
11468 getStreamer().EmitValueToAlignment(4, 0, 1, 0);
11469 return false;
11470 }
11471 return true;
11472}
11473
11474/// parseDirectiveThumbSet
11475/// ::= .thumb_set name, value
11476bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
11477 MCAsmParser &Parser = getParser();
11478
11479 StringRef Name;
11480 if (check(Parser.parseIdentifier(Name),
11481 "expected identifier after '.thumb_set'") ||
11482 parseToken(AsmToken::Comma, "expected comma after name '" + Name + "'"))
11483 return true;
11484
11485 MCSymbol *Sym;
11486 const MCExpr *Value;
11487 if (MCParserUtils::parseAssignmentExpression(Name, /* allow_redef */ true,
11488 Parser, Sym, Value))
11489 return true;
11490
11491 getTargetStreamer().emitThumbSet(Sym, Value);
11492 return false;
11493}
11494
11495/// Force static initialization.
11496extern "C" void LLVMInitializeARMAsmParser() {
11497 RegisterMCAsmParser<ARMAsmParser> X(getTheARMLETarget());
11498 RegisterMCAsmParser<ARMAsmParser> Y(getTheARMBETarget());
11499 RegisterMCAsmParser<ARMAsmParser> A(getTheThumbLETarget());
11500 RegisterMCAsmParser<ARMAsmParser> B(getTheThumbBETarget());
11501}
11502
11503#define GET_REGISTER_MATCHER
11504#define GET_SUBTARGET_FEATURE_NAME
11505#define GET_MATCHER_IMPLEMENTATION
11506#define GET_MNEMONIC_SPELL_CHECKER
11507#include "ARMGenAsmMatcher.inc"
11508
11509// Some diagnostics need to vary with subtarget features, so they are handled
11510// here. For example, the DPR class has either 16 or 32 registers, depending
11511// on the FPU available.
11512const char *
11513ARMAsmParser::getCustomOperandDiag(ARMMatchResultTy MatchError) {
11514 switch (MatchError) {
11515 // rGPR contains sp starting with ARMv8.
11516 case Match_rGPR:
11517 return hasV8Ops() ? "operand must be a register in range [r0, r14]"
11518 : "operand must be a register in range [r0, r12] or r14";
11519 // DPR contains 16 registers for some FPUs, and 32 for others.
11520 case Match_DPR:
11521 return hasD32() ? "operand must be a register in range [d0, d31]"
11522 : "operand must be a register in range [d0, d15]";
11523 case Match_DPR_RegList:
11524 return hasD32() ? "operand must be a list of registers in range [d0, d31]"
11525 : "operand must be a list of registers in range [d0, d15]";
11526
11527 // For all other diags, use the static string from tablegen.
11528 default:
11529 return getMatchKindDiag(MatchError);
11530 }
11531}
11532
11533// Process the list of near-misses, throwing away ones we don't want to report
11534// to the user, and converting the rest to a source location and string that
11535// should be reported.
11536void
11537ARMAsmParser::FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
11538 SmallVectorImpl<NearMissMessage> &NearMissesOut,
11539 SMLoc IDLoc, OperandVector &Operands) {
11540 // TODO: If operand didn't match, sub in a dummy one and run target
11541 // predicate, so that we can avoid reporting near-misses that are invalid?
11542 // TODO: Many operand types dont have SuperClasses set, so we report
11543 // redundant ones.
11544 // TODO: Some operands are superclasses of registers (e.g.
11545 // MCK_RegShiftedImm), we don't have any way to represent that currently.
11546 // TODO: This is not all ARM-specific, can some of it be factored out?
11547
11548 // Record some information about near-misses that we have already seen, so
11549 // that we can avoid reporting redundant ones. For example, if there are
11550 // variants of an instruction that take 8- and 16-bit immediates, we want
11551 // to only report the widest one.
11552 std::multimap<unsigned, unsigned> OperandMissesSeen;
11553 SmallSet<FeatureBitset, 4> FeatureMissesSeen;
11554 bool ReportedTooFewOperands = false;
11555
11556 // Process the near-misses in reverse order, so that we see more general ones
11557 // first, and so can avoid emitting more specific ones.
11558 for (NearMissInfo &I : reverse(NearMissesIn)) {
11559 switch (I.getKind()) {
11560 case NearMissInfo::NearMissOperand: {
11561 SMLoc OperandLoc =
11562 ((ARMOperand &)*Operands[I.getOperandIndex()]).getStartLoc();
11563 const char *OperandDiag =
11564 getCustomOperandDiag((ARMMatchResultTy)I.getOperandError());
11565
11566 // If we have already emitted a message for a superclass, don't also report
11567 // the sub-class. We consider all operand classes that we don't have a
11568 // specialised diagnostic for to be equal for the propose of this check,
11569 // so that we don't report the generic error multiple times on the same
11570 // operand.
11571 unsigned DupCheckMatchClass = OperandDiag ? I.getOperandClass() : ~0U;
11572 auto PrevReports = OperandMissesSeen.equal_range(I.getOperandIndex());
11573 if (std::any_of(PrevReports.first, PrevReports.second,
11574 [DupCheckMatchClass](
11575 const std::pair<unsigned, unsigned> Pair) {
11576 if (DupCheckMatchClass == ~0U || Pair.second == ~0U)
11577 return Pair.second == DupCheckMatchClass;
11578 else
11579 return isSubclass((MatchClassKind)DupCheckMatchClass,
11580 (MatchClassKind)Pair.second);
11581 }))
11582 break;
11583 OperandMissesSeen.insert(
11584 std::make_pair(I.getOperandIndex(), DupCheckMatchClass));
11585
11586 NearMissMessage Message;
11587 Message.Loc = OperandLoc;
11588 if (OperandDiag) {
11589 Message.Message = OperandDiag;
11590 } else if (I.getOperandClass() == InvalidMatchClass) {
11591 Message.Message = "too many operands for instruction";
11592 } else {
11593 Message.Message = "invalid operand for instruction";
11594 LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("asm-parser")) { dbgs() << "Missing diagnostic string for operand class "
<< getMatchClassName((MatchClassKind)I.getOperandClass
()) << I.getOperandClass() << ", error " <<
I.getOperandError() << ", opcode " << MII.getName
(I.getOpcode()) << "\n"; } } while (false)
11595 dbgs() << "Missing diagnostic string for operand class "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("asm-parser")) { dbgs() << "Missing diagnostic string for operand class "
<< getMatchClassName((MatchClassKind)I.getOperandClass
()) << I.getOperandClass() << ", error " <<
I.getOperandError() << ", opcode " << MII.getName
(I.getOpcode()) << "\n"; } } while (false)
11596 << getMatchClassName((MatchClassKind)I.getOperandClass())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("asm-parser")) { dbgs() << "Missing diagnostic string for operand class "
<< getMatchClassName((MatchClassKind)I.getOperandClass
()) << I.getOperandClass() << ", error " <<
I.getOperandError() << ", opcode " << MII.getName
(I.getOpcode()) << "\n"; } } while (false)
11597 << I.getOperandClass() << ", error " << I.getOperandError()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("asm-parser")) { dbgs() << "Missing diagnostic string for operand class "
<< getMatchClassName((MatchClassKind)I.getOperandClass
()) << I.getOperandClass() << ", error " <<
I.getOperandError() << ", opcode " << MII.getName
(I.getOpcode()) << "\n"; } } while (false)
11598 << ", opcode " << MII.getName(I.getOpcode()) << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("asm-parser")) { dbgs() << "Missing diagnostic string for operand class "
<< getMatchClassName((MatchClassKind)I.getOperandClass
()) << I.getOperandClass() << ", error " <<
I.getOperandError() << ", opcode " << MII.getName
(I.getOpcode()) << "\n"; } } while (false)
;
11599 }
11600 NearMissesOut.emplace_back(Message);
11601 break;
11602 }
11603 case NearMissInfo::NearMissFeature: {
11604 const FeatureBitset &MissingFeatures = I.getFeatures();
11605 // Don't report the same set of features twice.
11606 if (FeatureMissesSeen.count(MissingFeatures))
11607 break;
11608 FeatureMissesSeen.insert(MissingFeatures);
11609
11610 // Special case: don't report a feature set which includes arm-mode for
11611 // targets that don't have ARM mode.
11612 if (MissingFeatures.test(Feature_IsARMBit) && !hasARM())
11613 break;
11614 // Don't report any near-misses that both require switching instruction
11615 // set, and adding other subtarget features.
11616 if (isThumb() && MissingFeatures.test(Feature_IsARMBit) &&
11617 MissingFeatures.count() > 1)
11618 break;
11619 if (!isThumb() && MissingFeatures.test(Feature_IsThumbBit) &&
11620 MissingFeatures.count() > 1)
11621 break;
11622 if (!isThumb() && MissingFeatures.test(Feature_IsThumb2Bit) &&
11623 (MissingFeatures & ~FeatureBitset({Feature_IsThumb2Bit,
11624 Feature_IsThumbBit})).any())
11625 break;
11626 if (isMClass() && MissingFeatures.test(Feature_HasNEONBit))
11627 break;
11628
11629 NearMissMessage Message;
11630 Message.Loc = IDLoc;
11631 raw_svector_ostream OS(Message.Message);
11632
11633 OS << "instruction requires:";
11634 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
11635 if (MissingFeatures.test(i))
11636 OS << ' ' << getSubtargetFeatureName(i);
11637
11638 NearMissesOut.emplace_back(Message);
11639
11640 break;
11641 }
11642 case NearMissInfo::NearMissPredicate: {
11643 NearMissMessage Message;
11644 Message.Loc = IDLoc;
11645 switch (I.getPredicateError()) {
11646 case Match_RequiresNotITBlock:
11647 Message.Message = "flag setting instruction only valid outside IT block";
11648 break;
11649 case Match_RequiresITBlock:
11650 Message.Message = "instruction only valid inside IT block";
11651 break;
11652 case Match_RequiresV6:
11653 Message.Message = "instruction variant requires ARMv6 or later";
11654 break;
11655 case Match_RequiresThumb2:
11656 Message.Message = "instruction variant requires Thumb2";
11657 break;
11658 case Match_RequiresV8:
11659 Message.Message = "instruction variant requires ARMv8 or later";
11660 break;
11661 case Match_RequiresFlagSetting:
11662 Message.Message = "no flag-preserving variant of this instruction available";
11663 break;
11664 case Match_InvalidOperand:
11665 Message.Message = "invalid operand for instruction";
11666 break;
11667 default:
11668 llvm_unreachable("Unhandled target predicate error")::llvm::llvm_unreachable_internal("Unhandled target predicate error"
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 11668)
;
11669 break;
11670 }
11671 NearMissesOut.emplace_back(Message);
11672 break;
11673 }
11674 case NearMissInfo::NearMissTooFewOperands: {
11675 if (!ReportedTooFewOperands) {
11676 SMLoc EndLoc = ((ARMOperand &)*Operands.back()).getEndLoc();
11677 NearMissesOut.emplace_back(NearMissMessage{
11678 EndLoc, StringRef("too few operands for instruction")});
11679 ReportedTooFewOperands = true;
11680 }
11681 break;
11682 }
11683 case NearMissInfo::NoNearMiss:
11684 // This should never leave the matcher.
11685 llvm_unreachable("not a near-miss")::llvm::llvm_unreachable_internal("not a near-miss", "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 11685)
;
11686 break;
11687 }
11688 }
11689}
11690
11691void ARMAsmParser::ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses,
11692 SMLoc IDLoc, OperandVector &Operands) {
11693 SmallVector<NearMissMessage, 4> Messages;
11694 FilterNearMisses(NearMisses, Messages, IDLoc, Operands);
11695
11696 if (Messages.size() == 0) {
11697 // No near-misses were found, so the best we can do is "invalid
11698 // instruction".
11699 Error(IDLoc, "invalid instruction");
11700 } else if (Messages.size() == 1) {
11701 // One near miss was found, report it as the sole error.
11702 Error(Messages[0].Loc, Messages[0].Message);
11703 } else {
11704 // More than one near miss, so report a generic "invalid instruction"
11705 // error, followed by notes for each of the near-misses.
11706 Error(IDLoc, "invalid instruction, any one of the following would fix this:");
11707 for (auto &M : Messages) {
11708 Note(M.Loc, M.Message);
11709 }
11710 }
11711}
11712
11713/// parseDirectiveArchExtension
11714/// ::= .arch_extension [no]feature
11715bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
11716 // FIXME: This structure should be moved inside ARMTargetParser
11717 // when we start to table-generate them, and we can use the ARM
11718 // flags below, that were generated by table-gen.
11719 static const struct {
11720 const unsigned Kind;
11721 const FeatureBitset ArchCheck;
11722 const FeatureBitset Features;
11723 } Extensions[] = {
11724 { ARM::AEK_CRC, {Feature_HasV8Bit}, {ARM::FeatureCRC} },
11725 { ARM::AEK_CRYPTO, {Feature_HasV8Bit},
11726 {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
11727 { ARM::AEK_FP, {Feature_HasV8Bit},
11728 {ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8} },
11729 { (ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM),
11730 {Feature_HasV7Bit, Feature_IsNotMClassBit},
11731 {ARM::FeatureHWDivThumb, ARM::FeatureHWDivARM} },
11732 { ARM::AEK_MP, {Feature_HasV7Bit, Feature_IsNotMClassBit},
11733 {ARM::FeatureMP} },
11734 { ARM::AEK_SIMD, {Feature_HasV8Bit},
11735 {ARM::FeatureNEON, ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8} },
11736 { ARM::AEK_SEC, {Feature_HasV6KBit}, {ARM::FeatureTrustZone} },
11737 // FIXME: Only available in A-class, isel not predicated
11738 { ARM::AEK_VIRT, {Feature_HasV7Bit}, {ARM::FeatureVirtualization} },
11739 { ARM::AEK_FP16, {Feature_HasV8_2aBit},
11740 {ARM::FeatureFPARMv8, ARM::FeatureFullFP16} },
11741 { ARM::AEK_RAS, {Feature_HasV8Bit}, {ARM::FeatureRAS} },
11742 { ARM::AEK_LOB, {Feature_HasV8_1MMainlineBit}, {ARM::FeatureLOB} },
11743 // FIXME: Unsupported extensions.
11744 { ARM::AEK_OS, {}, {} },
11745 { ARM::AEK_IWMMXT, {}, {} },
11746 { ARM::AEK_IWMMXT2, {}, {} },
11747 { ARM::AEK_MAVERICK, {}, {} },
11748 { ARM::AEK_XSCALE, {}, {} },
11749 };
11750
11751 MCAsmParser &Parser = getParser();
11752
11753 if (getLexer().isNot(AsmToken::Identifier))
11754 return Error(getLexer().getLoc(), "expected architecture extension name");
11755
11756 StringRef Name = Parser.getTok().getString();
11757 SMLoc ExtLoc = Parser.getTok().getLoc();
11758 Lex();
11759
11760 if (parseToken(AsmToken::EndOfStatement,
11761 "unexpected token in '.arch_extension' directive"))
11762 return true;
11763
11764 bool EnableFeature = true;
11765 if (Name.startswith_lower("no")) {
11766 EnableFeature = false;
11767 Name = Name.substr(2);
11768 }
11769 unsigned FeatureKind = ARM::parseArchExt(Name);
11770 if (FeatureKind == ARM::AEK_INVALID)
11771 return Error(ExtLoc, "unknown architectural extension: " + Name);
11772
11773 for (const auto &Extension : Extensions) {
11774 if (Extension.Kind != FeatureKind)
11775 continue;
11776
11777 if (Extension.Features.none())
11778 return Error(ExtLoc, "unsupported architectural extension: " + Name);
11779
11780 if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck)
11781 return Error(ExtLoc, "architectural extension '" + Name +
11782 "' is not "
11783 "allowed for the current base architecture");
11784
11785 MCSubtargetInfo &STI = copySTI();
11786 if (EnableFeature) {
11787 STI.SetFeatureBitsTransitively(Extension.Features);
11788 } else {
11789 STI.ClearFeatureBitsTransitively(Extension.Features);
11790 }
11791 FeatureBitset Features = ComputeAvailableFeatures(STI.getFeatureBits());
11792 setAvailableFeatures(Features);
11793 return false;
11794 }
11795
11796 return Error(ExtLoc, "unknown architectural extension: " + Name);
11797}
11798
11799// Define this matcher function after the auto-generated include so we
11800// have the match class enum definitions.
11801unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
11802 unsigned Kind) {
11803 ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
11804 // If the kind is a token for a literal immediate, check if our asm
11805 // operand matches. This is for InstAliases which have a fixed-value
11806 // immediate in the syntax.
11807 switch (Kind) {
11808 default: break;
11809 case MCK__HASH_0:
11810 if (Op.isImm())
11811 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
11812 if (CE->getValue() == 0)
11813 return Match_Success;
11814 break;
11815 case MCK__HASH_8:
11816 if (Op.isImm())
11817 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
11818 if (CE->getValue() == 8)
11819 return Match_Success;
11820 break;
11821 case MCK__HASH_16:
11822 if (Op.isImm())
11823 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
11824 if (CE->getValue() == 16)
11825 return Match_Success;
11826 break;
11827 case MCK_ModImm:
11828 if (Op.isImm()) {
11829 const MCExpr *SOExpr = Op.getImm();
11830 int64_t Value;
11831 if (!SOExpr->evaluateAsAbsolute(Value))
11832 return Match_Success;
11833 assert((Value >= std::numeric_limits<int32_t>::min() &&(((Value >= std::numeric_limits<int32_t>::min() &&
Value <= std::numeric_limits<uint32_t>::max()) &&
"expression value must be representable in 32 bits") ? static_cast
<void> (0) : __assert_fail ("(Value >= std::numeric_limits<int32_t>::min() && Value <= std::numeric_limits<uint32_t>::max()) && \"expression value must be representable in 32 bits\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 11835, __PRETTY_FUNCTION__))
11834 Value <= std::numeric_limits<uint32_t>::max()) &&(((Value >= std::numeric_limits<int32_t>::min() &&
Value <= std::numeric_limits<uint32_t>::max()) &&
"expression value must be representable in 32 bits") ? static_cast
<void> (0) : __assert_fail ("(Value >= std::numeric_limits<int32_t>::min() && Value <= std::numeric_limits<uint32_t>::max()) && \"expression value must be representable in 32 bits\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 11835, __PRETTY_FUNCTION__))
11835 "expression value must be representable in 32 bits")(((Value >= std::numeric_limits<int32_t>::min() &&
Value <= std::numeric_limits<uint32_t>::max()) &&
"expression value must be representable in 32 bits") ? static_cast
<void> (0) : __assert_fail ("(Value >= std::numeric_limits<int32_t>::min() && Value <= std::numeric_limits<uint32_t>::max()) && \"expression value must be representable in 32 bits\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 11835, __PRETTY_FUNCTION__))
;
11836 }
11837 break;
11838 case MCK_rGPR:
11839 if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP)
11840 return Match_Success;
11841 return Match_rGPR;
11842 case MCK_GPRPair:
11843 if (Op.isReg() &&
11844 MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
11845 return Match_Success;
11846 break;
11847 }
11848 return Match_InvalidOperand;
11849}
11850
11851bool ARMAsmParser::isMnemonicVPTPredicable(StringRef Mnemonic,
11852 StringRef ExtraToken) {
11853 if (!hasMVE())
11854 return false;
11855
11856 return Mnemonic.startswith("vabav") || Mnemonic.startswith("vaddv") ||
11857 Mnemonic.startswith("vaddlv") || Mnemonic.startswith("vminnmv") ||
11858 Mnemonic.startswith("vminnmav") || Mnemonic.startswith("vminv") ||
11859 Mnemonic.startswith("vminav") || Mnemonic.startswith("vmaxnmv") ||
11860 Mnemonic.startswith("vmaxnmav") || Mnemonic.startswith("vmaxv") ||
11861 Mnemonic.startswith("vmaxav") || Mnemonic.startswith("vmladav") ||
11862 Mnemonic.startswith("vrmlaldavh") || Mnemonic.startswith("vrmlalvh") ||
11863 Mnemonic.startswith("vmlsdav") || Mnemonic.startswith("vmlav") ||
11864 Mnemonic.startswith("vmlaldav") || Mnemonic.startswith("vmlalv") ||
11865 Mnemonic.startswith("vmaxnm") || Mnemonic.startswith("vminnm") ||
11866 Mnemonic.startswith("vmax") || Mnemonic.startswith("vmin") ||
11867 Mnemonic.startswith("vshlc") || Mnemonic.startswith("vmovlt") ||
11868 Mnemonic.startswith("vmovlb") || Mnemonic.startswith("vshll") ||
11869 Mnemonic.startswith("vrshrn") || Mnemonic.startswith("vshrn") ||
11870 Mnemonic.startswith("vqrshrun") || Mnemonic.startswith("vqshrun") ||
11871 Mnemonic.startswith("vqrshrn") || Mnemonic.startswith("vqshrn") ||
11872 Mnemonic.startswith("vbic") || Mnemonic.startswith("vrev64") ||
11873 Mnemonic.startswith("vrev32") || Mnemonic.startswith("vrev16") ||
11874 Mnemonic.startswith("vmvn") || Mnemonic.startswith("veor") ||
11875 Mnemonic.startswith("vorn") || Mnemonic.startswith("vorr") ||
11876 Mnemonic.startswith("vand") || Mnemonic.startswith("vmul") ||
11877 Mnemonic.startswith("vqrdmulh") || Mnemonic.startswith("vqdmulh") ||
11878 Mnemonic.startswith("vsub") || Mnemonic.startswith("vadd") ||
11879 Mnemonic.startswith("vqsub") || Mnemonic.startswith("vqadd") ||
11880 Mnemonic.startswith("vabd") || Mnemonic.startswith("vrhadd") ||
11881 Mnemonic.startswith("vhsub") || Mnemonic.startswith("vhadd") ||
11882 Mnemonic.startswith("vdup") || Mnemonic.startswith("vcls") ||
11883 Mnemonic.startswith("vclz") || Mnemonic.startswith("vneg") ||
11884 Mnemonic.startswith("vabs") || Mnemonic.startswith("vqneg") ||
11885 Mnemonic.startswith("vqabs") ||
11886 (Mnemonic.startswith("vrint") && Mnemonic != "vrintr") ||
11887 Mnemonic.startswith("vcmla") || Mnemonic.startswith("vfma") ||
11888 Mnemonic.startswith("vfms") || Mnemonic.startswith("vcadd") ||
11889 Mnemonic.startswith("vadd") || Mnemonic.startswith("vsub") ||
11890 Mnemonic.startswith("vshl") || Mnemonic.startswith("vqshl") ||
11891 Mnemonic.startswith("vqrshl") || Mnemonic.startswith("vrshl") ||
11892 Mnemonic.startswith("vsri") || Mnemonic.startswith("vsli") ||
11893 Mnemonic.startswith("vrshr") || Mnemonic.startswith("vshr") ||
11894 Mnemonic.startswith("vpsel") || Mnemonic.startswith("vcmp") ||
11895 Mnemonic.startswith("vqdmladh") || Mnemonic.startswith("vqrdmladh") ||
11896 Mnemonic.startswith("vqdmlsdh") || Mnemonic.startswith("vqrdmlsdh") ||
11897 Mnemonic.startswith("vcmul") || Mnemonic.startswith("vrmulh") ||
11898 Mnemonic.startswith("vqmovn") || Mnemonic.startswith("vqmovun") ||
11899 Mnemonic.startswith("vmovnt") || Mnemonic.startswith("vmovnb") ||
11900 Mnemonic.startswith("vmaxa") || Mnemonic.startswith("vmaxnma") ||
11901 Mnemonic.startswith("vhcadd") || Mnemonic.startswith("vadc") ||
11902 Mnemonic.startswith("vsbc") || Mnemonic.startswith("vrshr") ||
11903 Mnemonic.startswith("vshr") || Mnemonic.startswith("vstrb") ||
11904 Mnemonic.startswith("vldrb") ||
11905 (Mnemonic.startswith("vstrh") && Mnemonic != "vstrhi") ||
11906 (Mnemonic.startswith("vldrh") && Mnemonic != "vldrhi") ||
11907 Mnemonic.startswith("vstrw") || Mnemonic.startswith("vldrw") ||
11908 Mnemonic.startswith("vldrd") || Mnemonic.startswith("vstrd") ||
11909 Mnemonic.startswith("vqdmull") || Mnemonic.startswith("vbrsr") ||
11910 Mnemonic.startswith("vfmas") || Mnemonic.startswith("vmlas") ||
11911 Mnemonic.startswith("vmla") || Mnemonic.startswith("vqdmlash") ||
11912 Mnemonic.startswith("vqdmlah") || Mnemonic.startswith("vqrdmlash") ||
11913 Mnemonic.startswith("vqrdmlah") || Mnemonic.startswith("viwdup") ||
11914 Mnemonic.startswith("vdwdup") || Mnemonic.startswith("vidup") ||
11915 Mnemonic.startswith("vddup") || Mnemonic.startswith("vctp") ||
11916 Mnemonic.startswith("vpnot") || Mnemonic.startswith("vbic") ||
11917 Mnemonic.startswith("vrmlsldavh") || Mnemonic.startswith("vmlsldav") ||
11918 Mnemonic.startswith("vcvt") ||
11919 (Mnemonic.startswith("vmov") &&
11920 !(ExtraToken == ".f16" || ExtraToken == ".32" ||
11921 ExtraToken == ".16" || ExtraToken == ".8"));
11922}