File: | llvm/lib/CodeGen/MachineInstr.cpp |
Warning: | line 194, column 3 Null pointer passed to 2nd parameter expecting 'nonnull' |
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1 | //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===// | ||||||
2 | // | ||||||
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | ||||||
4 | // See https://llvm.org/LICENSE.txt for license information. | ||||||
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||||||
6 | // | ||||||
7 | //===----------------------------------------------------------------------===// | ||||||
8 | // | ||||||
9 | // Methods common to all machine instructions. | ||||||
10 | // | ||||||
11 | //===----------------------------------------------------------------------===// | ||||||
12 | |||||||
13 | #include "llvm/CodeGen/MachineInstr.h" | ||||||
14 | #include "llvm/ADT/APFloat.h" | ||||||
15 | #include "llvm/ADT/ArrayRef.h" | ||||||
16 | #include "llvm/ADT/FoldingSet.h" | ||||||
17 | #include "llvm/ADT/Hashing.h" | ||||||
18 | #include "llvm/ADT/None.h" | ||||||
19 | #include "llvm/ADT/STLExtras.h" | ||||||
20 | #include "llvm/ADT/SmallBitVector.h" | ||||||
21 | #include "llvm/ADT/SmallString.h" | ||||||
22 | #include "llvm/ADT/SmallVector.h" | ||||||
23 | #include "llvm/Analysis/AliasAnalysis.h" | ||||||
24 | #include "llvm/Analysis/Loads.h" | ||||||
25 | #include "llvm/Analysis/MemoryLocation.h" | ||||||
26 | #include "llvm/CodeGen/GlobalISel/RegisterBank.h" | ||||||
27 | #include "llvm/CodeGen/MachineBasicBlock.h" | ||||||
28 | #include "llvm/CodeGen/MachineFrameInfo.h" | ||||||
29 | #include "llvm/CodeGen/MachineFunction.h" | ||||||
30 | #include "llvm/CodeGen/MachineInstrBuilder.h" | ||||||
31 | #include "llvm/CodeGen/MachineInstrBundle.h" | ||||||
32 | #include "llvm/CodeGen/MachineMemOperand.h" | ||||||
33 | #include "llvm/CodeGen/MachineModuleInfo.h" | ||||||
34 | #include "llvm/CodeGen/MachineOperand.h" | ||||||
35 | #include "llvm/CodeGen/MachineRegisterInfo.h" | ||||||
36 | #include "llvm/CodeGen/PseudoSourceValue.h" | ||||||
37 | #include "llvm/CodeGen/TargetInstrInfo.h" | ||||||
38 | #include "llvm/CodeGen/TargetRegisterInfo.h" | ||||||
39 | #include "llvm/CodeGen/TargetSubtargetInfo.h" | ||||||
40 | #include "llvm/Config/llvm-config.h" | ||||||
41 | #include "llvm/IR/Constants.h" | ||||||
42 | #include "llvm/IR/DebugInfoMetadata.h" | ||||||
43 | #include "llvm/IR/DebugLoc.h" | ||||||
44 | #include "llvm/IR/DerivedTypes.h" | ||||||
45 | #include "llvm/IR/Function.h" | ||||||
46 | #include "llvm/IR/InlineAsm.h" | ||||||
47 | #include "llvm/IR/InstrTypes.h" | ||||||
48 | #include "llvm/IR/Intrinsics.h" | ||||||
49 | #include "llvm/IR/LLVMContext.h" | ||||||
50 | #include "llvm/IR/Metadata.h" | ||||||
51 | #include "llvm/IR/Module.h" | ||||||
52 | #include "llvm/IR/ModuleSlotTracker.h" | ||||||
53 | #include "llvm/IR/Operator.h" | ||||||
54 | #include "llvm/IR/Type.h" | ||||||
55 | #include "llvm/IR/Value.h" | ||||||
56 | #include "llvm/MC/MCInstrDesc.h" | ||||||
57 | #include "llvm/MC/MCRegisterInfo.h" | ||||||
58 | #include "llvm/MC/MCSymbol.h" | ||||||
59 | #include "llvm/Support/Casting.h" | ||||||
60 | #include "llvm/Support/CommandLine.h" | ||||||
61 | #include "llvm/Support/Compiler.h" | ||||||
62 | #include "llvm/Support/Debug.h" | ||||||
63 | #include "llvm/Support/ErrorHandling.h" | ||||||
64 | #include "llvm/Support/LowLevelTypeImpl.h" | ||||||
65 | #include "llvm/Support/MathExtras.h" | ||||||
66 | #include "llvm/Support/raw_ostream.h" | ||||||
67 | #include "llvm/Target/TargetIntrinsicInfo.h" | ||||||
68 | #include "llvm/Target/TargetMachine.h" | ||||||
69 | #include <algorithm> | ||||||
70 | #include <cassert> | ||||||
71 | #include <cstddef> | ||||||
72 | #include <cstdint> | ||||||
73 | #include <cstring> | ||||||
74 | #include <iterator> | ||||||
75 | #include <utility> | ||||||
76 | |||||||
77 | using namespace llvm; | ||||||
78 | |||||||
79 | static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) { | ||||||
80 | if (const MachineBasicBlock *MBB = MI.getParent()) | ||||||
81 | if (const MachineFunction *MF = MBB->getParent()) | ||||||
82 | return MF; | ||||||
83 | return nullptr; | ||||||
84 | } | ||||||
85 | |||||||
86 | // Try to crawl up to the machine function and get TRI and IntrinsicInfo from | ||||||
87 | // it. | ||||||
88 | static void tryToGetTargetInfo(const MachineInstr &MI, | ||||||
89 | const TargetRegisterInfo *&TRI, | ||||||
90 | const MachineRegisterInfo *&MRI, | ||||||
91 | const TargetIntrinsicInfo *&IntrinsicInfo, | ||||||
92 | const TargetInstrInfo *&TII, | ||||||
93 | const MIRFormatter *&MIRF) { | ||||||
94 | |||||||
95 | if (const MachineFunction *MF = getMFIfAvailable(MI)) { | ||||||
96 | TRI = MF->getSubtarget().getRegisterInfo(); | ||||||
97 | MRI = &MF->getRegInfo(); | ||||||
98 | IntrinsicInfo = MF->getTarget().getIntrinsicInfo(); | ||||||
99 | TII = MF->getSubtarget().getInstrInfo(); | ||||||
100 | MIRF = MF->getTarget().getMIRFormatter(); | ||||||
101 | } | ||||||
102 | } | ||||||
103 | |||||||
104 | void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) { | ||||||
105 | if (MCID->ImplicitDefs) | ||||||
106 | for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; | ||||||
107 | ++ImpDefs) | ||||||
108 | addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true)); | ||||||
109 | if (MCID->ImplicitUses) | ||||||
110 | for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses; | ||||||
111 | ++ImpUses) | ||||||
112 | addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true)); | ||||||
113 | } | ||||||
114 | |||||||
115 | /// MachineInstr ctor - This constructor creates a MachineInstr and adds the | ||||||
116 | /// implicit operands. It reserves space for the number of operands specified by | ||||||
117 | /// the MCInstrDesc. | ||||||
118 | MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid, | ||||||
119 | DebugLoc dl, bool NoImp) | ||||||
120 | : MCID(&tid), debugLoc(std::move(dl)) { | ||||||
121 | assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor" ) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 121, __PRETTY_FUNCTION__)); | ||||||
122 | |||||||
123 | // Reserve space for the expected number of operands. | ||||||
124 | if (unsigned NumOps = MCID->getNumOperands() + | ||||||
125 | MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) { | ||||||
126 | CapOperands = OperandCapacity::get(NumOps); | ||||||
127 | Operands = MF.allocateOperandArray(CapOperands); | ||||||
128 | } | ||||||
129 | |||||||
130 | if (!NoImp) | ||||||
131 | addImplicitDefUseOperands(MF); | ||||||
132 | } | ||||||
133 | |||||||
134 | /// MachineInstr ctor - Copies MachineInstr arg exactly | ||||||
135 | /// | ||||||
136 | MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) | ||||||
137 | : MCID(&MI.getDesc()), Info(MI.Info), debugLoc(MI.getDebugLoc()) { | ||||||
138 | assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor" ) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 138, __PRETTY_FUNCTION__)); | ||||||
139 | |||||||
140 | CapOperands = OperandCapacity::get(MI.getNumOperands()); | ||||||
141 | Operands = MF.allocateOperandArray(CapOperands); | ||||||
142 | |||||||
143 | // Copy operands. | ||||||
144 | for (const MachineOperand &MO : MI.operands()) | ||||||
145 | addOperand(MF, MO); | ||||||
146 | |||||||
147 | // Copy all the sensible flags. | ||||||
148 | setFlags(MI.Flags); | ||||||
149 | } | ||||||
150 | |||||||
151 | /// getRegInfo - If this instruction is embedded into a MachineFunction, | ||||||
152 | /// return the MachineRegisterInfo object for the current function, otherwise | ||||||
153 | /// return null. | ||||||
154 | MachineRegisterInfo *MachineInstr::getRegInfo() { | ||||||
155 | if (MachineBasicBlock *MBB = getParent()) | ||||||
156 | return &MBB->getParent()->getRegInfo(); | ||||||
157 | return nullptr; | ||||||
158 | } | ||||||
159 | |||||||
160 | /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in | ||||||
161 | /// this instruction from their respective use lists. This requires that the | ||||||
162 | /// operands already be on their use lists. | ||||||
163 | void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) { | ||||||
164 | for (MachineOperand &MO : operands()) | ||||||
165 | if (MO.isReg()) | ||||||
166 | MRI.removeRegOperandFromUseList(&MO); | ||||||
167 | } | ||||||
168 | |||||||
169 | /// AddRegOperandsToUseLists - Add all of the register operands in | ||||||
170 | /// this instruction from their respective use lists. This requires that the | ||||||
171 | /// operands not be on their use lists yet. | ||||||
172 | void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) { | ||||||
173 | for (MachineOperand &MO : operands()) | ||||||
174 | if (MO.isReg()) | ||||||
175 | MRI.addRegOperandToUseList(&MO); | ||||||
176 | } | ||||||
177 | |||||||
178 | void MachineInstr::addOperand(const MachineOperand &Op) { | ||||||
179 | MachineBasicBlock *MBB = getParent(); | ||||||
180 | assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs")((MBB && "Use MachineInstrBuilder to add operands to dangling instrs" ) ? static_cast<void> (0) : __assert_fail ("MBB && \"Use MachineInstrBuilder to add operands to dangling instrs\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 180, __PRETTY_FUNCTION__)); | ||||||
181 | MachineFunction *MF = MBB->getParent(); | ||||||
182 | assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs")((MF && "Use MachineInstrBuilder to add operands to dangling instrs" ) ? static_cast<void> (0) : __assert_fail ("MF && \"Use MachineInstrBuilder to add operands to dangling instrs\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 182, __PRETTY_FUNCTION__)); | ||||||
183 | addOperand(*MF, Op); | ||||||
184 | } | ||||||
185 | |||||||
186 | /// Move NumOps MachineOperands from Src to Dst, with support for overlapping | ||||||
187 | /// ranges. If MRI is non-null also update use-def chains. | ||||||
188 | static void moveOperands(MachineOperand *Dst, MachineOperand *Src, | ||||||
189 | unsigned NumOps, MachineRegisterInfo *MRI) { | ||||||
190 | if (MRI
| ||||||
191 | return MRI->moveOperands(Dst, Src, NumOps); | ||||||
192 | |||||||
193 | // MachineOperand is a trivially copyable type so we can just use memmove. | ||||||
194 | std::memmove(Dst, Src, NumOps * sizeof(MachineOperand)); | ||||||
| |||||||
195 | } | ||||||
196 | |||||||
197 | /// addOperand - Add the specified operand to the instruction. If it is an | ||||||
198 | /// implicit operand, it is added to the end of the operand list. If it is | ||||||
199 | /// an explicit operand it is added at the end of the explicit operand list | ||||||
200 | /// (before the first implicit operand). | ||||||
201 | void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) { | ||||||
202 | assert(MCID && "Cannot add operands before providing an instr descriptor")((MCID && "Cannot add operands before providing an instr descriptor" ) ? static_cast<void> (0) : __assert_fail ("MCID && \"Cannot add operands before providing an instr descriptor\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 202, __PRETTY_FUNCTION__)); | ||||||
203 | |||||||
204 | // Check if we're adding one of our existing operands. | ||||||
205 | if (&Op >= Operands && &Op < Operands + NumOperands) { | ||||||
206 | // This is unusual: MI->addOperand(MI->getOperand(i)). | ||||||
207 | // If adding Op requires reallocating or moving existing operands around, | ||||||
208 | // the Op reference could go stale. Support it by copying Op. | ||||||
209 | MachineOperand CopyOp(Op); | ||||||
210 | return addOperand(MF, CopyOp); | ||||||
211 | } | ||||||
212 | |||||||
213 | // Find the insert location for the new operand. Implicit registers go at | ||||||
214 | // the end, everything else goes before the implicit regs. | ||||||
215 | // | ||||||
216 | // FIXME: Allow mixed explicit and implicit operands on inline asm. | ||||||
217 | // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as | ||||||
218 | // implicit-defs, but they must not be moved around. See the FIXME in | ||||||
219 | // InstrEmitter.cpp. | ||||||
220 | unsigned OpNo = getNumOperands(); | ||||||
221 | bool isImpReg = Op.isReg() && Op.isImplicit(); | ||||||
222 | if (!isImpReg
| ||||||
223 | while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { | ||||||
224 | --OpNo; | ||||||
225 | assert(!Operands[OpNo].isTied() && "Cannot move tied operands")((!Operands[OpNo].isTied() && "Cannot move tied operands" ) ? static_cast<void> (0) : __assert_fail ("!Operands[OpNo].isTied() && \"Cannot move tied operands\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 225, __PRETTY_FUNCTION__)); | ||||||
226 | } | ||||||
227 | } | ||||||
228 | |||||||
229 | #ifndef NDEBUG | ||||||
230 | bool isDebugOp = Op.getType() == MachineOperand::MO_Metadata || | ||||||
231 | Op.getType() == MachineOperand::MO_MCSymbol; | ||||||
232 | // OpNo now points as the desired insertion point. Unless this is a variadic | ||||||
233 | // instruction, only implicit regs are allowed beyond MCID->getNumOperands(). | ||||||
234 | // RegMask operands go between the explicit and implicit operands. | ||||||
235 | assert
< MCID->getNumOperands() || isDebugOp) && "Trying to add an operand to a machine instr that is already done!" ) ? static_cast<void> (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && \"Trying to add an operand to a machine instr that is already done!\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 237, __PRETTY_FUNCTION__)) | ||||||
236 | OpNo < MCID->getNumOperands() || isDebugOp) &&(((isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && "Trying to add an operand to a machine instr that is already done!" ) ? static_cast<void> (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && \"Trying to add an operand to a machine instr that is already done!\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 237, __PRETTY_FUNCTION__)) | ||||||
237 | "Trying to add an operand to a machine instr that is already done!")(((isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && "Trying to add an operand to a machine instr that is already done!" ) ? static_cast<void> (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && \"Trying to add an operand to a machine instr that is already done!\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 237, __PRETTY_FUNCTION__)); | ||||||
238 | #endif | ||||||
239 | |||||||
240 | MachineRegisterInfo *MRI = getRegInfo(); | ||||||
241 | |||||||
242 | // Determine if the Operands array needs to be reallocated. | ||||||
243 | // Save the old capacity and operand array. | ||||||
244 | OperandCapacity OldCap = CapOperands; | ||||||
245 | MachineOperand *OldOperands = Operands; | ||||||
246 | if (!OldOperands || OldCap.getSize() == getNumOperands()) { | ||||||
247 | CapOperands = OldOperands
| ||||||
248 | Operands = MF.allocateOperandArray(CapOperands); | ||||||
249 | // Move the operands before the insertion point. | ||||||
250 | if (OpNo) | ||||||
251 | moveOperands(Operands, OldOperands, OpNo, MRI); | ||||||
252 | } | ||||||
253 | |||||||
254 | // Move the operands following the insertion point. | ||||||
255 | if (OpNo != NumOperands) | ||||||
256 | moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo, | ||||||
257 | MRI); | ||||||
258 | ++NumOperands; | ||||||
259 | |||||||
260 | // Deallocate the old operand array. | ||||||
261 | if (OldOperands != Operands && OldOperands) | ||||||
262 | MF.deallocateOperandArray(OldCap, OldOperands); | ||||||
263 | |||||||
264 | // Copy Op into place. It still needs to be inserted into the MRI use lists. | ||||||
265 | MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op); | ||||||
266 | NewMO->ParentMI = this; | ||||||
267 | |||||||
268 | // When adding a register operand, tell MRI about it. | ||||||
269 | if (NewMO->isReg()) { | ||||||
270 | // Ensure isOnRegUseList() returns false, regardless of Op's status. | ||||||
271 | NewMO->Contents.Reg.Prev = nullptr; | ||||||
272 | // Ignore existing ties. This is not a property that can be copied. | ||||||
273 | NewMO->TiedTo = 0; | ||||||
274 | // Add the new operand to MRI, but only for instructions in an MBB. | ||||||
275 | if (MRI) | ||||||
276 | MRI->addRegOperandToUseList(NewMO); | ||||||
277 | // The MCID operand information isn't accurate until we start adding | ||||||
278 | // explicit operands. The implicit operands are added first, then the | ||||||
279 | // explicits are inserted before them. | ||||||
280 | if (!isImpReg) { | ||||||
281 | // Tie uses to defs as indicated in MCInstrDesc. | ||||||
282 | if (NewMO->isUse()) { | ||||||
283 | int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); | ||||||
284 | if (DefIdx != -1) | ||||||
285 | tieOperands(DefIdx, OpNo); | ||||||
286 | } | ||||||
287 | // If the register operand is flagged as early, mark the operand as such. | ||||||
288 | if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) | ||||||
289 | NewMO->setIsEarlyClobber(true); | ||||||
290 | } | ||||||
291 | } | ||||||
292 | } | ||||||
293 | |||||||
294 | /// RemoveOperand - Erase an operand from an instruction, leaving it with one | ||||||
295 | /// fewer operand than it started with. | ||||||
296 | /// | ||||||
297 | void MachineInstr::RemoveOperand(unsigned OpNo) { | ||||||
298 | assert(OpNo < getNumOperands() && "Invalid operand number")((OpNo < getNumOperands() && "Invalid operand number" ) ? static_cast<void> (0) : __assert_fail ("OpNo < getNumOperands() && \"Invalid operand number\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 298, __PRETTY_FUNCTION__)); | ||||||
299 | untieRegOperand(OpNo); | ||||||
300 | |||||||
301 | #ifndef NDEBUG | ||||||
302 | // Moving tied operands would break the ties. | ||||||
303 | for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i) | ||||||
304 | if (Operands[i].isReg()) | ||||||
305 | assert(!Operands[i].isTied() && "Cannot move tied operands")((!Operands[i].isTied() && "Cannot move tied operands" ) ? static_cast<void> (0) : __assert_fail ("!Operands[i].isTied() && \"Cannot move tied operands\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 305, __PRETTY_FUNCTION__)); | ||||||
306 | #endif | ||||||
307 | |||||||
308 | MachineRegisterInfo *MRI = getRegInfo(); | ||||||
309 | if (MRI && Operands[OpNo].isReg()) | ||||||
310 | MRI->removeRegOperandFromUseList(Operands + OpNo); | ||||||
311 | |||||||
312 | // Don't call the MachineOperand destructor. A lot of this code depends on | ||||||
313 | // MachineOperand having a trivial destructor anyway, and adding a call here | ||||||
314 | // wouldn't make it 'destructor-correct'. | ||||||
315 | |||||||
316 | if (unsigned N = NumOperands - 1 - OpNo) | ||||||
317 | moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI); | ||||||
318 | --NumOperands; | ||||||
319 | } | ||||||
320 | |||||||
321 | void MachineInstr::setExtraInfo(MachineFunction &MF, | ||||||
322 | ArrayRef<MachineMemOperand *> MMOs, | ||||||
323 | MCSymbol *PreInstrSymbol, | ||||||
324 | MCSymbol *PostInstrSymbol, | ||||||
325 | MDNode *HeapAllocMarker) { | ||||||
326 | bool HasPreInstrSymbol = PreInstrSymbol != nullptr; | ||||||
327 | bool HasPostInstrSymbol = PostInstrSymbol != nullptr; | ||||||
328 | bool HasHeapAllocMarker = HeapAllocMarker != nullptr; | ||||||
329 | int NumPointers = | ||||||
330 | MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol + HasHeapAllocMarker; | ||||||
331 | |||||||
332 | // Drop all extra info if there is none. | ||||||
333 | if (NumPointers <= 0) { | ||||||
334 | Info.clear(); | ||||||
335 | return; | ||||||
336 | } | ||||||
337 | |||||||
338 | // If more than one pointer, then store out of line. Store heap alloc markers | ||||||
339 | // out of line because PointerSumType cannot hold more than 4 tag types with | ||||||
340 | // 32-bit pointers. | ||||||
341 | // FIXME: Maybe we should make the symbols in the extra info mutable? | ||||||
342 | else if (NumPointers > 1 || HasHeapAllocMarker) { | ||||||
343 | Info.set<EIIK_OutOfLine>(MF.createMIExtraInfo( | ||||||
344 | MMOs, PreInstrSymbol, PostInstrSymbol, HeapAllocMarker)); | ||||||
345 | return; | ||||||
346 | } | ||||||
347 | |||||||
348 | // Otherwise store the single pointer inline. | ||||||
349 | if (HasPreInstrSymbol) | ||||||
350 | Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol); | ||||||
351 | else if (HasPostInstrSymbol) | ||||||
352 | Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol); | ||||||
353 | else | ||||||
354 | Info.set<EIIK_MMO>(MMOs[0]); | ||||||
355 | } | ||||||
356 | |||||||
357 | void MachineInstr::dropMemRefs(MachineFunction &MF) { | ||||||
358 | if (memoperands_empty()) | ||||||
359 | return; | ||||||
360 | |||||||
361 | setExtraInfo(MF, {}, getPreInstrSymbol(), getPostInstrSymbol(), | ||||||
362 | getHeapAllocMarker()); | ||||||
363 | } | ||||||
364 | |||||||
365 | void MachineInstr::setMemRefs(MachineFunction &MF, | ||||||
366 | ArrayRef<MachineMemOperand *> MMOs) { | ||||||
367 | if (MMOs.empty()) { | ||||||
368 | dropMemRefs(MF); | ||||||
369 | return; | ||||||
370 | } | ||||||
371 | |||||||
372 | setExtraInfo(MF, MMOs, getPreInstrSymbol(), getPostInstrSymbol(), | ||||||
373 | getHeapAllocMarker()); | ||||||
374 | } | ||||||
375 | |||||||
376 | void MachineInstr::addMemOperand(MachineFunction &MF, | ||||||
377 | MachineMemOperand *MO) { | ||||||
378 | SmallVector<MachineMemOperand *, 2> MMOs; | ||||||
379 | MMOs.append(memoperands_begin(), memoperands_end()); | ||||||
380 | MMOs.push_back(MO); | ||||||
381 | setMemRefs(MF, MMOs); | ||||||
382 | } | ||||||
383 | |||||||
384 | void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) { | ||||||
385 | if (this == &MI) | ||||||
386 | // Nothing to do for a self-clone! | ||||||
387 | return; | ||||||
388 | |||||||
389 | assert(&MF == MI.getMF() &&((&MF == MI.getMF() && "Invalid machine functions when cloning memory refrences!" ) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory refrences!\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 390, __PRETTY_FUNCTION__)) | ||||||
390 | "Invalid machine functions when cloning memory refrences!")((&MF == MI.getMF() && "Invalid machine functions when cloning memory refrences!" ) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory refrences!\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 390, __PRETTY_FUNCTION__)); | ||||||
391 | // See if we can just steal the extra info already allocated for the | ||||||
392 | // instruction. We can do this whenever the pre- and post-instruction symbols | ||||||
393 | // are the same (including null). | ||||||
394 | if (getPreInstrSymbol() == MI.getPreInstrSymbol() && | ||||||
395 | getPostInstrSymbol() == MI.getPostInstrSymbol() && | ||||||
396 | getHeapAllocMarker() == MI.getHeapAllocMarker()) { | ||||||
397 | Info = MI.Info; | ||||||
398 | return; | ||||||
399 | } | ||||||
400 | |||||||
401 | // Otherwise, fall back on a copy-based clone. | ||||||
402 | setMemRefs(MF, MI.memoperands()); | ||||||
403 | } | ||||||
404 | |||||||
405 | /// Check to see if the MMOs pointed to by the two MemRefs arrays are | ||||||
406 | /// identical. | ||||||
407 | static bool hasIdenticalMMOs(ArrayRef<MachineMemOperand *> LHS, | ||||||
408 | ArrayRef<MachineMemOperand *> RHS) { | ||||||
409 | if (LHS.size() != RHS.size()) | ||||||
410 | return false; | ||||||
411 | |||||||
412 | auto LHSPointees = make_pointee_range(LHS); | ||||||
413 | auto RHSPointees = make_pointee_range(RHS); | ||||||
414 | return std::equal(LHSPointees.begin(), LHSPointees.end(), | ||||||
415 | RHSPointees.begin()); | ||||||
416 | } | ||||||
417 | |||||||
418 | void MachineInstr::cloneMergedMemRefs(MachineFunction &MF, | ||||||
419 | ArrayRef<const MachineInstr *> MIs) { | ||||||
420 | // Try handling easy numbers of MIs with simpler mechanisms. | ||||||
421 | if (MIs.empty()) { | ||||||
422 | dropMemRefs(MF); | ||||||
423 | return; | ||||||
424 | } | ||||||
425 | if (MIs.size() == 1) { | ||||||
426 | cloneMemRefs(MF, *MIs[0]); | ||||||
427 | return; | ||||||
428 | } | ||||||
429 | // Because an empty memoperands list provides *no* information and must be | ||||||
430 | // handled conservatively (assuming the instruction can do anything), the only | ||||||
431 | // way to merge with it is to drop all other memoperands. | ||||||
432 | if (MIs[0]->memoperands_empty()) { | ||||||
433 | dropMemRefs(MF); | ||||||
434 | return; | ||||||
435 | } | ||||||
436 | |||||||
437 | // Handle the general case. | ||||||
438 | SmallVector<MachineMemOperand *, 2> MergedMMOs; | ||||||
439 | // Start with the first instruction. | ||||||
440 | assert(&MF == MIs[0]->getMF() &&((&MF == MIs[0]->getMF() && "Invalid machine functions when cloning memory references!" ) ? static_cast<void> (0) : __assert_fail ("&MF == MIs[0]->getMF() && \"Invalid machine functions when cloning memory references!\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 441, __PRETTY_FUNCTION__)) | ||||||
441 | "Invalid machine functions when cloning memory references!")((&MF == MIs[0]->getMF() && "Invalid machine functions when cloning memory references!" ) ? static_cast<void> (0) : __assert_fail ("&MF == MIs[0]->getMF() && \"Invalid machine functions when cloning memory references!\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 441, __PRETTY_FUNCTION__)); | ||||||
442 | MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end()); | ||||||
443 | // Now walk all the other instructions and accumulate any different MMOs. | ||||||
444 | for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) { | ||||||
445 | assert(&MF == MI.getMF() &&((&MF == MI.getMF() && "Invalid machine functions when cloning memory references!" ) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory references!\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 446, __PRETTY_FUNCTION__)) | ||||||
446 | "Invalid machine functions when cloning memory references!")((&MF == MI.getMF() && "Invalid machine functions when cloning memory references!" ) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory references!\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 446, __PRETTY_FUNCTION__)); | ||||||
447 | |||||||
448 | // Skip MIs with identical operands to the first. This is a somewhat | ||||||
449 | // arbitrary hack but will catch common cases without being quadratic. | ||||||
450 | // TODO: We could fully implement merge semantics here if needed. | ||||||
451 | if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands())) | ||||||
452 | continue; | ||||||
453 | |||||||
454 | // Because an empty memoperands list provides *no* information and must be | ||||||
455 | // handled conservatively (assuming the instruction can do anything), the | ||||||
456 | // only way to merge with it is to drop all other memoperands. | ||||||
457 | if (MI.memoperands_empty()) { | ||||||
458 | dropMemRefs(MF); | ||||||
459 | return; | ||||||
460 | } | ||||||
461 | |||||||
462 | // Otherwise accumulate these into our temporary buffer of the merged state. | ||||||
463 | MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end()); | ||||||
464 | } | ||||||
465 | |||||||
466 | setMemRefs(MF, MergedMMOs); | ||||||
467 | } | ||||||
468 | |||||||
469 | void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) { | ||||||
470 | // Do nothing if old and new symbols are the same. | ||||||
471 | if (Symbol == getPreInstrSymbol()) | ||||||
472 | return; | ||||||
473 | |||||||
474 | // If there was only one symbol and we're removing it, just clear info. | ||||||
475 | if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) { | ||||||
476 | Info.clear(); | ||||||
477 | return; | ||||||
478 | } | ||||||
479 | |||||||
480 | setExtraInfo(MF, memoperands(), Symbol, getPostInstrSymbol(), | ||||||
481 | getHeapAllocMarker()); | ||||||
482 | } | ||||||
483 | |||||||
484 | void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) { | ||||||
485 | // Do nothing if old and new symbols are the same. | ||||||
486 | if (Symbol == getPostInstrSymbol()) | ||||||
487 | return; | ||||||
488 | |||||||
489 | // If there was only one symbol and we're removing it, just clear info. | ||||||
490 | if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) { | ||||||
491 | Info.clear(); | ||||||
492 | return; | ||||||
493 | } | ||||||
494 | |||||||
495 | setExtraInfo(MF, memoperands(), getPreInstrSymbol(), Symbol, | ||||||
496 | getHeapAllocMarker()); | ||||||
497 | } | ||||||
498 | |||||||
499 | void MachineInstr::setHeapAllocMarker(MachineFunction &MF, MDNode *Marker) { | ||||||
500 | // Do nothing if old and new symbols are the same. | ||||||
501 | if (Marker == getHeapAllocMarker()) | ||||||
502 | return; | ||||||
503 | |||||||
504 | setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(), | ||||||
505 | Marker); | ||||||
506 | } | ||||||
507 | |||||||
508 | void MachineInstr::cloneInstrSymbols(MachineFunction &MF, | ||||||
509 | const MachineInstr &MI) { | ||||||
510 | if (this == &MI) | ||||||
511 | // Nothing to do for a self-clone! | ||||||
512 | return; | ||||||
513 | |||||||
514 | assert(&MF == MI.getMF() &&((&MF == MI.getMF() && "Invalid machine functions when cloning instruction symbols!" ) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning instruction symbols!\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 515, __PRETTY_FUNCTION__)) | ||||||
515 | "Invalid machine functions when cloning instruction symbols!")((&MF == MI.getMF() && "Invalid machine functions when cloning instruction symbols!" ) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning instruction symbols!\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 515, __PRETTY_FUNCTION__)); | ||||||
516 | |||||||
517 | setPreInstrSymbol(MF, MI.getPreInstrSymbol()); | ||||||
518 | setPostInstrSymbol(MF, MI.getPostInstrSymbol()); | ||||||
519 | setHeapAllocMarker(MF, MI.getHeapAllocMarker()); | ||||||
520 | } | ||||||
521 | |||||||
522 | uint16_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const { | ||||||
523 | // For now, the just return the union of the flags. If the flags get more | ||||||
524 | // complicated over time, we might need more logic here. | ||||||
525 | return getFlags() | Other.getFlags(); | ||||||
526 | } | ||||||
527 | |||||||
528 | uint16_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) { | ||||||
529 | uint16_t MIFlags = 0; | ||||||
530 | // Copy the wrapping flags. | ||||||
531 | if (const OverflowingBinaryOperator *OB = | ||||||
532 | dyn_cast<OverflowingBinaryOperator>(&I)) { | ||||||
533 | if (OB->hasNoSignedWrap()) | ||||||
534 | MIFlags |= MachineInstr::MIFlag::NoSWrap; | ||||||
535 | if (OB->hasNoUnsignedWrap()) | ||||||
536 | MIFlags |= MachineInstr::MIFlag::NoUWrap; | ||||||
537 | } | ||||||
538 | |||||||
539 | // Copy the exact flag. | ||||||
540 | if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I)) | ||||||
541 | if (PE->isExact()) | ||||||
542 | MIFlags |= MachineInstr::MIFlag::IsExact; | ||||||
543 | |||||||
544 | // Copy the fast-math flags. | ||||||
545 | if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) { | ||||||
546 | const FastMathFlags Flags = FP->getFastMathFlags(); | ||||||
547 | if (Flags.noNaNs()) | ||||||
548 | MIFlags |= MachineInstr::MIFlag::FmNoNans; | ||||||
549 | if (Flags.noInfs()) | ||||||
550 | MIFlags |= MachineInstr::MIFlag::FmNoInfs; | ||||||
551 | if (Flags.noSignedZeros()) | ||||||
552 | MIFlags |= MachineInstr::MIFlag::FmNsz; | ||||||
553 | if (Flags.allowReciprocal()) | ||||||
554 | MIFlags |= MachineInstr::MIFlag::FmArcp; | ||||||
555 | if (Flags.allowContract()) | ||||||
556 | MIFlags |= MachineInstr::MIFlag::FmContract; | ||||||
557 | if (Flags.approxFunc()) | ||||||
558 | MIFlags |= MachineInstr::MIFlag::FmAfn; | ||||||
559 | if (Flags.allowReassoc()) | ||||||
560 | MIFlags |= MachineInstr::MIFlag::FmReassoc; | ||||||
561 | } | ||||||
562 | |||||||
563 | return MIFlags; | ||||||
564 | } | ||||||
565 | |||||||
566 | void MachineInstr::copyIRFlags(const Instruction &I) { | ||||||
567 | Flags = copyFlagsFromInstruction(I); | ||||||
568 | } | ||||||
569 | |||||||
570 | bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const { | ||||||
571 | assert(!isBundledWithPred() && "Must be called on bundle header")((!isBundledWithPred() && "Must be called on bundle header" ) ? static_cast<void> (0) : __assert_fail ("!isBundledWithPred() && \"Must be called on bundle header\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 571, __PRETTY_FUNCTION__)); | ||||||
572 | for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) { | ||||||
573 | if (MII->getDesc().getFlags() & Mask) { | ||||||
574 | if (Type == AnyInBundle) | ||||||
575 | return true; | ||||||
576 | } else { | ||||||
577 | if (Type == AllInBundle && !MII->isBundle()) | ||||||
578 | return false; | ||||||
579 | } | ||||||
580 | // This was the last instruction in the bundle. | ||||||
581 | if (!MII->isBundledWithSucc()) | ||||||
582 | return Type == AllInBundle; | ||||||
583 | } | ||||||
584 | } | ||||||
585 | |||||||
586 | bool MachineInstr::isIdenticalTo(const MachineInstr &Other, | ||||||
587 | MICheckType Check) const { | ||||||
588 | // If opcodes or number of operands are not the same then the two | ||||||
589 | // instructions are obviously not identical. | ||||||
590 | if (Other.getOpcode() != getOpcode() || | ||||||
591 | Other.getNumOperands() != getNumOperands()) | ||||||
592 | return false; | ||||||
593 | |||||||
594 | if (isBundle()) { | ||||||
595 | // We have passed the test above that both instructions have the same | ||||||
596 | // opcode, so we know that both instructions are bundles here. Let's compare | ||||||
597 | // MIs inside the bundle. | ||||||
598 | assert(Other.isBundle() && "Expected that both instructions are bundles.")((Other.isBundle() && "Expected that both instructions are bundles." ) ? static_cast<void> (0) : __assert_fail ("Other.isBundle() && \"Expected that both instructions are bundles.\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 598, __PRETTY_FUNCTION__)); | ||||||
599 | MachineBasicBlock::const_instr_iterator I1 = getIterator(); | ||||||
600 | MachineBasicBlock::const_instr_iterator I2 = Other.getIterator(); | ||||||
601 | // Loop until we analysed the last intruction inside at least one of the | ||||||
602 | // bundles. | ||||||
603 | while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) { | ||||||
604 | ++I1; | ||||||
605 | ++I2; | ||||||
606 | if (!I1->isIdenticalTo(*I2, Check)) | ||||||
607 | return false; | ||||||
608 | } | ||||||
609 | // If we've reached the end of just one of the two bundles, but not both, | ||||||
610 | // the instructions are not identical. | ||||||
611 | if (I1->isBundledWithSucc() || I2->isBundledWithSucc()) | ||||||
612 | return false; | ||||||
613 | } | ||||||
614 | |||||||
615 | // Check operands to make sure they match. | ||||||
616 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { | ||||||
617 | const MachineOperand &MO = getOperand(i); | ||||||
618 | const MachineOperand &OMO = Other.getOperand(i); | ||||||
619 | if (!MO.isReg()) { | ||||||
620 | if (!MO.isIdenticalTo(OMO)) | ||||||
621 | return false; | ||||||
622 | continue; | ||||||
623 | } | ||||||
624 | |||||||
625 | // Clients may or may not want to ignore defs when testing for equality. | ||||||
626 | // For example, machine CSE pass only cares about finding common | ||||||
627 | // subexpressions, so it's safe to ignore virtual register defs. | ||||||
628 | if (MO.isDef()) { | ||||||
629 | if (Check == IgnoreDefs) | ||||||
630 | continue; | ||||||
631 | else if (Check == IgnoreVRegDefs) { | ||||||
632 | if (!Register::isVirtualRegister(MO.getReg()) || | ||||||
633 | !Register::isVirtualRegister(OMO.getReg())) | ||||||
634 | if (!MO.isIdenticalTo(OMO)) | ||||||
635 | return false; | ||||||
636 | } else { | ||||||
637 | if (!MO.isIdenticalTo(OMO)) | ||||||
638 | return false; | ||||||
639 | if (Check == CheckKillDead && MO.isDead() != OMO.isDead()) | ||||||
640 | return false; | ||||||
641 | } | ||||||
642 | } else { | ||||||
643 | if (!MO.isIdenticalTo(OMO)) | ||||||
644 | return false; | ||||||
645 | if (Check == CheckKillDead && MO.isKill() != OMO.isKill()) | ||||||
646 | return false; | ||||||
647 | } | ||||||
648 | } | ||||||
649 | // If DebugLoc does not match then two debug instructions are not identical. | ||||||
650 | if (isDebugInstr()) | ||||||
651 | if (getDebugLoc() && Other.getDebugLoc() && | ||||||
652 | getDebugLoc() != Other.getDebugLoc()) | ||||||
653 | return false; | ||||||
654 | return true; | ||||||
655 | } | ||||||
656 | |||||||
657 | const MachineFunction *MachineInstr::getMF() const { | ||||||
658 | return getParent()->getParent(); | ||||||
659 | } | ||||||
660 | |||||||
661 | MachineInstr *MachineInstr::removeFromParent() { | ||||||
662 | assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast <void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 662, __PRETTY_FUNCTION__)); | ||||||
663 | return getParent()->remove(this); | ||||||
664 | } | ||||||
665 | |||||||
666 | MachineInstr *MachineInstr::removeFromBundle() { | ||||||
667 | assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast <void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 667, __PRETTY_FUNCTION__)); | ||||||
668 | return getParent()->remove_instr(this); | ||||||
669 | } | ||||||
670 | |||||||
671 | void MachineInstr::eraseFromParent() { | ||||||
672 | assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast <void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 672, __PRETTY_FUNCTION__)); | ||||||
673 | getParent()->erase(this); | ||||||
674 | } | ||||||
675 | |||||||
676 | void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() { | ||||||
677 | assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast <void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 677, __PRETTY_FUNCTION__)); | ||||||
678 | MachineBasicBlock *MBB = getParent(); | ||||||
679 | MachineFunction *MF = MBB->getParent(); | ||||||
680 | assert(MF && "Not embedded in a function!")((MF && "Not embedded in a function!") ? static_cast< void> (0) : __assert_fail ("MF && \"Not embedded in a function!\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 680, __PRETTY_FUNCTION__)); | ||||||
681 | |||||||
682 | MachineInstr *MI = (MachineInstr *)this; | ||||||
683 | MachineRegisterInfo &MRI = MF->getRegInfo(); | ||||||
684 | |||||||
685 | for (const MachineOperand &MO : MI->operands()) { | ||||||
686 | if (!MO.isReg() || !MO.isDef()) | ||||||
687 | continue; | ||||||
688 | Register Reg = MO.getReg(); | ||||||
689 | if (!Reg.isVirtual()) | ||||||
690 | continue; | ||||||
691 | MRI.markUsesInDebugValueAsUndef(Reg); | ||||||
692 | } | ||||||
693 | MI->eraseFromParent(); | ||||||
694 | } | ||||||
695 | |||||||
696 | void MachineInstr::eraseFromBundle() { | ||||||
697 | assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast <void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 697, __PRETTY_FUNCTION__)); | ||||||
698 | getParent()->erase_instr(this); | ||||||
699 | } | ||||||
700 | |||||||
701 | unsigned MachineInstr::getNumExplicitOperands() const { | ||||||
702 | unsigned NumOperands = MCID->getNumOperands(); | ||||||
703 | if (!MCID->isVariadic()) | ||||||
704 | return NumOperands; | ||||||
705 | |||||||
706 | for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) { | ||||||
707 | const MachineOperand &MO = getOperand(I); | ||||||
708 | // The operands must always be in the following order: | ||||||
709 | // - explicit reg defs, | ||||||
710 | // - other explicit operands (reg uses, immediates, etc.), | ||||||
711 | // - implicit reg defs | ||||||
712 | // - implicit reg uses | ||||||
713 | if (MO.isReg() && MO.isImplicit()) | ||||||
714 | break; | ||||||
715 | ++NumOperands; | ||||||
716 | } | ||||||
717 | return NumOperands; | ||||||
718 | } | ||||||
719 | |||||||
720 | unsigned MachineInstr::getNumExplicitDefs() const { | ||||||
721 | unsigned NumDefs = MCID->getNumDefs(); | ||||||
722 | if (!MCID->isVariadic()) | ||||||
723 | return NumDefs; | ||||||
724 | |||||||
725 | for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) { | ||||||
726 | const MachineOperand &MO = getOperand(I); | ||||||
727 | if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) | ||||||
728 | break; | ||||||
729 | ++NumDefs; | ||||||
730 | } | ||||||
731 | return NumDefs; | ||||||
732 | } | ||||||
733 | |||||||
734 | void MachineInstr::bundleWithPred() { | ||||||
735 | assert(!isBundledWithPred() && "MI is already bundled with its predecessor")((!isBundledWithPred() && "MI is already bundled with its predecessor" ) ? static_cast<void> (0) : __assert_fail ("!isBundledWithPred() && \"MI is already bundled with its predecessor\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 735, __PRETTY_FUNCTION__)); | ||||||
736 | setFlag(BundledPred); | ||||||
737 | MachineBasicBlock::instr_iterator Pred = getIterator(); | ||||||
738 | --Pred; | ||||||
739 | assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags")((!Pred->isBundledWithSucc() && "Inconsistent bundle flags" ) ? static_cast<void> (0) : __assert_fail ("!Pred->isBundledWithSucc() && \"Inconsistent bundle flags\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 739, __PRETTY_FUNCTION__)); | ||||||
740 | Pred->setFlag(BundledSucc); | ||||||
741 | } | ||||||
742 | |||||||
743 | void MachineInstr::bundleWithSucc() { | ||||||
744 | assert(!isBundledWithSucc() && "MI is already bundled with its successor")((!isBundledWithSucc() && "MI is already bundled with its successor" ) ? static_cast<void> (0) : __assert_fail ("!isBundledWithSucc() && \"MI is already bundled with its successor\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 744, __PRETTY_FUNCTION__)); | ||||||
745 | setFlag(BundledSucc); | ||||||
746 | MachineBasicBlock::instr_iterator Succ = getIterator(); | ||||||
747 | ++Succ; | ||||||
748 | assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags")((!Succ->isBundledWithPred() && "Inconsistent bundle flags" ) ? static_cast<void> (0) : __assert_fail ("!Succ->isBundledWithPred() && \"Inconsistent bundle flags\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 748, __PRETTY_FUNCTION__)); | ||||||
749 | Succ->setFlag(BundledPred); | ||||||
750 | } | ||||||
751 | |||||||
752 | void MachineInstr::unbundleFromPred() { | ||||||
753 | assert(isBundledWithPred() && "MI isn't bundled with its predecessor")((isBundledWithPred() && "MI isn't bundled with its predecessor" ) ? static_cast<void> (0) : __assert_fail ("isBundledWithPred() && \"MI isn't bundled with its predecessor\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 753, __PRETTY_FUNCTION__)); | ||||||
754 | clearFlag(BundledPred); | ||||||
755 | MachineBasicBlock::instr_iterator Pred = getIterator(); | ||||||
756 | --Pred; | ||||||
757 | assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags")((Pred->isBundledWithSucc() && "Inconsistent bundle flags" ) ? static_cast<void> (0) : __assert_fail ("Pred->isBundledWithSucc() && \"Inconsistent bundle flags\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 757, __PRETTY_FUNCTION__)); | ||||||
758 | Pred->clearFlag(BundledSucc); | ||||||
759 | } | ||||||
760 | |||||||
761 | void MachineInstr::unbundleFromSucc() { | ||||||
762 | assert(isBundledWithSucc() && "MI isn't bundled with its successor")((isBundledWithSucc() && "MI isn't bundled with its successor" ) ? static_cast<void> (0) : __assert_fail ("isBundledWithSucc() && \"MI isn't bundled with its successor\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 762, __PRETTY_FUNCTION__)); | ||||||
763 | clearFlag(BundledSucc); | ||||||
764 | MachineBasicBlock::instr_iterator Succ = getIterator(); | ||||||
765 | ++Succ; | ||||||
766 | assert(Succ->isBundledWithPred() && "Inconsistent bundle flags")((Succ->isBundledWithPred() && "Inconsistent bundle flags" ) ? static_cast<void> (0) : __assert_fail ("Succ->isBundledWithPred() && \"Inconsistent bundle flags\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 766, __PRETTY_FUNCTION__)); | ||||||
767 | Succ->clearFlag(BundledPred); | ||||||
768 | } | ||||||
769 | |||||||
770 | bool MachineInstr::isStackAligningInlineAsm() const { | ||||||
771 | if (isInlineAsm()) { | ||||||
772 | unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); | ||||||
773 | if (ExtraInfo & InlineAsm::Extra_IsAlignStack) | ||||||
774 | return true; | ||||||
775 | } | ||||||
776 | return false; | ||||||
777 | } | ||||||
778 | |||||||
779 | InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const { | ||||||
780 | assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!")((isInlineAsm() && "getInlineAsmDialect() only works for inline asms!" ) ? static_cast<void> (0) : __assert_fail ("isInlineAsm() && \"getInlineAsmDialect() only works for inline asms!\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 780, __PRETTY_FUNCTION__)); | ||||||
781 | unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); | ||||||
782 | return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0); | ||||||
783 | } | ||||||
784 | |||||||
785 | int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, | ||||||
786 | unsigned *GroupNo) const { | ||||||
787 | assert(isInlineAsm() && "Expected an inline asm instruction")((isInlineAsm() && "Expected an inline asm instruction" ) ? static_cast<void> (0) : __assert_fail ("isInlineAsm() && \"Expected an inline asm instruction\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 787, __PRETTY_FUNCTION__)); | ||||||
788 | assert(OpIdx < getNumOperands() && "OpIdx out of range")((OpIdx < getNumOperands() && "OpIdx out of range" ) ? static_cast<void> (0) : __assert_fail ("OpIdx < getNumOperands() && \"OpIdx out of range\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 788, __PRETTY_FUNCTION__)); | ||||||
789 | |||||||
790 | // Ignore queries about the initial operands. | ||||||
791 | if (OpIdx < InlineAsm::MIOp_FirstOperand) | ||||||
792 | return -1; | ||||||
793 | |||||||
794 | unsigned Group = 0; | ||||||
795 | unsigned NumOps; | ||||||
796 | for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e; | ||||||
797 | i += NumOps) { | ||||||
798 | const MachineOperand &FlagMO = getOperand(i); | ||||||
799 | // If we reach the implicit register operands, stop looking. | ||||||
800 | if (!FlagMO.isImm()) | ||||||
801 | return -1; | ||||||
802 | NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm()); | ||||||
803 | if (i + NumOps > OpIdx) { | ||||||
804 | if (GroupNo) | ||||||
805 | *GroupNo = Group; | ||||||
806 | return i; | ||||||
807 | } | ||||||
808 | ++Group; | ||||||
809 | } | ||||||
810 | return -1; | ||||||
811 | } | ||||||
812 | |||||||
813 | const DILabel *MachineInstr::getDebugLabel() const { | ||||||
814 | assert(isDebugLabel() && "not a DBG_LABEL")((isDebugLabel() && "not a DBG_LABEL") ? static_cast< void> (0) : __assert_fail ("isDebugLabel() && \"not a DBG_LABEL\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 814, __PRETTY_FUNCTION__)); | ||||||
815 | return cast<DILabel>(getOperand(0).getMetadata()); | ||||||
816 | } | ||||||
817 | |||||||
818 | const DILocalVariable *MachineInstr::getDebugVariable() const { | ||||||
819 | assert(isDebugValue() && "not a DBG_VALUE")((isDebugValue() && "not a DBG_VALUE") ? static_cast< void> (0) : __assert_fail ("isDebugValue() && \"not a DBG_VALUE\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 819, __PRETTY_FUNCTION__)); | ||||||
820 | return cast<DILocalVariable>(getOperand(2).getMetadata()); | ||||||
821 | } | ||||||
822 | |||||||
823 | const DIExpression *MachineInstr::getDebugExpression() const { | ||||||
824 | assert(isDebugValue() && "not a DBG_VALUE")((isDebugValue() && "not a DBG_VALUE") ? static_cast< void> (0) : __assert_fail ("isDebugValue() && \"not a DBG_VALUE\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 824, __PRETTY_FUNCTION__)); | ||||||
825 | return cast<DIExpression>(getOperand(3).getMetadata()); | ||||||
826 | } | ||||||
827 | |||||||
828 | bool MachineInstr::isDebugEntryValue() const { | ||||||
829 | return isDebugValue() && getDebugExpression()->isEntryValue(); | ||||||
830 | } | ||||||
831 | |||||||
832 | const TargetRegisterClass* | ||||||
833 | MachineInstr::getRegClassConstraint(unsigned OpIdx, | ||||||
834 | const TargetInstrInfo *TII, | ||||||
835 | const TargetRegisterInfo *TRI) const { | ||||||
836 | assert(getParent() && "Can't have an MBB reference here!")((getParent() && "Can't have an MBB reference here!") ? static_cast<void> (0) : __assert_fail ("getParent() && \"Can't have an MBB reference here!\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 836, __PRETTY_FUNCTION__)); | ||||||
837 | assert(getMF() && "Can't have an MF reference here!")((getMF() && "Can't have an MF reference here!") ? static_cast <void> (0) : __assert_fail ("getMF() && \"Can't have an MF reference here!\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 837, __PRETTY_FUNCTION__)); | ||||||
838 | const MachineFunction &MF = *getMF(); | ||||||
839 | |||||||
840 | // Most opcodes have fixed constraints in their MCInstrDesc. | ||||||
841 | if (!isInlineAsm()) | ||||||
842 | return TII->getRegClass(getDesc(), OpIdx, TRI, MF); | ||||||
843 | |||||||
844 | if (!getOperand(OpIdx).isReg()) | ||||||
845 | return nullptr; | ||||||
846 | |||||||
847 | // For tied uses on inline asm, get the constraint from the def. | ||||||
848 | unsigned DefIdx; | ||||||
849 | if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) | ||||||
850 | OpIdx = DefIdx; | ||||||
851 | |||||||
852 | // Inline asm stores register class constraints in the flag word. | ||||||
853 | int FlagIdx = findInlineAsmFlagIdx(OpIdx); | ||||||
854 | if (FlagIdx < 0) | ||||||
855 | return nullptr; | ||||||
856 | |||||||
857 | unsigned Flag = getOperand(FlagIdx).getImm(); | ||||||
858 | unsigned RCID; | ||||||
859 | if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse || | ||||||
860 | InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef || | ||||||
861 | InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) && | ||||||
862 | InlineAsm::hasRegClassConstraint(Flag, RCID)) | ||||||
863 | return TRI->getRegClass(RCID); | ||||||
864 | |||||||
865 | // Assume that all registers in a memory operand are pointers. | ||||||
866 | if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem) | ||||||
867 | return TRI->getPointerRegClass(MF); | ||||||
868 | |||||||
869 | return nullptr; | ||||||
870 | } | ||||||
871 | |||||||
872 | const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg( | ||||||
873 | Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, | ||||||
874 | const TargetRegisterInfo *TRI, bool ExploreBundle) const { | ||||||
875 | // Check every operands inside the bundle if we have | ||||||
876 | // been asked to. | ||||||
877 | if (ExploreBundle) | ||||||
878 | for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC; | ||||||
879 | ++OpndIt) | ||||||
880 | CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl( | ||||||
881 | OpndIt.getOperandNo(), Reg, CurRC, TII, TRI); | ||||||
882 | else | ||||||
883 | // Otherwise, just check the current operands. | ||||||
884 | for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i) | ||||||
885 | CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI); | ||||||
886 | return CurRC; | ||||||
887 | } | ||||||
888 | |||||||
889 | const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl( | ||||||
890 | unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC, | ||||||
891 | const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const { | ||||||
892 | assert(CurRC && "Invalid initial register class")((CurRC && "Invalid initial register class") ? static_cast <void> (0) : __assert_fail ("CurRC && \"Invalid initial register class\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 892, __PRETTY_FUNCTION__)); | ||||||
893 | // Check if Reg is constrained by some of its use/def from MI. | ||||||
894 | const MachineOperand &MO = getOperand(OpIdx); | ||||||
895 | if (!MO.isReg() || MO.getReg() != Reg) | ||||||
896 | return CurRC; | ||||||
897 | // If yes, accumulate the constraints through the operand. | ||||||
898 | return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI); | ||||||
899 | } | ||||||
900 | |||||||
901 | const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect( | ||||||
902 | unsigned OpIdx, const TargetRegisterClass *CurRC, | ||||||
903 | const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const { | ||||||
904 | const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); | ||||||
905 | const MachineOperand &MO = getOperand(OpIdx); | ||||||
906 | assert(MO.isReg() &&((MO.isReg() && "Cannot get register constraints for non-register operand" ) ? static_cast<void> (0) : __assert_fail ("MO.isReg() && \"Cannot get register constraints for non-register operand\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 907, __PRETTY_FUNCTION__)) | ||||||
907 | "Cannot get register constraints for non-register operand")((MO.isReg() && "Cannot get register constraints for non-register operand" ) ? static_cast<void> (0) : __assert_fail ("MO.isReg() && \"Cannot get register constraints for non-register operand\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 907, __PRETTY_FUNCTION__)); | ||||||
908 | assert(CurRC && "Invalid initial register class")((CurRC && "Invalid initial register class") ? static_cast <void> (0) : __assert_fail ("CurRC && \"Invalid initial register class\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 908, __PRETTY_FUNCTION__)); | ||||||
909 | if (unsigned SubIdx = MO.getSubReg()) { | ||||||
910 | if (OpRC) | ||||||
911 | CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx); | ||||||
912 | else | ||||||
913 | CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx); | ||||||
914 | } else if (OpRC) | ||||||
915 | CurRC = TRI->getCommonSubClass(CurRC, OpRC); | ||||||
916 | return CurRC; | ||||||
917 | } | ||||||
918 | |||||||
919 | /// Return the number of instructions inside the MI bundle, not counting the | ||||||
920 | /// header instruction. | ||||||
921 | unsigned MachineInstr::getBundleSize() const { | ||||||
922 | MachineBasicBlock::const_instr_iterator I = getIterator(); | ||||||
923 | unsigned Size = 0; | ||||||
924 | while (I->isBundledWithSucc()) { | ||||||
925 | ++Size; | ||||||
926 | ++I; | ||||||
927 | } | ||||||
928 | return Size; | ||||||
929 | } | ||||||
930 | |||||||
931 | /// Returns true if the MachineInstr has an implicit-use operand of exactly | ||||||
932 | /// the given register (not considering sub/super-registers). | ||||||
933 | bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const { | ||||||
934 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { | ||||||
935 | const MachineOperand &MO = getOperand(i); | ||||||
936 | if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg) | ||||||
937 | return true; | ||||||
938 | } | ||||||
939 | return false; | ||||||
940 | } | ||||||
941 | |||||||
942 | /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of | ||||||
943 | /// the specific register or -1 if it is not found. It further tightens | ||||||
944 | /// the search criteria to a use that kills the register if isKill is true. | ||||||
945 | int MachineInstr::findRegisterUseOperandIdx( | ||||||
946 | Register Reg, bool isKill, const TargetRegisterInfo *TRI) const { | ||||||
947 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { | ||||||
948 | const MachineOperand &MO = getOperand(i); | ||||||
949 | if (!MO.isReg() || !MO.isUse()) | ||||||
950 | continue; | ||||||
951 | Register MOReg = MO.getReg(); | ||||||
952 | if (!MOReg) | ||||||
953 | continue; | ||||||
954 | if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg))) | ||||||
955 | if (!isKill || MO.isKill()) | ||||||
956 | return i; | ||||||
957 | } | ||||||
958 | return -1; | ||||||
959 | } | ||||||
960 | |||||||
961 | /// readsWritesVirtualRegister - Return a pair of bools (reads, writes) | ||||||
962 | /// indicating if this instruction reads or writes Reg. This also considers | ||||||
963 | /// partial defines. | ||||||
964 | std::pair<bool,bool> | ||||||
965 | MachineInstr::readsWritesVirtualRegister(Register Reg, | ||||||
966 | SmallVectorImpl<unsigned> *Ops) const { | ||||||
967 | bool PartDef = false; // Partial redefine. | ||||||
968 | bool FullDef = false; // Full define. | ||||||
969 | bool Use = false; | ||||||
970 | |||||||
971 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { | ||||||
972 | const MachineOperand &MO = getOperand(i); | ||||||
973 | if (!MO.isReg() || MO.getReg() != Reg) | ||||||
974 | continue; | ||||||
975 | if (Ops) | ||||||
976 | Ops->push_back(i); | ||||||
977 | if (MO.isUse()) | ||||||
978 | Use |= !MO.isUndef(); | ||||||
979 | else if (MO.getSubReg() && !MO.isUndef()) | ||||||
980 | // A partial def undef doesn't count as reading the register. | ||||||
981 | PartDef = true; | ||||||
982 | else | ||||||
983 | FullDef = true; | ||||||
984 | } | ||||||
985 | // A partial redefine uses Reg unless there is also a full define. | ||||||
986 | return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef); | ||||||
987 | } | ||||||
988 | |||||||
989 | /// findRegisterDefOperandIdx() - Returns the operand index that is a def of | ||||||
990 | /// the specified register or -1 if it is not found. If isDead is true, defs | ||||||
991 | /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it | ||||||
992 | /// also checks if there is a def of a super-register. | ||||||
993 | int | ||||||
994 | MachineInstr::findRegisterDefOperandIdx(Register Reg, bool isDead, bool Overlap, | ||||||
995 | const TargetRegisterInfo *TRI) const { | ||||||
996 | bool isPhys = Register::isPhysicalRegister(Reg); | ||||||
997 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { | ||||||
998 | const MachineOperand &MO = getOperand(i); | ||||||
999 | // Accept regmask operands when Overlap is set. | ||||||
1000 | // Ignore them when looking for a specific def operand (Overlap == false). | ||||||
1001 | if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg)) | ||||||
1002 | return i; | ||||||
1003 | if (!MO.isReg() || !MO.isDef()) | ||||||
1004 | continue; | ||||||
1005 | Register MOReg = MO.getReg(); | ||||||
1006 | bool Found = (MOReg == Reg); | ||||||
1007 | if (!Found && TRI && isPhys && Register::isPhysicalRegister(MOReg)) { | ||||||
1008 | if (Overlap) | ||||||
1009 | Found = TRI->regsOverlap(MOReg, Reg); | ||||||
1010 | else | ||||||
1011 | Found = TRI->isSubRegister(MOReg, Reg); | ||||||
1012 | } | ||||||
1013 | if (Found && (!isDead || MO.isDead())) | ||||||
1014 | return i; | ||||||
1015 | } | ||||||
1016 | return -1; | ||||||
1017 | } | ||||||
1018 | |||||||
1019 | /// findFirstPredOperandIdx() - Find the index of the first operand in the | ||||||
1020 | /// operand list that is used to represent the predicate. It returns -1 if | ||||||
1021 | /// none is found. | ||||||
1022 | int MachineInstr::findFirstPredOperandIdx() const { | ||||||
1023 | // Don't call MCID.findFirstPredOperandIdx() because this variant | ||||||
1024 | // is sometimes called on an instruction that's not yet complete, and | ||||||
1025 | // so the number of operands is less than the MCID indicates. In | ||||||
1026 | // particular, the PTX target does this. | ||||||
1027 | const MCInstrDesc &MCID = getDesc(); | ||||||
1028 | if (MCID.isPredicable()) { | ||||||
1029 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) | ||||||
1030 | if (MCID.OpInfo[i].isPredicate()) | ||||||
1031 | return i; | ||||||
1032 | } | ||||||
1033 | |||||||
1034 | return -1; | ||||||
1035 | } | ||||||
1036 | |||||||
1037 | // MachineOperand::TiedTo is 4 bits wide. | ||||||
1038 | const unsigned TiedMax = 15; | ||||||
1039 | |||||||
1040 | /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other. | ||||||
1041 | /// | ||||||
1042 | /// Use and def operands can be tied together, indicated by a non-zero TiedTo | ||||||
1043 | /// field. TiedTo can have these values: | ||||||
1044 | /// | ||||||
1045 | /// 0: Operand is not tied to anything. | ||||||
1046 | /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1). | ||||||
1047 | /// TiedMax: Tied to an operand >= TiedMax-1. | ||||||
1048 | /// | ||||||
1049 | /// The tied def must be one of the first TiedMax operands on a normal | ||||||
1050 | /// instruction. INLINEASM instructions allow more tied defs. | ||||||
1051 | /// | ||||||
1052 | void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { | ||||||
1053 | MachineOperand &DefMO = getOperand(DefIdx); | ||||||
1054 | MachineOperand &UseMO = getOperand(UseIdx); | ||||||
1055 | assert(DefMO.isDef() && "DefIdx must be a def operand")((DefMO.isDef() && "DefIdx must be a def operand") ? static_cast <void> (0) : __assert_fail ("DefMO.isDef() && \"DefIdx must be a def operand\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 1055, __PRETTY_FUNCTION__)); | ||||||
1056 | assert(UseMO.isUse() && "UseIdx must be a use operand")((UseMO.isUse() && "UseIdx must be a use operand") ? static_cast <void> (0) : __assert_fail ("UseMO.isUse() && \"UseIdx must be a use operand\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 1056, __PRETTY_FUNCTION__)); | ||||||
1057 | assert(!DefMO.isTied() && "Def is already tied to another use")((!DefMO.isTied() && "Def is already tied to another use" ) ? static_cast<void> (0) : __assert_fail ("!DefMO.isTied() && \"Def is already tied to another use\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 1057, __PRETTY_FUNCTION__)); | ||||||
1058 | assert(!UseMO.isTied() && "Use is already tied to another def")((!UseMO.isTied() && "Use is already tied to another def" ) ? static_cast<void> (0) : __assert_fail ("!UseMO.isTied() && \"Use is already tied to another def\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 1058, __PRETTY_FUNCTION__)); | ||||||
1059 | |||||||
1060 | if (DefIdx < TiedMax) | ||||||
1061 | UseMO.TiedTo = DefIdx + 1; | ||||||
1062 | else { | ||||||
1063 | // Inline asm can use the group descriptors to find tied operands, but on | ||||||
1064 | // normal instruction, the tied def must be within the first TiedMax | ||||||
1065 | // operands. | ||||||
1066 | assert(isInlineAsm() && "DefIdx out of range")((isInlineAsm() && "DefIdx out of range") ? static_cast <void> (0) : __assert_fail ("isInlineAsm() && \"DefIdx out of range\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 1066, __PRETTY_FUNCTION__)); | ||||||
1067 | UseMO.TiedTo = TiedMax; | ||||||
1068 | } | ||||||
1069 | |||||||
1070 | // UseIdx can be out of range, we'll search for it in findTiedOperandIdx(). | ||||||
1071 | DefMO.TiedTo = std::min(UseIdx + 1, TiedMax); | ||||||
1072 | } | ||||||
1073 | |||||||
1074 | /// Given the index of a tied register operand, find the operand it is tied to. | ||||||
1075 | /// Defs are tied to uses and vice versa. Returns the index of the tied operand | ||||||
1076 | /// which must exist. | ||||||
1077 | unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const { | ||||||
1078 | const MachineOperand &MO = getOperand(OpIdx); | ||||||
1079 | assert(MO.isTied() && "Operand isn't tied")((MO.isTied() && "Operand isn't tied") ? static_cast< void> (0) : __assert_fail ("MO.isTied() && \"Operand isn't tied\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 1079, __PRETTY_FUNCTION__)); | ||||||
1080 | |||||||
1081 | // Normally TiedTo is in range. | ||||||
1082 | if (MO.TiedTo < TiedMax) | ||||||
1083 | return MO.TiedTo - 1; | ||||||
1084 | |||||||
1085 | // Uses on normal instructions can be out of range. | ||||||
1086 | if (!isInlineAsm()) { | ||||||
1087 | // Normal tied defs must be in the 0..TiedMax-1 range. | ||||||
1088 | if (MO.isUse()) | ||||||
1089 | return TiedMax - 1; | ||||||
1090 | // MO is a def. Search for the tied use. | ||||||
1091 | for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) { | ||||||
1092 | const MachineOperand &UseMO = getOperand(i); | ||||||
1093 | if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1) | ||||||
1094 | return i; | ||||||
1095 | } | ||||||
1096 | llvm_unreachable("Can't find tied use")::llvm::llvm_unreachable_internal("Can't find tied use", "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 1096); | ||||||
1097 | } | ||||||
1098 | |||||||
1099 | // Now deal with inline asm by parsing the operand group descriptor flags. | ||||||
1100 | // Find the beginning of each operand group. | ||||||
1101 | SmallVector<unsigned, 8> GroupIdx; | ||||||
1102 | unsigned OpIdxGroup = ~0u; | ||||||
1103 | unsigned NumOps; | ||||||
1104 | for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e; | ||||||
1105 | i += NumOps) { | ||||||
1106 | const MachineOperand &FlagMO = getOperand(i); | ||||||
1107 | assert(FlagMO.isImm() && "Invalid tied operand on inline asm")((FlagMO.isImm() && "Invalid tied operand on inline asm" ) ? static_cast<void> (0) : __assert_fail ("FlagMO.isImm() && \"Invalid tied operand on inline asm\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 1107, __PRETTY_FUNCTION__)); | ||||||
1108 | unsigned CurGroup = GroupIdx.size(); | ||||||
1109 | GroupIdx.push_back(i); | ||||||
1110 | NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm()); | ||||||
1111 | // OpIdx belongs to this operand group. | ||||||
1112 | if (OpIdx > i && OpIdx < i + NumOps) | ||||||
1113 | OpIdxGroup = CurGroup; | ||||||
1114 | unsigned TiedGroup; | ||||||
1115 | if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup)) | ||||||
1116 | continue; | ||||||
1117 | // Operands in this group are tied to operands in TiedGroup which must be | ||||||
1118 | // earlier. Find the number of operands between the two groups. | ||||||
1119 | unsigned Delta = i - GroupIdx[TiedGroup]; | ||||||
1120 | |||||||
1121 | // OpIdx is a use tied to TiedGroup. | ||||||
1122 | if (OpIdxGroup == CurGroup) | ||||||
1123 | return OpIdx - Delta; | ||||||
1124 | |||||||
1125 | // OpIdx is a def tied to this use group. | ||||||
1126 | if (OpIdxGroup == TiedGroup) | ||||||
1127 | return OpIdx + Delta; | ||||||
1128 | } | ||||||
1129 | llvm_unreachable("Invalid tied operand on inline asm")::llvm::llvm_unreachable_internal("Invalid tied operand on inline asm" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 1129); | ||||||
1130 | } | ||||||
1131 | |||||||
1132 | /// clearKillInfo - Clears kill flags on all operands. | ||||||
1133 | /// | ||||||
1134 | void MachineInstr::clearKillInfo() { | ||||||
1135 | for (MachineOperand &MO : operands()) { | ||||||
1136 | if (MO.isReg() && MO.isUse()) | ||||||
1137 | MO.setIsKill(false); | ||||||
1138 | } | ||||||
1139 | } | ||||||
1140 | |||||||
1141 | void MachineInstr::substituteRegister(Register FromReg, Register ToReg, | ||||||
1142 | unsigned SubIdx, | ||||||
1143 | const TargetRegisterInfo &RegInfo) { | ||||||
1144 | if (Register::isPhysicalRegister(ToReg)) { | ||||||
1145 | if (SubIdx) | ||||||
1146 | ToReg = RegInfo.getSubReg(ToReg, SubIdx); | ||||||
1147 | for (MachineOperand &MO : operands()) { | ||||||
1148 | if (!MO.isReg() || MO.getReg() != FromReg) | ||||||
1149 | continue; | ||||||
1150 | MO.substPhysReg(ToReg, RegInfo); | ||||||
1151 | } | ||||||
1152 | } else { | ||||||
1153 | for (MachineOperand &MO : operands()) { | ||||||
1154 | if (!MO.isReg() || MO.getReg() != FromReg) | ||||||
1155 | continue; | ||||||
1156 | MO.substVirtReg(ToReg, SubIdx, RegInfo); | ||||||
1157 | } | ||||||
1158 | } | ||||||
1159 | } | ||||||
1160 | |||||||
1161 | /// isSafeToMove - Return true if it is safe to move this instruction. If | ||||||
1162 | /// SawStore is set to true, it means that there is a store (or call) between | ||||||
1163 | /// the instruction's location and its intended destination. | ||||||
1164 | bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const { | ||||||
1165 | // Ignore stuff that we obviously can't move. | ||||||
1166 | // | ||||||
1167 | // Treat volatile loads as stores. This is not strictly necessary for | ||||||
1168 | // volatiles, but it is required for atomic loads. It is not allowed to move | ||||||
1169 | // a load across an atomic load with Ordering > Monotonic. | ||||||
1170 | if (mayStore() || isCall() || isPHI() || | ||||||
1171 | (mayLoad() && hasOrderedMemoryRef())) { | ||||||
1172 | SawStore = true; | ||||||
1173 | return false; | ||||||
1174 | } | ||||||
1175 | |||||||
1176 | if (isPosition() || isDebugInstr() || isTerminator() || | ||||||
1177 | mayRaiseFPException() || hasUnmodeledSideEffects()) | ||||||
1178 | return false; | ||||||
1179 | |||||||
1180 | // See if this instruction does a load. If so, we have to guarantee that the | ||||||
1181 | // loaded value doesn't change between the load and the its intended | ||||||
1182 | // destination. The check for isInvariantLoad gives the targe the chance to | ||||||
1183 | // classify the load as always returning a constant, e.g. a constant pool | ||||||
1184 | // load. | ||||||
1185 | if (mayLoad() && !isDereferenceableInvariantLoad(AA)) | ||||||
1186 | // Otherwise, this is a real load. If there is a store between the load and | ||||||
1187 | // end of block, we can't move it. | ||||||
1188 | return !SawStore; | ||||||
1189 | |||||||
1190 | return true; | ||||||
1191 | } | ||||||
1192 | |||||||
1193 | bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other, | ||||||
1194 | bool UseTBAA) const { | ||||||
1195 | const MachineFunction *MF = getMF(); | ||||||
1196 | const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); | ||||||
1197 | const MachineFrameInfo &MFI = MF->getFrameInfo(); | ||||||
1198 | |||||||
1199 | // If neither instruction stores to memory, they can't alias in any | ||||||
1200 | // meaningful way, even if they read from the same address. | ||||||
1201 | if (!mayStore() && !Other.mayStore()) | ||||||
1202 | return false; | ||||||
1203 | |||||||
1204 | // Let the target decide if memory accesses cannot possibly overlap. | ||||||
1205 | if (TII->areMemAccessesTriviallyDisjoint(*this, Other)) | ||||||
1206 | return false; | ||||||
1207 | |||||||
1208 | // FIXME: Need to handle multiple memory operands to support all targets. | ||||||
1209 | if (!hasOneMemOperand() || !Other.hasOneMemOperand()) | ||||||
1210 | return true; | ||||||
1211 | |||||||
1212 | MachineMemOperand *MMOa = *memoperands_begin(); | ||||||
1213 | MachineMemOperand *MMOb = *Other.memoperands_begin(); | ||||||
1214 | |||||||
1215 | // The following interface to AA is fashioned after DAGCombiner::isAlias | ||||||
1216 | // and operates with MachineMemOperand offset with some important | ||||||
1217 | // assumptions: | ||||||
1218 | // - LLVM fundamentally assumes flat address spaces. | ||||||
1219 | // - MachineOperand offset can *only* result from legalization and | ||||||
1220 | // cannot affect queries other than the trivial case of overlap | ||||||
1221 | // checking. | ||||||
1222 | // - These offsets never wrap and never step outside | ||||||
1223 | // of allocated objects. | ||||||
1224 | // - There should never be any negative offsets here. | ||||||
1225 | // | ||||||
1226 | // FIXME: Modify API to hide this math from "user" | ||||||
1227 | // Even before we go to AA we can reason locally about some | ||||||
1228 | // memory objects. It can save compile time, and possibly catch some | ||||||
1229 | // corner cases not currently covered. | ||||||
1230 | |||||||
1231 | int64_t OffsetA = MMOa->getOffset(); | ||||||
1232 | int64_t OffsetB = MMOb->getOffset(); | ||||||
1233 | int64_t MinOffset = std::min(OffsetA, OffsetB); | ||||||
1234 | |||||||
1235 | uint64_t WidthA = MMOa->getSize(); | ||||||
1236 | uint64_t WidthB = MMOb->getSize(); | ||||||
1237 | bool KnownWidthA = WidthA != MemoryLocation::UnknownSize; | ||||||
1238 | bool KnownWidthB = WidthB != MemoryLocation::UnknownSize; | ||||||
1239 | |||||||
1240 | const Value *ValA = MMOa->getValue(); | ||||||
1241 | const Value *ValB = MMOb->getValue(); | ||||||
1242 | bool SameVal = (ValA && ValB && (ValA == ValB)); | ||||||
1243 | if (!SameVal) { | ||||||
1244 | const PseudoSourceValue *PSVa = MMOa->getPseudoValue(); | ||||||
1245 | const PseudoSourceValue *PSVb = MMOb->getPseudoValue(); | ||||||
1246 | if (PSVa && ValB && !PSVa->mayAlias(&MFI)) | ||||||
1247 | return false; | ||||||
1248 | if (PSVb && ValA && !PSVb->mayAlias(&MFI)) | ||||||
1249 | return false; | ||||||
1250 | if (PSVa && PSVb && (PSVa == PSVb)) | ||||||
1251 | SameVal = true; | ||||||
1252 | } | ||||||
1253 | |||||||
1254 | if (SameVal) { | ||||||
1255 | if (!KnownWidthA || !KnownWidthB) | ||||||
1256 | return true; | ||||||
1257 | int64_t MaxOffset = std::max(OffsetA, OffsetB); | ||||||
1258 | int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB; | ||||||
1259 | return (MinOffset + LowWidth > MaxOffset); | ||||||
1260 | } | ||||||
1261 | |||||||
1262 | if (!AA) | ||||||
1263 | return true; | ||||||
1264 | |||||||
1265 | if (!ValA || !ValB) | ||||||
1266 | return true; | ||||||
1267 | |||||||
1268 | assert((OffsetA >= 0) && "Negative MachineMemOperand offset")(((OffsetA >= 0) && "Negative MachineMemOperand offset" ) ? static_cast<void> (0) : __assert_fail ("(OffsetA >= 0) && \"Negative MachineMemOperand offset\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 1268, __PRETTY_FUNCTION__)); | ||||||
1269 | assert((OffsetB >= 0) && "Negative MachineMemOperand offset")(((OffsetB >= 0) && "Negative MachineMemOperand offset" ) ? static_cast<void> (0) : __assert_fail ("(OffsetB >= 0) && \"Negative MachineMemOperand offset\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 1269, __PRETTY_FUNCTION__)); | ||||||
1270 | |||||||
1271 | int64_t OverlapA = KnownWidthA ? WidthA + OffsetA - MinOffset | ||||||
1272 | : MemoryLocation::UnknownSize; | ||||||
1273 | int64_t OverlapB = KnownWidthB ? WidthB + OffsetB - MinOffset | ||||||
1274 | : MemoryLocation::UnknownSize; | ||||||
1275 | |||||||
1276 | AliasResult AAResult = AA->alias( | ||||||
1277 | MemoryLocation(ValA, OverlapA, | ||||||
1278 | UseTBAA ? MMOa->getAAInfo() : AAMDNodes()), | ||||||
1279 | MemoryLocation(ValB, OverlapB, | ||||||
1280 | UseTBAA ? MMOb->getAAInfo() : AAMDNodes())); | ||||||
1281 | |||||||
1282 | return (AAResult != NoAlias); | ||||||
1283 | } | ||||||
1284 | |||||||
1285 | /// hasOrderedMemoryRef - Return true if this instruction may have an ordered | ||||||
1286 | /// or volatile memory reference, or if the information describing the memory | ||||||
1287 | /// reference is not available. Return false if it is known to have no ordered | ||||||
1288 | /// memory references. | ||||||
1289 | bool MachineInstr::hasOrderedMemoryRef() const { | ||||||
1290 | // An instruction known never to access memory won't have a volatile access. | ||||||
1291 | if (!mayStore() && | ||||||
1292 | !mayLoad() && | ||||||
1293 | !isCall() && | ||||||
1294 | !hasUnmodeledSideEffects()) | ||||||
1295 | return false; | ||||||
1296 | |||||||
1297 | // Otherwise, if the instruction has no memory reference information, | ||||||
1298 | // conservatively assume it wasn't preserved. | ||||||
1299 | if (memoperands_empty()) | ||||||
1300 | return true; | ||||||
1301 | |||||||
1302 | // Check if any of our memory operands are ordered. | ||||||
1303 | return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) { | ||||||
1304 | return !MMO->isUnordered(); | ||||||
1305 | }); | ||||||
1306 | } | ||||||
1307 | |||||||
1308 | /// isDereferenceableInvariantLoad - Return true if this instruction will never | ||||||
1309 | /// trap and is loading from a location whose value is invariant across a run of | ||||||
1310 | /// this function. | ||||||
1311 | bool MachineInstr::isDereferenceableInvariantLoad(AAResults *AA) const { | ||||||
1312 | // If the instruction doesn't load at all, it isn't an invariant load. | ||||||
1313 | if (!mayLoad()) | ||||||
1314 | return false; | ||||||
1315 | |||||||
1316 | // If the instruction has lost its memoperands, conservatively assume that | ||||||
1317 | // it may not be an invariant load. | ||||||
1318 | if (memoperands_empty()) | ||||||
1319 | return false; | ||||||
1320 | |||||||
1321 | const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo(); | ||||||
1322 | |||||||
1323 | for (MachineMemOperand *MMO : memoperands()) { | ||||||
1324 | if (!MMO->isUnordered()) | ||||||
1325 | // If the memory operand has ordering side effects, we can't move the | ||||||
1326 | // instruction. Such an instruction is technically an invariant load, | ||||||
1327 | // but the caller code would need updated to expect that. | ||||||
1328 | return false; | ||||||
1329 | if (MMO->isStore()) return false; | ||||||
1330 | if (MMO->isInvariant() && MMO->isDereferenceable()) | ||||||
1331 | continue; | ||||||
1332 | |||||||
1333 | // A load from a constant PseudoSourceValue is invariant. | ||||||
1334 | if (const PseudoSourceValue *PSV = MMO->getPseudoValue()) | ||||||
1335 | if (PSV->isConstant(&MFI)) | ||||||
1336 | continue; | ||||||
1337 | |||||||
1338 | if (const Value *V = MMO->getValue()) { | ||||||
1339 | // If we have an AliasAnalysis, ask it whether the memory is constant. | ||||||
1340 | if (AA && | ||||||
1341 | AA->pointsToConstantMemory( | ||||||
1342 | MemoryLocation(V, MMO->getSize(), MMO->getAAInfo()))) | ||||||
1343 | continue; | ||||||
1344 | } | ||||||
1345 | |||||||
1346 | // Otherwise assume conservatively. | ||||||
1347 | return false; | ||||||
1348 | } | ||||||
1349 | |||||||
1350 | // Everything checks out. | ||||||
1351 | return true; | ||||||
1352 | } | ||||||
1353 | |||||||
1354 | /// isConstantValuePHI - If the specified instruction is a PHI that always | ||||||
1355 | /// merges together the same virtual register, return the register, otherwise | ||||||
1356 | /// return 0. | ||||||
1357 | unsigned MachineInstr::isConstantValuePHI() const { | ||||||
1358 | if (!isPHI()) | ||||||
1359 | return 0; | ||||||
1360 | assert(getNumOperands() >= 3 &&((getNumOperands() >= 3 && "It's illegal to have a PHI without source operands" ) ? static_cast<void> (0) : __assert_fail ("getNumOperands() >= 3 && \"It's illegal to have a PHI without source operands\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 1361, __PRETTY_FUNCTION__)) | ||||||
1361 | "It's illegal to have a PHI without source operands")((getNumOperands() >= 3 && "It's illegal to have a PHI without source operands" ) ? static_cast<void> (0) : __assert_fail ("getNumOperands() >= 3 && \"It's illegal to have a PHI without source operands\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 1361, __PRETTY_FUNCTION__)); | ||||||
1362 | |||||||
1363 | Register Reg = getOperand(1).getReg(); | ||||||
1364 | for (unsigned i = 3, e = getNumOperands(); i < e; i += 2) | ||||||
1365 | if (getOperand(i).getReg() != Reg) | ||||||
1366 | return 0; | ||||||
1367 | return Reg; | ||||||
1368 | } | ||||||
1369 | |||||||
1370 | bool MachineInstr::hasUnmodeledSideEffects() const { | ||||||
1371 | if (hasProperty(MCID::UnmodeledSideEffects)) | ||||||
1372 | return true; | ||||||
1373 | if (isInlineAsm()) { | ||||||
1374 | unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); | ||||||
1375 | if (ExtraInfo & InlineAsm::Extra_HasSideEffects) | ||||||
1376 | return true; | ||||||
1377 | } | ||||||
1378 | |||||||
1379 | return false; | ||||||
1380 | } | ||||||
1381 | |||||||
1382 | bool MachineInstr::isLoadFoldBarrier() const { | ||||||
1383 | return mayStore() || isCall() || hasUnmodeledSideEffects(); | ||||||
1384 | } | ||||||
1385 | |||||||
1386 | /// allDefsAreDead - Return true if all the defs of this instruction are dead. | ||||||
1387 | /// | ||||||
1388 | bool MachineInstr::allDefsAreDead() const { | ||||||
1389 | for (const MachineOperand &MO : operands()) { | ||||||
1390 | if (!MO.isReg() || MO.isUse()) | ||||||
1391 | continue; | ||||||
1392 | if (!MO.isDead()) | ||||||
1393 | return false; | ||||||
1394 | } | ||||||
1395 | return true; | ||||||
1396 | } | ||||||
1397 | |||||||
1398 | /// copyImplicitOps - Copy implicit register operands from specified | ||||||
1399 | /// instruction to this instruction. | ||||||
1400 | void MachineInstr::copyImplicitOps(MachineFunction &MF, | ||||||
1401 | const MachineInstr &MI) { | ||||||
1402 | for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands(); | ||||||
1403 | i != e; ++i) { | ||||||
1404 | const MachineOperand &MO = MI.getOperand(i); | ||||||
1405 | if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask()) | ||||||
1406 | addOperand(MF, MO); | ||||||
1407 | } | ||||||
1408 | } | ||||||
1409 | |||||||
1410 | bool MachineInstr::hasComplexRegisterTies() const { | ||||||
1411 | const MCInstrDesc &MCID = getDesc(); | ||||||
1412 | for (unsigned I = 0, E = getNumOperands(); I < E; ++I) { | ||||||
1413 | const auto &Operand = getOperand(I); | ||||||
1414 | if (!Operand.isReg() || Operand.isDef()) | ||||||
1415 | // Ignore the defined registers as MCID marks only the uses as tied. | ||||||
1416 | continue; | ||||||
1417 | int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO); | ||||||
1418 | int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1; | ||||||
1419 | if (ExpectedTiedIdx != TiedIdx) | ||||||
1420 | return true; | ||||||
1421 | } | ||||||
1422 | return false; | ||||||
1423 | } | ||||||
1424 | |||||||
1425 | LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, | ||||||
1426 | const MachineRegisterInfo &MRI) const { | ||||||
1427 | const MachineOperand &Op = getOperand(OpIdx); | ||||||
1428 | if (!Op.isReg()) | ||||||
1429 | return LLT{}; | ||||||
1430 | |||||||
1431 | if (isVariadic() || OpIdx >= getNumExplicitOperands()) | ||||||
1432 | return MRI.getType(Op.getReg()); | ||||||
1433 | |||||||
1434 | auto &OpInfo = getDesc().OpInfo[OpIdx]; | ||||||
1435 | if (!OpInfo.isGenericType()) | ||||||
1436 | return MRI.getType(Op.getReg()); | ||||||
1437 | |||||||
1438 | if (PrintedTypes[OpInfo.getGenericTypeIndex()]) | ||||||
1439 | return LLT{}; | ||||||
1440 | |||||||
1441 | LLT TypeToPrint = MRI.getType(Op.getReg()); | ||||||
1442 | // Don't mark the type index printed if it wasn't actually printed: maybe | ||||||
1443 | // another operand with the same type index has an actual type attached: | ||||||
1444 | if (TypeToPrint.isValid()) | ||||||
1445 | PrintedTypes.set(OpInfo.getGenericTypeIndex()); | ||||||
1446 | return TypeToPrint; | ||||||
1447 | } | ||||||
1448 | |||||||
1449 | #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) | ||||||
1450 | LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void MachineInstr::dump() const { | ||||||
1451 | dbgs() << " "; | ||||||
1452 | print(dbgs()); | ||||||
1453 | } | ||||||
1454 | #endif | ||||||
1455 | |||||||
1456 | void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers, | ||||||
1457 | bool SkipDebugLoc, bool AddNewLine, | ||||||
1458 | const TargetInstrInfo *TII) const { | ||||||
1459 | const Module *M = nullptr; | ||||||
1460 | const Function *F = nullptr; | ||||||
1461 | if (const MachineFunction *MF = getMFIfAvailable(*this)) { | ||||||
1462 | F = &MF->getFunction(); | ||||||
1463 | M = F->getParent(); | ||||||
1464 | if (!TII) | ||||||
1465 | TII = MF->getSubtarget().getInstrInfo(); | ||||||
1466 | } | ||||||
1467 | |||||||
1468 | ModuleSlotTracker MST(M); | ||||||
1469 | if (F) | ||||||
1470 | MST.incorporateFunction(*F); | ||||||
1471 | print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII); | ||||||
1472 | } | ||||||
1473 | |||||||
1474 | void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, | ||||||
1475 | bool IsStandalone, bool SkipOpers, bool SkipDebugLoc, | ||||||
1476 | bool AddNewLine, const TargetInstrInfo *TII) const { | ||||||
1477 | // We can be a bit tidier if we know the MachineFunction. | ||||||
1478 | const MachineFunction *MF = nullptr; | ||||||
1479 | const TargetRegisterInfo *TRI = nullptr; | ||||||
1480 | const MachineRegisterInfo *MRI = nullptr; | ||||||
1481 | const TargetIntrinsicInfo *IntrinsicInfo = nullptr; | ||||||
1482 | const MIRFormatter *MIRF = nullptr; | ||||||
1483 | tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII, MIRF); | ||||||
1484 | |||||||
1485 | if (isCFIInstruction()) | ||||||
1486 | assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction")((getNumOperands() == 1 && "Expected 1 operand in CFI instruction" ) ? static_cast<void> (0) : __assert_fail ("getNumOperands() == 1 && \"Expected 1 operand in CFI instruction\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 1486, __PRETTY_FUNCTION__)); | ||||||
1487 | |||||||
1488 | SmallBitVector PrintedTypes(8); | ||||||
1489 | bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies(); | ||||||
1490 | auto getTiedOperandIdx = [&](unsigned OpIdx) { | ||||||
1491 | if (!ShouldPrintRegisterTies) | ||||||
1492 | return 0U; | ||||||
1493 | const MachineOperand &MO = getOperand(OpIdx); | ||||||
1494 | if (MO.isReg() && MO.isTied() && !MO.isDef()) | ||||||
1495 | return findTiedOperandIdx(OpIdx); | ||||||
1496 | return 0U; | ||||||
1497 | }; | ||||||
1498 | unsigned StartOp = 0; | ||||||
1499 | unsigned e = getNumOperands(); | ||||||
1500 | |||||||
1501 | // Print explicitly defined operands on the left of an assignment syntax. | ||||||
1502 | while (StartOp < e) { | ||||||
1503 | const MachineOperand &MO = getOperand(StartOp); | ||||||
1504 | if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) | ||||||
1505 | break; | ||||||
1506 | |||||||
1507 | if (StartOp != 0) | ||||||
1508 | OS << ", "; | ||||||
1509 | |||||||
1510 | LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{}; | ||||||
1511 | unsigned TiedOperandIdx = getTiedOperandIdx(StartOp); | ||||||
1512 | MO.print(OS, MST, TypeToPrint, StartOp, /*PrintDef=*/false, IsStandalone, | ||||||
1513 | ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo); | ||||||
1514 | ++StartOp; | ||||||
1515 | } | ||||||
1516 | |||||||
1517 | if (StartOp != 0) | ||||||
1518 | OS << " = "; | ||||||
1519 | |||||||
1520 | if (getFlag(MachineInstr::FrameSetup)) | ||||||
1521 | OS << "frame-setup "; | ||||||
1522 | if (getFlag(MachineInstr::FrameDestroy)) | ||||||
1523 | OS << "frame-destroy "; | ||||||
1524 | if (getFlag(MachineInstr::FmNoNans)) | ||||||
1525 | OS << "nnan "; | ||||||
1526 | if (getFlag(MachineInstr::FmNoInfs)) | ||||||
1527 | OS << "ninf "; | ||||||
1528 | if (getFlag(MachineInstr::FmNsz)) | ||||||
1529 | OS << "nsz "; | ||||||
1530 | if (getFlag(MachineInstr::FmArcp)) | ||||||
1531 | OS << "arcp "; | ||||||
1532 | if (getFlag(MachineInstr::FmContract)) | ||||||
1533 | OS << "contract "; | ||||||
1534 | if (getFlag(MachineInstr::FmAfn)) | ||||||
1535 | OS << "afn "; | ||||||
1536 | if (getFlag(MachineInstr::FmReassoc)) | ||||||
1537 | OS << "reassoc "; | ||||||
1538 | if (getFlag(MachineInstr::NoUWrap)) | ||||||
1539 | OS << "nuw "; | ||||||
1540 | if (getFlag(MachineInstr::NoSWrap)) | ||||||
1541 | OS << "nsw "; | ||||||
1542 | if (getFlag(MachineInstr::IsExact)) | ||||||
1543 | OS << "exact "; | ||||||
1544 | if (getFlag(MachineInstr::FPExcept)) | ||||||
1545 | OS << "fpexcept "; | ||||||
1546 | |||||||
1547 | // Print the opcode name. | ||||||
1548 | if (TII) | ||||||
1549 | OS << TII->getName(getOpcode()); | ||||||
1550 | else | ||||||
1551 | OS << "UNKNOWN"; | ||||||
1552 | |||||||
1553 | if (SkipOpers) | ||||||
1554 | return; | ||||||
1555 | |||||||
1556 | // Print the rest of the operands. | ||||||
1557 | bool FirstOp = true; | ||||||
1558 | unsigned AsmDescOp = ~0u; | ||||||
1559 | unsigned AsmOpCount = 0; | ||||||
1560 | |||||||
1561 | if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) { | ||||||
1562 | // Print asm string. | ||||||
1563 | OS << " "; | ||||||
1564 | const unsigned OpIdx = InlineAsm::MIOp_AsmString; | ||||||
1565 | LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{}; | ||||||
1566 | unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx); | ||||||
1567 | getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone, | ||||||
1568 | ShouldPrintRegisterTies, TiedOperandIdx, TRI, | ||||||
1569 | IntrinsicInfo); | ||||||
1570 | |||||||
1571 | // Print HasSideEffects, MayLoad, MayStore, IsAlignStack | ||||||
1572 | unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); | ||||||
1573 | if (ExtraInfo & InlineAsm::Extra_HasSideEffects) | ||||||
1574 | OS << " [sideeffect]"; | ||||||
1575 | if (ExtraInfo & InlineAsm::Extra_MayLoad) | ||||||
1576 | OS << " [mayload]"; | ||||||
1577 | if (ExtraInfo & InlineAsm::Extra_MayStore) | ||||||
1578 | OS << " [maystore]"; | ||||||
1579 | if (ExtraInfo & InlineAsm::Extra_IsConvergent) | ||||||
1580 | OS << " [isconvergent]"; | ||||||
1581 | if (ExtraInfo & InlineAsm::Extra_IsAlignStack) | ||||||
1582 | OS << " [alignstack]"; | ||||||
1583 | if (getInlineAsmDialect() == InlineAsm::AD_ATT) | ||||||
1584 | OS << " [attdialect]"; | ||||||
1585 | if (getInlineAsmDialect() == InlineAsm::AD_Intel) | ||||||
1586 | OS << " [inteldialect]"; | ||||||
1587 | |||||||
1588 | StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand; | ||||||
1589 | FirstOp = false; | ||||||
1590 | } | ||||||
1591 | |||||||
1592 | for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { | ||||||
1593 | const MachineOperand &MO = getOperand(i); | ||||||
1594 | |||||||
1595 | if (FirstOp) FirstOp = false; else OS << ","; | ||||||
1596 | OS << " "; | ||||||
1597 | |||||||
1598 | if (isDebugValue() && MO.isMetadata()) { | ||||||
1599 | // Pretty print DBG_VALUE instructions. | ||||||
1600 | auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata()); | ||||||
1601 | if (DIV && !DIV->getName().empty()) | ||||||
1602 | OS << "!\"" << DIV->getName() << '\"'; | ||||||
1603 | else { | ||||||
1604 | LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{}; | ||||||
1605 | unsigned TiedOperandIdx = getTiedOperandIdx(i); | ||||||
1606 | MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone, | ||||||
1607 | ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo); | ||||||
1608 | } | ||||||
1609 | } else if (isDebugLabel() && MO.isMetadata()) { | ||||||
1610 | // Pretty print DBG_LABEL instructions. | ||||||
1611 | auto *DIL = dyn_cast<DILabel>(MO.getMetadata()); | ||||||
1612 | if (DIL && !DIL->getName().empty()) | ||||||
1613 | OS << "\"" << DIL->getName() << '\"'; | ||||||
1614 | else { | ||||||
1615 | LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{}; | ||||||
1616 | unsigned TiedOperandIdx = getTiedOperandIdx(i); | ||||||
1617 | MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone, | ||||||
1618 | ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo); | ||||||
1619 | } | ||||||
1620 | } else if (i == AsmDescOp && MO.isImm()) { | ||||||
1621 | // Pretty print the inline asm operand descriptor. | ||||||
1622 | OS << '$' << AsmOpCount++; | ||||||
1623 | unsigned Flag = MO.getImm(); | ||||||
1624 | switch (InlineAsm::getKind(Flag)) { | ||||||
1625 | case InlineAsm::Kind_RegUse: OS << ":[reguse"; break; | ||||||
1626 | case InlineAsm::Kind_RegDef: OS << ":[regdef"; break; | ||||||
1627 | case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break; | ||||||
1628 | case InlineAsm::Kind_Clobber: OS << ":[clobber"; break; | ||||||
1629 | case InlineAsm::Kind_Imm: OS << ":[imm"; break; | ||||||
1630 | case InlineAsm::Kind_Mem: OS << ":[mem"; break; | ||||||
1631 | default: OS << ":[??" << InlineAsm::getKind(Flag); break; | ||||||
1632 | } | ||||||
1633 | |||||||
1634 | unsigned RCID = 0; | ||||||
1635 | if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) && | ||||||
1636 | InlineAsm::hasRegClassConstraint(Flag, RCID)) { | ||||||
1637 | if (TRI) { | ||||||
1638 | OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); | ||||||
1639 | } else | ||||||
1640 | OS << ":RC" << RCID; | ||||||
1641 | } | ||||||
1642 | |||||||
1643 | if (InlineAsm::isMemKind(Flag)) { | ||||||
1644 | unsigned MCID = InlineAsm::getMemoryConstraintID(Flag); | ||||||
1645 | switch (MCID) { | ||||||
1646 | case InlineAsm::Constraint_es: OS << ":es"; break; | ||||||
1647 | case InlineAsm::Constraint_i: OS << ":i"; break; | ||||||
1648 | case InlineAsm::Constraint_m: OS << ":m"; break; | ||||||
1649 | case InlineAsm::Constraint_o: OS << ":o"; break; | ||||||
1650 | case InlineAsm::Constraint_v: OS << ":v"; break; | ||||||
1651 | case InlineAsm::Constraint_Q: OS << ":Q"; break; | ||||||
1652 | case InlineAsm::Constraint_R: OS << ":R"; break; | ||||||
1653 | case InlineAsm::Constraint_S: OS << ":S"; break; | ||||||
1654 | case InlineAsm::Constraint_T: OS << ":T"; break; | ||||||
1655 | case InlineAsm::Constraint_Um: OS << ":Um"; break; | ||||||
1656 | case InlineAsm::Constraint_Un: OS << ":Un"; break; | ||||||
1657 | case InlineAsm::Constraint_Uq: OS << ":Uq"; break; | ||||||
1658 | case InlineAsm::Constraint_Us: OS << ":Us"; break; | ||||||
1659 | case InlineAsm::Constraint_Ut: OS << ":Ut"; break; | ||||||
1660 | case InlineAsm::Constraint_Uv: OS << ":Uv"; break; | ||||||
1661 | case InlineAsm::Constraint_Uy: OS << ":Uy"; break; | ||||||
1662 | case InlineAsm::Constraint_X: OS << ":X"; break; | ||||||
1663 | case InlineAsm::Constraint_Z: OS << ":Z"; break; | ||||||
1664 | case InlineAsm::Constraint_ZC: OS << ":ZC"; break; | ||||||
1665 | case InlineAsm::Constraint_Zy: OS << ":Zy"; break; | ||||||
1666 | default: OS << ":?"; break; | ||||||
1667 | } | ||||||
1668 | } | ||||||
1669 | |||||||
1670 | unsigned TiedTo = 0; | ||||||
1671 | if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo)) | ||||||
1672 | OS << " tiedto:$" << TiedTo; | ||||||
1673 | |||||||
1674 | OS << ']'; | ||||||
1675 | |||||||
1676 | // Compute the index of the next operand descriptor. | ||||||
1677 | AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag); | ||||||
1678 | } else { | ||||||
1679 | LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{}; | ||||||
1680 | unsigned TiedOperandIdx = getTiedOperandIdx(i); | ||||||
1681 | if (MO.isImm() && isOperandSubregIdx(i)) | ||||||
1682 | MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI); | ||||||
1683 | else | ||||||
1684 | MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone, | ||||||
1685 | ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo); | ||||||
1686 | } | ||||||
1687 | } | ||||||
1688 | |||||||
1689 | // Print any optional symbols attached to this instruction as-if they were | ||||||
1690 | // operands. | ||||||
1691 | if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) { | ||||||
1692 | if (!FirstOp) { | ||||||
1693 | FirstOp = false; | ||||||
1694 | OS << ','; | ||||||
1695 | } | ||||||
1696 | OS << " pre-instr-symbol "; | ||||||
1697 | MachineOperand::printSymbol(OS, *PreInstrSymbol); | ||||||
1698 | } | ||||||
1699 | if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) { | ||||||
1700 | if (!FirstOp) { | ||||||
1701 | FirstOp = false; | ||||||
1702 | OS << ','; | ||||||
1703 | } | ||||||
1704 | OS << " post-instr-symbol "; | ||||||
1705 | MachineOperand::printSymbol(OS, *PostInstrSymbol); | ||||||
1706 | } | ||||||
1707 | if (MDNode *HeapAllocMarker = getHeapAllocMarker()) { | ||||||
1708 | if (!FirstOp) { | ||||||
1709 | FirstOp = false; | ||||||
1710 | OS << ','; | ||||||
1711 | } | ||||||
1712 | OS << " heap-alloc-marker "; | ||||||
1713 | HeapAllocMarker->printAsOperand(OS, MST); | ||||||
1714 | } | ||||||
1715 | |||||||
1716 | if (!SkipDebugLoc) { | ||||||
1717 | if (const DebugLoc &DL = getDebugLoc()) { | ||||||
1718 | if (!FirstOp) | ||||||
1719 | OS << ','; | ||||||
1720 | OS << " debug-location "; | ||||||
1721 | DL->printAsOperand(OS, MST); | ||||||
1722 | } | ||||||
1723 | } | ||||||
1724 | |||||||
1725 | if (!memoperands_empty()) { | ||||||
1726 | SmallVector<StringRef, 0> SSNs; | ||||||
1727 | const LLVMContext *Context = nullptr; | ||||||
1728 | std::unique_ptr<LLVMContext> CtxPtr; | ||||||
1729 | const MachineFrameInfo *MFI = nullptr; | ||||||
1730 | if (const MachineFunction *MF = getMFIfAvailable(*this)) { | ||||||
1731 | MFI = &MF->getFrameInfo(); | ||||||
1732 | Context = &MF->getFunction().getContext(); | ||||||
1733 | } else { | ||||||
1734 | CtxPtr = std::make_unique<LLVMContext>(); | ||||||
1735 | Context = CtxPtr.get(); | ||||||
1736 | } | ||||||
1737 | |||||||
1738 | OS << " :: "; | ||||||
1739 | bool NeedComma = false; | ||||||
1740 | for (const MachineMemOperand *Op : memoperands()) { | ||||||
1741 | if (NeedComma) | ||||||
1742 | OS << ", "; | ||||||
1743 | Op->print(OS, MST, SSNs, *Context, MFI, TII, MIRF); | ||||||
1744 | NeedComma = true; | ||||||
1745 | } | ||||||
1746 | } | ||||||
1747 | |||||||
1748 | if (SkipDebugLoc) | ||||||
1749 | return; | ||||||
1750 | |||||||
1751 | bool HaveSemi = false; | ||||||
1752 | |||||||
1753 | // Print debug location information. | ||||||
1754 | if (const DebugLoc &DL = getDebugLoc()) { | ||||||
1755 | if (!HaveSemi) { | ||||||
1756 | OS << ';'; | ||||||
1757 | HaveSemi = true; | ||||||
1758 | } | ||||||
1759 | OS << ' '; | ||||||
1760 | DL.print(OS); | ||||||
1761 | } | ||||||
1762 | |||||||
1763 | // Print extra comments for DEBUG_VALUE. | ||||||
1764 | if (isDebugValue() && getOperand(e - 2).isMetadata()) { | ||||||
1765 | if (!HaveSemi) { | ||||||
1766 | OS << ";"; | ||||||
1767 | HaveSemi = true; | ||||||
1768 | } | ||||||
1769 | auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata()); | ||||||
1770 | OS << " line no:" << DV->getLine(); | ||||||
1771 | if (auto *InlinedAt = debugLoc->getInlinedAt()) { | ||||||
1772 | DebugLoc InlinedAtDL(InlinedAt); | ||||||
1773 | if (InlinedAtDL && MF) { | ||||||
1774 | OS << " inlined @[ "; | ||||||
1775 | InlinedAtDL.print(OS); | ||||||
1776 | OS << " ]"; | ||||||
1777 | } | ||||||
1778 | } | ||||||
1779 | if (isIndirectDebugValue()) | ||||||
1780 | OS << " indirect"; | ||||||
1781 | } | ||||||
1782 | // TODO: DBG_LABEL | ||||||
1783 | |||||||
1784 | if (AddNewLine) | ||||||
1785 | OS << '\n'; | ||||||
1786 | } | ||||||
1787 | |||||||
1788 | bool MachineInstr::addRegisterKilled(Register IncomingReg, | ||||||
1789 | const TargetRegisterInfo *RegInfo, | ||||||
1790 | bool AddIfNotFound) { | ||||||
1791 | bool isPhysReg = Register::isPhysicalRegister(IncomingReg); | ||||||
1792 | bool hasAliases = isPhysReg && | ||||||
1793 | MCRegAliasIterator(IncomingReg, RegInfo, false).isValid(); | ||||||
1794 | bool Found = false; | ||||||
1795 | SmallVector<unsigned,4> DeadOps; | ||||||
1796 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { | ||||||
1797 | MachineOperand &MO = getOperand(i); | ||||||
1798 | if (!MO.isReg() || !MO.isUse() || MO.isUndef()) | ||||||
1799 | continue; | ||||||
1800 | |||||||
1801 | // DEBUG_VALUE nodes do not contribute to code generation and should | ||||||
1802 | // always be ignored. Failure to do so may result in trying to modify | ||||||
1803 | // KILL flags on DEBUG_VALUE nodes. | ||||||
1804 | if (MO.isDebug()) | ||||||
1805 | continue; | ||||||
1806 | |||||||
1807 | Register Reg = MO.getReg(); | ||||||
1808 | if (!Reg) | ||||||
1809 | continue; | ||||||
1810 | |||||||
1811 | if (Reg == IncomingReg) { | ||||||
1812 | if (!Found) { | ||||||
1813 | if (MO.isKill()) | ||||||
1814 | // The register is already marked kill. | ||||||
1815 | return true; | ||||||
1816 | if (isPhysReg && isRegTiedToDefOperand(i)) | ||||||
1817 | // Two-address uses of physregs must not be marked kill. | ||||||
1818 | return true; | ||||||
1819 | MO.setIsKill(); | ||||||
1820 | Found = true; | ||||||
1821 | } | ||||||
1822 | } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) { | ||||||
1823 | // A super-register kill already exists. | ||||||
1824 | if (RegInfo->isSuperRegister(IncomingReg, Reg)) | ||||||
1825 | return true; | ||||||
1826 | if (RegInfo->isSubRegister(IncomingReg, Reg)) | ||||||
1827 | DeadOps.push_back(i); | ||||||
1828 | } | ||||||
1829 | } | ||||||
1830 | |||||||
1831 | // Trim unneeded kill operands. | ||||||
1832 | while (!DeadOps.empty()) { | ||||||
1833 | unsigned OpIdx = DeadOps.back(); | ||||||
1834 | if (getOperand(OpIdx).isImplicit() && | ||||||
1835 | (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0)) | ||||||
1836 | RemoveOperand(OpIdx); | ||||||
1837 | else | ||||||
1838 | getOperand(OpIdx).setIsKill(false); | ||||||
1839 | DeadOps.pop_back(); | ||||||
1840 | } | ||||||
1841 | |||||||
1842 | // If not found, this means an alias of one of the operands is killed. Add a | ||||||
1843 | // new implicit operand if required. | ||||||
1844 | if (!Found && AddIfNotFound) { | ||||||
1845 | addOperand(MachineOperand::CreateReg(IncomingReg, | ||||||
1846 | false /*IsDef*/, | ||||||
1847 | true /*IsImp*/, | ||||||
1848 | true /*IsKill*/)); | ||||||
1849 | return true; | ||||||
1850 | } | ||||||
1851 | return Found; | ||||||
1852 | } | ||||||
1853 | |||||||
1854 | void MachineInstr::clearRegisterKills(Register Reg, | ||||||
1855 | const TargetRegisterInfo *RegInfo) { | ||||||
1856 | if (!Register::isPhysicalRegister(Reg)) | ||||||
1857 | RegInfo = nullptr; | ||||||
1858 | for (MachineOperand &MO : operands()) { | ||||||
1859 | if (!MO.isReg() || !MO.isUse() || !MO.isKill()) | ||||||
1860 | continue; | ||||||
1861 | Register OpReg = MO.getReg(); | ||||||
1862 | if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg) | ||||||
1863 | MO.setIsKill(false); | ||||||
1864 | } | ||||||
1865 | } | ||||||
1866 | |||||||
1867 | bool MachineInstr::addRegisterDead(Register Reg, | ||||||
1868 | const TargetRegisterInfo *RegInfo, | ||||||
1869 | bool AddIfNotFound) { | ||||||
1870 | bool isPhysReg = Register::isPhysicalRegister(Reg); | ||||||
1871 | bool hasAliases = isPhysReg && | ||||||
1872 | MCRegAliasIterator(Reg, RegInfo, false).isValid(); | ||||||
1873 | bool Found = false; | ||||||
1874 | SmallVector<unsigned,4> DeadOps; | ||||||
1875 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { | ||||||
1876 | MachineOperand &MO = getOperand(i); | ||||||
1877 | if (!MO.isReg() || !MO.isDef()) | ||||||
1878 | continue; | ||||||
1879 | Register MOReg = MO.getReg(); | ||||||
1880 | if (!MOReg) | ||||||
1881 | continue; | ||||||
1882 | |||||||
1883 | if (MOReg == Reg) { | ||||||
1884 | MO.setIsDead(); | ||||||
1885 | Found = true; | ||||||
1886 | } else if (hasAliases && MO.isDead() && | ||||||
1887 | Register::isPhysicalRegister(MOReg)) { | ||||||
1888 | // There exists a super-register that's marked dead. | ||||||
1889 | if (RegInfo->isSuperRegister(Reg, MOReg)) | ||||||
1890 | return true; | ||||||
1891 | if (RegInfo->isSubRegister(Reg, MOReg)) | ||||||
1892 | DeadOps.push_back(i); | ||||||
1893 | } | ||||||
1894 | } | ||||||
1895 | |||||||
1896 | // Trim unneeded dead operands. | ||||||
1897 | while (!DeadOps.empty()) { | ||||||
1898 | unsigned OpIdx = DeadOps.back(); | ||||||
1899 | if (getOperand(OpIdx).isImplicit() && | ||||||
1900 | (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0)) | ||||||
1901 | RemoveOperand(OpIdx); | ||||||
1902 | else | ||||||
1903 | getOperand(OpIdx).setIsDead(false); | ||||||
1904 | DeadOps.pop_back(); | ||||||
1905 | } | ||||||
1906 | |||||||
1907 | // If not found, this means an alias of one of the operands is dead. Add a | ||||||
1908 | // new implicit operand if required. | ||||||
1909 | if (Found || !AddIfNotFound) | ||||||
1910 | return Found; | ||||||
1911 | |||||||
1912 | addOperand(MachineOperand::CreateReg(Reg, | ||||||
1913 | true /*IsDef*/, | ||||||
1914 | true /*IsImp*/, | ||||||
1915 | false /*IsKill*/, | ||||||
1916 | true /*IsDead*/)); | ||||||
1917 | return true; | ||||||
1918 | } | ||||||
1919 | |||||||
1920 | void MachineInstr::clearRegisterDeads(Register Reg) { | ||||||
1921 | for (MachineOperand &MO : operands()) { | ||||||
1922 | if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg) | ||||||
1923 | continue; | ||||||
1924 | MO.setIsDead(false); | ||||||
1925 | } | ||||||
1926 | } | ||||||
1927 | |||||||
1928 | void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) { | ||||||
1929 | for (MachineOperand &MO : operands()) { | ||||||
1930 | if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0) | ||||||
1931 | continue; | ||||||
1932 | MO.setIsUndef(IsUndef); | ||||||
1933 | } | ||||||
1934 | } | ||||||
1935 | |||||||
1936 | void MachineInstr::addRegisterDefined(Register Reg, | ||||||
1937 | const TargetRegisterInfo *RegInfo) { | ||||||
1938 | if (Register::isPhysicalRegister(Reg)) { | ||||||
1939 | MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo); | ||||||
1940 | if (MO) | ||||||
1941 | return; | ||||||
1942 | } else { | ||||||
1943 | for (const MachineOperand &MO : operands()) { | ||||||
1944 | if (MO.isReg() && MO.getReg() == Reg && MO.isDef() && | ||||||
1945 | MO.getSubReg() == 0) | ||||||
1946 | return; | ||||||
1947 | } | ||||||
1948 | } | ||||||
1949 | addOperand(MachineOperand::CreateReg(Reg, | ||||||
1950 | true /*IsDef*/, | ||||||
1951 | true /*IsImp*/)); | ||||||
1952 | } | ||||||
1953 | |||||||
1954 | void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs, | ||||||
1955 | const TargetRegisterInfo &TRI) { | ||||||
1956 | bool HasRegMask = false; | ||||||
1957 | for (MachineOperand &MO : operands()) { | ||||||
1958 | if (MO.isRegMask()) { | ||||||
1959 | HasRegMask = true; | ||||||
1960 | continue; | ||||||
1961 | } | ||||||
1962 | if (!MO.isReg() || !MO.isDef()) continue; | ||||||
1963 | Register Reg = MO.getReg(); | ||||||
1964 | if (!Reg.isPhysical()) | ||||||
1965 | continue; | ||||||
1966 | // If there are no uses, including partial uses, the def is dead. | ||||||
1967 | if (llvm::none_of(UsedRegs, | ||||||
1968 | [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); })) | ||||||
1969 | MO.setIsDead(); | ||||||
1970 | } | ||||||
1971 | |||||||
1972 | // This is a call with a register mask operand. | ||||||
1973 | // Mask clobbers are always dead, so add defs for the non-dead defines. | ||||||
1974 | if (HasRegMask) | ||||||
1975 | for (ArrayRef<Register>::iterator I = UsedRegs.begin(), E = UsedRegs.end(); | ||||||
1976 | I != E; ++I) | ||||||
1977 | addRegisterDefined(*I, &TRI); | ||||||
1978 | } | ||||||
1979 | |||||||
1980 | unsigned | ||||||
1981 | MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) { | ||||||
1982 | // Build up a buffer of hash code components. | ||||||
1983 | SmallVector<size_t, 16> HashComponents; | ||||||
1984 | HashComponents.reserve(MI->getNumOperands() + 1); | ||||||
1985 | HashComponents.push_back(MI->getOpcode()); | ||||||
1986 | for (const MachineOperand &MO : MI->operands()) { | ||||||
1987 | if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg())) | ||||||
1988 | continue; // Skip virtual register defs. | ||||||
1989 | |||||||
1990 | HashComponents.push_back(hash_value(MO)); | ||||||
1991 | } | ||||||
1992 | return hash_combine_range(HashComponents.begin(), HashComponents.end()); | ||||||
1993 | } | ||||||
1994 | |||||||
1995 | void MachineInstr::emitError(StringRef Msg) const { | ||||||
1996 | // Find the source location cookie. | ||||||
1997 | unsigned LocCookie = 0; | ||||||
1998 | const MDNode *LocMD = nullptr; | ||||||
1999 | for (unsigned i = getNumOperands(); i != 0; --i) { | ||||||
2000 | if (getOperand(i-1).isMetadata() && | ||||||
2001 | (LocMD = getOperand(i-1).getMetadata()) && | ||||||
2002 | LocMD->getNumOperands() != 0) { | ||||||
2003 | if (const ConstantInt *CI = | ||||||
2004 | mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) { | ||||||
2005 | LocCookie = CI->getZExtValue(); | ||||||
2006 | break; | ||||||
2007 | } | ||||||
2008 | } | ||||||
2009 | } | ||||||
2010 | |||||||
2011 | if (const MachineBasicBlock *MBB = getParent()) | ||||||
2012 | if (const MachineFunction *MF = MBB->getParent()) | ||||||
2013 | return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg); | ||||||
2014 | report_fatal_error(Msg); | ||||||
2015 | } | ||||||
2016 | |||||||
2017 | MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL, | ||||||
2018 | const MCInstrDesc &MCID, bool IsIndirect, | ||||||
2019 | Register Reg, const MDNode *Variable, | ||||||
2020 | const MDNode *Expr) { | ||||||
2021 | assert(isa<DILocalVariable>(Variable) && "not a variable")((isa<DILocalVariable>(Variable) && "not a variable" ) ? static_cast<void> (0) : __assert_fail ("isa<DILocalVariable>(Variable) && \"not a variable\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 2021, __PRETTY_FUNCTION__)); | ||||||
2022 | assert(cast<DIExpression>(Expr)->isValid() && "not an expression")((cast<DIExpression>(Expr)->isValid() && "not an expression" ) ? static_cast<void> (0) : __assert_fail ("cast<DIExpression>(Expr)->isValid() && \"not an expression\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 2022, __PRETTY_FUNCTION__)); | ||||||
2023 | assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic (DL) && "Expected inlined-at fields to agree") ? static_cast <void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 2024, __PRETTY_FUNCTION__)) | ||||||
2024 | "Expected inlined-at fields to agree")((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic (DL) && "Expected inlined-at fields to agree") ? static_cast <void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 2024, __PRETTY_FUNCTION__)); | ||||||
2025 | auto MIB = BuildMI(MF, DL, MCID).addReg(Reg, RegState::Debug); | ||||||
2026 | if (IsIndirect) | ||||||
2027 | MIB.addImm(0U); | ||||||
2028 | else | ||||||
2029 | MIB.addReg(0U, RegState::Debug); | ||||||
2030 | return MIB.addMetadata(Variable).addMetadata(Expr); | ||||||
2031 | } | ||||||
2032 | |||||||
2033 | MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL, | ||||||
2034 | const MCInstrDesc &MCID, bool IsIndirect, | ||||||
2035 | MachineOperand &MO, const MDNode *Variable, | ||||||
2036 | const MDNode *Expr) { | ||||||
2037 | assert(isa<DILocalVariable>(Variable) && "not a variable")((isa<DILocalVariable>(Variable) && "not a variable" ) ? static_cast<void> (0) : __assert_fail ("isa<DILocalVariable>(Variable) && \"not a variable\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 2037, __PRETTY_FUNCTION__)); | ||||||
2038 | assert(cast<DIExpression>(Expr)->isValid() && "not an expression")((cast<DIExpression>(Expr)->isValid() && "not an expression" ) ? static_cast<void> (0) : __assert_fail ("cast<DIExpression>(Expr)->isValid() && \"not an expression\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 2038, __PRETTY_FUNCTION__)); | ||||||
2039 | assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic (DL) && "Expected inlined-at fields to agree") ? static_cast <void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 2040, __PRETTY_FUNCTION__)) | ||||||
2040 | "Expected inlined-at fields to agree")((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic (DL) && "Expected inlined-at fields to agree") ? static_cast <void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 2040, __PRETTY_FUNCTION__)); | ||||||
2041 | if (MO.isReg()) | ||||||
2042 | return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr); | ||||||
2043 | |||||||
2044 | auto MIB = BuildMI(MF, DL, MCID).add(MO); | ||||||
2045 | if (IsIndirect) | ||||||
2046 | MIB.addImm(0U); | ||||||
2047 | else | ||||||
2048 | MIB.addReg(0U, RegState::Debug); | ||||||
2049 | return MIB.addMetadata(Variable).addMetadata(Expr); | ||||||
2050 | } | ||||||
2051 | |||||||
2052 | MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB, | ||||||
2053 | MachineBasicBlock::iterator I, | ||||||
2054 | const DebugLoc &DL, const MCInstrDesc &MCID, | ||||||
2055 | bool IsIndirect, Register Reg, | ||||||
2056 | const MDNode *Variable, const MDNode *Expr) { | ||||||
2057 | MachineFunction &MF = *BB.getParent(); | ||||||
2058 | MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr); | ||||||
2059 | BB.insert(I, MI); | ||||||
2060 | return MachineInstrBuilder(MF, MI); | ||||||
2061 | } | ||||||
2062 | |||||||
2063 | MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB, | ||||||
2064 | MachineBasicBlock::iterator I, | ||||||
2065 | const DebugLoc &DL, const MCInstrDesc &MCID, | ||||||
2066 | bool IsIndirect, MachineOperand &MO, | ||||||
2067 | const MDNode *Variable, const MDNode *Expr) { | ||||||
2068 | MachineFunction &MF = *BB.getParent(); | ||||||
2069 | MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr); | ||||||
2070 | BB.insert(I, MI); | ||||||
2071 | return MachineInstrBuilder(MF, *MI); | ||||||
2072 | } | ||||||
2073 | |||||||
2074 | /// Compute the new DIExpression to use with a DBG_VALUE for a spill slot. | ||||||
2075 | /// This prepends DW_OP_deref when spilling an indirect DBG_VALUE. | ||||||
2076 | static const DIExpression *computeExprForSpill(const MachineInstr &MI) { | ||||||
2077 | assert(MI.getOperand(0).isReg() && "can't spill non-register")((MI.getOperand(0).isReg() && "can't spill non-register" ) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(0).isReg() && \"can't spill non-register\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 2077, __PRETTY_FUNCTION__)); | ||||||
2078 | assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&((MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc ()) && "Expected inlined-at fields to agree") ? static_cast <void> (0) : __assert_fail ("MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) && \"Expected inlined-at fields to agree\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 2079, __PRETTY_FUNCTION__)) | ||||||
2079 | "Expected inlined-at fields to agree")((MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc ()) && "Expected inlined-at fields to agree") ? static_cast <void> (0) : __assert_fail ("MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) && \"Expected inlined-at fields to agree\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 2079, __PRETTY_FUNCTION__)); | ||||||
2080 | |||||||
2081 | const DIExpression *Expr = MI.getDebugExpression(); | ||||||
2082 | if (MI.isIndirectDebugValue()) { | ||||||
2083 | assert(MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset")((MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset" ) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(1).getImm() == 0 && \"DBG_VALUE with nonzero offset\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/lib/CodeGen/MachineInstr.cpp" , 2083, __PRETTY_FUNCTION__)); | ||||||
2084 | Expr = DIExpression::prepend(Expr, DIExpression::DerefBefore); | ||||||
2085 | } | ||||||
2086 | return Expr; | ||||||
2087 | } | ||||||
2088 | |||||||
2089 | MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB, | ||||||
2090 | MachineBasicBlock::iterator I, | ||||||
2091 | const MachineInstr &Orig, | ||||||
2092 | int FrameIndex) { | ||||||
2093 | const DIExpression *Expr = computeExprForSpill(Orig); | ||||||
2094 | return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc()) | ||||||
| |||||||
2095 | .addFrameIndex(FrameIndex) | ||||||
2096 | .addImm(0U) | ||||||
2097 | .addMetadata(Orig.getDebugVariable()) | ||||||
2098 | .addMetadata(Expr); | ||||||
2099 | } | ||||||
2100 | |||||||
2101 | void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex) { | ||||||
2102 | const DIExpression *Expr = computeExprForSpill(Orig); | ||||||
2103 | Orig.getOperand(0).ChangeToFrameIndex(FrameIndex); | ||||||
2104 | Orig.getOperand(1).ChangeToImmediate(0U); | ||||||
2105 | Orig.getOperand(3).setMetadata(Expr); | ||||||
2106 | } | ||||||
2107 | |||||||
2108 | void MachineInstr::collectDebugValues( | ||||||
2109 | SmallVectorImpl<MachineInstr *> &DbgValues) { | ||||||
2110 | MachineInstr &MI = *this; | ||||||
2111 | if (!MI.getOperand(0).isReg()) | ||||||
2112 | return; | ||||||
2113 | |||||||
2114 | MachineBasicBlock::iterator DI = MI; ++DI; | ||||||
2115 | for (MachineBasicBlock::iterator DE = MI.getParent()->end(); | ||||||
2116 | DI != DE; ++DI) { | ||||||
2117 | if (!DI->isDebugValue()) | ||||||
2118 | return; | ||||||
2119 | if (DI->getOperand(0).isReg() && | ||||||
2120 | DI->getOperand(0).getReg() == MI.getOperand(0).getReg()) | ||||||
2121 | DbgValues.push_back(&*DI); | ||||||
2122 | } | ||||||
2123 | } | ||||||
2124 | |||||||
2125 | void MachineInstr::changeDebugValuesDefReg(Register Reg) { | ||||||
2126 | // Collect matching debug values. | ||||||
2127 | SmallVector<MachineInstr *, 2> DbgValues; | ||||||
2128 | |||||||
2129 | if (!getOperand(0).isReg()) | ||||||
2130 | return; | ||||||
2131 | |||||||
2132 | unsigned DefReg = getOperand(0).getReg(); | ||||||
2133 | auto *MRI = getRegInfo(); | ||||||
2134 | for (auto &MO : MRI->use_operands(DefReg)) { | ||||||
2135 | auto *DI = MO.getParent(); | ||||||
2136 | if (!DI->isDebugValue()) | ||||||
2137 | continue; | ||||||
2138 | if (DI->getOperand(0).isReg() && | ||||||
2139 | DI->getOperand(0).getReg() == DefReg){ | ||||||
2140 | DbgValues.push_back(DI); | ||||||
2141 | } | ||||||
2142 | } | ||||||
2143 | |||||||
2144 | // Propagate Reg to debug value instructions. | ||||||
2145 | for (auto *DBI : DbgValues) | ||||||
2146 | DBI->getOperand(0).setReg(Reg); | ||||||
2147 | } | ||||||
2148 | |||||||
2149 | using MMOList = SmallVector<const MachineMemOperand *, 2>; | ||||||
2150 | |||||||
2151 | static unsigned getSpillSlotSize(MMOList &Accesses, | ||||||
2152 | const MachineFrameInfo &MFI) { | ||||||
2153 | unsigned Size = 0; | ||||||
2154 | for (auto A : Accesses) | ||||||
2155 | if (MFI.isSpillSlotObjectIndex( | ||||||
2156 | cast<FixedStackPseudoSourceValue>(A->getPseudoValue()) | ||||||
2157 | ->getFrameIndex())) | ||||||
2158 | Size += A->getSize(); | ||||||
2159 | return Size; | ||||||
2160 | } | ||||||
2161 | |||||||
2162 | Optional<unsigned> | ||||||
2163 | MachineInstr::getSpillSize(const TargetInstrInfo *TII) const { | ||||||
2164 | int FI; | ||||||
2165 | if (TII->isStoreToStackSlotPostFE(*this, FI)) { | ||||||
2166 | const MachineFrameInfo &MFI = getMF()->getFrameInfo(); | ||||||
2167 | if (MFI.isSpillSlotObjectIndex(FI)) | ||||||
2168 | return (*memoperands_begin())->getSize(); | ||||||
2169 | } | ||||||
2170 | return None; | ||||||
2171 | } | ||||||
2172 | |||||||
2173 | Optional<unsigned> | ||||||
2174 | MachineInstr::getFoldedSpillSize(const TargetInstrInfo *TII) const { | ||||||
2175 | MMOList Accesses; | ||||||
2176 | if (TII->hasStoreToStackSlot(*this, Accesses)) | ||||||
2177 | return getSpillSlotSize(Accesses, getMF()->getFrameInfo()); | ||||||
2178 | return None; | ||||||
2179 | } | ||||||
2180 | |||||||
2181 | Optional<unsigned> | ||||||
2182 | MachineInstr::getRestoreSize(const TargetInstrInfo *TII) const { | ||||||
2183 | int FI; | ||||||
2184 | if (TII->isLoadFromStackSlotPostFE(*this, FI)) { | ||||||
2185 | const MachineFrameInfo &MFI = getMF()->getFrameInfo(); | ||||||
2186 | if (MFI.isSpillSlotObjectIndex(FI)) | ||||||
2187 | return (*memoperands_begin())->getSize(); | ||||||
2188 | } | ||||||
2189 | return None; | ||||||
2190 | } | ||||||
2191 | |||||||
2192 | Optional<unsigned> | ||||||
2193 | MachineInstr::getFoldedRestoreSize(const TargetInstrInfo *TII) const { | ||||||
2194 | MMOList Accesses; | ||||||
2195 | if (TII->hasLoadFromStackSlot(*this, Accesses)) | ||||||
2196 | return getSpillSlotSize(Accesses, getMF()->getFrameInfo()); | ||||||
2197 | return None; | ||||||
2198 | } |
1 | //===- CodeGen/MachineInstrBuilder.h - Simplify creation of MIs --*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file exposes a function named BuildMI, which is useful for dramatically |
10 | // simplifying how MachineInstr's are created. It allows use of code like this: |
11 | // |
12 | // M = BuildMI(MBB, MI, DL, TII.get(X86::ADD8rr), Dst) |
13 | // .addReg(argVal1) |
14 | // .addReg(argVal2); |
15 | // |
16 | //===----------------------------------------------------------------------===// |
17 | |
18 | #ifndef LLVM_CODEGEN_MACHINEINSTRBUILDER_H |
19 | #define LLVM_CODEGEN_MACHINEINSTRBUILDER_H |
20 | |
21 | #include "llvm/ADT/ArrayRef.h" |
22 | #include "llvm/CodeGen/GlobalISel/Utils.h" |
23 | #include "llvm/CodeGen/MachineBasicBlock.h" |
24 | #include "llvm/CodeGen/MachineFunction.h" |
25 | #include "llvm/CodeGen/MachineInstr.h" |
26 | #include "llvm/CodeGen/MachineInstrBundle.h" |
27 | #include "llvm/CodeGen/MachineOperand.h" |
28 | #include "llvm/CodeGen/TargetRegisterInfo.h" |
29 | #include "llvm/IR/InstrTypes.h" |
30 | #include "llvm/IR/Intrinsics.h" |
31 | #include "llvm/Support/ErrorHandling.h" |
32 | #include <cassert> |
33 | #include <cstdint> |
34 | #include <utility> |
35 | |
36 | namespace llvm { |
37 | |
38 | class MCInstrDesc; |
39 | class MDNode; |
40 | |
41 | namespace RegState { |
42 | |
43 | enum { |
44 | Define = 0x2, |
45 | Implicit = 0x4, |
46 | Kill = 0x8, |
47 | Dead = 0x10, |
48 | Undef = 0x20, |
49 | EarlyClobber = 0x40, |
50 | Debug = 0x80, |
51 | InternalRead = 0x100, |
52 | Renamable = 0x200, |
53 | DefineNoRead = Define | Undef, |
54 | ImplicitDefine = Implicit | Define, |
55 | ImplicitKill = Implicit | Kill |
56 | }; |
57 | |
58 | } // end namespace RegState |
59 | |
60 | class MachineInstrBuilder { |
61 | MachineFunction *MF = nullptr; |
62 | MachineInstr *MI = nullptr; |
63 | |
64 | public: |
65 | MachineInstrBuilder() = default; |
66 | |
67 | /// Create a MachineInstrBuilder for manipulating an existing instruction. |
68 | /// F must be the machine function that was used to allocate I. |
69 | MachineInstrBuilder(MachineFunction &F, MachineInstr *I) : MF(&F), MI(I) {} |
70 | MachineInstrBuilder(MachineFunction &F, MachineBasicBlock::iterator I) |
71 | : MF(&F), MI(&*I) {} |
72 | |
73 | /// Allow automatic conversion to the machine instruction we are working on. |
74 | operator MachineInstr*() const { return MI; } |
75 | MachineInstr *operator->() const { return MI; } |
76 | operator MachineBasicBlock::iterator() const { return MI; } |
77 | |
78 | /// If conversion operators fail, use this method to get the MachineInstr |
79 | /// explicitly. |
80 | MachineInstr *getInstr() const { return MI; } |
81 | |
82 | /// Get the register for the operand index. |
83 | /// The operand at the index should be a register (asserted by |
84 | /// MachineOperand). |
85 | Register getReg(unsigned Idx) const { return MI->getOperand(Idx).getReg(); } |
86 | |
87 | /// Add a new virtual register operand. |
88 | const MachineInstrBuilder &addReg(Register RegNo, unsigned flags = 0, |
89 | unsigned SubReg = 0) const { |
90 | assert((flags & 0x1) == 0 &&(((flags & 0x1) == 0 && "Passing in 'true' to addReg is forbidden! Use enums instead." ) ? static_cast<void> (0) : __assert_fail ("(flags & 0x1) == 0 && \"Passing in 'true' to addReg is forbidden! Use enums instead.\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/include/llvm/CodeGen/MachineInstrBuilder.h" , 91, __PRETTY_FUNCTION__)) |
91 | "Passing in 'true' to addReg is forbidden! Use enums instead.")(((flags & 0x1) == 0 && "Passing in 'true' to addReg is forbidden! Use enums instead." ) ? static_cast<void> (0) : __assert_fail ("(flags & 0x1) == 0 && \"Passing in 'true' to addReg is forbidden! Use enums instead.\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/include/llvm/CodeGen/MachineInstrBuilder.h" , 91, __PRETTY_FUNCTION__)); |
92 | MI->addOperand(*MF, MachineOperand::CreateReg(RegNo, |
93 | flags & RegState::Define, |
94 | flags & RegState::Implicit, |
95 | flags & RegState::Kill, |
96 | flags & RegState::Dead, |
97 | flags & RegState::Undef, |
98 | flags & RegState::EarlyClobber, |
99 | SubReg, |
100 | flags & RegState::Debug, |
101 | flags & RegState::InternalRead, |
102 | flags & RegState::Renamable)); |
103 | return *this; |
104 | } |
105 | |
106 | /// Add a virtual register definition operand. |
107 | const MachineInstrBuilder &addDef(Register RegNo, unsigned Flags = 0, |
108 | unsigned SubReg = 0) const { |
109 | return addReg(RegNo, Flags | RegState::Define, SubReg); |
110 | } |
111 | |
112 | /// Add a virtual register use operand. It is an error for Flags to contain |
113 | /// `RegState::Define` when calling this function. |
114 | const MachineInstrBuilder &addUse(Register RegNo, unsigned Flags = 0, |
115 | unsigned SubReg = 0) const { |
116 | assert(!(Flags & RegState::Define) &&((!(Flags & RegState::Define) && "Misleading addUse defines register, use addReg instead." ) ? static_cast<void> (0) : __assert_fail ("!(Flags & RegState::Define) && \"Misleading addUse defines register, use addReg instead.\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/include/llvm/CodeGen/MachineInstrBuilder.h" , 117, __PRETTY_FUNCTION__)) |
117 | "Misleading addUse defines register, use addReg instead.")((!(Flags & RegState::Define) && "Misleading addUse defines register, use addReg instead." ) ? static_cast<void> (0) : __assert_fail ("!(Flags & RegState::Define) && \"Misleading addUse defines register, use addReg instead.\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/include/llvm/CodeGen/MachineInstrBuilder.h" , 117, __PRETTY_FUNCTION__)); |
118 | return addReg(RegNo, Flags, SubReg); |
119 | } |
120 | |
121 | /// Add a new immediate operand. |
122 | const MachineInstrBuilder &addImm(int64_t Val) const { |
123 | MI->addOperand(*MF, MachineOperand::CreateImm(Val)); |
124 | return *this; |
125 | } |
126 | |
127 | const MachineInstrBuilder &addCImm(const ConstantInt *Val) const { |
128 | MI->addOperand(*MF, MachineOperand::CreateCImm(Val)); |
129 | return *this; |
130 | } |
131 | |
132 | const MachineInstrBuilder &addFPImm(const ConstantFP *Val) const { |
133 | MI->addOperand(*MF, MachineOperand::CreateFPImm(Val)); |
134 | return *this; |
135 | } |
136 | |
137 | const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB, |
138 | unsigned TargetFlags = 0) const { |
139 | MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags)); |
140 | return *this; |
141 | } |
142 | |
143 | const MachineInstrBuilder &addFrameIndex(int Idx) const { |
144 | MI->addOperand(*MF, MachineOperand::CreateFI(Idx)); |
145 | return *this; |
146 | } |
147 | |
148 | const MachineInstrBuilder & |
149 | addConstantPoolIndex(unsigned Idx, int Offset = 0, |
150 | unsigned TargetFlags = 0) const { |
151 | MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags)); |
152 | return *this; |
153 | } |
154 | |
155 | const MachineInstrBuilder &addTargetIndex(unsigned Idx, int64_t Offset = 0, |
156 | unsigned TargetFlags = 0) const { |
157 | MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset, |
158 | TargetFlags)); |
159 | return *this; |
160 | } |
161 | |
162 | const MachineInstrBuilder &addJumpTableIndex(unsigned Idx, |
163 | unsigned TargetFlags = 0) const { |
164 | MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags)); |
165 | return *this; |
166 | } |
167 | |
168 | const MachineInstrBuilder &addGlobalAddress(const GlobalValue *GV, |
169 | int64_t Offset = 0, |
170 | unsigned TargetFlags = 0) const { |
171 | MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags)); |
172 | return *this; |
173 | } |
174 | |
175 | const MachineInstrBuilder &addExternalSymbol(const char *FnName, |
176 | unsigned TargetFlags = 0) const { |
177 | MI->addOperand(*MF, MachineOperand::CreateES(FnName, TargetFlags)); |
178 | return *this; |
179 | } |
180 | |
181 | const MachineInstrBuilder &addBlockAddress(const BlockAddress *BA, |
182 | int64_t Offset = 0, |
183 | unsigned TargetFlags = 0) const { |
184 | MI->addOperand(*MF, MachineOperand::CreateBA(BA, Offset, TargetFlags)); |
185 | return *this; |
186 | } |
187 | |
188 | const MachineInstrBuilder &addRegMask(const uint32_t *Mask) const { |
189 | MI->addOperand(*MF, MachineOperand::CreateRegMask(Mask)); |
190 | return *this; |
191 | } |
192 | |
193 | const MachineInstrBuilder &addMemOperand(MachineMemOperand *MMO) const { |
194 | MI->addMemOperand(*MF, MMO); |
195 | return *this; |
196 | } |
197 | |
198 | const MachineInstrBuilder & |
199 | setMemRefs(ArrayRef<MachineMemOperand *> MMOs) const { |
200 | MI->setMemRefs(*MF, MMOs); |
201 | return *this; |
202 | } |
203 | |
204 | const MachineInstrBuilder &cloneMemRefs(const MachineInstr &OtherMI) const { |
205 | MI->cloneMemRefs(*MF, OtherMI); |
206 | return *this; |
207 | } |
208 | |
209 | const MachineInstrBuilder & |
210 | cloneMergedMemRefs(ArrayRef<const MachineInstr *> OtherMIs) const { |
211 | MI->cloneMergedMemRefs(*MF, OtherMIs); |
212 | return *this; |
213 | } |
214 | |
215 | const MachineInstrBuilder &add(const MachineOperand &MO) const { |
216 | MI->addOperand(*MF, MO); |
217 | return *this; |
218 | } |
219 | |
220 | const MachineInstrBuilder &add(ArrayRef<MachineOperand> MOs) const { |
221 | for (const MachineOperand &MO : MOs) { |
222 | MI->addOperand(*MF, MO); |
223 | } |
224 | return *this; |
225 | } |
226 | |
227 | const MachineInstrBuilder &addMetadata(const MDNode *MD) const { |
228 | MI->addOperand(*MF, MachineOperand::CreateMetadata(MD)); |
229 | assert((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable())(((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable ()) : true) && "first MDNode argument of a DBG_VALUE not a variable" ) ? static_cast<void> (0) : __assert_fail ("(MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable()) : true) && \"first MDNode argument of a DBG_VALUE not a variable\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/include/llvm/CodeGen/MachineInstrBuilder.h" , 231, __PRETTY_FUNCTION__)) |
230 | : true) &&(((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable ()) : true) && "first MDNode argument of a DBG_VALUE not a variable" ) ? static_cast<void> (0) : __assert_fail ("(MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable()) : true) && \"first MDNode argument of a DBG_VALUE not a variable\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/include/llvm/CodeGen/MachineInstrBuilder.h" , 231, __PRETTY_FUNCTION__)) |
231 | "first MDNode argument of a DBG_VALUE not a variable")(((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable ()) : true) && "first MDNode argument of a DBG_VALUE not a variable" ) ? static_cast<void> (0) : __assert_fail ("(MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable()) : true) && \"first MDNode argument of a DBG_VALUE not a variable\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/include/llvm/CodeGen/MachineInstrBuilder.h" , 231, __PRETTY_FUNCTION__)); |
232 | assert((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel())(((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel ()) : true) && "first MDNode argument of a DBG_LABEL not a label" ) ? static_cast<void> (0) : __assert_fail ("(MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel()) : true) && \"first MDNode argument of a DBG_LABEL not a label\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/include/llvm/CodeGen/MachineInstrBuilder.h" , 234, __PRETTY_FUNCTION__)) |
233 | : true) &&(((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel ()) : true) && "first MDNode argument of a DBG_LABEL not a label" ) ? static_cast<void> (0) : __assert_fail ("(MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel()) : true) && \"first MDNode argument of a DBG_LABEL not a label\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/include/llvm/CodeGen/MachineInstrBuilder.h" , 234, __PRETTY_FUNCTION__)) |
234 | "first MDNode argument of a DBG_LABEL not a label")(((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel ()) : true) && "first MDNode argument of a DBG_LABEL not a label" ) ? static_cast<void> (0) : __assert_fail ("(MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel()) : true) && \"first MDNode argument of a DBG_LABEL not a label\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/include/llvm/CodeGen/MachineInstrBuilder.h" , 234, __PRETTY_FUNCTION__)); |
235 | return *this; |
236 | } |
237 | |
238 | const MachineInstrBuilder &addCFIIndex(unsigned CFIIndex) const { |
239 | MI->addOperand(*MF, MachineOperand::CreateCFIIndex(CFIIndex)); |
240 | return *this; |
241 | } |
242 | |
243 | const MachineInstrBuilder &addIntrinsicID(Intrinsic::ID ID) const { |
244 | MI->addOperand(*MF, MachineOperand::CreateIntrinsicID(ID)); |
245 | return *this; |
246 | } |
247 | |
248 | const MachineInstrBuilder &addPredicate(CmpInst::Predicate Pred) const { |
249 | MI->addOperand(*MF, MachineOperand::CreatePredicate(Pred)); |
250 | return *this; |
251 | } |
252 | |
253 | const MachineInstrBuilder &addShuffleMask(const Constant *Val) const { |
254 | MI->addOperand(*MF, MachineOperand::CreateShuffleMask(Val)); |
255 | return *this; |
256 | } |
257 | |
258 | const MachineInstrBuilder &addSym(MCSymbol *Sym, |
259 | unsigned char TargetFlags = 0) const { |
260 | MI->addOperand(*MF, MachineOperand::CreateMCSymbol(Sym, TargetFlags)); |
261 | return *this; |
262 | } |
263 | |
264 | const MachineInstrBuilder &setMIFlags(unsigned Flags) const { |
265 | MI->setFlags(Flags); |
266 | return *this; |
267 | } |
268 | |
269 | const MachineInstrBuilder &setMIFlag(MachineInstr::MIFlag Flag) const { |
270 | MI->setFlag(Flag); |
271 | return *this; |
272 | } |
273 | |
274 | // Add a displacement from an existing MachineOperand with an added offset. |
275 | const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off, |
276 | unsigned char TargetFlags = 0) const { |
277 | // If caller specifies new TargetFlags then use it, otherwise the |
278 | // default behavior is to copy the target flags from the existing |
279 | // MachineOperand. This means if the caller wants to clear the |
280 | // target flags it needs to do so explicitly. |
281 | if (0 == TargetFlags) |
282 | TargetFlags = Disp.getTargetFlags(); |
283 | |
284 | switch (Disp.getType()) { |
285 | default: |
286 | llvm_unreachable("Unhandled operand type in addDisp()")::llvm::llvm_unreachable_internal("Unhandled operand type in addDisp()" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/include/llvm/CodeGen/MachineInstrBuilder.h" , 286); |
287 | case MachineOperand::MO_Immediate: |
288 | return addImm(Disp.getImm() + off); |
289 | case MachineOperand::MO_ConstantPoolIndex: |
290 | return addConstantPoolIndex(Disp.getIndex(), Disp.getOffset() + off, |
291 | TargetFlags); |
292 | case MachineOperand::MO_GlobalAddress: |
293 | return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off, |
294 | TargetFlags); |
295 | case MachineOperand::MO_BlockAddress: |
296 | return addBlockAddress(Disp.getBlockAddress(), Disp.getOffset() + off, |
297 | TargetFlags); |
298 | } |
299 | } |
300 | |
301 | /// Copy all the implicit operands from OtherMI onto this one. |
302 | const MachineInstrBuilder & |
303 | copyImplicitOps(const MachineInstr &OtherMI) const { |
304 | MI->copyImplicitOps(*MF, OtherMI); |
305 | return *this; |
306 | } |
307 | |
308 | bool constrainAllUses(const TargetInstrInfo &TII, |
309 | const TargetRegisterInfo &TRI, |
310 | const RegisterBankInfo &RBI) const { |
311 | return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); |
312 | } |
313 | }; |
314 | |
315 | /// Builder interface. Specify how to create the initial instruction itself. |
316 | inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, |
317 | const MCInstrDesc &MCID) { |
318 | return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL)); |
319 | } |
320 | |
321 | /// This version of the builder sets up the first operand as a |
322 | /// destination virtual register. |
323 | inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, |
324 | const MCInstrDesc &MCID, Register DestReg) { |
325 | return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL)) |
326 | .addReg(DestReg, RegState::Define); |
327 | } |
328 | |
329 | /// This version of the builder inserts the newly-built instruction before |
330 | /// the given position in the given MachineBasicBlock, and sets up the first |
331 | /// operand as a destination virtual register. |
332 | inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, |
333 | MachineBasicBlock::iterator I, |
334 | const DebugLoc &DL, const MCInstrDesc &MCID, |
335 | Register DestReg) { |
336 | MachineFunction &MF = *BB.getParent(); |
337 | MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); |
338 | BB.insert(I, MI); |
339 | return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define); |
340 | } |
341 | |
342 | /// This version of the builder inserts the newly-built instruction before |
343 | /// the given position in the given MachineBasicBlock, and sets up the first |
344 | /// operand as a destination virtual register. |
345 | /// |
346 | /// If \c I is inside a bundle, then the newly inserted \a MachineInstr is |
347 | /// added to the same bundle. |
348 | inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, |
349 | MachineBasicBlock::instr_iterator I, |
350 | const DebugLoc &DL, const MCInstrDesc &MCID, |
351 | Register DestReg) { |
352 | MachineFunction &MF = *BB.getParent(); |
353 | MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); |
354 | BB.insert(I, MI); |
355 | return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define); |
356 | } |
357 | |
358 | inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I, |
359 | const DebugLoc &DL, const MCInstrDesc &MCID, |
360 | Register DestReg) { |
361 | // Calling the overload for instr_iterator is always correct. However, the |
362 | // definition is not available in headers, so inline the check. |
363 | if (I.isInsideBundle()) |
364 | return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID, DestReg); |
365 | return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID, DestReg); |
366 | } |
367 | |
368 | inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I, |
369 | const DebugLoc &DL, const MCInstrDesc &MCID, |
370 | Register DestReg) { |
371 | return BuildMI(BB, *I, DL, MCID, DestReg); |
372 | } |
373 | |
374 | /// This version of the builder inserts the newly-built instruction before the |
375 | /// given position in the given MachineBasicBlock, and does NOT take a |
376 | /// destination register. |
377 | inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, |
378 | MachineBasicBlock::iterator I, |
379 | const DebugLoc &DL, |
380 | const MCInstrDesc &MCID) { |
381 | MachineFunction &MF = *BB.getParent(); |
382 | MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); |
383 | BB.insert(I, MI); |
384 | return MachineInstrBuilder(MF, MI); |
385 | } |
386 | |
387 | inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, |
388 | MachineBasicBlock::instr_iterator I, |
389 | const DebugLoc &DL, |
390 | const MCInstrDesc &MCID) { |
391 | MachineFunction &MF = *BB.getParent(); |
392 | MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); |
393 | BB.insert(I, MI); |
394 | return MachineInstrBuilder(MF, MI); |
395 | } |
396 | |
397 | inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I, |
398 | const DebugLoc &DL, |
399 | const MCInstrDesc &MCID) { |
400 | // Calling the overload for instr_iterator is always correct. However, the |
401 | // definition is not available in headers, so inline the check. |
402 | if (I.isInsideBundle()) |
403 | return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID); |
404 | return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID); |
405 | } |
406 | |
407 | inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I, |
408 | const DebugLoc &DL, |
409 | const MCInstrDesc &MCID) { |
410 | return BuildMI(BB, *I, DL, MCID); |
411 | } |
412 | |
413 | /// This version of the builder inserts the newly-built instruction at the end |
414 | /// of the given MachineBasicBlock, and does NOT take a destination register. |
415 | inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc &DL, |
416 | const MCInstrDesc &MCID) { |
417 | return BuildMI(*BB, BB->end(), DL, MCID); |
418 | } |
419 | |
420 | /// This version of the builder inserts the newly-built instruction at the |
421 | /// end of the given MachineBasicBlock, and sets up the first operand as a |
422 | /// destination virtual register. |
423 | inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc &DL, |
424 | const MCInstrDesc &MCID, Register DestReg) { |
425 | return BuildMI(*BB, BB->end(), DL, MCID, DestReg); |
426 | } |
427 | |
428 | /// This version of the builder builds a DBG_VALUE intrinsic |
429 | /// for either a value in a register or a register-indirect |
430 | /// address. The convention is that a DBG_VALUE is indirect iff the |
431 | /// second operand is an immediate. |
432 | MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, |
433 | const MCInstrDesc &MCID, bool IsIndirect, |
434 | Register Reg, const MDNode *Variable, |
435 | const MDNode *Expr); |
436 | |
437 | /// This version of the builder builds a DBG_VALUE intrinsic |
438 | /// for a MachineOperand. |
439 | MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, |
440 | const MCInstrDesc &MCID, bool IsIndirect, |
441 | MachineOperand &MO, const MDNode *Variable, |
442 | const MDNode *Expr); |
443 | |
444 | /// This version of the builder builds a DBG_VALUE intrinsic |
445 | /// for either a value in a register or a register-indirect |
446 | /// address and inserts it at position I. |
447 | MachineInstrBuilder BuildMI(MachineBasicBlock &BB, |
448 | MachineBasicBlock::iterator I, const DebugLoc &DL, |
449 | const MCInstrDesc &MCID, bool IsIndirect, |
450 | Register Reg, const MDNode *Variable, |
451 | const MDNode *Expr); |
452 | |
453 | /// This version of the builder builds a DBG_VALUE intrinsic |
454 | /// for a machine operand and inserts it at position I. |
455 | MachineInstrBuilder BuildMI(MachineBasicBlock &BB, |
456 | MachineBasicBlock::iterator I, const DebugLoc &DL, |
457 | const MCInstrDesc &MCID, bool IsIndirect, |
458 | MachineOperand &MO, const MDNode *Variable, |
459 | const MDNode *Expr); |
460 | |
461 | /// Clone a DBG_VALUE whose value has been spilled to FrameIndex. |
462 | MachineInstr *buildDbgValueForSpill(MachineBasicBlock &BB, |
463 | MachineBasicBlock::iterator I, |
464 | const MachineInstr &Orig, int FrameIndex); |
465 | |
466 | /// Update a DBG_VALUE whose value has been spilled to FrameIndex. Useful when |
467 | /// modifying an instruction in place while iterating over a basic block. |
468 | void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex); |
469 | |
470 | inline unsigned getDefRegState(bool B) { |
471 | return B ? RegState::Define : 0; |
472 | } |
473 | inline unsigned getImplRegState(bool B) { |
474 | return B ? RegState::Implicit : 0; |
475 | } |
476 | inline unsigned getKillRegState(bool B) { |
477 | return B ? RegState::Kill : 0; |
478 | } |
479 | inline unsigned getDeadRegState(bool B) { |
480 | return B ? RegState::Dead : 0; |
481 | } |
482 | inline unsigned getUndefRegState(bool B) { |
483 | return B ? RegState::Undef : 0; |
484 | } |
485 | inline unsigned getInternalReadRegState(bool B) { |
486 | return B ? RegState::InternalRead : 0; |
487 | } |
488 | inline unsigned getDebugRegState(bool B) { |
489 | return B ? RegState::Debug : 0; |
490 | } |
491 | inline unsigned getRenamableRegState(bool B) { |
492 | return B ? RegState::Renamable : 0; |
493 | } |
494 | |
495 | /// Get all register state flags from machine operand \p RegOp. |
496 | inline unsigned getRegState(const MachineOperand &RegOp) { |
497 | assert(RegOp.isReg() && "Not a register operand")((RegOp.isReg() && "Not a register operand") ? static_cast <void> (0) : __assert_fail ("RegOp.isReg() && \"Not a register operand\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/include/llvm/CodeGen/MachineInstrBuilder.h" , 497, __PRETTY_FUNCTION__)); |
498 | return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) | |
499 | getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) | |
500 | getUndefRegState(RegOp.isUndef()) | |
501 | getInternalReadRegState(RegOp.isInternalRead()) | |
502 | getDebugRegState(RegOp.isDebug()) | |
503 | getRenamableRegState(Register::isPhysicalRegister(RegOp.getReg()) && |
504 | RegOp.isRenamable()); |
505 | } |
506 | |
507 | /// Helper class for constructing bundles of MachineInstrs. |
508 | /// |
509 | /// MIBundleBuilder can create a bundle from scratch by inserting new |
510 | /// MachineInstrs one at a time, or it can create a bundle from a sequence of |
511 | /// existing MachineInstrs in a basic block. |
512 | class MIBundleBuilder { |
513 | MachineBasicBlock &MBB; |
514 | MachineBasicBlock::instr_iterator Begin; |
515 | MachineBasicBlock::instr_iterator End; |
516 | |
517 | public: |
518 | /// Create an MIBundleBuilder that inserts instructions into a new bundle in |
519 | /// BB above the bundle or instruction at Pos. |
520 | MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator Pos) |
521 | : MBB(BB), Begin(Pos.getInstrIterator()), End(Begin) {} |
522 | |
523 | /// Create a bundle from the sequence of instructions between B and E. |
524 | MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator B, |
525 | MachineBasicBlock::iterator E) |
526 | : MBB(BB), Begin(B.getInstrIterator()), End(E.getInstrIterator()) { |
527 | assert(B != E && "No instructions to bundle")((B != E && "No instructions to bundle") ? static_cast <void> (0) : __assert_fail ("B != E && \"No instructions to bundle\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/include/llvm/CodeGen/MachineInstrBuilder.h" , 527, __PRETTY_FUNCTION__)); |
528 | ++B; |
529 | while (B != E) { |
530 | MachineInstr &MI = *B; |
531 | ++B; |
532 | MI.bundleWithPred(); |
533 | } |
534 | } |
535 | |
536 | /// Create an MIBundleBuilder representing an existing instruction or bundle |
537 | /// that has MI as its head. |
538 | explicit MIBundleBuilder(MachineInstr *MI) |
539 | : MBB(*MI->getParent()), Begin(MI), |
540 | End(getBundleEnd(MI->getIterator())) {} |
541 | |
542 | /// Return a reference to the basic block containing this bundle. |
543 | MachineBasicBlock &getMBB() const { return MBB; } |
544 | |
545 | /// Return true if no instructions have been inserted in this bundle yet. |
546 | /// Empty bundles aren't representable in a MachineBasicBlock. |
547 | bool empty() const { return Begin == End; } |
548 | |
549 | /// Return an iterator to the first bundled instruction. |
550 | MachineBasicBlock::instr_iterator begin() const { return Begin; } |
551 | |
552 | /// Return an iterator beyond the last bundled instruction. |
553 | MachineBasicBlock::instr_iterator end() const { return End; } |
554 | |
555 | /// Insert MI into this bundle before I which must point to an instruction in |
556 | /// the bundle, or end(). |
557 | MIBundleBuilder &insert(MachineBasicBlock::instr_iterator I, |
558 | MachineInstr *MI) { |
559 | MBB.insert(I, MI); |
560 | if (I == Begin) { |
561 | if (!empty()) |
562 | MI->bundleWithSucc(); |
563 | Begin = MI->getIterator(); |
564 | return *this; |
565 | } |
566 | if (I == End) { |
567 | MI->bundleWithPred(); |
568 | return *this; |
569 | } |
570 | // MI was inserted in the middle of the bundle, so its neighbors' flags are |
571 | // already fine. Update MI's bundle flags manually. |
572 | MI->setFlag(MachineInstr::BundledPred); |
573 | MI->setFlag(MachineInstr::BundledSucc); |
574 | return *this; |
575 | } |
576 | |
577 | /// Insert MI into MBB by prepending it to the instructions in the bundle. |
578 | /// MI will become the first instruction in the bundle. |
579 | MIBundleBuilder &prepend(MachineInstr *MI) { |
580 | return insert(begin(), MI); |
581 | } |
582 | |
583 | /// Insert MI into MBB by appending it to the instructions in the bundle. |
584 | /// MI will become the last instruction in the bundle. |
585 | MIBundleBuilder &append(MachineInstr *MI) { |
586 | return insert(end(), MI); |
587 | } |
588 | }; |
589 | |
590 | } // end namespace llvm |
591 | |
592 | #endif // LLVM_CODEGEN_MACHINEINSTRBUILDER_H |
1 | //===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file contains the declaration of the MachineInstr class, which is the |
10 | // basic representation for all target dependent machine instructions used by |
11 | // the back end. |
12 | // |
13 | //===----------------------------------------------------------------------===// |
14 | |
15 | #ifndef LLVM_CODEGEN_MACHINEINSTR_H |
16 | #define LLVM_CODEGEN_MACHINEINSTR_H |
17 | |
18 | #include "llvm/ADT/DenseMapInfo.h" |
19 | #include "llvm/ADT/PointerSumType.h" |
20 | #include "llvm/ADT/ilist.h" |
21 | #include "llvm/ADT/ilist_node.h" |
22 | #include "llvm/ADT/iterator_range.h" |
23 | #include "llvm/CodeGen/MachineMemOperand.h" |
24 | #include "llvm/CodeGen/MachineOperand.h" |
25 | #include "llvm/CodeGen/TargetOpcodes.h" |
26 | #include "llvm/IR/DebugLoc.h" |
27 | #include "llvm/IR/InlineAsm.h" |
28 | #include "llvm/MC/MCInstrDesc.h" |
29 | #include "llvm/MC/MCSymbol.h" |
30 | #include "llvm/Support/ArrayRecycler.h" |
31 | #include "llvm/Support/TrailingObjects.h" |
32 | #include <algorithm> |
33 | #include <cassert> |
34 | #include <cstdint> |
35 | #include <utility> |
36 | |
37 | namespace llvm { |
38 | |
39 | class AAResults; |
40 | template <typename T> class ArrayRef; |
41 | class DIExpression; |
42 | class DILocalVariable; |
43 | class MachineBasicBlock; |
44 | class MachineFunction; |
45 | class MachineMemOperand; |
46 | class MachineRegisterInfo; |
47 | class ModuleSlotTracker; |
48 | class raw_ostream; |
49 | template <typename T> class SmallVectorImpl; |
50 | class SmallBitVector; |
51 | class StringRef; |
52 | class TargetInstrInfo; |
53 | class TargetRegisterClass; |
54 | class TargetRegisterInfo; |
55 | |
56 | //===----------------------------------------------------------------------===// |
57 | /// Representation of each machine instruction. |
58 | /// |
59 | /// This class isn't a POD type, but it must have a trivial destructor. When a |
60 | /// MachineFunction is deleted, all the contained MachineInstrs are deallocated |
61 | /// without having their destructor called. |
62 | /// |
63 | class MachineInstr |
64 | : public ilist_node_with_parent<MachineInstr, MachineBasicBlock, |
65 | ilist_sentinel_tracking<true>> { |
66 | public: |
67 | using mmo_iterator = ArrayRef<MachineMemOperand *>::iterator; |
68 | |
69 | /// Flags to specify different kinds of comments to output in |
70 | /// assembly code. These flags carry semantic information not |
71 | /// otherwise easily derivable from the IR text. |
72 | /// |
73 | enum CommentFlag { |
74 | ReloadReuse = 0x1, // higher bits are reserved for target dep comments. |
75 | NoSchedComment = 0x2, |
76 | TAsmComments = 0x4 // Target Asm comments should start from this value. |
77 | }; |
78 | |
79 | enum MIFlag { |
80 | NoFlags = 0, |
81 | FrameSetup = 1 << 0, // Instruction is used as a part of |
82 | // function frame setup code. |
83 | FrameDestroy = 1 << 1, // Instruction is used as a part of |
84 | // function frame destruction code. |
85 | BundledPred = 1 << 2, // Instruction has bundled predecessors. |
86 | BundledSucc = 1 << 3, // Instruction has bundled successors. |
87 | FmNoNans = 1 << 4, // Instruction does not support Fast |
88 | // math nan values. |
89 | FmNoInfs = 1 << 5, // Instruction does not support Fast |
90 | // math infinity values. |
91 | FmNsz = 1 << 6, // Instruction is not required to retain |
92 | // signed zero values. |
93 | FmArcp = 1 << 7, // Instruction supports Fast math |
94 | // reciprocal approximations. |
95 | FmContract = 1 << 8, // Instruction supports Fast math |
96 | // contraction operations like fma. |
97 | FmAfn = 1 << 9, // Instruction may map to Fast math |
98 | // instrinsic approximation. |
99 | FmReassoc = 1 << 10, // Instruction supports Fast math |
100 | // reassociation of operand order. |
101 | NoUWrap = 1 << 11, // Instruction supports binary operator |
102 | // no unsigned wrap. |
103 | NoSWrap = 1 << 12, // Instruction supports binary operator |
104 | // no signed wrap. |
105 | IsExact = 1 << 13, // Instruction supports division is |
106 | // known to be exact. |
107 | FPExcept = 1 << 14, // Instruction may raise floating-point |
108 | // exceptions. |
109 | }; |
110 | |
111 | private: |
112 | const MCInstrDesc *MCID; // Instruction descriptor. |
113 | MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block. |
114 | |
115 | // Operands are allocated by an ArrayRecycler. |
116 | MachineOperand *Operands = nullptr; // Pointer to the first operand. |
117 | unsigned NumOperands = 0; // Number of operands on instruction. |
118 | using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity; |
119 | OperandCapacity CapOperands; // Capacity of the Operands array. |
120 | |
121 | uint16_t Flags = 0; // Various bits of additional |
122 | // information about machine |
123 | // instruction. |
124 | |
125 | uint8_t AsmPrinterFlags = 0; // Various bits of information used by |
126 | // the AsmPrinter to emit helpful |
127 | // comments. This is *not* semantic |
128 | // information. Do not use this for |
129 | // anything other than to convey comment |
130 | // information to AsmPrinter. |
131 | |
132 | /// Internal implementation detail class that provides out-of-line storage for |
133 | /// extra info used by the machine instruction when this info cannot be stored |
134 | /// in-line within the instruction itself. |
135 | /// |
136 | /// This has to be defined eagerly due to the implementation constraints of |
137 | /// `PointerSumType` where it is used. |
138 | class ExtraInfo final |
139 | : TrailingObjects<ExtraInfo, MachineMemOperand *, MCSymbol *, MDNode *> { |
140 | public: |
141 | static ExtraInfo *create(BumpPtrAllocator &Allocator, |
142 | ArrayRef<MachineMemOperand *> MMOs, |
143 | MCSymbol *PreInstrSymbol = nullptr, |
144 | MCSymbol *PostInstrSymbol = nullptr, |
145 | MDNode *HeapAllocMarker = nullptr) { |
146 | bool HasPreInstrSymbol = PreInstrSymbol != nullptr; |
147 | bool HasPostInstrSymbol = PostInstrSymbol != nullptr; |
148 | bool HasHeapAllocMarker = HeapAllocMarker != nullptr; |
149 | auto *Result = new (Allocator.Allocate( |
150 | totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *>( |
151 | MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol, |
152 | HasHeapAllocMarker), |
153 | alignof(ExtraInfo))) |
154 | ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol, |
155 | HasHeapAllocMarker); |
156 | |
157 | // Copy the actual data into the trailing objects. |
158 | std::copy(MMOs.begin(), MMOs.end(), |
159 | Result->getTrailingObjects<MachineMemOperand *>()); |
160 | |
161 | if (HasPreInstrSymbol) |
162 | Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol; |
163 | if (HasPostInstrSymbol) |
164 | Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] = |
165 | PostInstrSymbol; |
166 | if (HasHeapAllocMarker) |
167 | Result->getTrailingObjects<MDNode *>()[0] = HeapAllocMarker; |
168 | |
169 | return Result; |
170 | } |
171 | |
172 | ArrayRef<MachineMemOperand *> getMMOs() const { |
173 | return makeArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs); |
174 | } |
175 | |
176 | MCSymbol *getPreInstrSymbol() const { |
177 | return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr; |
178 | } |
179 | |
180 | MCSymbol *getPostInstrSymbol() const { |
181 | return HasPostInstrSymbol |
182 | ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] |
183 | : nullptr; |
184 | } |
185 | |
186 | MDNode *getHeapAllocMarker() const { |
187 | return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr; |
188 | } |
189 | |
190 | private: |
191 | friend TrailingObjects; |
192 | |
193 | // Description of the extra info, used to interpret the actual optional |
194 | // data appended. |
195 | // |
196 | // Note that this is not terribly space optimized. This leaves a great deal |
197 | // of flexibility to fit more in here later. |
198 | const int NumMMOs; |
199 | const bool HasPreInstrSymbol; |
200 | const bool HasPostInstrSymbol; |
201 | const bool HasHeapAllocMarker; |
202 | |
203 | // Implement the `TrailingObjects` internal API. |
204 | size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const { |
205 | return NumMMOs; |
206 | } |
207 | size_t numTrailingObjects(OverloadToken<MCSymbol *>) const { |
208 | return HasPreInstrSymbol + HasPostInstrSymbol; |
209 | } |
210 | size_t numTrailingObjects(OverloadToken<MDNode *>) const { |
211 | return HasHeapAllocMarker; |
212 | } |
213 | |
214 | // Just a boring constructor to allow us to initialize the sizes. Always use |
215 | // the `create` routine above. |
216 | ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol, |
217 | bool HasHeapAllocMarker) |
218 | : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol), |
219 | HasPostInstrSymbol(HasPostInstrSymbol), |
220 | HasHeapAllocMarker(HasHeapAllocMarker) {} |
221 | }; |
222 | |
223 | /// Enumeration of the kinds of inline extra info available. It is important |
224 | /// that the `MachineMemOperand` inline kind has a tag value of zero to make |
225 | /// it accessible as an `ArrayRef`. |
226 | enum ExtraInfoInlineKinds { |
227 | EIIK_MMO = 0, |
228 | EIIK_PreInstrSymbol, |
229 | EIIK_PostInstrSymbol, |
230 | EIIK_OutOfLine |
231 | }; |
232 | |
233 | // We store extra information about the instruction here. The common case is |
234 | // expected to be nothing or a single pointer (typically a MMO or a symbol). |
235 | // We work to optimize this common case by storing it inline here rather than |
236 | // requiring a separate allocation, but we fall back to an allocation when |
237 | // multiple pointers are needed. |
238 | PointerSumType<ExtraInfoInlineKinds, |
239 | PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>, |
240 | PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>, |
241 | PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>, |
242 | PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>> |
243 | Info; |
244 | |
245 | DebugLoc debugLoc; // Source line information. |
246 | |
247 | // Intrusive list support |
248 | friend struct ilist_traits<MachineInstr>; |
249 | friend struct ilist_callback_traits<MachineBasicBlock>; |
250 | void setParent(MachineBasicBlock *P) { Parent = P; } |
251 | |
252 | /// This constructor creates a copy of the given |
253 | /// MachineInstr in the given MachineFunction. |
254 | MachineInstr(MachineFunction &, const MachineInstr &); |
255 | |
256 | /// This constructor create a MachineInstr and add the implicit operands. |
257 | /// It reserves space for number of operands specified by |
258 | /// MCInstrDesc. An explicit DebugLoc is supplied. |
259 | MachineInstr(MachineFunction &, const MCInstrDesc &tid, DebugLoc dl, |
260 | bool NoImp = false); |
261 | |
262 | // MachineInstrs are pool-allocated and owned by MachineFunction. |
263 | friend class MachineFunction; |
264 | |
265 | public: |
266 | MachineInstr(const MachineInstr &) = delete; |
267 | MachineInstr &operator=(const MachineInstr &) = delete; |
268 | // Use MachineFunction::DeleteMachineInstr() instead. |
269 | ~MachineInstr() = delete; |
270 | |
271 | const MachineBasicBlock* getParent() const { return Parent; } |
272 | MachineBasicBlock* getParent() { return Parent; } |
273 | |
274 | /// Return the function that contains the basic block that this instruction |
275 | /// belongs to. |
276 | /// |
277 | /// Note: this is undefined behaviour if the instruction does not have a |
278 | /// parent. |
279 | const MachineFunction *getMF() const; |
280 | MachineFunction *getMF() { |
281 | return const_cast<MachineFunction *>( |
282 | static_cast<const MachineInstr *>(this)->getMF()); |
283 | } |
284 | |
285 | /// Return the asm printer flags bitvector. |
286 | uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; } |
287 | |
288 | /// Clear the AsmPrinter bitvector. |
289 | void clearAsmPrinterFlags() { AsmPrinterFlags = 0; } |
290 | |
291 | /// Return whether an AsmPrinter flag is set. |
292 | bool getAsmPrinterFlag(CommentFlag Flag) const { |
293 | return AsmPrinterFlags & Flag; |
294 | } |
295 | |
296 | /// Set a flag for the AsmPrinter. |
297 | void setAsmPrinterFlag(uint8_t Flag) { |
298 | AsmPrinterFlags |= Flag; |
299 | } |
300 | |
301 | /// Clear specific AsmPrinter flags. |
302 | void clearAsmPrinterFlag(CommentFlag Flag) { |
303 | AsmPrinterFlags &= ~Flag; |
304 | } |
305 | |
306 | /// Return the MI flags bitvector. |
307 | uint16_t getFlags() const { |
308 | return Flags; |
309 | } |
310 | |
311 | /// Return whether an MI flag is set. |
312 | bool getFlag(MIFlag Flag) const { |
313 | return Flags & Flag; |
314 | } |
315 | |
316 | /// Set a MI flag. |
317 | void setFlag(MIFlag Flag) { |
318 | Flags |= (uint16_t)Flag; |
319 | } |
320 | |
321 | void setFlags(unsigned flags) { |
322 | // Filter out the automatically maintained flags. |
323 | unsigned Mask = BundledPred | BundledSucc; |
324 | Flags = (Flags & Mask) | (flags & ~Mask); |
325 | } |
326 | |
327 | /// clearFlag - Clear a MI flag. |
328 | void clearFlag(MIFlag Flag) { |
329 | Flags &= ~((uint16_t)Flag); |
330 | } |
331 | |
332 | /// Return true if MI is in a bundle (but not the first MI in a bundle). |
333 | /// |
334 | /// A bundle looks like this before it's finalized: |
335 | /// ---------------- |
336 | /// | MI | |
337 | /// ---------------- |
338 | /// | |
339 | /// ---------------- |
340 | /// | MI * | |
341 | /// ---------------- |
342 | /// | |
343 | /// ---------------- |
344 | /// | MI * | |
345 | /// ---------------- |
346 | /// In this case, the first MI starts a bundle but is not inside a bundle, the |
347 | /// next 2 MIs are considered "inside" the bundle. |
348 | /// |
349 | /// After a bundle is finalized, it looks like this: |
350 | /// ---------------- |
351 | /// | Bundle | |
352 | /// ---------------- |
353 | /// | |
354 | /// ---------------- |
355 | /// | MI * | |
356 | /// ---------------- |
357 | /// | |
358 | /// ---------------- |
359 | /// | MI * | |
360 | /// ---------------- |
361 | /// | |
362 | /// ---------------- |
363 | /// | MI * | |
364 | /// ---------------- |
365 | /// The first instruction has the special opcode "BUNDLE". It's not "inside" |
366 | /// a bundle, but the next three MIs are. |
367 | bool isInsideBundle() const { |
368 | return getFlag(BundledPred); |
369 | } |
370 | |
371 | /// Return true if this instruction part of a bundle. This is true |
372 | /// if either itself or its following instruction is marked "InsideBundle". |
373 | bool isBundled() const { |
374 | return isBundledWithPred() || isBundledWithSucc(); |
375 | } |
376 | |
377 | /// Return true if this instruction is part of a bundle, and it is not the |
378 | /// first instruction in the bundle. |
379 | bool isBundledWithPred() const { return getFlag(BundledPred); } |
380 | |
381 | /// Return true if this instruction is part of a bundle, and it is not the |
382 | /// last instruction in the bundle. |
383 | bool isBundledWithSucc() const { return getFlag(BundledSucc); } |
384 | |
385 | /// Bundle this instruction with its predecessor. This can be an unbundled |
386 | /// instruction, or it can be the first instruction in a bundle. |
387 | void bundleWithPred(); |
388 | |
389 | /// Bundle this instruction with its successor. This can be an unbundled |
390 | /// instruction, or it can be the last instruction in a bundle. |
391 | void bundleWithSucc(); |
392 | |
393 | /// Break bundle above this instruction. |
394 | void unbundleFromPred(); |
395 | |
396 | /// Break bundle below this instruction. |
397 | void unbundleFromSucc(); |
398 | |
399 | /// Returns the debug location id of this MachineInstr. |
400 | const DebugLoc &getDebugLoc() const { return debugLoc; } |
401 | |
402 | /// Return the debug variable referenced by |
403 | /// this DBG_VALUE instruction. |
404 | const DILocalVariable *getDebugVariable() const; |
405 | |
406 | /// Return the complex address expression referenced by |
407 | /// this DBG_VALUE instruction. |
408 | const DIExpression *getDebugExpression() const; |
409 | |
410 | /// Return the debug label referenced by |
411 | /// this DBG_LABEL instruction. |
412 | const DILabel *getDebugLabel() const; |
413 | |
414 | /// Emit an error referring to the source location of this instruction. |
415 | /// This should only be used for inline assembly that is somehow |
416 | /// impossible to compile. Other errors should have been handled much |
417 | /// earlier. |
418 | /// |
419 | /// If this method returns, the caller should try to recover from the error. |
420 | void emitError(StringRef Msg) const; |
421 | |
422 | /// Returns the target instruction descriptor of this MachineInstr. |
423 | const MCInstrDesc &getDesc() const { return *MCID; } |
424 | |
425 | /// Returns the opcode of this MachineInstr. |
426 | unsigned getOpcode() const { return MCID->Opcode; } |
427 | |
428 | /// Retuns the total number of operands. |
429 | unsigned getNumOperands() const { return NumOperands; } |
430 | |
431 | const MachineOperand& getOperand(unsigned i) const { |
432 | assert(i < getNumOperands() && "getOperand() out of range!")((i < getNumOperands() && "getOperand() out of range!" ) ? static_cast<void> (0) : __assert_fail ("i < getNumOperands() && \"getOperand() out of range!\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/include/llvm/CodeGen/MachineInstr.h" , 432, __PRETTY_FUNCTION__)); |
433 | return Operands[i]; |
434 | } |
435 | MachineOperand& getOperand(unsigned i) { |
436 | assert(i < getNumOperands() && "getOperand() out of range!")((i < getNumOperands() && "getOperand() out of range!" ) ? static_cast<void> (0) : __assert_fail ("i < getNumOperands() && \"getOperand() out of range!\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/include/llvm/CodeGen/MachineInstr.h" , 436, __PRETTY_FUNCTION__)); |
437 | return Operands[i]; |
438 | } |
439 | |
440 | /// Returns the total number of definitions. |
441 | unsigned getNumDefs() const { |
442 | return getNumExplicitDefs() + MCID->getNumImplicitDefs(); |
443 | } |
444 | |
445 | /// Returns true if the instruction has implicit definition. |
446 | bool hasImplicitDef() const { |
447 | for (unsigned I = getNumExplicitOperands(), E = getNumOperands(); |
448 | I != E; ++I) { |
449 | const MachineOperand &MO = getOperand(I); |
450 | if (MO.isDef() && MO.isImplicit()) |
451 | return true; |
452 | } |
453 | return false; |
454 | } |
455 | |
456 | /// Returns the implicit operands number. |
457 | unsigned getNumImplicitOperands() const { |
458 | return getNumOperands() - getNumExplicitOperands(); |
459 | } |
460 | |
461 | /// Return true if operand \p OpIdx is a subregister index. |
462 | bool isOperandSubregIdx(unsigned OpIdx) const { |
463 | assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate &&((getOperand(OpIdx).getType() == MachineOperand::MO_Immediate && "Expected MO_Immediate operand type.") ? static_cast <void> (0) : __assert_fail ("getOperand(OpIdx).getType() == MachineOperand::MO_Immediate && \"Expected MO_Immediate operand type.\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/include/llvm/CodeGen/MachineInstr.h" , 464, __PRETTY_FUNCTION__)) |
464 | "Expected MO_Immediate operand type.")((getOperand(OpIdx).getType() == MachineOperand::MO_Immediate && "Expected MO_Immediate operand type.") ? static_cast <void> (0) : __assert_fail ("getOperand(OpIdx).getType() == MachineOperand::MO_Immediate && \"Expected MO_Immediate operand type.\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/include/llvm/CodeGen/MachineInstr.h" , 464, __PRETTY_FUNCTION__)); |
465 | if (isExtractSubreg() && OpIdx == 2) |
466 | return true; |
467 | if (isInsertSubreg() && OpIdx == 3) |
468 | return true; |
469 | if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0) |
470 | return true; |
471 | if (isSubregToReg() && OpIdx == 3) |
472 | return true; |
473 | return false; |
474 | } |
475 | |
476 | /// Returns the number of non-implicit operands. |
477 | unsigned getNumExplicitOperands() const; |
478 | |
479 | /// Returns the number of non-implicit definitions. |
480 | unsigned getNumExplicitDefs() const; |
481 | |
482 | /// iterator/begin/end - Iterate over all operands of a machine instruction. |
483 | using mop_iterator = MachineOperand *; |
484 | using const_mop_iterator = const MachineOperand *; |
485 | |
486 | mop_iterator operands_begin() { return Operands; } |
487 | mop_iterator operands_end() { return Operands + NumOperands; } |
488 | |
489 | const_mop_iterator operands_begin() const { return Operands; } |
490 | const_mop_iterator operands_end() const { return Operands + NumOperands; } |
491 | |
492 | iterator_range<mop_iterator> operands() { |
493 | return make_range(operands_begin(), operands_end()); |
494 | } |
495 | iterator_range<const_mop_iterator> operands() const { |
496 | return make_range(operands_begin(), operands_end()); |
497 | } |
498 | iterator_range<mop_iterator> explicit_operands() { |
499 | return make_range(operands_begin(), |
500 | operands_begin() + getNumExplicitOperands()); |
501 | } |
502 | iterator_range<const_mop_iterator> explicit_operands() const { |
503 | return make_range(operands_begin(), |
504 | operands_begin() + getNumExplicitOperands()); |
505 | } |
506 | iterator_range<mop_iterator> implicit_operands() { |
507 | return make_range(explicit_operands().end(), operands_end()); |
508 | } |
509 | iterator_range<const_mop_iterator> implicit_operands() const { |
510 | return make_range(explicit_operands().end(), operands_end()); |
511 | } |
512 | /// Returns a range over all explicit operands that are register definitions. |
513 | /// Implicit definition are not included! |
514 | iterator_range<mop_iterator> defs() { |
515 | return make_range(operands_begin(), |
516 | operands_begin() + getNumExplicitDefs()); |
517 | } |
518 | /// \copydoc defs() |
519 | iterator_range<const_mop_iterator> defs() const { |
520 | return make_range(operands_begin(), |
521 | operands_begin() + getNumExplicitDefs()); |
522 | } |
523 | /// Returns a range that includes all operands that are register uses. |
524 | /// This may include unrelated operands which are not register uses. |
525 | iterator_range<mop_iterator> uses() { |
526 | return make_range(operands_begin() + getNumExplicitDefs(), operands_end()); |
527 | } |
528 | /// \copydoc uses() |
529 | iterator_range<const_mop_iterator> uses() const { |
530 | return make_range(operands_begin() + getNumExplicitDefs(), operands_end()); |
531 | } |
532 | iterator_range<mop_iterator> explicit_uses() { |
533 | return make_range(operands_begin() + getNumExplicitDefs(), |
534 | operands_begin() + getNumExplicitOperands()); |
535 | } |
536 | iterator_range<const_mop_iterator> explicit_uses() const { |
537 | return make_range(operands_begin() + getNumExplicitDefs(), |
538 | operands_begin() + getNumExplicitOperands()); |
539 | } |
540 | |
541 | /// Returns the number of the operand iterator \p I points to. |
542 | unsigned getOperandNo(const_mop_iterator I) const { |
543 | return I - operands_begin(); |
544 | } |
545 | |
546 | /// Access to memory operands of the instruction. If there are none, that does |
547 | /// not imply anything about whether the function accesses memory. Instead, |
548 | /// the caller must behave conservatively. |
549 | ArrayRef<MachineMemOperand *> memoperands() const { |
550 | if (!Info) |
551 | return {}; |
552 | |
553 | if (Info.is<EIIK_MMO>()) |
554 | return makeArrayRef(Info.getAddrOfZeroTagPointer(), 1); |
555 | |
556 | if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) |
557 | return EI->getMMOs(); |
558 | |
559 | return {}; |
560 | } |
561 | |
562 | /// Access to memory operands of the instruction. |
563 | /// |
564 | /// If `memoperands_begin() == memoperands_end()`, that does not imply |
565 | /// anything about whether the function accesses memory. Instead, the caller |
566 | /// must behave conservatively. |
567 | mmo_iterator memoperands_begin() const { return memoperands().begin(); } |
568 | |
569 | /// Access to memory operands of the instruction. |
570 | /// |
571 | /// If `memoperands_begin() == memoperands_end()`, that does not imply |
572 | /// anything about whether the function accesses memory. Instead, the caller |
573 | /// must behave conservatively. |
574 | mmo_iterator memoperands_end() const { return memoperands().end(); } |
575 | |
576 | /// Return true if we don't have any memory operands which described the |
577 | /// memory access done by this instruction. If this is true, calling code |
578 | /// must be conservative. |
579 | bool memoperands_empty() const { return memoperands().empty(); } |
580 | |
581 | /// Return true if this instruction has exactly one MachineMemOperand. |
582 | bool hasOneMemOperand() const { return memoperands().size() == 1; } |
583 | |
584 | /// Return the number of memory operands. |
585 | unsigned getNumMemOperands() const { return memoperands().size(); } |
586 | |
587 | /// Helper to extract a pre-instruction symbol if one has been added. |
588 | MCSymbol *getPreInstrSymbol() const { |
589 | if (!Info) |
590 | return nullptr; |
591 | if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>()) |
592 | return S; |
593 | if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) |
594 | return EI->getPreInstrSymbol(); |
595 | |
596 | return nullptr; |
597 | } |
598 | |
599 | /// Helper to extract a post-instruction symbol if one has been added. |
600 | MCSymbol *getPostInstrSymbol() const { |
601 | if (!Info) |
602 | return nullptr; |
603 | if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>()) |
604 | return S; |
605 | if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) |
606 | return EI->getPostInstrSymbol(); |
607 | |
608 | return nullptr; |
609 | } |
610 | |
611 | /// Helper to extract a heap alloc marker if one has been added. |
612 | MDNode *getHeapAllocMarker() const { |
613 | if (!Info) |
614 | return nullptr; |
615 | if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) |
616 | return EI->getHeapAllocMarker(); |
617 | |
618 | return nullptr; |
619 | } |
620 | |
621 | /// API for querying MachineInstr properties. They are the same as MCInstrDesc |
622 | /// queries but they are bundle aware. |
623 | |
624 | enum QueryType { |
625 | IgnoreBundle, // Ignore bundles |
626 | AnyInBundle, // Return true if any instruction in bundle has property |
627 | AllInBundle // Return true if all instructions in bundle have property |
628 | }; |
629 | |
630 | /// Return true if the instruction (or in the case of a bundle, |
631 | /// the instructions inside the bundle) has the specified property. |
632 | /// The first argument is the property being queried. |
633 | /// The second argument indicates whether the query should look inside |
634 | /// instruction bundles. |
635 | bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const { |
636 | assert(MCFlag < 64 &&((MCFlag < 64 && "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle." ) ? static_cast<void> (0) : __assert_fail ("MCFlag < 64 && \"MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/include/llvm/CodeGen/MachineInstr.h" , 637, __PRETTY_FUNCTION__)) |
637 | "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.")((MCFlag < 64 && "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle." ) ? static_cast<void> (0) : __assert_fail ("MCFlag < 64 && \"MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/include/llvm/CodeGen/MachineInstr.h" , 637, __PRETTY_FUNCTION__)); |
638 | // Inline the fast path for unbundled or bundle-internal instructions. |
639 | if (Type == IgnoreBundle || !isBundled() || isBundledWithPred()) |
640 | return getDesc().getFlags() & (1ULL << MCFlag); |
641 | |
642 | // If this is the first instruction in a bundle, take the slow path. |
643 | return hasPropertyInBundle(1ULL << MCFlag, Type); |
644 | } |
645 | |
646 | /// Return true if this is an instruction that should go through the usual |
647 | /// legalization steps. |
648 | bool isPreISelOpcode(QueryType Type = IgnoreBundle) const { |
649 | return hasProperty(MCID::PreISelOpcode, Type); |
650 | } |
651 | |
652 | /// Return true if this instruction can have a variable number of operands. |
653 | /// In this case, the variable operands will be after the normal |
654 | /// operands but before the implicit definitions and uses (if any are |
655 | /// present). |
656 | bool isVariadic(QueryType Type = IgnoreBundle) const { |
657 | return hasProperty(MCID::Variadic, Type); |
658 | } |
659 | |
660 | /// Set if this instruction has an optional definition, e.g. |
661 | /// ARM instructions which can set condition code if 's' bit is set. |
662 | bool hasOptionalDef(QueryType Type = IgnoreBundle) const { |
663 | return hasProperty(MCID::HasOptionalDef, Type); |
664 | } |
665 | |
666 | /// Return true if this is a pseudo instruction that doesn't |
667 | /// correspond to a real machine instruction. |
668 | bool isPseudo(QueryType Type = IgnoreBundle) const { |
669 | return hasProperty(MCID::Pseudo, Type); |
670 | } |
671 | |
672 | bool isReturn(QueryType Type = AnyInBundle) const { |
673 | return hasProperty(MCID::Return, Type); |
674 | } |
675 | |
676 | /// Return true if this is an instruction that marks the end of an EH scope, |
677 | /// i.e., a catchpad or a cleanuppad instruction. |
678 | bool isEHScopeReturn(QueryType Type = AnyInBundle) const { |
679 | return hasProperty(MCID::EHScopeReturn, Type); |
680 | } |
681 | |
682 | bool isCall(QueryType Type = AnyInBundle) const { |
683 | return hasProperty(MCID::Call, Type); |
684 | } |
685 | |
686 | /// Returns true if the specified instruction stops control flow |
687 | /// from executing the instruction immediately following it. Examples include |
688 | /// unconditional branches and return instructions. |
689 | bool isBarrier(QueryType Type = AnyInBundle) const { |
690 | return hasProperty(MCID::Barrier, Type); |
691 | } |
692 | |
693 | /// Returns true if this instruction part of the terminator for a basic block. |
694 | /// Typically this is things like return and branch instructions. |
695 | /// |
696 | /// Various passes use this to insert code into the bottom of a basic block, |
697 | /// but before control flow occurs. |
698 | bool isTerminator(QueryType Type = AnyInBundle) const { |
699 | return hasProperty(MCID::Terminator, Type); |
700 | } |
701 | |
702 | /// Returns true if this is a conditional, unconditional, or indirect branch. |
703 | /// Predicates below can be used to discriminate between |
704 | /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to |
705 | /// get more information. |
706 | bool isBranch(QueryType Type = AnyInBundle) const { |
707 | return hasProperty(MCID::Branch, Type); |
708 | } |
709 | |
710 | /// Return true if this is an indirect branch, such as a |
711 | /// branch through a register. |
712 | bool isIndirectBranch(QueryType Type = AnyInBundle) const { |
713 | return hasProperty(MCID::IndirectBranch, Type); |
714 | } |
715 | |
716 | /// Return true if this is a branch which may fall |
717 | /// through to the next instruction or may transfer control flow to some other |
718 | /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more |
719 | /// information about this branch. |
720 | bool isConditionalBranch(QueryType Type = AnyInBundle) const { |
721 | return isBranch(Type) && !isBarrier(Type) && !isIndirectBranch(Type); |
722 | } |
723 | |
724 | /// Return true if this is a branch which always |
725 | /// transfers control flow to some other block. The |
726 | /// TargetInstrInfo::AnalyzeBranch method can be used to get more information |
727 | /// about this branch. |
728 | bool isUnconditionalBranch(QueryType Type = AnyInBundle) const { |
729 | return isBranch(Type) && isBarrier(Type) && !isIndirectBranch(Type); |
730 | } |
731 | |
732 | /// Return true if this instruction has a predicate operand that |
733 | /// controls execution. It may be set to 'always', or may be set to other |
734 | /// values. There are various methods in TargetInstrInfo that can be used to |
735 | /// control and modify the predicate in this instruction. |
736 | bool isPredicable(QueryType Type = AllInBundle) const { |
737 | // If it's a bundle than all bundled instructions must be predicable for this |
738 | // to return true. |
739 | return hasProperty(MCID::Predicable, Type); |
740 | } |
741 | |
742 | /// Return true if this instruction is a comparison. |
743 | bool isCompare(QueryType Type = IgnoreBundle) const { |
744 | return hasProperty(MCID::Compare, Type); |
745 | } |
746 | |
747 | /// Return true if this instruction is a move immediate |
748 | /// (including conditional moves) instruction. |
749 | bool isMoveImmediate(QueryType Type = IgnoreBundle) const { |
750 | return hasProperty(MCID::MoveImm, Type); |
751 | } |
752 | |
753 | /// Return true if this instruction is a register move. |
754 | /// (including moving values from subreg to reg) |
755 | bool isMoveReg(QueryType Type = IgnoreBundle) const { |
756 | return hasProperty(MCID::MoveReg, Type); |
757 | } |
758 | |
759 | /// Return true if this instruction is a bitcast instruction. |
760 | bool isBitcast(QueryType Type = IgnoreBundle) const { |
761 | return hasProperty(MCID::Bitcast, Type); |
762 | } |
763 | |
764 | /// Return true if this instruction is a select instruction. |
765 | bool isSelect(QueryType Type = IgnoreBundle) const { |
766 | return hasProperty(MCID::Select, Type); |
767 | } |
768 | |
769 | /// Return true if this instruction cannot be safely duplicated. |
770 | /// For example, if the instruction has a unique labels attached |
771 | /// to it, duplicating it would cause multiple definition errors. |
772 | bool isNotDuplicable(QueryType Type = AnyInBundle) const { |
773 | return hasProperty(MCID::NotDuplicable, Type); |
774 | } |
775 | |
776 | /// Return true if this instruction is convergent. |
777 | /// Convergent instructions can not be made control-dependent on any |
778 | /// additional values. |
779 | bool isConvergent(QueryType Type = AnyInBundle) const { |
780 | if (isInlineAsm()) { |
781 | unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); |
782 | if (ExtraInfo & InlineAsm::Extra_IsConvergent) |
783 | return true; |
784 | } |
785 | return hasProperty(MCID::Convergent, Type); |
786 | } |
787 | |
788 | /// Returns true if the specified instruction has a delay slot |
789 | /// which must be filled by the code generator. |
790 | bool hasDelaySlot(QueryType Type = AnyInBundle) const { |
791 | return hasProperty(MCID::DelaySlot, Type); |
792 | } |
793 | |
794 | /// Return true for instructions that can be folded as |
795 | /// memory operands in other instructions. The most common use for this |
796 | /// is instructions that are simple loads from memory that don't modify |
797 | /// the loaded value in any way, but it can also be used for instructions |
798 | /// that can be expressed as constant-pool loads, such as V_SETALLONES |
799 | /// on x86, to allow them to be folded when it is beneficial. |
800 | /// This should only be set on instructions that return a value in their |
801 | /// only virtual register definition. |
802 | bool canFoldAsLoad(QueryType Type = IgnoreBundle) const { |
803 | return hasProperty(MCID::FoldableAsLoad, Type); |
804 | } |
805 | |
806 | /// Return true if this instruction behaves |
807 | /// the same way as the generic REG_SEQUENCE instructions. |
808 | /// E.g., on ARM, |
809 | /// dX VMOVDRR rY, rZ |
810 | /// is equivalent to |
811 | /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1. |
812 | /// |
813 | /// Note that for the optimizers to be able to take advantage of |
814 | /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be |
815 | /// override accordingly. |
816 | bool isRegSequenceLike(QueryType Type = IgnoreBundle) const { |
817 | return hasProperty(MCID::RegSequence, Type); |
818 | } |
819 | |
820 | /// Return true if this instruction behaves |
821 | /// the same way as the generic EXTRACT_SUBREG instructions. |
822 | /// E.g., on ARM, |
823 | /// rX, rY VMOVRRD dZ |
824 | /// is equivalent to two EXTRACT_SUBREG: |
825 | /// rX = EXTRACT_SUBREG dZ, ssub_0 |
826 | /// rY = EXTRACT_SUBREG dZ, ssub_1 |
827 | /// |
828 | /// Note that for the optimizers to be able to take advantage of |
829 | /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be |
830 | /// override accordingly. |
831 | bool isExtractSubregLike(QueryType Type = IgnoreBundle) const { |
832 | return hasProperty(MCID::ExtractSubreg, Type); |
833 | } |
834 | |
835 | /// Return true if this instruction behaves |
836 | /// the same way as the generic INSERT_SUBREG instructions. |
837 | /// E.g., on ARM, |
838 | /// dX = VSETLNi32 dY, rZ, Imm |
839 | /// is equivalent to a INSERT_SUBREG: |
840 | /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm) |
841 | /// |
842 | /// Note that for the optimizers to be able to take advantage of |
843 | /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be |
844 | /// override accordingly. |
845 | bool isInsertSubregLike(QueryType Type = IgnoreBundle) const { |
846 | return hasProperty(MCID::InsertSubreg, Type); |
847 | } |
848 | |
849 | //===--------------------------------------------------------------------===// |
850 | // Side Effect Analysis |
851 | //===--------------------------------------------------------------------===// |
852 | |
853 | /// Return true if this instruction could possibly read memory. |
854 | /// Instructions with this flag set are not necessarily simple load |
855 | /// instructions, they may load a value and modify it, for example. |
856 | bool mayLoad(QueryType Type = AnyInBundle) const { |
857 | if (isInlineAsm()) { |
858 | unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); |
859 | if (ExtraInfo & InlineAsm::Extra_MayLoad) |
860 | return true; |
861 | } |
862 | return hasProperty(MCID::MayLoad, Type); |
863 | } |
864 | |
865 | /// Return true if this instruction could possibly modify memory. |
866 | /// Instructions with this flag set are not necessarily simple store |
867 | /// instructions, they may store a modified value based on their operands, or |
868 | /// may not actually modify anything, for example. |
869 | bool mayStore(QueryType Type = AnyInBundle) const { |
870 | if (isInlineAsm()) { |
871 | unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); |
872 | if (ExtraInfo & InlineAsm::Extra_MayStore) |
873 | return true; |
874 | } |
875 | return hasProperty(MCID::MayStore, Type); |
876 | } |
877 | |
878 | /// Return true if this instruction could possibly read or modify memory. |
879 | bool mayLoadOrStore(QueryType Type = AnyInBundle) const { |
880 | return mayLoad(Type) || mayStore(Type); |
881 | } |
882 | |
883 | /// Return true if this instruction could possibly raise a floating-point |
884 | /// exception. This is the case if the instruction is a floating-point |
885 | /// instruction that can in principle raise an exception, as indicated |
886 | /// by the MCID::MayRaiseFPException property, *and* at the same time, |
887 | /// the instruction is used in a context where we expect floating-point |
888 | /// exceptions might be enabled, as indicated by the FPExcept MI flag. |
889 | bool mayRaiseFPException() const { |
890 | return hasProperty(MCID::MayRaiseFPException) && |
891 | getFlag(MachineInstr::MIFlag::FPExcept); |
892 | } |
893 | |
894 | //===--------------------------------------------------------------------===// |
895 | // Flags that indicate whether an instruction can be modified by a method. |
896 | //===--------------------------------------------------------------------===// |
897 | |
898 | /// Return true if this may be a 2- or 3-address |
899 | /// instruction (of the form "X = op Y, Z, ..."), which produces the same |
900 | /// result if Y and Z are exchanged. If this flag is set, then the |
901 | /// TargetInstrInfo::commuteInstruction method may be used to hack on the |
902 | /// instruction. |
903 | /// |
904 | /// Note that this flag may be set on instructions that are only commutable |
905 | /// sometimes. In these cases, the call to commuteInstruction will fail. |
906 | /// Also note that some instructions require non-trivial modification to |
907 | /// commute them. |
908 | bool isCommutable(QueryType Type = IgnoreBundle) const { |
909 | return hasProperty(MCID::Commutable, Type); |
910 | } |
911 | |
912 | /// Return true if this is a 2-address instruction |
913 | /// which can be changed into a 3-address instruction if needed. Doing this |
914 | /// transformation can be profitable in the register allocator, because it |
915 | /// means that the instruction can use a 2-address form if possible, but |
916 | /// degrade into a less efficient form if the source and dest register cannot |
917 | /// be assigned to the same register. For example, this allows the x86 |
918 | /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which |
919 | /// is the same speed as the shift but has bigger code size. |
920 | /// |
921 | /// If this returns true, then the target must implement the |
922 | /// TargetInstrInfo::convertToThreeAddress method for this instruction, which |
923 | /// is allowed to fail if the transformation isn't valid for this specific |
924 | /// instruction (e.g. shl reg, 4 on x86). |
925 | /// |
926 | bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const { |
927 | return hasProperty(MCID::ConvertibleTo3Addr, Type); |
928 | } |
929 | |
930 | /// Return true if this instruction requires |
931 | /// custom insertion support when the DAG scheduler is inserting it into a |
932 | /// machine basic block. If this is true for the instruction, it basically |
933 | /// means that it is a pseudo instruction used at SelectionDAG time that is |
934 | /// expanded out into magic code by the target when MachineInstrs are formed. |
935 | /// |
936 | /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method |
937 | /// is used to insert this into the MachineBasicBlock. |
938 | bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const { |
939 | return hasProperty(MCID::UsesCustomInserter, Type); |
940 | } |
941 | |
942 | /// Return true if this instruction requires *adjustment* |
943 | /// after instruction selection by calling a target hook. For example, this |
944 | /// can be used to fill in ARM 's' optional operand depending on whether |
945 | /// the conditional flag register is used. |
946 | bool hasPostISelHook(QueryType Type = IgnoreBundle) const { |
947 | return hasProperty(MCID::HasPostISelHook, Type); |
948 | } |
949 | |
950 | /// Returns true if this instruction is a candidate for remat. |
951 | /// This flag is deprecated, please don't use it anymore. If this |
952 | /// flag is set, the isReallyTriviallyReMaterializable() method is called to |
953 | /// verify the instruction is really rematable. |
954 | bool isRematerializable(QueryType Type = AllInBundle) const { |
955 | // It's only possible to re-mat a bundle if all bundled instructions are |
956 | // re-materializable. |
957 | return hasProperty(MCID::Rematerializable, Type); |
958 | } |
959 | |
960 | /// Returns true if this instruction has the same cost (or less) than a move |
961 | /// instruction. This is useful during certain types of optimizations |
962 | /// (e.g., remat during two-address conversion or machine licm) |
963 | /// where we would like to remat or hoist the instruction, but not if it costs |
964 | /// more than moving the instruction into the appropriate register. Note, we |
965 | /// are not marking copies from and to the same register class with this flag. |
966 | bool isAsCheapAsAMove(QueryType Type = AllInBundle) const { |
967 | // Only returns true for a bundle if all bundled instructions are cheap. |
968 | return hasProperty(MCID::CheapAsAMove, Type); |
969 | } |
970 | |
971 | /// Returns true if this instruction source operands |
972 | /// have special register allocation requirements that are not captured by the |
973 | /// operand register classes. e.g. ARM::STRD's two source registers must be an |
974 | /// even / odd pair, ARM::STM registers have to be in ascending order. |
975 | /// Post-register allocation passes should not attempt to change allocations |
976 | /// for sources of instructions with this flag. |
977 | bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const { |
978 | return hasProperty(MCID::ExtraSrcRegAllocReq, Type); |
979 | } |
980 | |
981 | /// Returns true if this instruction def operands |
982 | /// have special register allocation requirements that are not captured by the |
983 | /// operand register classes. e.g. ARM::LDRD's two def registers must be an |
984 | /// even / odd pair, ARM::LDM registers have to be in ascending order. |
985 | /// Post-register allocation passes should not attempt to change allocations |
986 | /// for definitions of instructions with this flag. |
987 | bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const { |
988 | return hasProperty(MCID::ExtraDefRegAllocReq, Type); |
989 | } |
990 | |
991 | enum MICheckType { |
992 | CheckDefs, // Check all operands for equality |
993 | CheckKillDead, // Check all operands including kill / dead markers |
994 | IgnoreDefs, // Ignore all definitions |
995 | IgnoreVRegDefs // Ignore virtual register definitions |
996 | }; |
997 | |
998 | /// Return true if this instruction is identical to \p Other. |
999 | /// Two instructions are identical if they have the same opcode and all their |
1000 | /// operands are identical (with respect to MachineOperand::isIdenticalTo()). |
1001 | /// Note that this means liveness related flags (dead, undef, kill) do not |
1002 | /// affect the notion of identical. |
1003 | bool isIdenticalTo(const MachineInstr &Other, |
1004 | MICheckType Check = CheckDefs) const; |
1005 | |
1006 | /// Unlink 'this' from the containing basic block, and return it without |
1007 | /// deleting it. |
1008 | /// |
1009 | /// This function can not be used on bundled instructions, use |
1010 | /// removeFromBundle() to remove individual instructions from a bundle. |
1011 | MachineInstr *removeFromParent(); |
1012 | |
1013 | /// Unlink this instruction from its basic block and return it without |
1014 | /// deleting it. |
1015 | /// |
1016 | /// If the instruction is part of a bundle, the other instructions in the |
1017 | /// bundle remain bundled. |
1018 | MachineInstr *removeFromBundle(); |
1019 | |
1020 | /// Unlink 'this' from the containing basic block and delete it. |
1021 | /// |
1022 | /// If this instruction is the header of a bundle, the whole bundle is erased. |
1023 | /// This function can not be used for instructions inside a bundle, use |
1024 | /// eraseFromBundle() to erase individual bundled instructions. |
1025 | void eraseFromParent(); |
1026 | |
1027 | /// Unlink 'this' from the containing basic block and delete it. |
1028 | /// |
1029 | /// For all definitions mark their uses in DBG_VALUE nodes |
1030 | /// as undefined. Otherwise like eraseFromParent(). |
1031 | void eraseFromParentAndMarkDBGValuesForRemoval(); |
1032 | |
1033 | /// Unlink 'this' form its basic block and delete it. |
1034 | /// |
1035 | /// If the instruction is part of a bundle, the other instructions in the |
1036 | /// bundle remain bundled. |
1037 | void eraseFromBundle(); |
1038 | |
1039 | bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; } |
1040 | bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; } |
1041 | bool isAnnotationLabel() const { |
1042 | return getOpcode() == TargetOpcode::ANNOTATION_LABEL; |
1043 | } |
1044 | |
1045 | /// Returns true if the MachineInstr represents a label. |
1046 | bool isLabel() const { |
1047 | return isEHLabel() || isGCLabel() || isAnnotationLabel(); |
1048 | } |
1049 | |
1050 | bool isCFIInstruction() const { |
1051 | return getOpcode() == TargetOpcode::CFI_INSTRUCTION; |
1052 | } |
1053 | |
1054 | // True if the instruction represents a position in the function. |
1055 | bool isPosition() const { return isLabel() || isCFIInstruction(); } |
1056 | |
1057 | bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; } |
1058 | bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; } |
1059 | bool isDebugInstr() const { return isDebugValue() || isDebugLabel(); } |
1060 | |
1061 | /// A DBG_VALUE is indirect iff the first operand is a register and |
1062 | /// the second operand is an immediate. |
1063 | bool isIndirectDebugValue() const { |
1064 | return isDebugValue() |
1065 | && getOperand(0).isReg() |
1066 | && getOperand(1).isImm(); |
1067 | } |
1068 | |
1069 | /// A DBG_VALUE is an entry value iff its debug expression contains the |
1070 | /// DW_OP_LLVM_entry_value operation. |
1071 | bool isDebugEntryValue() const; |
1072 | |
1073 | /// Return true if the instruction is a debug value which describes a part of |
1074 | /// a variable as unavailable. |
1075 | bool isUndefDebugValue() const { |
1076 | return isDebugValue() && getOperand(0).isReg() && !getOperand(0).getReg().isValid(); |
1077 | } |
1078 | |
1079 | bool isPHI() const { |
1080 | return getOpcode() == TargetOpcode::PHI || |
1081 | getOpcode() == TargetOpcode::G_PHI; |
1082 | } |
1083 | bool isKill() const { return getOpcode() == TargetOpcode::KILL; } |
1084 | bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; } |
1085 | bool isInlineAsm() const { |
1086 | return getOpcode() == TargetOpcode::INLINEASM || |
1087 | getOpcode() == TargetOpcode::INLINEASM_BR; |
1088 | } |
1089 | |
1090 | /// FIXME: Seems like a layering violation that the AsmDialect, which is X86 |
1091 | /// specific, be attached to a generic MachineInstr. |
1092 | bool isMSInlineAsm() const { |
1093 | return isInlineAsm() && getInlineAsmDialect() == InlineAsm::AD_Intel; |
1094 | } |
1095 | |
1096 | bool isStackAligningInlineAsm() const; |
1097 | InlineAsm::AsmDialect getInlineAsmDialect() const; |
1098 | |
1099 | bool isInsertSubreg() const { |
1100 | return getOpcode() == TargetOpcode::INSERT_SUBREG; |
1101 | } |
1102 | |
1103 | bool isSubregToReg() const { |
1104 | return getOpcode() == TargetOpcode::SUBREG_TO_REG; |
1105 | } |
1106 | |
1107 | bool isRegSequence() const { |
1108 | return getOpcode() == TargetOpcode::REG_SEQUENCE; |
1109 | } |
1110 | |
1111 | bool isBundle() const { |
1112 | return getOpcode() == TargetOpcode::BUNDLE; |
1113 | } |
1114 | |
1115 | bool isCopy() const { |
1116 | return getOpcode() == TargetOpcode::COPY; |
1117 | } |
1118 | |
1119 | bool isFullCopy() const { |
1120 | return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg(); |
1121 | } |
1122 | |
1123 | bool isExtractSubreg() const { |
1124 | return getOpcode() == TargetOpcode::EXTRACT_SUBREG; |
1125 | } |
1126 | |
1127 | /// Return true if the instruction behaves like a copy. |
1128 | /// This does not include native copy instructions. |
1129 | bool isCopyLike() const { |
1130 | return isCopy() || isSubregToReg(); |
1131 | } |
1132 | |
1133 | /// Return true is the instruction is an identity copy. |
1134 | bool isIdentityCopy() const { |
1135 | return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() && |
1136 | getOperand(0).getSubReg() == getOperand(1).getSubReg(); |
1137 | } |
1138 | |
1139 | /// Return true if this instruction doesn't produce any output in the form of |
1140 | /// executable instructions. |
1141 | bool isMetaInstruction() const { |
1142 | switch (getOpcode()) { |
1143 | default: |
1144 | return false; |
1145 | case TargetOpcode::IMPLICIT_DEF: |
1146 | case TargetOpcode::KILL: |
1147 | case TargetOpcode::CFI_INSTRUCTION: |
1148 | case TargetOpcode::EH_LABEL: |
1149 | case TargetOpcode::GC_LABEL: |
1150 | case TargetOpcode::DBG_VALUE: |
1151 | case TargetOpcode::DBG_LABEL: |
1152 | case TargetOpcode::LIFETIME_START: |
1153 | case TargetOpcode::LIFETIME_END: |
1154 | return true; |
1155 | } |
1156 | } |
1157 | |
1158 | /// Return true if this is a transient instruction that is either very likely |
1159 | /// to be eliminated during register allocation (such as copy-like |
1160 | /// instructions), or if this instruction doesn't have an execution-time cost. |
1161 | bool isTransient() const { |
1162 | switch (getOpcode()) { |
1163 | default: |
1164 | return isMetaInstruction(); |
1165 | // Copy-like instructions are usually eliminated during register allocation. |
1166 | case TargetOpcode::PHI: |
1167 | case TargetOpcode::G_PHI: |
1168 | case TargetOpcode::COPY: |
1169 | case TargetOpcode::INSERT_SUBREG: |
1170 | case TargetOpcode::SUBREG_TO_REG: |
1171 | case TargetOpcode::REG_SEQUENCE: |
1172 | return true; |
1173 | } |
1174 | } |
1175 | |
1176 | /// Return the number of instructions inside the MI bundle, excluding the |
1177 | /// bundle header. |
1178 | /// |
1179 | /// This is the number of instructions that MachineBasicBlock::iterator |
1180 | /// skips, 0 for unbundled instructions. |
1181 | unsigned getBundleSize() const; |
1182 | |
1183 | /// Return true if the MachineInstr reads the specified register. |
1184 | /// If TargetRegisterInfo is passed, then it also checks if there |
1185 | /// is a read of a super-register. |
1186 | /// This does not count partial redefines of virtual registers as reads: |
1187 | /// %reg1024:6 = OP. |
1188 | bool readsRegister(Register Reg, |
1189 | const TargetRegisterInfo *TRI = nullptr) const { |
1190 | return findRegisterUseOperandIdx(Reg, false, TRI) != -1; |
1191 | } |
1192 | |
1193 | /// Return true if the MachineInstr reads the specified virtual register. |
1194 | /// Take into account that a partial define is a |
1195 | /// read-modify-write operation. |
1196 | bool readsVirtualRegister(Register Reg) const { |
1197 | return readsWritesVirtualRegister(Reg).first; |
1198 | } |
1199 | |
1200 | /// Return a pair of bools (reads, writes) indicating if this instruction |
1201 | /// reads or writes Reg. This also considers partial defines. |
1202 | /// If Ops is not null, all operand indices for Reg are added. |
1203 | std::pair<bool,bool> readsWritesVirtualRegister(Register Reg, |
1204 | SmallVectorImpl<unsigned> *Ops = nullptr) const; |
1205 | |
1206 | /// Return true if the MachineInstr kills the specified register. |
1207 | /// If TargetRegisterInfo is passed, then it also checks if there is |
1208 | /// a kill of a super-register. |
1209 | bool killsRegister(Register Reg, |
1210 | const TargetRegisterInfo *TRI = nullptr) const { |
1211 | return findRegisterUseOperandIdx(Reg, true, TRI) != -1; |
1212 | } |
1213 | |
1214 | /// Return true if the MachineInstr fully defines the specified register. |
1215 | /// If TargetRegisterInfo is passed, then it also checks |
1216 | /// if there is a def of a super-register. |
1217 | /// NOTE: It's ignoring subreg indices on virtual registers. |
1218 | bool definesRegister(Register Reg, |
1219 | const TargetRegisterInfo *TRI = nullptr) const { |
1220 | return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1; |
1221 | } |
1222 | |
1223 | /// Return true if the MachineInstr modifies (fully define or partially |
1224 | /// define) the specified register. |
1225 | /// NOTE: It's ignoring subreg indices on virtual registers. |
1226 | bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const { |
1227 | return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1; |
1228 | } |
1229 | |
1230 | /// Returns true if the register is dead in this machine instruction. |
1231 | /// If TargetRegisterInfo is passed, then it also checks |
1232 | /// if there is a dead def of a super-register. |
1233 | bool registerDefIsDead(Register Reg, |
1234 | const TargetRegisterInfo *TRI = nullptr) const { |
1235 | return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1; |
1236 | } |
1237 | |
1238 | /// Returns true if the MachineInstr has an implicit-use operand of exactly |
1239 | /// the given register (not considering sub/super-registers). |
1240 | bool hasRegisterImplicitUseOperand(Register Reg) const; |
1241 | |
1242 | /// Returns the operand index that is a use of the specific register or -1 |
1243 | /// if it is not found. It further tightens the search criteria to a use |
1244 | /// that kills the register if isKill is true. |
1245 | int findRegisterUseOperandIdx(Register Reg, bool isKill = false, |
1246 | const TargetRegisterInfo *TRI = nullptr) const; |
1247 | |
1248 | /// Wrapper for findRegisterUseOperandIdx, it returns |
1249 | /// a pointer to the MachineOperand rather than an index. |
1250 | MachineOperand *findRegisterUseOperand(Register Reg, bool isKill = false, |
1251 | const TargetRegisterInfo *TRI = nullptr) { |
1252 | int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI); |
1253 | return (Idx == -1) ? nullptr : &getOperand(Idx); |
1254 | } |
1255 | |
1256 | const MachineOperand *findRegisterUseOperand( |
1257 | Register Reg, bool isKill = false, |
1258 | const TargetRegisterInfo *TRI = nullptr) const { |
1259 | return const_cast<MachineInstr *>(this)-> |
1260 | findRegisterUseOperand(Reg, isKill, TRI); |
1261 | } |
1262 | |
1263 | /// Returns the operand index that is a def of the specified register or |
1264 | /// -1 if it is not found. If isDead is true, defs that are not dead are |
1265 | /// skipped. If Overlap is true, then it also looks for defs that merely |
1266 | /// overlap the specified register. If TargetRegisterInfo is non-null, |
1267 | /// then it also checks if there is a def of a super-register. |
1268 | /// This may also return a register mask operand when Overlap is true. |
1269 | int findRegisterDefOperandIdx(Register Reg, |
1270 | bool isDead = false, bool Overlap = false, |
1271 | const TargetRegisterInfo *TRI = nullptr) const; |
1272 | |
1273 | /// Wrapper for findRegisterDefOperandIdx, it returns |
1274 | /// a pointer to the MachineOperand rather than an index. |
1275 | MachineOperand * |
1276 | findRegisterDefOperand(Register Reg, bool isDead = false, |
1277 | bool Overlap = false, |
1278 | const TargetRegisterInfo *TRI = nullptr) { |
1279 | int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI); |
1280 | return (Idx == -1) ? nullptr : &getOperand(Idx); |
1281 | } |
1282 | |
1283 | const MachineOperand * |
1284 | findRegisterDefOperand(Register Reg, bool isDead = false, |
1285 | bool Overlap = false, |
1286 | const TargetRegisterInfo *TRI = nullptr) const { |
1287 | return const_cast<MachineInstr *>(this)->findRegisterDefOperand( |
1288 | Reg, isDead, Overlap, TRI); |
1289 | } |
1290 | |
1291 | /// Find the index of the first operand in the |
1292 | /// operand list that is used to represent the predicate. It returns -1 if |
1293 | /// none is found. |
1294 | int findFirstPredOperandIdx() const; |
1295 | |
1296 | /// Find the index of the flag word operand that |
1297 | /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if |
1298 | /// getOperand(OpIdx) does not belong to an inline asm operand group. |
1299 | /// |
1300 | /// If GroupNo is not NULL, it will receive the number of the operand group |
1301 | /// containing OpIdx. |
1302 | /// |
1303 | /// The flag operand is an immediate that can be decoded with methods like |
1304 | /// InlineAsm::hasRegClassConstraint(). |
1305 | int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const; |
1306 | |
1307 | /// Compute the static register class constraint for operand OpIdx. |
1308 | /// For normal instructions, this is derived from the MCInstrDesc. |
1309 | /// For inline assembly it is derived from the flag words. |
1310 | /// |
1311 | /// Returns NULL if the static register class constraint cannot be |
1312 | /// determined. |
1313 | const TargetRegisterClass* |
1314 | getRegClassConstraint(unsigned OpIdx, |
1315 | const TargetInstrInfo *TII, |
1316 | const TargetRegisterInfo *TRI) const; |
1317 | |
1318 | /// Applies the constraints (def/use) implied by this MI on \p Reg to |
1319 | /// the given \p CurRC. |
1320 | /// If \p ExploreBundle is set and MI is part of a bundle, all the |
1321 | /// instructions inside the bundle will be taken into account. In other words, |
1322 | /// this method accumulates all the constraints of the operand of this MI and |
1323 | /// the related bundle if MI is a bundle or inside a bundle. |
1324 | /// |
1325 | /// Returns the register class that satisfies both \p CurRC and the |
1326 | /// constraints set by MI. Returns NULL if such a register class does not |
1327 | /// exist. |
1328 | /// |
1329 | /// \pre CurRC must not be NULL. |
1330 | const TargetRegisterClass *getRegClassConstraintEffectForVReg( |
1331 | Register Reg, const TargetRegisterClass *CurRC, |
1332 | const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, |
1333 | bool ExploreBundle = false) const; |
1334 | |
1335 | /// Applies the constraints (def/use) implied by the \p OpIdx operand |
1336 | /// to the given \p CurRC. |
1337 | /// |
1338 | /// Returns the register class that satisfies both \p CurRC and the |
1339 | /// constraints set by \p OpIdx MI. Returns NULL if such a register class |
1340 | /// does not exist. |
1341 | /// |
1342 | /// \pre CurRC must not be NULL. |
1343 | /// \pre The operand at \p OpIdx must be a register. |
1344 | const TargetRegisterClass * |
1345 | getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, |
1346 | const TargetInstrInfo *TII, |
1347 | const TargetRegisterInfo *TRI) const; |
1348 | |
1349 | /// Add a tie between the register operands at DefIdx and UseIdx. |
1350 | /// The tie will cause the register allocator to ensure that the two |
1351 | /// operands are assigned the same physical register. |
1352 | /// |
1353 | /// Tied operands are managed automatically for explicit operands in the |
1354 | /// MCInstrDesc. This method is for exceptional cases like inline asm. |
1355 | void tieOperands(unsigned DefIdx, unsigned UseIdx); |
1356 | |
1357 | /// Given the index of a tied register operand, find the |
1358 | /// operand it is tied to. Defs are tied to uses and vice versa. Returns the |
1359 | /// index of the tied operand which must exist. |
1360 | unsigned findTiedOperandIdx(unsigned OpIdx) const; |
1361 | |
1362 | /// Given the index of a register def operand, |
1363 | /// check if the register def is tied to a source operand, due to either |
1364 | /// two-address elimination or inline assembly constraints. Returns the |
1365 | /// first tied use operand index by reference if UseOpIdx is not null. |
1366 | bool isRegTiedToUseOperand(unsigned DefOpIdx, |
1367 | unsigned *UseOpIdx = nullptr) const { |
1368 | const MachineOperand &MO = getOperand(DefOpIdx); |
1369 | if (!MO.isReg() || !MO.isDef() || !MO.isTied()) |
1370 | return false; |
1371 | if (UseOpIdx) |
1372 | *UseOpIdx = findTiedOperandIdx(DefOpIdx); |
1373 | return true; |
1374 | } |
1375 | |
1376 | /// Return true if the use operand of the specified index is tied to a def |
1377 | /// operand. It also returns the def operand index by reference if DefOpIdx |
1378 | /// is not null. |
1379 | bool isRegTiedToDefOperand(unsigned UseOpIdx, |
1380 | unsigned *DefOpIdx = nullptr) const { |
1381 | const MachineOperand &MO = getOperand(UseOpIdx); |
1382 | if (!MO.isReg() || !MO.isUse() || !MO.isTied()) |
1383 | return false; |
1384 | if (DefOpIdx) |
1385 | *DefOpIdx = findTiedOperandIdx(UseOpIdx); |
1386 | return true; |
1387 | } |
1388 | |
1389 | /// Clears kill flags on all operands. |
1390 | void clearKillInfo(); |
1391 | |
1392 | /// Replace all occurrences of FromReg with ToReg:SubIdx, |
1393 | /// properly composing subreg indices where necessary. |
1394 | void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, |
1395 | const TargetRegisterInfo &RegInfo); |
1396 | |
1397 | /// We have determined MI kills a register. Look for the |
1398 | /// operand that uses it and mark it as IsKill. If AddIfNotFound is true, |
1399 | /// add a implicit operand if it's not found. Returns true if the operand |
1400 | /// exists / is added. |
1401 | bool addRegisterKilled(Register IncomingReg, |
1402 | const TargetRegisterInfo *RegInfo, |
1403 | bool AddIfNotFound = false); |
1404 | |
1405 | /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes |
1406 | /// all aliasing registers. |
1407 | void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo); |
1408 | |
1409 | /// We have determined MI defined a register without a use. |
1410 | /// Look for the operand that defines it and mark it as IsDead. If |
1411 | /// AddIfNotFound is true, add a implicit operand if it's not found. Returns |
1412 | /// true if the operand exists / is added. |
1413 | bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, |
1414 | bool AddIfNotFound = false); |
1415 | |
1416 | /// Clear all dead flags on operands defining register @p Reg. |
1417 | void clearRegisterDeads(Register Reg); |
1418 | |
1419 | /// Mark all subregister defs of register @p Reg with the undef flag. |
1420 | /// This function is used when we determined to have a subregister def in an |
1421 | /// otherwise undefined super register. |
1422 | void setRegisterDefReadUndef(Register Reg, bool IsUndef = true); |
1423 | |
1424 | /// We have determined MI defines a register. Make sure there is an operand |
1425 | /// defining Reg. |
1426 | void addRegisterDefined(Register Reg, |
1427 | const TargetRegisterInfo *RegInfo = nullptr); |
1428 | |
1429 | /// Mark every physreg used by this instruction as |
1430 | /// dead except those in the UsedRegs list. |
1431 | /// |
1432 | /// On instructions with register mask operands, also add implicit-def |
1433 | /// operands for all registers in UsedRegs. |
1434 | void setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs, |
1435 | const TargetRegisterInfo &TRI); |
1436 | |
1437 | /// Return true if it is safe to move this instruction. If |
1438 | /// SawStore is set to true, it means that there is a store (or call) between |
1439 | /// the instruction's location and its intended destination. |
1440 | bool isSafeToMove(AAResults *AA, bool &SawStore) const; |
1441 | |
1442 | /// Returns true if this instruction's memory access aliases the memory |
1443 | /// access of Other. |
1444 | // |
1445 | /// Assumes any physical registers used to compute addresses |
1446 | /// have the same value for both instructions. Returns false if neither |
1447 | /// instruction writes to memory. |
1448 | /// |
1449 | /// @param AA Optional alias analysis, used to compare memory operands. |
1450 | /// @param Other MachineInstr to check aliasing against. |
1451 | /// @param UseTBAA Whether to pass TBAA information to alias analysis. |
1452 | bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const; |
1453 | |
1454 | /// Return true if this instruction may have an ordered |
1455 | /// or volatile memory reference, or if the information describing the memory |
1456 | /// reference is not available. Return false if it is known to have no |
1457 | /// ordered or volatile memory references. |
1458 | bool hasOrderedMemoryRef() const; |
1459 | |
1460 | /// Return true if this load instruction never traps and points to a memory |
1461 | /// location whose value doesn't change during the execution of this function. |
1462 | /// |
1463 | /// Examples include loading a value from the constant pool or from the |
1464 | /// argument area of a function (if it does not change). If the instruction |
1465 | /// does multiple loads, this returns true only if all of the loads are |
1466 | /// dereferenceable and invariant. |
1467 | bool isDereferenceableInvariantLoad(AAResults *AA) const; |
1468 | |
1469 | /// If the specified instruction is a PHI that always merges together the |
1470 | /// same virtual register, return the register, otherwise return 0. |
1471 | unsigned isConstantValuePHI() const; |
1472 | |
1473 | /// Return true if this instruction has side effects that are not modeled |
1474 | /// by mayLoad / mayStore, etc. |
1475 | /// For all instructions, the property is encoded in MCInstrDesc::Flags |
1476 | /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is |
1477 | /// INLINEASM instruction, in which case the side effect property is encoded |
1478 | /// in one of its operands (see InlineAsm::Extra_HasSideEffect). |
1479 | /// |
1480 | bool hasUnmodeledSideEffects() const; |
1481 | |
1482 | /// Returns true if it is illegal to fold a load across this instruction. |
1483 | bool isLoadFoldBarrier() const; |
1484 | |
1485 | /// Return true if all the defs of this instruction are dead. |
1486 | bool allDefsAreDead() const; |
1487 | |
1488 | /// Return a valid size if the instruction is a spill instruction. |
1489 | Optional<unsigned> getSpillSize(const TargetInstrInfo *TII) const; |
1490 | |
1491 | /// Return a valid size if the instruction is a folded spill instruction. |
1492 | Optional<unsigned> getFoldedSpillSize(const TargetInstrInfo *TII) const; |
1493 | |
1494 | /// Return a valid size if the instruction is a restore instruction. |
1495 | Optional<unsigned> getRestoreSize(const TargetInstrInfo *TII) const; |
1496 | |
1497 | /// Return a valid size if the instruction is a folded restore instruction. |
1498 | Optional<unsigned> |
1499 | getFoldedRestoreSize(const TargetInstrInfo *TII) const; |
1500 | |
1501 | /// Copy implicit register operands from specified |
1502 | /// instruction to this instruction. |
1503 | void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI); |
1504 | |
1505 | /// Debugging support |
1506 | /// @{ |
1507 | /// Determine the generic type to be printed (if needed) on uses and defs. |
1508 | LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, |
1509 | const MachineRegisterInfo &MRI) const; |
1510 | |
1511 | /// Return true when an instruction has tied register that can't be determined |
1512 | /// by the instruction's descriptor. This is useful for MIR printing, to |
1513 | /// determine whether we need to print the ties or not. |
1514 | bool hasComplexRegisterTies() const; |
1515 | |
1516 | /// Print this MI to \p OS. |
1517 | /// Don't print information that can be inferred from other instructions if |
1518 | /// \p IsStandalone is false. It is usually true when only a fragment of the |
1519 | /// function is printed. |
1520 | /// Only print the defs and the opcode if \p SkipOpers is true. |
1521 | /// Otherwise, also print operands if \p SkipDebugLoc is true. |
1522 | /// Otherwise, also print the debug loc, with a terminating newline. |
1523 | /// \p TII is used to print the opcode name. If it's not present, but the |
1524 | /// MI is in a function, the opcode will be printed using the function's TII. |
1525 | void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false, |
1526 | bool SkipDebugLoc = false, bool AddNewLine = true, |
1527 | const TargetInstrInfo *TII = nullptr) const; |
1528 | void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true, |
1529 | bool SkipOpers = false, bool SkipDebugLoc = false, |
1530 | bool AddNewLine = true, |
1531 | const TargetInstrInfo *TII = nullptr) const; |
1532 | void dump() const; |
1533 | /// @} |
1534 | |
1535 | //===--------------------------------------------------------------------===// |
1536 | // Accessors used to build up machine instructions. |
1537 | |
1538 | /// Add the specified operand to the instruction. If it is an implicit |
1539 | /// operand, it is added to the end of the operand list. If it is an |
1540 | /// explicit operand it is added at the end of the explicit operand list |
1541 | /// (before the first implicit operand). |
1542 | /// |
1543 | /// MF must be the machine function that was used to allocate this |
1544 | /// instruction. |
1545 | /// |
1546 | /// MachineInstrBuilder provides a more convenient interface for creating |
1547 | /// instructions and adding operands. |
1548 | void addOperand(MachineFunction &MF, const MachineOperand &Op); |
1549 | |
1550 | /// Add an operand without providing an MF reference. This only works for |
1551 | /// instructions that are inserted in a basic block. |
1552 | /// |
1553 | /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be |
1554 | /// preferred. |
1555 | void addOperand(const MachineOperand &Op); |
1556 | |
1557 | /// Replace the instruction descriptor (thus opcode) of |
1558 | /// the current instruction with a new one. |
1559 | void setDesc(const MCInstrDesc &tid) { MCID = &tid; } |
1560 | |
1561 | /// Replace current source information with new such. |
1562 | /// Avoid using this, the constructor argument is preferable. |
1563 | void setDebugLoc(DebugLoc dl) { |
1564 | debugLoc = std::move(dl); |
1565 | assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor" ) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\"" , "/build/llvm-toolchain-snapshot-10~++20200110111110+a1cc19b5814/llvm/include/llvm/CodeGen/MachineInstr.h" , 1565, __PRETTY_FUNCTION__)); |
1566 | } |
1567 | |
1568 | /// Erase an operand from an instruction, leaving it with one |
1569 | /// fewer operand than it started with. |
1570 | void RemoveOperand(unsigned OpNo); |
1571 | |
1572 | /// Clear this MachineInstr's memory reference descriptor list. This resets |
1573 | /// the memrefs to their most conservative state. This should be used only |
1574 | /// as a last resort since it greatly pessimizes our knowledge of the memory |
1575 | /// access performed by the instruction. |
1576 | void dropMemRefs(MachineFunction &MF); |
1577 | |
1578 | /// Assign this MachineInstr's memory reference descriptor list. |
1579 | /// |
1580 | /// Unlike other methods, this *will* allocate them into a new array |
1581 | /// associated with the provided `MachineFunction`. |
1582 | void setMemRefs(MachineFunction &MF, ArrayRef<MachineMemOperand *> MemRefs); |
1583 | |
1584 | /// Add a MachineMemOperand to the machine instruction. |
1585 | /// This function should be used only occasionally. The setMemRefs function |
1586 | /// is the primary method for setting up a MachineInstr's MemRefs list. |
1587 | void addMemOperand(MachineFunction &MF, MachineMemOperand *MO); |
1588 | |
1589 | /// Clone another MachineInstr's memory reference descriptor list and replace |
1590 | /// ours with it. |
1591 | /// |
1592 | /// Note that `*this` may be the incoming MI! |
1593 | /// |
1594 | /// Prefer this API whenever possible as it can avoid allocations in common |
1595 | /// cases. |
1596 | void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI); |
1597 | |
1598 | /// Clone the merge of multiple MachineInstrs' memory reference descriptors |
1599 | /// list and replace ours with it. |
1600 | /// |
1601 | /// Note that `*this` may be one of the incoming MIs! |
1602 | /// |
1603 | /// Prefer this API whenever possible as it can avoid allocations in common |
1604 | /// cases. |
1605 | void cloneMergedMemRefs(MachineFunction &MF, |
1606 | ArrayRef<const MachineInstr *> MIs); |
1607 | |
1608 | /// Set a symbol that will be emitted just prior to the instruction itself. |
1609 | /// |
1610 | /// Setting this to a null pointer will remove any such symbol. |
1611 | /// |
1612 | /// FIXME: This is not fully implemented yet. |
1613 | void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol); |
1614 | |
1615 | /// Set a symbol that will be emitted just after the instruction itself. |
1616 | /// |
1617 | /// Setting this to a null pointer will remove any such symbol. |
1618 | /// |
1619 | /// FIXME: This is not fully implemented yet. |
1620 | void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol); |
1621 | |
1622 | /// Clone another MachineInstr's pre- and post- instruction symbols and |
1623 | /// replace ours with it. |
1624 | void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI); |
1625 | |
1626 | /// Set a marker on instructions that denotes where we should create and emit |
1627 | /// heap alloc site labels. This waits until after instruction selection and |
1628 | /// optimizations to create the label, so it should still work if the |
1629 | /// instruction is removed or duplicated. |
1630 | void setHeapAllocMarker(MachineFunction &MF, MDNode *MD); |
1631 | |
1632 | /// Return the MIFlags which represent both MachineInstrs. This |
1633 | /// should be used when merging two MachineInstrs into one. This routine does |
1634 | /// not modify the MIFlags of this MachineInstr. |
1635 | uint16_t mergeFlagsWith(const MachineInstr& Other) const; |
1636 | |
1637 | static uint16_t copyFlagsFromInstruction(const Instruction &I); |
1638 | |
1639 | /// Copy all flags to MachineInst MIFlags |
1640 | void copyIRFlags(const Instruction &I); |
1641 | |
1642 | /// Break any tie involving OpIdx. |
1643 | void untieRegOperand(unsigned OpIdx) { |
1644 | MachineOperand &MO = getOperand(OpIdx); |
1645 | if (MO.isReg() && MO.isTied()) { |
1646 | getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0; |
1647 | MO.TiedTo = 0; |
1648 | } |
1649 | } |
1650 | |
1651 | /// Add all implicit def and use operands to this instruction. |
1652 | void addImplicitDefUseOperands(MachineFunction &MF); |
1653 | |
1654 | /// Scan instructions immediately following MI and collect any matching |
1655 | /// DBG_VALUEs. |
1656 | void collectDebugValues(SmallVectorImpl<MachineInstr *> &DbgValues); |
1657 | |
1658 | /// Find all DBG_VALUEs that point to the register def in this instruction |
1659 | /// and point them to \p Reg instead. |
1660 | void changeDebugValuesDefReg(Register Reg); |
1661 | |
1662 | /// Returns the Intrinsic::ID for this instruction. |
1663 | /// \pre Must have an intrinsic ID operand. |
1664 | unsigned getIntrinsicID() const { |
1665 | return getOperand(getNumExplicitDefs()).getIntrinsicID(); |
1666 | } |
1667 | |
1668 | private: |
1669 | /// If this instruction is embedded into a MachineFunction, return the |
1670 | /// MachineRegisterInfo object for the current function, otherwise |
1671 | /// return null. |
1672 | MachineRegisterInfo *getRegInfo(); |
1673 | |
1674 | /// Unlink all of the register operands in this instruction from their |
1675 | /// respective use lists. This requires that the operands already be on their |
1676 | /// use lists. |
1677 | void RemoveRegOperandsFromUseLists(MachineRegisterInfo&); |
1678 | |
1679 | /// Add all of the register operands in this instruction from their |
1680 | /// respective use lists. This requires that the operands not be on their |
1681 | /// use lists yet. |
1682 | void AddRegOperandsToUseLists(MachineRegisterInfo&); |
1683 | |
1684 | /// Slow path for hasProperty when we're dealing with a bundle. |
1685 | bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const; |
1686 | |
1687 | /// Implements the logic of getRegClassConstraintEffectForVReg for the |
1688 | /// this MI and the given operand index \p OpIdx. |
1689 | /// If the related operand does not constrained Reg, this returns CurRC. |
1690 | const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl( |
1691 | unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC, |
1692 | const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const; |
1693 | |
1694 | /// Stores extra instruction information inline or allocates as ExtraInfo |
1695 | /// based on the number of pointers. |
1696 | void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs, |
1697 | MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol, |
1698 | MDNode *HeapAllocMarker); |
1699 | }; |
1700 | |
1701 | /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the |
1702 | /// instruction rather than by pointer value. |
1703 | /// The hashing and equality testing functions ignore definitions so this is |
1704 | /// useful for CSE, etc. |
1705 | struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> { |
1706 | static inline MachineInstr *getEmptyKey() { |
1707 | return nullptr; |
1708 | } |
1709 | |
1710 | static inline MachineInstr *getTombstoneKey() { |
1711 | return reinterpret_cast<MachineInstr*>(-1); |
1712 | } |
1713 | |
1714 | static unsigned getHashValue(const MachineInstr* const &MI); |
1715 | |
1716 | static bool isEqual(const MachineInstr* const &LHS, |
1717 | const MachineInstr* const &RHS) { |
1718 | if (RHS == getEmptyKey() || RHS == getTombstoneKey() || |
1719 | LHS == getEmptyKey() || LHS == getTombstoneKey()) |
1720 | return LHS == RHS; |
1721 | return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs); |
1722 | } |
1723 | }; |
1724 | |
1725 | //===----------------------------------------------------------------------===// |
1726 | // Debugging Support |
1727 | |
1728 | inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) { |
1729 | MI.print(OS); |
1730 | return OS; |
1731 | } |
1732 | |
1733 | } // end namespace llvm |
1734 | |
1735 | #endif // LLVM_CODEGEN_MACHINEINSTR_H |