Bug Summary

File:lib/Target/Mips/MicroMipsSizeReduction.cpp
Warning:line 648, column 17
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name MicroMipsSizeReduction.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn338205/build-llvm/lib/Target/Mips -I /build/llvm-toolchain-snapshot-7~svn338205/lib/Target/Mips -I /build/llvm-toolchain-snapshot-7~svn338205/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn338205/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/c++/8 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/x86_64-linux-gnu/c++/8 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/x86_64-linux-gnu/c++/8 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/c++/8/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/lib/gcc/x86_64-linux-gnu/8/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn338205/build-llvm/lib/Target/Mips -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-07-29-043837-17923-1 -x c++ /build/llvm-toolchain-snapshot-7~svn338205/lib/Target/Mips/MicroMipsSizeReduction.cpp -faddrsig
1//=== MicroMipsSizeReduction.cpp - MicroMips size reduction pass --------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9///\file
10/// This pass is used to reduce the size of instructions where applicable.
11///
12/// TODO: Implement microMIPS64 support.
13//===----------------------------------------------------------------------===//
14#include "Mips.h"
15#include "MipsInstrInfo.h"
16#include "MipsSubtarget.h"
17#include "llvm/ADT/Statistic.h"
18#include "llvm/CodeGen/MachineFunctionPass.h"
19#include "llvm/Support/Debug.h"
20
21using namespace llvm;
22
23#define DEBUG_TYPE"micromips-reduce-size" "micromips-reduce-size"
24#define MICROMIPS_SIZE_REDUCE_NAME"MicroMips instruction size reduce pass" "MicroMips instruction size reduce pass"
25
26STATISTIC(NumReduced, "Number of instructions reduced (32-bit to 16-bit ones, "static llvm::Statistic NumReduced = {"micromips-reduce-size",
"NumReduced", "Number of instructions reduced (32-bit to 16-bit ones, "
"or two instructions into one", {0}, {false}}
27 "or two instructions into one")static llvm::Statistic NumReduced = {"micromips-reduce-size",
"NumReduced", "Number of instructions reduced (32-bit to 16-bit ones, "
"or two instructions into one", {0}, {false}};
28
29namespace {
30
31/// Order of operands to transfer
32// TODO: Will be extended when additional optimizations are added
33enum OperandTransfer {
34 OT_NA, ///< Not applicable
35 OT_OperandsAll, ///< Transfer all operands
36 OT_Operands02, ///< Transfer operands 0 and 2
37 OT_Operand2, ///< Transfer just operand 2
38 OT_OperandsXOR, ///< Transfer operands for XOR16
39 OT_OperandsLwp, ///< Transfer operands for LWP
40 OT_OperandsSwp, ///< Transfer operands for SWP
41};
42
43/// Reduction type
44// TODO: Will be extended when additional optimizations are added
45enum ReduceType {
46 RT_TwoInstr, ///< Reduce two instructions into one instruction
47 RT_OneInstr ///< Reduce one instruction into a smaller instruction
48};
49
50// Information about immediate field restrictions
51struct ImmField {
52 ImmField() : ImmFieldOperand(-1), Shift(0), LBound(0), HBound(0) {}
53 ImmField(uint8_t Shift, int16_t LBound, int16_t HBound,
54 int8_t ImmFieldOperand)
55 : ImmFieldOperand(ImmFieldOperand), Shift(Shift), LBound(LBound),
56 HBound(HBound) {}
57 int8_t ImmFieldOperand; // Immediate operand, -1 if it does not exist
58 uint8_t Shift; // Shift value
59 int16_t LBound; // Low bound of the immediate operand
60 int16_t HBound; // High bound of the immediate operand
61};
62
63/// Information about operands
64// TODO: Will be extended when additional optimizations are added
65struct OpInfo {
66 OpInfo(enum OperandTransfer TransferOperands)
67 : TransferOperands(TransferOperands) {}
68 OpInfo() : TransferOperands(OT_NA) {}
69
70 enum OperandTransfer
71 TransferOperands; ///< Operands to transfer to the new instruction
72};
73
74// Information about opcodes
75struct OpCodes {
76 OpCodes(unsigned WideOpc, unsigned NarrowOpc)
77 : WideOpc(WideOpc), NarrowOpc(NarrowOpc) {}
78
79 unsigned WideOpc; ///< Wide opcode
80 unsigned NarrowOpc; ///< Narrow opcode
81};
82
83typedef struct ReduceEntryFunArgs ReduceEntryFunArgs;
84
85/// ReduceTable - A static table with information on mapping from wide
86/// opcodes to narrow
87struct ReduceEntry {
88
89 enum ReduceType eRType; ///< Reduction type
90 bool (*ReduceFunction)(
91 ReduceEntryFunArgs *Arguments); ///< Pointer to reduce function
92 struct OpCodes Ops; ///< All relevant OpCodes
93 struct OpInfo OpInf; ///< Characteristics of operands
94 struct ImmField Imm; ///< Characteristics of immediate field
95
96 ReduceEntry(enum ReduceType RType, struct OpCodes Op,
97 bool (*F)(ReduceEntryFunArgs *Arguments), struct OpInfo OpInf,
98 struct ImmField Imm)
99 : eRType(RType), ReduceFunction(F), Ops(Op), OpInf(OpInf), Imm(Imm) {}
100
101 unsigned NarrowOpc() const { return Ops.NarrowOpc; }
102 unsigned WideOpc() const { return Ops.WideOpc; }
103 int16_t LBound() const { return Imm.LBound; }
104 int16_t HBound() const { return Imm.HBound; }
105 uint8_t Shift() const { return Imm.Shift; }
106 int8_t ImmField() const { return Imm.ImmFieldOperand; }
107 enum OperandTransfer TransferOperands() const {
108 return OpInf.TransferOperands;
109 }
110 enum ReduceType RType() const { return eRType; }
111
112 // operator used by std::equal_range
113 bool operator<(const unsigned int r) const { return (WideOpc() < r); }
114
115 // operator used by std::equal_range
116 friend bool operator<(const unsigned int r, const struct ReduceEntry &re) {
117 return (r < re.WideOpc());
118 }
119};
120
121// Function arguments for ReduceFunction
122struct ReduceEntryFunArgs {
123 MachineInstr *MI; // Instruction
124 const ReduceEntry &Entry; // Entry field
125 MachineBasicBlock::instr_iterator
126 &NextMII; // Iterator to next instruction in block
127
128 ReduceEntryFunArgs(MachineInstr *argMI, const ReduceEntry &argEntry,
129 MachineBasicBlock::instr_iterator &argNextMII)
130 : MI(argMI), Entry(argEntry), NextMII(argNextMII) {}
131};
132
133typedef llvm::SmallVector<ReduceEntry, 32> ReduceEntryVector;
134
135class MicroMipsSizeReduce : public MachineFunctionPass {
136public:
137 static char ID;
138 MicroMipsSizeReduce();
139
140 static const MipsInstrInfo *MipsII;
141 const MipsSubtarget *Subtarget;
142
143 bool runOnMachineFunction(MachineFunction &MF) override;
144
145 llvm::StringRef getPassName() const override {
146 return "microMIPS instruction size reduction pass";
147 }
148
149private:
150 /// Reduces width of instructions in the specified basic block.
151 bool ReduceMBB(MachineBasicBlock &MBB);
152
153 /// Attempts to reduce MI, returns true on success.
154 bool ReduceMI(const MachineBasicBlock::instr_iterator &MII,
155 MachineBasicBlock::instr_iterator &NextMII);
156
157 // Attempts to reduce LW/SW instruction into LWSP/SWSP,
158 // returns true on success.
159 static bool ReduceXWtoXWSP(ReduceEntryFunArgs *Arguments);
160
161 // Attempts to reduce two LW/SW instructions into LWP/SWP instruction,
162 // returns true on success.
163 static bool ReduceXWtoXWP(ReduceEntryFunArgs *Arguments);
164
165 // Attempts to reduce LBU/LHU instruction into LBU16/LHU16,
166 // returns true on success.
167 static bool ReduceLXUtoLXU16(ReduceEntryFunArgs *Arguments);
168
169 // Attempts to reduce SB/SH instruction into SB16/SH16,
170 // returns true on success.
171 static bool ReduceSXtoSX16(ReduceEntryFunArgs *Arguments);
172
173 // Attempts to reduce arithmetic instructions, returns true on success.
174 static bool ReduceArithmeticInstructions(ReduceEntryFunArgs *Arguments);
175
176 // Attempts to reduce ADDIU into ADDIUSP instruction,
177 // returns true on success.
178 static bool ReduceADDIUToADDIUSP(ReduceEntryFunArgs *Arguments);
179
180 // Attempts to reduce ADDIU into ADDIUR1SP instruction,
181 // returns true on success.
182 static bool ReduceADDIUToADDIUR1SP(ReduceEntryFunArgs *Arguments);
183
184 // Attempts to reduce XOR into XOR16 instruction,
185 // returns true on success.
186 static bool ReduceXORtoXOR16(ReduceEntryFunArgs *Arguments);
187
188 // Changes opcode of an instruction, replaces an instruction with a
189 // new one, or replaces two instructions with a new instruction
190 // depending on their order i.e. if these are consecutive forward
191 // or consecutive backward
192 static bool ReplaceInstruction(MachineInstr *MI, const ReduceEntry &Entry,
193 MachineInstr *MI2 = nullptr,
194 bool ConsecutiveForward = true);
195
196 // Table with transformation rules for each instruction.
197 static ReduceEntryVector ReduceTable;
198};
199
200char MicroMipsSizeReduce::ID = 0;
201const MipsInstrInfo *MicroMipsSizeReduce::MipsII;
202
203// This table must be sorted by WideOpc as a main criterion and
204// ReduceType as a sub-criterion (when wide opcodes are the same).
205ReduceEntryVector MicroMipsSizeReduce::ReduceTable = {
206
207 // ReduceType, OpCodes, ReduceFunction,
208 // OpInfo(TransferOperands),
209 // ImmField(Shift, LBound, HBound, ImmFieldPosition)
210 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUR1SP_MM),
211 ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},
212 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUSP_MM), ReduceADDIUToADDIUSP,
213 OpInfo(OT_Operand2), ImmField(0, 0, 0, 2)},
214 {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUR1SP_MM),
215 ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},
216 {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUSP_MM),
217 ReduceADDIUToADDIUSP, OpInfo(OT_Operand2), ImmField(0, 0, 0, 2)},
218 {RT_OneInstr, OpCodes(Mips::ADDu, Mips::ADDU16_MM),
219 ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
220 ImmField(0, 0, 0, -1)},
221 {RT_OneInstr, OpCodes(Mips::ADDu_MM, Mips::ADDU16_MM),
222 ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
223 ImmField(0, 0, 0, -1)},
224 {RT_OneInstr, OpCodes(Mips::LBu, Mips::LBU16_MM), ReduceLXUtoLXU16,
225 OpInfo(OT_OperandsAll), ImmField(0, -1, 15, 2)},
226 {RT_OneInstr, OpCodes(Mips::LBu_MM, Mips::LBU16_MM), ReduceLXUtoLXU16,
227 OpInfo(OT_OperandsAll), ImmField(0, -1, 15, 2)},
228 {RT_OneInstr, OpCodes(Mips::LEA_ADDiu, Mips::ADDIUR1SP_MM),
229 ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},
230 {RT_OneInstr, OpCodes(Mips::LEA_ADDiu_MM, Mips::ADDIUR1SP_MM),
231 ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},
232 {RT_OneInstr, OpCodes(Mips::LHu, Mips::LHU16_MM), ReduceLXUtoLXU16,
233 OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},
234 {RT_OneInstr, OpCodes(Mips::LHu_MM, Mips::LHU16_MM), ReduceLXUtoLXU16,
235 OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},
236 {RT_TwoInstr, OpCodes(Mips::LW, Mips::LWP_MM), ReduceXWtoXWP,
237 OpInfo(OT_OperandsLwp), ImmField(0, -2048, 2048, 2)},
238 {RT_OneInstr, OpCodes(Mips::LW, Mips::LWSP_MM), ReduceXWtoXWSP,
239 OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
240 {RT_TwoInstr, OpCodes(Mips::LW16_MM, Mips::LWP_MM), ReduceXWtoXWP,
241 OpInfo(OT_OperandsLwp), ImmField(0, -2048, 2048, 2)},
242 {RT_TwoInstr, OpCodes(Mips::LW_MM, Mips::LWP_MM), ReduceXWtoXWP,
243 OpInfo(OT_OperandsLwp), ImmField(0, -2048, 2048, 2)},
244 {RT_OneInstr, OpCodes(Mips::LW_MM, Mips::LWSP_MM), ReduceXWtoXWSP,
245 OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
246 {RT_OneInstr, OpCodes(Mips::SB, Mips::SB16_MM), ReduceSXtoSX16,
247 OpInfo(OT_OperandsAll), ImmField(0, 0, 16, 2)},
248 {RT_OneInstr, OpCodes(Mips::SB_MM, Mips::SB16_MM), ReduceSXtoSX16,
249 OpInfo(OT_OperandsAll), ImmField(0, 0, 16, 2)},
250 {RT_OneInstr, OpCodes(Mips::SH, Mips::SH16_MM), ReduceSXtoSX16,
251 OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},
252 {RT_OneInstr, OpCodes(Mips::SH_MM, Mips::SH16_MM), ReduceSXtoSX16,
253 OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},
254 {RT_OneInstr, OpCodes(Mips::SUBu, Mips::SUBU16_MM),
255 ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
256 ImmField(0, 0, 0, -1)},
257 {RT_OneInstr, OpCodes(Mips::SUBu_MM, Mips::SUBU16_MM),
258 ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
259 ImmField(0, 0, 0, -1)},
260 {RT_TwoInstr, OpCodes(Mips::SW, Mips::SWP_MM), ReduceXWtoXWP,
261 OpInfo(OT_OperandsSwp), ImmField(0, -2048, 2048, 2)},
262 {RT_OneInstr, OpCodes(Mips::SW, Mips::SWSP_MM), ReduceXWtoXWSP,
263 OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
264 {RT_TwoInstr, OpCodes(Mips::SW16_MM, Mips::SWP_MM), ReduceXWtoXWP,
265 OpInfo(OT_OperandsSwp), ImmField(0, -2048, 2048, 2)},
266 {RT_TwoInstr, OpCodes(Mips::SW_MM, Mips::SWP_MM), ReduceXWtoXWP,
267 OpInfo(OT_OperandsSwp), ImmField(0, -2048, 2048, 2)},
268 {RT_OneInstr, OpCodes(Mips::SW_MM, Mips::SWSP_MM), ReduceXWtoXWSP,
269 OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
270 {RT_OneInstr, OpCodes(Mips::XOR, Mips::XOR16_MM), ReduceXORtoXOR16,
271 OpInfo(OT_OperandsXOR), ImmField(0, 0, 0, -1)},
272 {RT_OneInstr, OpCodes(Mips::XOR_MM, Mips::XOR16_MM), ReduceXORtoXOR16,
273 OpInfo(OT_OperandsXOR), ImmField(0, 0, 0, -1)}};
274} // end anonymous namespace
275
276INITIALIZE_PASS(MicroMipsSizeReduce, DEBUG_TYPE, MICROMIPS_SIZE_REDUCE_NAME,static void *initializeMicroMipsSizeReducePassOnce(PassRegistry
&Registry) { PassInfo *PI = new PassInfo( "MicroMips instruction size reduce pass"
, "micromips-reduce-size", &MicroMipsSizeReduce::ID, PassInfo
::NormalCtor_t(callDefaultCtor<MicroMipsSizeReduce>), false
, false); Registry.registerPass(*PI, true); return PI; } static
llvm::once_flag InitializeMicroMipsSizeReducePassFlag; void llvm
::initializeMicroMipsSizeReducePass(PassRegistry &Registry
) { llvm::call_once(InitializeMicroMipsSizeReducePassFlag, initializeMicroMipsSizeReducePassOnce
, std::ref(Registry)); }
277 false, false)static void *initializeMicroMipsSizeReducePassOnce(PassRegistry
&Registry) { PassInfo *PI = new PassInfo( "MicroMips instruction size reduce pass"
, "micromips-reduce-size", &MicroMipsSizeReduce::ID, PassInfo
::NormalCtor_t(callDefaultCtor<MicroMipsSizeReduce>), false
, false); Registry.registerPass(*PI, true); return PI; } static
llvm::once_flag InitializeMicroMipsSizeReducePassFlag; void llvm
::initializeMicroMipsSizeReducePass(PassRegistry &Registry
) { llvm::call_once(InitializeMicroMipsSizeReducePassFlag, initializeMicroMipsSizeReducePassOnce
, std::ref(Registry)); }
278
279// Returns true if the machine operand MO is register SP.
280static bool IsSP(const MachineOperand &MO) {
281 if (MO.isReg() && ((MO.getReg() == Mips::SP)))
282 return true;
283 return false;
284}
285
286// Returns true if the machine operand MO is register $16, $17, or $2-$7.
287static bool isMMThreeBitGPRegister(const MachineOperand &MO) {
288 if (MO.isReg() && Mips::GPRMM16RegClass.contains(MO.getReg()))
289 return true;
290 return false;
291}
292
293// Returns true if the machine operand MO is register $0, $17, or $2-$7.
294static bool isMMSourceRegister(const MachineOperand &MO) {
295 if (MO.isReg() && Mips::GPRMM16ZeroRegClass.contains(MO.getReg()))
296 return true;
297 return false;
298}
299
300// Returns true if the operand Op is an immediate value
301// and writes the immediate value into variable Imm.
302static bool GetImm(MachineInstr *MI, unsigned Op, int64_t &Imm) {
303
304 if (!MI->getOperand(Op).isImm())
305 return false;
306 Imm = MI->getOperand(Op).getImm();
307 return true;
308}
309
310// Returns true if the value is a valid immediate for ADDIUSP.
311static bool AddiuspImmValue(int64_t Value) {
312 int64_t Value2 = Value >> 2;
313 if (((Value & (int64_t)maskTrailingZeros<uint64_t>(2)) == Value) &&
314 ((Value2 >= 2 && Value2 <= 257) || (Value2 >= -258 && Value2 <= -3)))
315 return true;
316 return false;
317}
318
319// Returns true if the variable Value has the number of least-significant zero
320// bits equal to Shift and if the shifted value is between the bounds.
321static bool InRange(int64_t Value, unsigned short Shift, int LBound,
322 int HBound) {
323 int64_t Value2 = Value >> Shift;
324 if (((Value & (int64_t)maskTrailingZeros<uint64_t>(Shift)) == Value) &&
325 (Value2 >= LBound) && (Value2 < HBound))
326 return true;
327 return false;
328}
329
330// Returns true if immediate operand is in range.
331static bool ImmInRange(MachineInstr *MI, const ReduceEntry &Entry) {
332
333 int64_t offset;
334
335 if (!GetImm(MI, Entry.ImmField(), offset))
336 return false;
337
338 if (!InRange(offset, Entry.Shift(), Entry.LBound(), Entry.HBound()))
339 return false;
340
341 return true;
342}
343
344// Returns true if MI can be reduced to lwp/swp instruction
345static bool CheckXWPInstr(MachineInstr *MI, bool ReduceToLwp,
346 const ReduceEntry &Entry) {
347
348 if (ReduceToLwp &&
349 !(MI->getOpcode() == Mips::LW || MI->getOpcode() == Mips::LW_MM ||
350 MI->getOpcode() == Mips::LW16_MM))
351 return false;
352
353 if (!ReduceToLwp &&
354 !(MI->getOpcode() == Mips::SW || MI->getOpcode() == Mips::SW_MM ||
355 MI->getOpcode() == Mips::SW16_MM))
356 return false;
357
358 unsigned reg = MI->getOperand(0).getReg();
359 if (reg == Mips::RA)
360 return false;
361
362 if (!ImmInRange(MI, Entry))
363 return false;
364
365 if (ReduceToLwp && (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()))
366 return false;
367
368 return true;
369}
370
371// Returns true if the registers Reg1 and Reg2 are consecutive
372static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) {
373 static SmallVector<unsigned, 31> Registers = {
374 Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
375 Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6,
376 Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
377 Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP,
378 Mips::SP, Mips::FP, Mips::RA};
379
380 for (uint8_t i = 0; i < Registers.size() - 1; i++) {
381 if (Registers[i] == Reg1) {
382 if (Registers[i + 1] == Reg2)
383 return true;
384 else
385 return false;
386 }
387 }
388 return false;
389}
390
391// Returns true if registers and offsets are consecutive
392static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) {
393
394 int64_t Offset1, Offset2;
395 if (!GetImm(MI1, 2, Offset1))
396 return false;
397 if (!GetImm(MI2, 2, Offset2))
398 return false;
399
400 unsigned Reg1 = MI1->getOperand(0).getReg();
401 unsigned Reg2 = MI2->getOperand(0).getReg();
402
403 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2)));
404}
405
406MicroMipsSizeReduce::MicroMipsSizeReduce() : MachineFunctionPass(ID) {}
407
408bool MicroMipsSizeReduce::ReduceMI(const MachineBasicBlock::instr_iterator &MII,
409 MachineBasicBlock::instr_iterator &NextMII) {
410
411 MachineInstr *MI = &*MII;
412 unsigned Opcode = MI->getOpcode();
413
414 // Search the table.
415 ReduceEntryVector::const_iterator Start = std::begin(ReduceTable);
416 ReduceEntryVector::const_iterator End = std::end(ReduceTable);
417
418 std::pair<ReduceEntryVector::const_iterator,
419 ReduceEntryVector::const_iterator>
420 Range = std::equal_range(Start, End, Opcode);
421
422 if (Range.first == Range.second)
423 return false;
424
425 for (ReduceEntryVector::const_iterator Entry = Range.first;
426 Entry != Range.second; ++Entry) {
427 ReduceEntryFunArgs Arguments(&(*MII), *Entry, NextMII);
428 if (((*Entry).ReduceFunction)(&Arguments))
429 return true;
430 }
431 return false;
432}
433
434bool MicroMipsSizeReduce::ReduceXWtoXWSP(ReduceEntryFunArgs *Arguments) {
435
436 MachineInstr *MI = Arguments->MI;
437 const ReduceEntry &Entry = Arguments->Entry;
438
439 if (!ImmInRange(MI, Entry))
440 return false;
441
442 if (!IsSP(MI->getOperand(1)))
443 return false;
444
445 return ReplaceInstruction(MI, Entry);
446}
447
448bool MicroMipsSizeReduce::ReduceXWtoXWP(ReduceEntryFunArgs *Arguments) {
449
450 const ReduceEntry &Entry = Arguments->Entry;
451 MachineBasicBlock::instr_iterator &NextMII = Arguments->NextMII;
452 const MachineBasicBlock::instr_iterator &E =
453 Arguments->MI->getParent()->instr_end();
454
455 if (NextMII == E)
456 return false;
457
458 MachineInstr *MI1 = Arguments->MI;
459 MachineInstr *MI2 = &*NextMII;
460
461 // ReduceToLwp = true/false - reduce to LWP/SWP instruction
462 bool ReduceToLwp = (MI1->getOpcode() == Mips::LW) ||
463 (MI1->getOpcode() == Mips::LW_MM) ||
464 (MI1->getOpcode() == Mips::LW16_MM);
465
466 if (!CheckXWPInstr(MI1, ReduceToLwp, Entry))
467 return false;
468
469 if (!CheckXWPInstr(MI2, ReduceToLwp, Entry))
470 return false;
471
472 unsigned Reg1 = MI1->getOperand(1).getReg();
473 unsigned Reg2 = MI2->getOperand(1).getReg();
474
475 if (Reg1 != Reg2)
476 return false;
477
478 bool ConsecutiveForward = ConsecutiveInstr(MI1, MI2);
479 bool ConsecutiveBackward = ConsecutiveInstr(MI2, MI1);
480
481 if (!(ConsecutiveForward || ConsecutiveBackward))
482 return false;
483
484 NextMII = std::next(NextMII);
485 return ReplaceInstruction(MI1, Entry, MI2, ConsecutiveForward);
486}
487
488bool MicroMipsSizeReduce::ReduceArithmeticInstructions(
489 ReduceEntryFunArgs *Arguments) {
490
491 MachineInstr *MI = Arguments->MI;
492 const ReduceEntry &Entry = Arguments->Entry;
493
494 if (!isMMThreeBitGPRegister(MI->getOperand(0)) ||
1
Taking false branch
→
495 !isMMThreeBitGPRegister(MI->getOperand(1)) ||
496 !isMMThreeBitGPRegister(MI->getOperand(2)))
497 return false;
498
499 return ReplaceInstruction(MI, Entry);
2
←
Passing null pointer value via 3rd parameter 'MI2'
→
3
←
Calling 'MicroMipsSizeReduce::ReplaceInstruction'
→
500}
501
502bool MicroMipsSizeReduce::ReduceADDIUToADDIUR1SP(
503 ReduceEntryFunArgs *Arguments) {
504
505 MachineInstr *MI = Arguments->MI;
506 const ReduceEntry &Entry = Arguments->Entry;
507
508 if (!ImmInRange(MI, Entry))
509 return false;
510
511 if (!isMMThreeBitGPRegister(MI->getOperand(0)) || !IsSP(MI->getOperand(1)))
512 return false;
513
514 return ReplaceInstruction(MI, Entry);
515}
516
517bool MicroMipsSizeReduce::ReduceADDIUToADDIUSP(ReduceEntryFunArgs *Arguments) {
518
519 MachineInstr *MI = Arguments->MI;
520 const ReduceEntry &Entry = Arguments->Entry;
521
522 int64_t ImmValue;
523 if (!GetImm(MI, Entry.ImmField(), ImmValue))
524 return false;
525
526 if (!AddiuspImmValue(ImmValue))
527 return false;
528
529 if (!IsSP(MI->getOperand(0)) || !IsSP(MI->getOperand(1)))
530 return false;
531
532 return ReplaceInstruction(MI, Entry);
533}
534
535bool MicroMipsSizeReduce::ReduceLXUtoLXU16(ReduceEntryFunArgs *Arguments) {
536
537 MachineInstr *MI = Arguments->MI;
538 const ReduceEntry &Entry = Arguments->Entry;
539
540 if (!ImmInRange(MI, Entry))
541 return false;
542
543 if (!isMMThreeBitGPRegister(MI->getOperand(0)) ||
544 !isMMThreeBitGPRegister(MI->getOperand(1)))
545 return false;
546
547 return ReplaceInstruction(MI, Entry);
548}
549
550bool MicroMipsSizeReduce::ReduceSXtoSX16(ReduceEntryFunArgs *Arguments) {
551
552 MachineInstr *MI = Arguments->MI;
553 const ReduceEntry &Entry = Arguments->Entry;
554
555 if (!ImmInRange(MI, Entry))
556 return false;
557
558 if (!isMMSourceRegister(MI->getOperand(0)) ||
559 !isMMThreeBitGPRegister(MI->getOperand(1)))
560 return false;
561
562 return ReplaceInstruction(MI, Entry);
563}
564
565bool MicroMipsSizeReduce::ReduceXORtoXOR16(ReduceEntryFunArgs *Arguments) {
566
567 MachineInstr *MI = Arguments->MI;
568 const ReduceEntry &Entry = Arguments->Entry;
569
570 if (!isMMThreeBitGPRegister(MI->getOperand(0)) ||
571 !isMMThreeBitGPRegister(MI->getOperand(1)) ||
572 !isMMThreeBitGPRegister(MI->getOperand(2)))
573 return false;
574
575 if (!(MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) &&
576 !(MI->getOperand(0).getReg() == MI->getOperand(1).getReg()))
577 return false;
578
579 return ReplaceInstruction(MI, Entry);
580}
581
582bool MicroMipsSizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
583 bool Modified = false;
584 MachineBasicBlock::instr_iterator MII = MBB.instr_begin(),
585 E = MBB.instr_end();
586 MachineBasicBlock::instr_iterator NextMII;
587
588 // Iterate through the instructions in the basic block
589 for (; MII != E; MII = NextMII) {
590 NextMII = std::next(MII);
591 MachineInstr *MI = &*MII;
592
593 // Don't reduce bundled instructions or pseudo operations
594 if (MI->isBundle() || MI->isTransient())
595 continue;
596
597 // Try to reduce 32-bit instruction into 16-bit instruction
598 Modified |= ReduceMI(MII, NextMII);
599 }
600
601 return Modified;
602}
603
604bool MicroMipsSizeReduce::ReplaceInstruction(MachineInstr *MI,
605 const ReduceEntry &Entry,
606 MachineInstr *MI2,
607 bool ConsecutiveForward) {
608
609 enum OperandTransfer OpTransfer = Entry.TransferOperands();
610
611 LLVM_DEBUG(dbgs() << "Converting 32-bit: " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("micromips-reduce-size")) { dbgs() << "Converting 32-bit: "
<< *MI; } } while (false);
612 ++NumReduced;
613
614 if (OpTransfer == OT_OperandsAll) {
4
←
Assuming 'OpTransfer' is not equal to OT_OperandsAll
→
5
←
Taking false branch
→
615 MI->setDesc(MipsII->get(Entry.NarrowOpc()));
616 LLVM_DEBUG(dbgs() << " to 16-bit: " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("micromips-reduce-size")) { dbgs() << " to 16-bit: "
<< *MI; } } while (false);
617 return true;
618 } else {
619 MachineBasicBlock &MBB = *MI->getParent();
620 const MCInstrDesc &NewMCID = MipsII->get(Entry.NarrowOpc());
621 DebugLoc dl = MI->getDebugLoc();
622 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
623 switch (OpTransfer) {
6
←
Control jumps to 'case OT_OperandsSwp:' at line 645
→
624 case OT_Operand2:
625 MIB.add(MI->getOperand(2));
626 break;
627 case OT_Operands02: {
628 MIB.add(MI->getOperand(0));
629 MIB.add(MI->getOperand(2));
630 break;
631 }
632 case OT_OperandsXOR: {
633 if (MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) {
634 MIB.add(MI->getOperand(0));
635 MIB.add(MI->getOperand(1));
636 MIB.add(MI->getOperand(2));
637 } else {
638 MIB.add(MI->getOperand(0));
639 MIB.add(MI->getOperand(2));
640 MIB.add(MI->getOperand(1));
641 }
642 break;
643 }
644 case OT_OperandsLwp:
645 case OT_OperandsSwp: {
646 if (ConsecutiveForward) {
7
←
Taking true branch
→
647 MIB.add(MI->getOperand(0));
648 MIB.add(MI2->getOperand(0));
8
←
Called C++ object pointer is null
649 MIB.add(MI->getOperand(1));
650 MIB.add(MI->getOperand(2));
651 } else { // consecutive backward
652 MIB.add(MI2->getOperand(0));
653 MIB.add(MI->getOperand(0));
654 MIB.add(MI2->getOperand(1));
655 MIB.add(MI2->getOperand(2));
656 }
657
658 LLVM_DEBUG(dbgs() << "and converting 32-bit: " << *MI2do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("micromips-reduce-size")) { dbgs() << "and converting 32-bit: "
<< *MI2 << " to: " << *MIB; } } while
(false)
659 << " to: " << *MIB)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("micromips-reduce-size")) { dbgs() << "and converting 32-bit: "
<< *MI2 << " to: " << *MIB; } } while
(false);
660
661 MBB.erase_instr(MI);
662 MBB.erase_instr(MI2);
663 return true;
664 }
665 default:
666 llvm_unreachable("Unknown operand transfer!")::llvm::llvm_unreachable_internal("Unknown operand transfer!"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/Mips/MicroMipsSizeReduction.cpp"
, 666);
667 }
668
669 // Transfer MI flags.
670 MIB.setMIFlags(MI->getFlags());
671
672 LLVM_DEBUG(dbgs() << " to 16-bit: " << *MIB)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("micromips-reduce-size")) { dbgs() << " to 16-bit: "
<< *MIB; } } while (false);
673 MBB.erase_instr(MI);
674 return true;
675 }
676 return false;
677}
678
679bool MicroMipsSizeReduce::runOnMachineFunction(MachineFunction &MF) {
680
681 Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
682
683 // TODO: Add support for the subtarget microMIPS32R6.
684 if (!Subtarget->inMicroMipsMode() || !Subtarget->hasMips32r2() ||
685 Subtarget->hasMips32r6())
686 return false;
687
688 MipsII = static_cast<const MipsInstrInfo *>(Subtarget->getInstrInfo());
689
690 bool Modified = false;
691 MachineFunction::iterator I = MF.begin(), E = MF.end();
692
693 for (; I != E; ++I)
694 Modified |= ReduceMBB(*I);
695 return Modified;
696}
697
698/// Returns an instance of the MicroMips size reduction pass.
699FunctionPass *llvm::createMicroMipsSizeReducePass() {
700 return new MicroMipsSizeReduce();
701}