Bug Summary

File:lib/Target/AMDGPU/SIISelLowering.cpp
Warning:line 8851, column 52
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name SIISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-8/lib/clang/8.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/include -I /build/llvm-toolchain-snapshot-8~svn350071/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/8.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-8/lib/clang/8.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/lib/Target/AMDGPU -fdebug-prefix-map=/build/llvm-toolchain-snapshot-8~svn350071=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-12-27-042839-1215-1 -x c++ /build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp -faddrsig
1//===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// Custom DAG lowering for SI
12//
13//===----------------------------------------------------------------------===//
14
15#if defined(_MSC_VER) || defined(__MINGW32__)
16// Provide M_PI.
17#define _USE_MATH_DEFINES
18#endif
19
20#include "SIISelLowering.h"
21#include "AMDGPU.h"
22#include "AMDGPUIntrinsicInfo.h"
23#include "AMDGPUSubtarget.h"
24#include "AMDGPUTargetMachine.h"
25#include "SIDefines.h"
26#include "SIInstrInfo.h"
27#include "SIMachineFunctionInfo.h"
28#include "SIRegisterInfo.h"
29#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
30#include "Utils/AMDGPUBaseInfo.h"
31#include "llvm/ADT/APFloat.h"
32#include "llvm/ADT/APInt.h"
33#include "llvm/ADT/ArrayRef.h"
34#include "llvm/ADT/BitVector.h"
35#include "llvm/ADT/SmallVector.h"
36#include "llvm/ADT/Statistic.h"
37#include "llvm/ADT/StringRef.h"
38#include "llvm/ADT/StringSwitch.h"
39#include "llvm/ADT/Twine.h"
40#include "llvm/CodeGen/Analysis.h"
41#include "llvm/CodeGen/CallingConvLower.h"
42#include "llvm/CodeGen/DAGCombine.h"
43#include "llvm/CodeGen/ISDOpcodes.h"
44#include "llvm/CodeGen/MachineBasicBlock.h"
45#include "llvm/CodeGen/MachineFrameInfo.h"
46#include "llvm/CodeGen/MachineFunction.h"
47#include "llvm/CodeGen/MachineInstr.h"
48#include "llvm/CodeGen/MachineInstrBuilder.h"
49#include "llvm/CodeGen/MachineMemOperand.h"
50#include "llvm/CodeGen/MachineModuleInfo.h"
51#include "llvm/CodeGen/MachineOperand.h"
52#include "llvm/CodeGen/MachineRegisterInfo.h"
53#include "llvm/CodeGen/SelectionDAG.h"
54#include "llvm/CodeGen/SelectionDAGNodes.h"
55#include "llvm/CodeGen/TargetCallingConv.h"
56#include "llvm/CodeGen/TargetRegisterInfo.h"
57#include "llvm/CodeGen/ValueTypes.h"
58#include "llvm/IR/Constants.h"
59#include "llvm/IR/DataLayout.h"
60#include "llvm/IR/DebugLoc.h"
61#include "llvm/IR/DerivedTypes.h"
62#include "llvm/IR/DiagnosticInfo.h"
63#include "llvm/IR/Function.h"
64#include "llvm/IR/GlobalValue.h"
65#include "llvm/IR/InstrTypes.h"
66#include "llvm/IR/Instruction.h"
67#include "llvm/IR/Instructions.h"
68#include "llvm/IR/IntrinsicInst.h"
69#include "llvm/IR/Type.h"
70#include "llvm/Support/Casting.h"
71#include "llvm/Support/CodeGen.h"
72#include "llvm/Support/CommandLine.h"
73#include "llvm/Support/Compiler.h"
74#include "llvm/Support/ErrorHandling.h"
75#include "llvm/Support/KnownBits.h"
76#include "llvm/Support/MachineValueType.h"
77#include "llvm/Support/MathExtras.h"
78#include "llvm/Target/TargetOptions.h"
79#include <cassert>
80#include <cmath>
81#include <cstdint>
82#include <iterator>
83#include <tuple>
84#include <utility>
85#include <vector>
86
87using namespace llvm;
88
89#define DEBUG_TYPE"si-lower" "si-lower"
90
91STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"si-lower", "NumTailCalls"
, "Number of tail calls", {0}, {false}}
;
92
93static cl::opt<bool> EnableVGPRIndexMode(
94 "amdgpu-vgpr-index-mode",
95 cl::desc("Use GPR indexing mode instead of movrel for vector indexing"),
96 cl::init(false));
97
98static cl::opt<unsigned> AssumeFrameIndexHighZeroBits(
99 "amdgpu-frame-index-zero-bits",
100 cl::desc("High bits of frame index assumed to be zero"),
101 cl::init(5),
102 cl::ReallyHidden);
103
104static unsigned findFirstFreeSGPR(CCState &CCInfo) {
105 unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
106 for (unsigned Reg = 0; Reg < NumSGPRs; ++Reg) {
107 if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) {
108 return AMDGPU::SGPR0 + Reg;
109 }
110 }
111 llvm_unreachable("Cannot allocate sgpr")::llvm::llvm_unreachable_internal("Cannot allocate sgpr", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 111)
;
112}
113
114SITargetLowering::SITargetLowering(const TargetMachine &TM,
115 const GCNSubtarget &STI)
116 : AMDGPUTargetLowering(TM, STI),
117 Subtarget(&STI) {
118 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
119 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
120
121 addRegisterClass(MVT::i32, &AMDGPU::SReg_32_XM0RegClass);
122 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
123
124 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
125 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
126 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
127
128 addRegisterClass(MVT::v2i64, &AMDGPU::SReg_128RegClass);
129 addRegisterClass(MVT::v2f64, &AMDGPU::SReg_128RegClass);
130
131 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
132 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
133
134 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
135 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
136
137 addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass);
138 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
139
140 if (Subtarget->has16BitInsts()) {
141 addRegisterClass(MVT::i16, &AMDGPU::SReg_32_XM0RegClass);
142 addRegisterClass(MVT::f16, &AMDGPU::SReg_32_XM0RegClass);
143
144 // Unless there are also VOP3P operations, not operations are really legal.
145 addRegisterClass(MVT::v2i16, &AMDGPU::SReg_32_XM0RegClass);
146 addRegisterClass(MVT::v2f16, &AMDGPU::SReg_32_XM0RegClass);
147 addRegisterClass(MVT::v4i16, &AMDGPU::SReg_64RegClass);
148 addRegisterClass(MVT::v4f16, &AMDGPU::SReg_64RegClass);
149 }
150
151 computeRegisterProperties(Subtarget->getRegisterInfo());
152
153 // We need to custom lower vector stores from local memory
154 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
155 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
156 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
157 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
158 setOperationAction(ISD::LOAD, MVT::i1, Custom);
159 setOperationAction(ISD::LOAD, MVT::v32i32, Custom);
160
161 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
162 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
163 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
164 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
165 setOperationAction(ISD::STORE, MVT::i1, Custom);
166 setOperationAction(ISD::STORE, MVT::v32i32, Custom);
167
168 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
169 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
170 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
171 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
172 setTruncStoreAction(MVT::v32i32, MVT::v32i16, Expand);
173 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Expand);
174 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Expand);
175 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Expand);
176 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Expand);
177 setTruncStoreAction(MVT::v32i32, MVT::v32i8, Expand);
178
179 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
180 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
181
182 setOperationAction(ISD::SELECT, MVT::i1, Promote);
183 setOperationAction(ISD::SELECT, MVT::i64, Custom);
184 setOperationAction(ISD::SELECT, MVT::f64, Promote);
185 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
186
187 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
188 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
189 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
190 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
191 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
192
193 setOperationAction(ISD::SETCC, MVT::i1, Promote);
194 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
195 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
196 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
197
198 setOperationAction(ISD::TRUNCATE, MVT::v2i32, Expand);
199 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
200
201 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
202 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
203 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
204 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
205 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
206 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
207 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
208
209 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
210 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
211 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
212 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i16, Custom);
213 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f16, Custom);
214 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2i16, Custom);
215 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2f16, Custom);
216
217 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v2f16, Custom);
218 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v4f16, Custom);
219 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
220
221 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
222 setOperationAction(ISD::INTRINSIC_VOID, MVT::v2i16, Custom);
223 setOperationAction(ISD::INTRINSIC_VOID, MVT::v2f16, Custom);
224 setOperationAction(ISD::INTRINSIC_VOID, MVT::v4f16, Custom);
225
226 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
227 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
228 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
229 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
230 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
231 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
232
233 setOperationAction(ISD::UADDO, MVT::i32, Legal);
234 setOperationAction(ISD::USUBO, MVT::i32, Legal);
235
236 setOperationAction(ISD::ADDCARRY, MVT::i32, Legal);
237 setOperationAction(ISD::SUBCARRY, MVT::i32, Legal);
238
239 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
240 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
241 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
242
243#if 0
244 setOperationAction(ISD::ADDCARRY, MVT::i64, Legal);
245 setOperationAction(ISD::SUBCARRY, MVT::i64, Legal);
246#endif
247
248 // We only support LOAD/STORE and vector manipulation ops for vectors
249 // with > 4 elements.
250 for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32,
251 MVT::v2i64, MVT::v2f64, MVT::v4i16, MVT::v4f16, MVT::v32i32 }) {
252 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
253 switch (Op) {
254 case ISD::LOAD:
255 case ISD::STORE:
256 case ISD::BUILD_VECTOR:
257 case ISD::BITCAST:
258 case ISD::EXTRACT_VECTOR_ELT:
259 case ISD::INSERT_VECTOR_ELT:
260 case ISD::INSERT_SUBVECTOR:
261 case ISD::EXTRACT_SUBVECTOR:
262 case ISD::SCALAR_TO_VECTOR:
263 break;
264 case ISD::CONCAT_VECTORS:
265 setOperationAction(Op, VT, Custom);
266 break;
267 default:
268 setOperationAction(Op, VT, Expand);
269 break;
270 }
271 }
272 }
273
274 setOperationAction(ISD::FP_EXTEND, MVT::v4f32, Expand);
275
276 // TODO: For dynamic 64-bit vector inserts/extracts, should emit a pseudo that
277 // is expanded to avoid having two separate loops in case the index is a VGPR.
278
279 // Most operations are naturally 32-bit vector operations. We only support
280 // load and store of i64 vectors, so promote v2i64 vector operations to v4i32.
281 for (MVT Vec64 : { MVT::v2i64, MVT::v2f64 }) {
282 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
283 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32);
284
285 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
286 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32);
287
288 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
289 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
290
291 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
292 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32);
293 }
294
295 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
296 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
297 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
298 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
299
300 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f16, Custom);
301 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
302
303 // Avoid stack access for these.
304 // TODO: Generalize to more vector types.
305 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i16, Custom);
306 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f16, Custom);
307 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
308 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f16, Custom);
309
310 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom);
311 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom);
312 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i8, Custom);
313 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i8, Custom);
314 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i8, Custom);
315
316 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i8, Custom);
317 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i8, Custom);
318 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i8, Custom);
319
320 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i16, Custom);
321 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f16, Custom);
322 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
323 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f16, Custom);
324
325 // BUFFER/FLAT_ATOMIC_CMP_SWAP on GCN GPUs needs input marshalling,
326 // and output demarshalling
327 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
328 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
329
330 // We can't return success/failure, only the old value,
331 // let LLVM add the comparison
332 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i32, Expand);
333 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i64, Expand);
334
335 if (Subtarget->hasFlatAddressSpace()) {
336 setOperationAction(ISD::ADDRSPACECAST, MVT::i32, Custom);
337 setOperationAction(ISD::ADDRSPACECAST, MVT::i64, Custom);
338 }
339
340 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
341 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
342
343 // On SI this is s_memtime and s_memrealtime on VI.
344 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
345 setOperationAction(ISD::TRAP, MVT::Other, Custom);
346 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Custom);
347
348 if (Subtarget->has16BitInsts()) {
349 setOperationAction(ISD::FLOG, MVT::f16, Custom);
350 setOperationAction(ISD::FEXP, MVT::f16, Custom);
351 setOperationAction(ISD::FLOG10, MVT::f16, Custom);
352 }
353
354 // v_mad_f32 does not support denormals according to some sources.
355 if (!Subtarget->hasFP32Denormals())
356 setOperationAction(ISD::FMAD, MVT::f32, Legal);
357
358 if (!Subtarget->hasBFI()) {
359 // fcopysign can be done in a single instruction with BFI.
360 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
361 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
362 }
363
364 if (!Subtarget->hasBCNT(32))
365 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
366
367 if (!Subtarget->hasBCNT(64))
368 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
369
370 if (Subtarget->hasFFBH())
371 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom);
372
373 if (Subtarget->hasFFBL())
374 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Custom);
375
376 // We only really have 32-bit BFE instructions (and 16-bit on VI).
377 //
378 // On SI+ there are 64-bit BFEs, but they are scalar only and there isn't any
379 // effort to match them now. We want this to be false for i64 cases when the
380 // extraction isn't restricted to the upper or lower half. Ideally we would
381 // have some pass reduce 64-bit extracts to 32-bit if possible. Extracts that
382 // span the midpoint are probably relatively rare, so don't worry about them
383 // for now.
384 if (Subtarget->hasBFE())
385 setHasExtractBitsInsn(true);
386
387 setOperationAction(ISD::FMINNUM, MVT::f32, Custom);
388 setOperationAction(ISD::FMAXNUM, MVT::f32, Custom);
389 setOperationAction(ISD::FMINNUM, MVT::f64, Custom);
390 setOperationAction(ISD::FMAXNUM, MVT::f64, Custom);
391
392
393 // These are really only legal for ieee_mode functions. We should be avoiding
394 // them for functions that don't have ieee_mode enabled, so just say they are
395 // legal.
396 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
397 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal);
398 setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal);
399 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal);
400
401
402 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
403 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
404 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
405 setOperationAction(ISD::FRINT, MVT::f64, Legal);
406 } else {
407 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
408 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
409 setOperationAction(ISD::FRINT, MVT::f64, Custom);
410 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
411 }
412
413 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
414
415 setOperationAction(ISD::FSIN, MVT::f32, Custom);
416 setOperationAction(ISD::FCOS, MVT::f32, Custom);
417 setOperationAction(ISD::FDIV, MVT::f32, Custom);
418 setOperationAction(ISD::FDIV, MVT::f64, Custom);
419
420 if (Subtarget->has16BitInsts()) {
421 setOperationAction(ISD::Constant, MVT::i16, Legal);
422
423 setOperationAction(ISD::SMIN, MVT::i16, Legal);
424 setOperationAction(ISD::SMAX, MVT::i16, Legal);
425
426 setOperationAction(ISD::UMIN, MVT::i16, Legal);
427 setOperationAction(ISD::UMAX, MVT::i16, Legal);
428
429 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Promote);
430 AddPromotedToType(ISD::SIGN_EXTEND, MVT::i16, MVT::i32);
431
432 setOperationAction(ISD::ROTR, MVT::i16, Promote);
433 setOperationAction(ISD::ROTL, MVT::i16, Promote);
434
435 setOperationAction(ISD::SDIV, MVT::i16, Promote);
436 setOperationAction(ISD::UDIV, MVT::i16, Promote);
437 setOperationAction(ISD::SREM, MVT::i16, Promote);
438 setOperationAction(ISD::UREM, MVT::i16, Promote);
439
440 setOperationAction(ISD::BSWAP, MVT::i16, Promote);
441 setOperationAction(ISD::BITREVERSE, MVT::i16, Promote);
442
443 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
444 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Promote);
445 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
446 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Promote);
447 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
448
449 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
450
451 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
452
453 setOperationAction(ISD::LOAD, MVT::i16, Custom);
454
455 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
456
457 setOperationAction(ISD::FP16_TO_FP, MVT::i16, Promote);
458 AddPromotedToType(ISD::FP16_TO_FP, MVT::i16, MVT::i32);
459 setOperationAction(ISD::FP_TO_FP16, MVT::i16, Promote);
460 AddPromotedToType(ISD::FP_TO_FP16, MVT::i16, MVT::i32);
461
462 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
463 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
464 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
465 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
466
467 // F16 - Constant Actions.
468 setOperationAction(ISD::ConstantFP, MVT::f16, Legal);
469
470 // F16 - Load/Store Actions.
471 setOperationAction(ISD::LOAD, MVT::f16, Promote);
472 AddPromotedToType(ISD::LOAD, MVT::f16, MVT::i16);
473 setOperationAction(ISD::STORE, MVT::f16, Promote);
474 AddPromotedToType(ISD::STORE, MVT::f16, MVT::i16);
475
476 // F16 - VOP1 Actions.
477 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
478 setOperationAction(ISD::FCOS, MVT::f16, Promote);
479 setOperationAction(ISD::FSIN, MVT::f16, Promote);
480 setOperationAction(ISD::FP_TO_SINT, MVT::f16, Promote);
481 setOperationAction(ISD::FP_TO_UINT, MVT::f16, Promote);
482 setOperationAction(ISD::SINT_TO_FP, MVT::f16, Promote);
483 setOperationAction(ISD::UINT_TO_FP, MVT::f16, Promote);
484 setOperationAction(ISD::FROUND, MVT::f16, Custom);
485
486 // F16 - VOP2 Actions.
487 setOperationAction(ISD::BR_CC, MVT::f16, Expand);
488 setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
489
490 setOperationAction(ISD::FDIV, MVT::f16, Custom);
491
492 // F16 - VOP3 Actions.
493 setOperationAction(ISD::FMA, MVT::f16, Legal);
494 if (!Subtarget->hasFP16Denormals())
495 setOperationAction(ISD::FMAD, MVT::f16, Legal);
496
497 for (MVT VT : {MVT::v2i16, MVT::v2f16, MVT::v4i16, MVT::v4f16}) {
498 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
499 switch (Op) {
500 case ISD::LOAD:
501 case ISD::STORE:
502 case ISD::BUILD_VECTOR:
503 case ISD::BITCAST:
504 case ISD::EXTRACT_VECTOR_ELT:
505 case ISD::INSERT_VECTOR_ELT:
506 case ISD::INSERT_SUBVECTOR:
507 case ISD::EXTRACT_SUBVECTOR:
508 case ISD::SCALAR_TO_VECTOR:
509 break;
510 case ISD::CONCAT_VECTORS:
511 setOperationAction(Op, VT, Custom);
512 break;
513 default:
514 setOperationAction(Op, VT, Expand);
515 break;
516 }
517 }
518 }
519
520 // XXX - Do these do anything? Vector constants turn into build_vector.
521 setOperationAction(ISD::Constant, MVT::v2i16, Legal);
522 setOperationAction(ISD::ConstantFP, MVT::v2f16, Legal);
523
524 setOperationAction(ISD::UNDEF, MVT::v2i16, Legal);
525 setOperationAction(ISD::UNDEF, MVT::v2f16, Legal);
526
527 setOperationAction(ISD::STORE, MVT::v2i16, Promote);
528 AddPromotedToType(ISD::STORE, MVT::v2i16, MVT::i32);
529 setOperationAction(ISD::STORE, MVT::v2f16, Promote);
530 AddPromotedToType(ISD::STORE, MVT::v2f16, MVT::i32);
531
532 setOperationAction(ISD::LOAD, MVT::v2i16, Promote);
533 AddPromotedToType(ISD::LOAD, MVT::v2i16, MVT::i32);
534 setOperationAction(ISD::LOAD, MVT::v2f16, Promote);
535 AddPromotedToType(ISD::LOAD, MVT::v2f16, MVT::i32);
536
537 setOperationAction(ISD::AND, MVT::v2i16, Promote);
538 AddPromotedToType(ISD::AND, MVT::v2i16, MVT::i32);
539 setOperationAction(ISD::OR, MVT::v2i16, Promote);
540 AddPromotedToType(ISD::OR, MVT::v2i16, MVT::i32);
541 setOperationAction(ISD::XOR, MVT::v2i16, Promote);
542 AddPromotedToType(ISD::XOR, MVT::v2i16, MVT::i32);
543
544 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
545 AddPromotedToType(ISD::LOAD, MVT::v4i16, MVT::v2i32);
546 setOperationAction(ISD::LOAD, MVT::v4f16, Promote);
547 AddPromotedToType(ISD::LOAD, MVT::v4f16, MVT::v2i32);
548
549 setOperationAction(ISD::STORE, MVT::v4i16, Promote);
550 AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::v2i32);
551 setOperationAction(ISD::STORE, MVT::v4f16, Promote);
552 AddPromotedToType(ISD::STORE, MVT::v4f16, MVT::v2i32);
553
554 setOperationAction(ISD::ANY_EXTEND, MVT::v2i32, Expand);
555 setOperationAction(ISD::ZERO_EXTEND, MVT::v2i32, Expand);
556 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i32, Expand);
557 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Expand);
558
559 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Expand);
560 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i32, Expand);
561 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Expand);
562
563 if (!Subtarget->hasVOP3PInsts()) {
564 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i16, Custom);
565 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f16, Custom);
566 }
567
568 setOperationAction(ISD::FNEG, MVT::v2f16, Legal);
569 // This isn't really legal, but this avoids the legalizer unrolling it (and
570 // allows matching fneg (fabs x) patterns)
571 setOperationAction(ISD::FABS, MVT::v2f16, Legal);
572
573 setOperationAction(ISD::FMAXNUM, MVT::f16, Custom);
574 setOperationAction(ISD::FMINNUM, MVT::f16, Custom);
575 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f16, Legal);
576 setOperationAction(ISD::FMINNUM_IEEE, MVT::f16, Legal);
577
578 setOperationAction(ISD::FMINNUM_IEEE, MVT::v4f16, Custom);
579 setOperationAction(ISD::FMAXNUM_IEEE, MVT::v4f16, Custom);
580
581 setOperationAction(ISD::FMINNUM, MVT::v4f16, Expand);
582 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Expand);
583 }
584
585 if (Subtarget->hasVOP3PInsts()) {
586 setOperationAction(ISD::ADD, MVT::v2i16, Legal);
587 setOperationAction(ISD::SUB, MVT::v2i16, Legal);
588 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
589 setOperationAction(ISD::SHL, MVT::v2i16, Legal);
590 setOperationAction(ISD::SRL, MVT::v2i16, Legal);
591 setOperationAction(ISD::SRA, MVT::v2i16, Legal);
592 setOperationAction(ISD::SMIN, MVT::v2i16, Legal);
593 setOperationAction(ISD::UMIN, MVT::v2i16, Legal);
594 setOperationAction(ISD::SMAX, MVT::v2i16, Legal);
595 setOperationAction(ISD::UMAX, MVT::v2i16, Legal);
596
597 setOperationAction(ISD::FADD, MVT::v2f16, Legal);
598 setOperationAction(ISD::FMUL, MVT::v2f16, Legal);
599 setOperationAction(ISD::FMA, MVT::v2f16, Legal);
600
601 setOperationAction(ISD::FMINNUM_IEEE, MVT::v2f16, Legal);
602 setOperationAction(ISD::FMAXNUM_IEEE, MVT::v2f16, Legal);
603
604 setOperationAction(ISD::FCANONICALIZE, MVT::v2f16, Legal);
605
606 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom);
607 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom);
608
609 setOperationAction(ISD::SHL, MVT::v4i16, Custom);
610 setOperationAction(ISD::SRA, MVT::v4i16, Custom);
611 setOperationAction(ISD::SRL, MVT::v4i16, Custom);
612 setOperationAction(ISD::ADD, MVT::v4i16, Custom);
613 setOperationAction(ISD::SUB, MVT::v4i16, Custom);
614 setOperationAction(ISD::MUL, MVT::v4i16, Custom);
615
616 setOperationAction(ISD::SMIN, MVT::v4i16, Custom);
617 setOperationAction(ISD::SMAX, MVT::v4i16, Custom);
618 setOperationAction(ISD::UMIN, MVT::v4i16, Custom);
619 setOperationAction(ISD::UMAX, MVT::v4i16, Custom);
620
621 setOperationAction(ISD::FADD, MVT::v4f16, Custom);
622 setOperationAction(ISD::FMUL, MVT::v4f16, Custom);
623
624 setOperationAction(ISD::FMAXNUM, MVT::v2f16, Custom);
625 setOperationAction(ISD::FMINNUM, MVT::v2f16, Custom);
626
627 setOperationAction(ISD::FMINNUM, MVT::v4f16, Custom);
628 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Custom);
629 setOperationAction(ISD::FCANONICALIZE, MVT::v4f16, Custom);
630
631 setOperationAction(ISD::FEXP, MVT::v2f16, Custom);
632 setOperationAction(ISD::SELECT, MVT::v4i16, Custom);
633 setOperationAction(ISD::SELECT, MVT::v4f16, Custom);
634 }
635
636 setOperationAction(ISD::FNEG, MVT::v4f16, Custom);
637 setOperationAction(ISD::FABS, MVT::v4f16, Custom);
638
639 if (Subtarget->has16BitInsts()) {
640 setOperationAction(ISD::SELECT, MVT::v2i16, Promote);
641 AddPromotedToType(ISD::SELECT, MVT::v2i16, MVT::i32);
642 setOperationAction(ISD::SELECT, MVT::v2f16, Promote);
643 AddPromotedToType(ISD::SELECT, MVT::v2f16, MVT::i32);
644 } else {
645 // Legalization hack.
646 setOperationAction(ISD::SELECT, MVT::v2i16, Custom);
647 setOperationAction(ISD::SELECT, MVT::v2f16, Custom);
648
649 setOperationAction(ISD::FNEG, MVT::v2f16, Custom);
650 setOperationAction(ISD::FABS, MVT::v2f16, Custom);
651 }
652
653 for (MVT VT : { MVT::v4i16, MVT::v4f16, MVT::v2i8, MVT::v4i8, MVT::v8i8 }) {
654 setOperationAction(ISD::SELECT, VT, Custom);
655 }
656
657 setTargetDAGCombine(ISD::ADD);
658 setTargetDAGCombine(ISD::ADDCARRY);
659 setTargetDAGCombine(ISD::SUB);
660 setTargetDAGCombine(ISD::SUBCARRY);
661 setTargetDAGCombine(ISD::FADD);
662 setTargetDAGCombine(ISD::FSUB);
663 setTargetDAGCombine(ISD::FMINNUM);
664 setTargetDAGCombine(ISD::FMAXNUM);
665 setTargetDAGCombine(ISD::FMINNUM_IEEE);
666 setTargetDAGCombine(ISD::FMAXNUM_IEEE);
667 setTargetDAGCombine(ISD::FMA);
668 setTargetDAGCombine(ISD::SMIN);
669 setTargetDAGCombine(ISD::SMAX);
670 setTargetDAGCombine(ISD::UMIN);
671 setTargetDAGCombine(ISD::UMAX);
672 setTargetDAGCombine(ISD::SETCC);
673 setTargetDAGCombine(ISD::AND);
674 setTargetDAGCombine(ISD::OR);
675 setTargetDAGCombine(ISD::XOR);
676 setTargetDAGCombine(ISD::SINT_TO_FP);
677 setTargetDAGCombine(ISD::UINT_TO_FP);
678 setTargetDAGCombine(ISD::FCANONICALIZE);
679 setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
680 setTargetDAGCombine(ISD::ZERO_EXTEND);
681 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
682 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
683
684 // All memory operations. Some folding on the pointer operand is done to help
685 // matching the constant offsets in the addressing modes.
686 setTargetDAGCombine(ISD::LOAD);
687 setTargetDAGCombine(ISD::STORE);
688 setTargetDAGCombine(ISD::ATOMIC_LOAD);
689 setTargetDAGCombine(ISD::ATOMIC_STORE);
690 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP);
691 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
692 setTargetDAGCombine(ISD::ATOMIC_SWAP);
693 setTargetDAGCombine(ISD::ATOMIC_LOAD_ADD);
694 setTargetDAGCombine(ISD::ATOMIC_LOAD_SUB);
695 setTargetDAGCombine(ISD::ATOMIC_LOAD_AND);
696 setTargetDAGCombine(ISD::ATOMIC_LOAD_OR);
697 setTargetDAGCombine(ISD::ATOMIC_LOAD_XOR);
698 setTargetDAGCombine(ISD::ATOMIC_LOAD_NAND);
699 setTargetDAGCombine(ISD::ATOMIC_LOAD_MIN);
700 setTargetDAGCombine(ISD::ATOMIC_LOAD_MAX);
701 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMIN);
702 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMAX);
703
704 setSchedulingPreference(Sched::RegPressure);
705
706 // SI at least has hardware support for floating point exceptions, but no way
707 // of using or handling them is implemented. They are also optional in OpenCL
708 // (Section 7.3)
709 setHasFloatingPointExceptions(Subtarget->hasFPExceptions());
710}
711
712const GCNSubtarget *SITargetLowering::getSubtarget() const {
713 return Subtarget;
714}
715
716//===----------------------------------------------------------------------===//
717// TargetLowering queries
718//===----------------------------------------------------------------------===//
719
720// v_mad_mix* support a conversion from f16 to f32.
721//
722// There is only one special case when denormals are enabled we don't currently,
723// where this is OK to use.
724bool SITargetLowering::isFPExtFoldable(unsigned Opcode,
725 EVT DestVT, EVT SrcVT) const {
726 return ((Opcode == ISD::FMAD && Subtarget->hasMadMixInsts()) ||
727 (Opcode == ISD::FMA && Subtarget->hasFmaMixInsts())) &&
728 DestVT.getScalarType() == MVT::f32 && !Subtarget->hasFP32Denormals() &&
729 SrcVT.getScalarType() == MVT::f16;
730}
731
732bool SITargetLowering::isShuffleMaskLegal(ArrayRef<int>, EVT) const {
733 // SI has some legal vector types, but no legal vector operations. Say no
734 // shuffles are legal in order to prefer scalarizing some vector operations.
735 return false;
736}
737
738MVT SITargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
739 CallingConv::ID CC,
740 EVT VT) const {
741 // TODO: Consider splitting all arguments into 32-bit pieces.
742 if (CC != CallingConv::AMDGPU_KERNEL && VT.isVector()) {
743 EVT ScalarVT = VT.getScalarType();
744 unsigned Size = ScalarVT.getSizeInBits();
745 if (Size == 32)
746 return ScalarVT.getSimpleVT();
747
748 if (Size == 64)
749 return MVT::i32;
750
751 if (Size == 16 && Subtarget->has16BitInsts())
752 return VT.isInteger() ? MVT::v2i16 : MVT::v2f16;
753 }
754
755 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
756}
757
758unsigned SITargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
759 CallingConv::ID CC,
760 EVT VT) const {
761 if (CC != CallingConv::AMDGPU_KERNEL && VT.isVector()) {
762 unsigned NumElts = VT.getVectorNumElements();
763 EVT ScalarVT = VT.getScalarType();
764 unsigned Size = ScalarVT.getSizeInBits();
765
766 if (Size == 32)
767 return NumElts;
768
769 if (Size == 64)
770 return 2 * NumElts;
771
772 if (Size == 16 && Subtarget->has16BitInsts())
773 return (VT.getVectorNumElements() + 1) / 2;
774 }
775
776 return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
777}
778
779unsigned SITargetLowering::getVectorTypeBreakdownForCallingConv(
780 LLVMContext &Context, CallingConv::ID CC,
781 EVT VT, EVT &IntermediateVT,
782 unsigned &NumIntermediates, MVT &RegisterVT) const {
783 if (CC != CallingConv::AMDGPU_KERNEL && VT.isVector()) {
784 unsigned NumElts = VT.getVectorNumElements();
785 EVT ScalarVT = VT.getScalarType();
786 unsigned Size = ScalarVT.getSizeInBits();
787 if (Size == 32) {
788 RegisterVT = ScalarVT.getSimpleVT();
789 IntermediateVT = RegisterVT;
790 NumIntermediates = NumElts;
791 return NumIntermediates;
792 }
793
794 if (Size == 64) {
795 RegisterVT = MVT::i32;
796 IntermediateVT = RegisterVT;
797 NumIntermediates = 2 * NumElts;
798 return NumIntermediates;
799 }
800
801 // FIXME: We should fix the ABI to be the same on targets without 16-bit
802 // support, but unless we can properly handle 3-vectors, it will be still be
803 // inconsistent.
804 if (Size == 16 && Subtarget->has16BitInsts()) {
805 RegisterVT = VT.isInteger() ? MVT::v2i16 : MVT::v2f16;
806 IntermediateVT = RegisterVT;
807 NumIntermediates = (NumElts + 1) / 2;
808 return NumIntermediates;
809 }
810 }
811
812 return TargetLowering::getVectorTypeBreakdownForCallingConv(
813 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
814}
815
816bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
817 const CallInst &CI,
818 MachineFunction &MF,
819 unsigned IntrID) const {
820 if (const AMDGPU::RsrcIntrinsic *RsrcIntr =
821 AMDGPU::lookupRsrcIntrinsic(IntrID)) {
822 AttributeList Attr = Intrinsic::getAttributes(CI.getContext(),
823 (Intrinsic::ID)IntrID);
824 if (Attr.hasFnAttribute(Attribute::ReadNone))
825 return false;
826
827 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
828
829 if (RsrcIntr->IsImage) {
830 Info.ptrVal = MFI->getImagePSV(
831 *MF.getSubtarget<GCNSubtarget>().getInstrInfo(),
832 CI.getArgOperand(RsrcIntr->RsrcArg));
833 Info.align = 0;
834 } else {
835 Info.ptrVal = MFI->getBufferPSV(
836 *MF.getSubtarget<GCNSubtarget>().getInstrInfo(),
837 CI.getArgOperand(RsrcIntr->RsrcArg));
838 }
839
840 Info.flags = MachineMemOperand::MODereferenceable;
841 if (Attr.hasFnAttribute(Attribute::ReadOnly)) {
842 Info.opc = ISD::INTRINSIC_W_CHAIN;
843 Info.memVT = MVT::getVT(CI.getType());
844 Info.flags |= MachineMemOperand::MOLoad;
845 } else if (Attr.hasFnAttribute(Attribute::WriteOnly)) {
846 Info.opc = ISD::INTRINSIC_VOID;
847 Info.memVT = MVT::getVT(CI.getArgOperand(0)->getType());
848 Info.flags |= MachineMemOperand::MOStore;
849 } else {
850 // Atomic
851 Info.opc = ISD::INTRINSIC_W_CHAIN;
852 Info.memVT = MVT::getVT(CI.getType());
853 Info.flags = MachineMemOperand::MOLoad |
854 MachineMemOperand::MOStore |
855 MachineMemOperand::MODereferenceable;
856
857 // XXX - Should this be volatile without known ordering?
858 Info.flags |= MachineMemOperand::MOVolatile;
859 }
860 return true;
861 }
862
863 switch (IntrID) {
864 case Intrinsic::amdgcn_atomic_inc:
865 case Intrinsic::amdgcn_atomic_dec:
866 case Intrinsic::amdgcn_ds_fadd:
867 case Intrinsic::amdgcn_ds_fmin:
868 case Intrinsic::amdgcn_ds_fmax: {
869 Info.opc = ISD::INTRINSIC_W_CHAIN;
870 Info.memVT = MVT::getVT(CI.getType());
871 Info.ptrVal = CI.getOperand(0);
872 Info.align = 0;
873 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
874
875 const ConstantInt *Vol = dyn_cast<ConstantInt>(CI.getOperand(4));
876 if (!Vol || !Vol->isZero())
877 Info.flags |= MachineMemOperand::MOVolatile;
878
879 return true;
880 }
881
882 default:
883 return false;
884 }
885}
886
887bool SITargetLowering::getAddrModeArguments(IntrinsicInst *II,
888 SmallVectorImpl<Value*> &Ops,
889 Type *&AccessTy) const {
890 switch (II->getIntrinsicID()) {
891 case Intrinsic::amdgcn_atomic_inc:
892 case Intrinsic::amdgcn_atomic_dec:
893 case Intrinsic::amdgcn_ds_fadd:
894 case Intrinsic::amdgcn_ds_fmin:
895 case Intrinsic::amdgcn_ds_fmax: {
896 Value *Ptr = II->getArgOperand(0);
897 AccessTy = II->getType();
898 Ops.push_back(Ptr);
899 return true;
900 }
901 default:
902 return false;
903 }
904}
905
906bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {
907 if (!Subtarget->hasFlatInstOffsets()) {
908 // Flat instructions do not have offsets, and only have the register
909 // address.
910 return AM.BaseOffs == 0 && AM.Scale == 0;
911 }
912
913 // GFX9 added a 13-bit signed offset. When using regular flat instructions,
914 // the sign bit is ignored and is treated as a 12-bit unsigned offset.
915
916 // Just r + i
917 return isUInt<12>(AM.BaseOffs) && AM.Scale == 0;
918}
919
920bool SITargetLowering::isLegalGlobalAddressingMode(const AddrMode &AM) const {
921 if (Subtarget->hasFlatGlobalInsts())
922 return isInt<13>(AM.BaseOffs) && AM.Scale == 0;
923
924 if (!Subtarget->hasAddr64() || Subtarget->useFlatForGlobal()) {
925 // Assume the we will use FLAT for all global memory accesses
926 // on VI.
927 // FIXME: This assumption is currently wrong. On VI we still use
928 // MUBUF instructions for the r + i addressing mode. As currently
929 // implemented, the MUBUF instructions only work on buffer < 4GB.
930 // It may be possible to support > 4GB buffers with MUBUF instructions,
931 // by setting the stride value in the resource descriptor which would
932 // increase the size limit to (stride * 4GB). However, this is risky,
933 // because it has never been validated.
934 return isLegalFlatAddressingMode(AM);
935 }
936
937 return isLegalMUBUFAddressingMode(AM);
938}
939
940bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {
941 // MUBUF / MTBUF instructions have a 12-bit unsigned byte offset, and
942 // additionally can do r + r + i with addr64. 32-bit has more addressing
943 // mode options. Depending on the resource constant, it can also do
944 // (i64 r0) + (i32 r1) * (i14 i).
945 //
946 // Private arrays end up using a scratch buffer most of the time, so also
947 // assume those use MUBUF instructions. Scratch loads / stores are currently
948 // implemented as mubuf instructions with offen bit set, so slightly
949 // different than the normal addr64.
950 if (!isUInt<12>(AM.BaseOffs))
951 return false;
952
953 // FIXME: Since we can split immediate into soffset and immediate offset,
954 // would it make sense to allow any immediate?
955
956 switch (AM.Scale) {
957 case 0: // r + i or just i, depending on HasBaseReg.
958 return true;
959 case 1:
960 return true; // We have r + r or r + i.
961 case 2:
962 if (AM.HasBaseReg) {
963 // Reject 2 * r + r.
964 return false;
965 }
966
967 // Allow 2 * r as r + r
968 // Or 2 * r + i is allowed as r + r + i.
969 return true;
970 default: // Don't allow n * r
971 return false;
972 }
973}
974
975bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
976 const AddrMode &AM, Type *Ty,
977 unsigned AS, Instruction *I) const {
978 // No global is ever allowed as a base.
979 if (AM.BaseGV)
980 return false;
981
982 if (AS == AMDGPUAS::GLOBAL_ADDRESS)
983 return isLegalGlobalAddressingMode(AM);
984
985 if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
986 AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT) {
987 // If the offset isn't a multiple of 4, it probably isn't going to be
988 // correctly aligned.
989 // FIXME: Can we get the real alignment here?
990 if (AM.BaseOffs % 4 != 0)
991 return isLegalMUBUFAddressingMode(AM);
992
993 // There are no SMRD extloads, so if we have to do a small type access we
994 // will use a MUBUF load.
995 // FIXME?: We also need to do this if unaligned, but we don't know the
996 // alignment here.
997 if (Ty->isSized() && DL.getTypeStoreSize(Ty) < 4)
998 return isLegalGlobalAddressingMode(AM);
999
1000 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) {
1001 // SMRD instructions have an 8-bit, dword offset on SI.
1002 if (!isUInt<8>(AM.BaseOffs / 4))
1003 return false;
1004 } else if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS) {
1005 // On CI+, this can also be a 32-bit literal constant offset. If it fits
1006 // in 8-bits, it can use a smaller encoding.
1007 if (!isUInt<32>(AM.BaseOffs / 4))
1008 return false;
1009 } else if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
1010 // On VI, these use the SMEM format and the offset is 20-bit in bytes.
1011 if (!isUInt<20>(AM.BaseOffs))
1012 return false;
1013 } else
1014 llvm_unreachable("unhandled generation")::llvm::llvm_unreachable_internal("unhandled generation", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1014)
;
1015
1016 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
1017 return true;
1018
1019 if (AM.Scale == 1 && AM.HasBaseReg)
1020 return true;
1021
1022 return false;
1023
1024 } else if (AS == AMDGPUAS::PRIVATE_ADDRESS) {
1025 return isLegalMUBUFAddressingMode(AM);
1026 } else if (AS == AMDGPUAS::LOCAL_ADDRESS ||
1027 AS == AMDGPUAS::REGION_ADDRESS) {
1028 // Basic, single offset DS instructions allow a 16-bit unsigned immediate
1029 // field.
1030 // XXX - If doing a 4-byte aligned 8-byte type access, we effectively have
1031 // an 8-bit dword offset but we don't know the alignment here.
1032 if (!isUInt<16>(AM.BaseOffs))
1033 return false;
1034
1035 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
1036 return true;
1037
1038 if (AM.Scale == 1 && AM.HasBaseReg)
1039 return true;
1040
1041 return false;
1042 } else if (AS == AMDGPUAS::FLAT_ADDRESS ||
1043 AS == AMDGPUAS::UNKNOWN_ADDRESS_SPACE) {
1044 // For an unknown address space, this usually means that this is for some
1045 // reason being used for pure arithmetic, and not based on some addressing
1046 // computation. We don't have instructions that compute pointers with any
1047 // addressing modes, so treat them as having no offset like flat
1048 // instructions.
1049 return isLegalFlatAddressingMode(AM);
1050 } else {
1051 llvm_unreachable("unhandled address space")::llvm::llvm_unreachable_internal("unhandled address space", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1051)
;
1052 }
1053}
1054
1055bool SITargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT,
1056 const SelectionDAG &DAG) const {
1057 if (AS == AMDGPUAS::GLOBAL_ADDRESS || AS == AMDGPUAS::FLAT_ADDRESS) {
1058 return (MemVT.getSizeInBits() <= 4 * 32);
1059 } else if (AS == AMDGPUAS::PRIVATE_ADDRESS) {
1060 unsigned MaxPrivateBits = 8 * getSubtarget()->getMaxPrivateElementSize();
1061 return (MemVT.getSizeInBits() <= MaxPrivateBits);
1062 } else if (AS == AMDGPUAS::LOCAL_ADDRESS) {
1063 return (MemVT.getSizeInBits() <= 2 * 32);
1064 }
1065 return true;
1066}
1067
1068bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1069 unsigned AddrSpace,
1070 unsigned Align,
1071 bool *IsFast) const {
1072 if (IsFast)
1073 *IsFast = false;
1074
1075 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
1076 // which isn't a simple VT.
1077 // Until MVT is extended to handle this, simply check for the size and
1078 // rely on the condition below: allow accesses if the size is a multiple of 4.
1079 if (VT == MVT::Other || (VT != MVT::Other && VT.getSizeInBits() > 1024 &&
1080 VT.getStoreSize() > 16)) {
1081 return false;
1082 }
1083
1084 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
1085 AddrSpace == AMDGPUAS::REGION_ADDRESS) {
1086 // ds_read/write_b64 require 8-byte alignment, but we can do a 4 byte
1087 // aligned, 8 byte access in a single operation using ds_read2/write2_b32
1088 // with adjacent offsets.
1089 bool AlignedBy4 = (Align % 4 == 0);
1090 if (IsFast)
1091 *IsFast = AlignedBy4;
1092
1093 return AlignedBy4;
1094 }
1095
1096 // FIXME: We have to be conservative here and assume that flat operations
1097 // will access scratch. If we had access to the IR function, then we
1098 // could determine if any private memory was used in the function.
1099 if (!Subtarget->hasUnalignedScratchAccess() &&
1100 (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
1101 AddrSpace == AMDGPUAS::FLAT_ADDRESS)) {
1102 bool AlignedBy4 = Align >= 4;
1103 if (IsFast)
1104 *IsFast = AlignedBy4;
1105
1106 return AlignedBy4;
1107 }
1108
1109 if (Subtarget->hasUnalignedBufferAccess()) {
1110 // If we have an uniform constant load, it still requires using a slow
1111 // buffer instruction if unaligned.
1112 if (IsFast) {
1113 *IsFast = (AddrSpace == AMDGPUAS::CONSTANT_ADDRESS ||
1114 AddrSpace == AMDGPUAS::CONSTANT_ADDRESS_32BIT) ?
1115 (Align % 4 == 0) : true;
1116 }
1117
1118 return true;
1119 }
1120
1121 // Smaller than dword value must be aligned.
1122 if (VT.bitsLT(MVT::i32))
1123 return false;
1124
1125 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
1126 // byte-address are ignored, thus forcing Dword alignment.
1127 // This applies to private, global, and constant memory.
1128 if (IsFast)
1129 *IsFast = true;
1130
1131 return VT.bitsGT(MVT::i32) && Align % 4 == 0;
1132}
1133
1134EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
1135 unsigned SrcAlign, bool IsMemset,
1136 bool ZeroMemset,
1137 bool MemcpyStrSrc,
1138 MachineFunction &MF) const {
1139 // FIXME: Should account for address space here.
1140
1141 // The default fallback uses the private pointer size as a guess for a type to
1142 // use. Make sure we switch these to 64-bit accesses.
1143
1144 if (Size >= 16 && DstAlign >= 4) // XXX: Should only do for global
1145 return MVT::v4i32;
1146
1147 if (Size >= 8 && DstAlign >= 4)
1148 return MVT::v2i32;
1149
1150 // Use the default.
1151 return MVT::Other;
1152}
1153
1154static bool isFlatGlobalAddrSpace(unsigned AS) {
1155 return AS == AMDGPUAS::GLOBAL_ADDRESS ||
1156 AS == AMDGPUAS::FLAT_ADDRESS ||
1157 AS == AMDGPUAS::CONSTANT_ADDRESS;
1158}
1159
1160bool SITargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1161 unsigned DestAS) const {
1162 return isFlatGlobalAddrSpace(SrcAS) && isFlatGlobalAddrSpace(DestAS);
1163}
1164
1165bool SITargetLowering::isMemOpHasNoClobberedMemOperand(const SDNode *N) const {
1166 const MemSDNode *MemNode = cast<MemSDNode>(N);
1167 const Value *Ptr = MemNode->getMemOperand()->getValue();
1168 const Instruction *I = dyn_cast_or_null<Instruction>(Ptr);
1169 return I && I->getMetadata("amdgpu.noclobber");
1170}
1171
1172bool SITargetLowering::isCheapAddrSpaceCast(unsigned SrcAS,
1173 unsigned DestAS) const {
1174 // Flat -> private/local is a simple truncate.
1175 // Flat -> global is no-op
1176 if (SrcAS == AMDGPUAS::FLAT_ADDRESS)
1177 return true;
1178
1179 return isNoopAddrSpaceCast(SrcAS, DestAS);
1180}
1181
1182bool SITargetLowering::isMemOpUniform(const SDNode *N) const {
1183 const MemSDNode *MemNode = cast<MemSDNode>(N);
1184
1185 return AMDGPUInstrInfo::isUniformMMO(MemNode->getMemOperand());
1186}
1187
1188TargetLoweringBase::LegalizeTypeAction
1189SITargetLowering::getPreferredVectorAction(MVT VT) const {
1190 if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16))
1191 return TypeSplitVector;
1192
1193 return TargetLoweringBase::getPreferredVectorAction(VT);
1194}
1195
1196bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
1197 Type *Ty) const {
1198 // FIXME: Could be smarter if called for vector constants.
1199 return true;
1200}
1201
1202bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {
1203 if (Subtarget->has16BitInsts() && VT == MVT::i16) {
1204 switch (Op) {
1205 case ISD::LOAD:
1206 case ISD::STORE:
1207
1208 // These operations are done with 32-bit instructions anyway.
1209 case ISD::AND:
1210 case ISD::OR:
1211 case ISD::XOR:
1212 case ISD::SELECT:
1213 // TODO: Extensions?
1214 return true;
1215 default:
1216 return false;
1217 }
1218 }
1219
1220 // SimplifySetCC uses this function to determine whether or not it should
1221 // create setcc with i1 operands. We don't have instructions for i1 setcc.
1222 if (VT == MVT::i1 && Op == ISD::SETCC)
1223 return false;
1224
1225 return TargetLowering::isTypeDesirableForOp(Op, VT);
1226}
1227
1228SDValue SITargetLowering::lowerKernArgParameterPtr(SelectionDAG &DAG,
1229 const SDLoc &SL,
1230 SDValue Chain,
1231 uint64_t Offset) const {
1232 const DataLayout &DL = DAG.getDataLayout();
1233 MachineFunction &MF = DAG.getMachineFunction();
1234 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
1235
1236 const ArgDescriptor *InputPtrReg;
1237 const TargetRegisterClass *RC;
1238
1239 std::tie(InputPtrReg, RC)
1240 = Info->getPreloadedValue(AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR);
1241
1242 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1243 MVT PtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
1244 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
1245 MRI.getLiveInVirtReg(InputPtrReg->getRegister()), PtrVT);
1246
1247 return DAG.getObjectPtrOffset(SL, BasePtr, Offset);
1248}
1249
1250SDValue SITargetLowering::getImplicitArgPtr(SelectionDAG &DAG,
1251 const SDLoc &SL) const {
1252 uint64_t Offset = getImplicitParameterOffset(DAG.getMachineFunction(),
1253 FIRST_IMPLICIT);
1254 return lowerKernArgParameterPtr(DAG, SL, DAG.getEntryNode(), Offset);
1255}
1256
1257SDValue SITargetLowering::convertArgType(SelectionDAG &DAG, EVT VT, EVT MemVT,
1258 const SDLoc &SL, SDValue Val,
1259 bool Signed,
1260 const ISD::InputArg *Arg) const {
1261 if (Arg && (Arg->Flags.isSExt() || Arg->Flags.isZExt()) &&
1262 VT.bitsLT(MemVT)) {
1263 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext;
1264 Val = DAG.getNode(Opc, SL, MemVT, Val, DAG.getValueType(VT));
1265 }
1266
1267 if (MemVT.isFloatingPoint())
1268 Val = getFPExtOrFPTrunc(DAG, Val, SL, VT);
1269 else if (Signed)
1270 Val = DAG.getSExtOrTrunc(Val, SL, VT);
1271 else
1272 Val = DAG.getZExtOrTrunc(Val, SL, VT);
1273
1274 return Val;
1275}
1276
1277SDValue SITargetLowering::lowerKernargMemParameter(
1278 SelectionDAG &DAG, EVT VT, EVT MemVT,
1279 const SDLoc &SL, SDValue Chain,
1280 uint64_t Offset, unsigned Align, bool Signed,
1281 const ISD::InputArg *Arg) const {
1282 Type *Ty = MemVT.getTypeForEVT(*DAG.getContext());
1283 PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
1284 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
1285
1286 // Try to avoid using an extload by loading earlier than the argument address,
1287 // and extracting the relevant bits. The load should hopefully be merged with
1288 // the previous argument.
1289 if (MemVT.getStoreSize() < 4 && Align < 4) {
1290 // TODO: Handle align < 4 and size >= 4 (can happen with packed structs).
1291 int64_t AlignDownOffset = alignDown(Offset, 4);
1292 int64_t OffsetDiff = Offset - AlignDownOffset;
1293
1294 EVT IntVT = MemVT.changeTypeToInteger();
1295
1296 // TODO: If we passed in the base kernel offset we could have a better
1297 // alignment than 4, but we don't really need it.
1298 SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, AlignDownOffset);
1299 SDValue Load = DAG.getLoad(MVT::i32, SL, Chain, Ptr, PtrInfo, 4,
1300 MachineMemOperand::MODereferenceable |
1301 MachineMemOperand::MOInvariant);
1302
1303 SDValue ShiftAmt = DAG.getConstant(OffsetDiff * 8, SL, MVT::i32);
1304 SDValue Extract = DAG.getNode(ISD::SRL, SL, MVT::i32, Load, ShiftAmt);
1305
1306 SDValue ArgVal = DAG.getNode(ISD::TRUNCATE, SL, IntVT, Extract);
1307 ArgVal = DAG.getNode(ISD::BITCAST, SL, MemVT, ArgVal);
1308 ArgVal = convertArgType(DAG, VT, MemVT, SL, ArgVal, Signed, Arg);
1309
1310
1311 return DAG.getMergeValues({ ArgVal, Load.getValue(1) }, SL);
1312 }
1313
1314 SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, Offset);
1315 SDValue Load = DAG.getLoad(MemVT, SL, Chain, Ptr, PtrInfo, Align,
1316 MachineMemOperand::MODereferenceable |
1317 MachineMemOperand::MOInvariant);
1318
1319 SDValue Val = convertArgType(DAG, VT, MemVT, SL, Load, Signed, Arg);
1320 return DAG.getMergeValues({ Val, Load.getValue(1) }, SL);
1321}
1322
1323SDValue SITargetLowering::lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
1324 const SDLoc &SL, SDValue Chain,
1325 const ISD::InputArg &Arg) const {
1326 MachineFunction &MF = DAG.getMachineFunction();
1327 MachineFrameInfo &MFI = MF.getFrameInfo();
1328
1329 if (Arg.Flags.isByVal()) {
1330 unsigned Size = Arg.Flags.getByValSize();
1331 int FrameIdx = MFI.CreateFixedObject(Size, VA.getLocMemOffset(), false);
1332 return DAG.getFrameIndex(FrameIdx, MVT::i32);
1333 }
1334
1335 unsigned ArgOffset = VA.getLocMemOffset();
1336 unsigned ArgSize = VA.getValVT().getStoreSize();
1337
1338 int FI = MFI.CreateFixedObject(ArgSize, ArgOffset, true);
1339
1340 // Create load nodes to retrieve arguments from the stack.
1341 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1342 SDValue ArgValue;
1343
1344 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
1345 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
1346 MVT MemVT = VA.getValVT();
1347
1348 switch (VA.getLocInfo()) {
1349 default:
1350 break;
1351 case CCValAssign::BCvt:
1352 MemVT = VA.getLocVT();
1353 break;
1354 case CCValAssign::SExt:
1355 ExtType = ISD::SEXTLOAD;
1356 break;
1357 case CCValAssign::ZExt:
1358 ExtType = ISD::ZEXTLOAD;
1359 break;
1360 case CCValAssign::AExt:
1361 ExtType = ISD::EXTLOAD;
1362 break;
1363 }
1364
1365 ArgValue = DAG.getExtLoad(
1366 ExtType, SL, VA.getLocVT(), Chain, FIN,
1367 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
1368 MemVT);
1369 return ArgValue;
1370}
1371
1372SDValue SITargetLowering::getPreloadedValue(SelectionDAG &DAG,
1373 const SIMachineFunctionInfo &MFI,
1374 EVT VT,
1375 AMDGPUFunctionArgInfo::PreloadedValue PVID) const {
1376 const ArgDescriptor *Reg;
1377 const TargetRegisterClass *RC;
1378
1379 std::tie(Reg, RC) = MFI.getPreloadedValue(PVID);
1380 return CreateLiveInRegister(DAG, RC, Reg->getRegister(), VT);
1381}
1382
1383static void processShaderInputArgs(SmallVectorImpl<ISD::InputArg> &Splits,
1384 CallingConv::ID CallConv,
1385 ArrayRef<ISD::InputArg> Ins,
1386 BitVector &Skipped,
1387 FunctionType *FType,
1388 SIMachineFunctionInfo *Info) {
1389 for (unsigned I = 0, E = Ins.size(), PSInputNum = 0; I != E; ++I) {
1390 const ISD::InputArg *Arg = &Ins[I];
1391
1392 assert((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) &&(((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits()
== 16) && "vector type argument should have been split"
) ? static_cast<void> (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"vector type argument should have been split\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1393, __PRETTY_FUNCTION__))
1393 "vector type argument should have been split")(((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits()
== 16) && "vector type argument should have been split"
) ? static_cast<void> (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"vector type argument should have been split\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1393, __PRETTY_FUNCTION__))
;
1394
1395 // First check if it's a PS input addr.
1396 if (CallConv == CallingConv::AMDGPU_PS &&
1397 !Arg->Flags.isInReg() && !Arg->Flags.isByVal() && PSInputNum <= 15) {
1398
1399 bool SkipArg = !Arg->Used && !Info->isPSInputAllocated(PSInputNum);
1400
1401 // Inconveniently only the first part of the split is marked as isSplit,
1402 // so skip to the end. We only want to increment PSInputNum once for the
1403 // entire split argument.
1404 if (Arg->Flags.isSplit()) {
1405 while (!Arg->Flags.isSplitEnd()) {
1406 assert(!Arg->VT.isVector() &&((!Arg->VT.isVector() && "unexpected vector split in ps argument type"
) ? static_cast<void> (0) : __assert_fail ("!Arg->VT.isVector() && \"unexpected vector split in ps argument type\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1407, __PRETTY_FUNCTION__))
1407 "unexpected vector split in ps argument type")((!Arg->VT.isVector() && "unexpected vector split in ps argument type"
) ? static_cast<void> (0) : __assert_fail ("!Arg->VT.isVector() && \"unexpected vector split in ps argument type\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1407, __PRETTY_FUNCTION__))
;
1408 if (!SkipArg)
1409 Splits.push_back(*Arg);
1410 Arg = &Ins[++I];
1411 }
1412 }
1413
1414 if (SkipArg) {
1415 // We can safely skip PS inputs.
1416 Skipped.set(Arg->getOrigArgIndex());
1417 ++PSInputNum;
1418 continue;
1419 }
1420
1421 Info->markPSInputAllocated(PSInputNum);
1422 if (Arg->Used)
1423 Info->markPSInputEnabled(PSInputNum);
1424
1425 ++PSInputNum;
1426 }
1427
1428 Splits.push_back(*Arg);
1429 }
1430}
1431
1432// Allocate special inputs passed in VGPRs.
1433static void allocateSpecialEntryInputVGPRs(CCState &CCInfo,
1434 MachineFunction &MF,
1435 const SIRegisterInfo &TRI,
1436 SIMachineFunctionInfo &Info) {
1437 if (Info.hasWorkItemIDX()) {
1438 unsigned Reg = AMDGPU::VGPR0;
1439 MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
1440
1441 CCInfo.AllocateReg(Reg);
1442 Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg));
1443 }
1444
1445 if (Info.hasWorkItemIDY()) {
1446 unsigned Reg = AMDGPU::VGPR1;
1447 MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
1448
1449 CCInfo.AllocateReg(Reg);
1450 Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg));
1451 }
1452
1453 if (Info.hasWorkItemIDZ()) {
1454 unsigned Reg = AMDGPU::VGPR2;
1455 MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
1456
1457 CCInfo.AllocateReg(Reg);
1458 Info.setWorkItemIDZ(ArgDescriptor::createRegister(Reg));
1459 }
1460}
1461
1462// Try to allocate a VGPR at the end of the argument list, or if no argument
1463// VGPRs are left allocating a stack slot.
1464static ArgDescriptor allocateVGPR32Input(CCState &CCInfo) {
1465 ArrayRef<MCPhysReg> ArgVGPRs
1466 = makeArrayRef(AMDGPU::VGPR_32RegClass.begin(), 32);
1467 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgVGPRs);
1468 if (RegIdx == ArgVGPRs.size()) {
1469 // Spill to stack required.
1470 int64_t Offset = CCInfo.AllocateStack(4, 4);
1471
1472 return ArgDescriptor::createStack(Offset);
1473 }
1474
1475 unsigned Reg = ArgVGPRs[RegIdx];
1476 Reg = CCInfo.AllocateReg(Reg);
1477 assert(Reg != AMDGPU::NoRegister)((Reg != AMDGPU::NoRegister) ? static_cast<void> (0) : __assert_fail
("Reg != AMDGPU::NoRegister", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1477, __PRETTY_FUNCTION__))
;
1478
1479 MachineFunction &MF = CCInfo.getMachineFunction();
1480 MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
1481 return ArgDescriptor::createRegister(Reg);
1482}
1483
1484static ArgDescriptor allocateSGPR32InputImpl(CCState &CCInfo,
1485 const TargetRegisterClass *RC,
1486 unsigned NumArgRegs) {
1487 ArrayRef<MCPhysReg> ArgSGPRs = makeArrayRef(RC->begin(), 32);
1488 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgSGPRs);
1489 if (RegIdx == ArgSGPRs.size())
1490 report_fatal_error("ran out of SGPRs for arguments");
1491
1492 unsigned Reg = ArgSGPRs[RegIdx];
1493 Reg = CCInfo.AllocateReg(Reg);
1494 assert(Reg != AMDGPU::NoRegister)((Reg != AMDGPU::NoRegister) ? static_cast<void> (0) : __assert_fail
("Reg != AMDGPU::NoRegister", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1494, __PRETTY_FUNCTION__))
;
1495
1496 MachineFunction &MF = CCInfo.getMachineFunction();
1497 MF.addLiveIn(Reg, RC);
1498 return ArgDescriptor::createRegister(Reg);
1499}
1500
1501static ArgDescriptor allocateSGPR32Input(CCState &CCInfo) {
1502 return allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_32RegClass, 32);
1503}
1504
1505static ArgDescriptor allocateSGPR64Input(CCState &CCInfo) {
1506 return allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_64RegClass, 16);
1507}
1508
1509static void allocateSpecialInputVGPRs(CCState &CCInfo,
1510 MachineFunction &MF,
1511 const SIRegisterInfo &TRI,
1512 SIMachineFunctionInfo &Info) {
1513 if (Info.hasWorkItemIDX())
1514 Info.setWorkItemIDX(allocateVGPR32Input(CCInfo));
1515
1516 if (Info.hasWorkItemIDY())
1517 Info.setWorkItemIDY(allocateVGPR32Input(CCInfo));
1518
1519 if (Info.hasWorkItemIDZ())
1520 Info.setWorkItemIDZ(allocateVGPR32Input(CCInfo));
1521}
1522
1523static void allocateSpecialInputSGPRs(CCState &CCInfo,
1524 MachineFunction &MF,
1525 const SIRegisterInfo &TRI,
1526 SIMachineFunctionInfo &Info) {
1527 auto &ArgInfo = Info.getArgInfo();
1528
1529 // TODO: Unify handling with private memory pointers.
1530
1531 if (Info.hasDispatchPtr())
1532 ArgInfo.DispatchPtr = allocateSGPR64Input(CCInfo);
1533
1534 if (Info.hasQueuePtr())
1535 ArgInfo.QueuePtr = allocateSGPR64Input(CCInfo);
1536
1537 if (Info.hasKernargSegmentPtr())
1538 ArgInfo.KernargSegmentPtr = allocateSGPR64Input(CCInfo);
1539
1540 if (Info.hasDispatchID())
1541 ArgInfo.DispatchID = allocateSGPR64Input(CCInfo);
1542
1543 // flat_scratch_init is not applicable for non-kernel functions.
1544
1545 if (Info.hasWorkGroupIDX())
1546 ArgInfo.WorkGroupIDX = allocateSGPR32Input(CCInfo);
1547
1548 if (Info.hasWorkGroupIDY())
1549 ArgInfo.WorkGroupIDY = allocateSGPR32Input(CCInfo);
1550
1551 if (Info.hasWorkGroupIDZ())
1552 ArgInfo.WorkGroupIDZ = allocateSGPR32Input(CCInfo);
1553
1554 if (Info.hasImplicitArgPtr())
1555 ArgInfo.ImplicitArgPtr = allocateSGPR64Input(CCInfo);
1556}
1557
1558// Allocate special inputs passed in user SGPRs.
1559static void allocateHSAUserSGPRs(CCState &CCInfo,
1560 MachineFunction &MF,
1561 const SIRegisterInfo &TRI,
1562 SIMachineFunctionInfo &Info) {
1563 if (Info.hasImplicitBufferPtr()) {
1564 unsigned ImplicitBufferPtrReg = Info.addImplicitBufferPtr(TRI);
1565 MF.addLiveIn(ImplicitBufferPtrReg, &AMDGPU::SGPR_64RegClass);
1566 CCInfo.AllocateReg(ImplicitBufferPtrReg);
1567 }
1568
1569 // FIXME: How should these inputs interact with inreg / custom SGPR inputs?
1570 if (Info.hasPrivateSegmentBuffer()) {
1571 unsigned PrivateSegmentBufferReg = Info.addPrivateSegmentBuffer(TRI);
1572 MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SGPR_128RegClass);
1573 CCInfo.AllocateReg(PrivateSegmentBufferReg);
1574 }
1575
1576 if (Info.hasDispatchPtr()) {
1577 unsigned DispatchPtrReg = Info.addDispatchPtr(TRI);
1578 MF.addLiveIn(DispatchPtrReg, &AMDGPU::SGPR_64RegClass);
1579 CCInfo.AllocateReg(DispatchPtrReg);
1580 }
1581
1582 if (Info.hasQueuePtr()) {
1583 unsigned QueuePtrReg = Info.addQueuePtr(TRI);
1584 MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass);
1585 CCInfo.AllocateReg(QueuePtrReg);
1586 }
1587
1588 if (Info.hasKernargSegmentPtr()) {
1589 unsigned InputPtrReg = Info.addKernargSegmentPtr(TRI);
1590 MF.addLiveIn(InputPtrReg, &AMDGPU::SGPR_64RegClass);
1591 CCInfo.AllocateReg(InputPtrReg);
1592 }
1593
1594 if (Info.hasDispatchID()) {
1595 unsigned DispatchIDReg = Info.addDispatchID(TRI);
1596 MF.addLiveIn(DispatchIDReg, &AMDGPU::SGPR_64RegClass);
1597 CCInfo.AllocateReg(DispatchIDReg);
1598 }
1599
1600 if (Info.hasFlatScratchInit()) {
1601 unsigned FlatScratchInitReg = Info.addFlatScratchInit(TRI);
1602 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass);
1603 CCInfo.AllocateReg(FlatScratchInitReg);
1604 }
1605
1606 // TODO: Add GridWorkGroupCount user SGPRs when used. For now with HSA we read
1607 // these from the dispatch pointer.
1608}
1609
1610// Allocate special input registers that are initialized per-wave.
1611static void allocateSystemSGPRs(CCState &CCInfo,
1612 MachineFunction &MF,
1613 SIMachineFunctionInfo &Info,
1614 CallingConv::ID CallConv,
1615 bool IsShader) {
1616 if (Info.hasWorkGroupIDX()) {
1617 unsigned Reg = Info.addWorkGroupIDX();
1618 MF.addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass);
1619 CCInfo.AllocateReg(Reg);
1620 }
1621
1622 if (Info.hasWorkGroupIDY()) {
1623 unsigned Reg = Info.addWorkGroupIDY();
1624 MF.addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass);
1625 CCInfo.AllocateReg(Reg);
1626 }
1627
1628 if (Info.hasWorkGroupIDZ()) {
1629 unsigned Reg = Info.addWorkGroupIDZ();
1630 MF.addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass);
1631 CCInfo.AllocateReg(Reg);
1632 }
1633
1634 if (Info.hasWorkGroupInfo()) {
1635 unsigned Reg = Info.addWorkGroupInfo();
1636 MF.addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass);
1637 CCInfo.AllocateReg(Reg);
1638 }
1639
1640 if (Info.hasPrivateSegmentWaveByteOffset()) {
1641 // Scratch wave offset passed in system SGPR.
1642 unsigned PrivateSegmentWaveByteOffsetReg;
1643
1644 if (IsShader) {
1645 PrivateSegmentWaveByteOffsetReg =
1646 Info.getPrivateSegmentWaveByteOffsetSystemSGPR();
1647
1648 // This is true if the scratch wave byte offset doesn't have a fixed
1649 // location.
1650 if (PrivateSegmentWaveByteOffsetReg == AMDGPU::NoRegister) {
1651 PrivateSegmentWaveByteOffsetReg = findFirstFreeSGPR(CCInfo);
1652 Info.setPrivateSegmentWaveByteOffset(PrivateSegmentWaveByteOffsetReg);
1653 }
1654 } else
1655 PrivateSegmentWaveByteOffsetReg = Info.addPrivateSegmentWaveByteOffset();
1656
1657 MF.addLiveIn(PrivateSegmentWaveByteOffsetReg, &AMDGPU::SGPR_32RegClass);
1658 CCInfo.AllocateReg(PrivateSegmentWaveByteOffsetReg);
1659 }
1660}
1661
1662static void reservePrivateMemoryRegs(const TargetMachine &TM,
1663 MachineFunction &MF,
1664 const SIRegisterInfo &TRI,
1665 SIMachineFunctionInfo &Info) {
1666 // Now that we've figured out where the scratch register inputs are, see if
1667 // should reserve the arguments and use them directly.
1668 MachineFrameInfo &MFI = MF.getFrameInfo();
1669 bool HasStackObjects = MFI.hasStackObjects();
1670
1671 // Record that we know we have non-spill stack objects so we don't need to
1672 // check all stack objects later.
1673 if (HasStackObjects)
1674 Info.setHasNonSpillStackObjects(true);
1675
1676 // Everything live out of a block is spilled with fast regalloc, so it's
1677 // almost certain that spilling will be required.
1678 if (TM.getOptLevel() == CodeGenOpt::None)
1679 HasStackObjects = true;
1680
1681 // For now assume stack access is needed in any callee functions, so we need
1682 // the scratch registers to pass in.
1683 bool RequiresStackAccess = HasStackObjects || MFI.hasCalls();
1684
1685 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1686 if (ST.isAmdHsaOrMesa(MF.getFunction())) {
1687 if (RequiresStackAccess) {
1688 // If we have stack objects, we unquestionably need the private buffer
1689 // resource. For the Code Object V2 ABI, this will be the first 4 user
1690 // SGPR inputs. We can reserve those and use them directly.
1691
1692 unsigned PrivateSegmentBufferReg = Info.getPreloadedReg(
1693 AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_BUFFER);
1694 Info.setScratchRSrcReg(PrivateSegmentBufferReg);
1695
1696 if (MFI.hasCalls()) {
1697 // If we have calls, we need to keep the frame register in a register
1698 // that won't be clobbered by a call, so ensure it is copied somewhere.
1699
1700 // This is not a problem for the scratch wave offset, because the same
1701 // registers are reserved in all functions.
1702
1703 // FIXME: Nothing is really ensuring this is a call preserved register,
1704 // it's just selected from the end so it happens to be.
1705 unsigned ReservedOffsetReg
1706 = TRI.reservedPrivateSegmentWaveByteOffsetReg(MF);
1707 Info.setScratchWaveOffsetReg(ReservedOffsetReg);
1708 } else {
1709 unsigned PrivateSegmentWaveByteOffsetReg = Info.getPreloadedReg(
1710 AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
1711 Info.setScratchWaveOffsetReg(PrivateSegmentWaveByteOffsetReg);
1712 }
1713 } else {
1714 unsigned ReservedBufferReg
1715 = TRI.reservedPrivateSegmentBufferReg(MF);
1716 unsigned ReservedOffsetReg
1717 = TRI.reservedPrivateSegmentWaveByteOffsetReg(MF);
1718
1719 // We tentatively reserve the last registers (skipping the last two
1720 // which may contain VCC). After register allocation, we'll replace
1721 // these with the ones immediately after those which were really
1722 // allocated. In the prologue copies will be inserted from the argument
1723 // to these reserved registers.
1724 Info.setScratchRSrcReg(ReservedBufferReg);
1725 Info.setScratchWaveOffsetReg(ReservedOffsetReg);
1726 }
1727 } else {
1728 unsigned ReservedBufferReg = TRI.reservedPrivateSegmentBufferReg(MF);
1729
1730 // Without HSA, relocations are used for the scratch pointer and the
1731 // buffer resource setup is always inserted in the prologue. Scratch wave
1732 // offset is still in an input SGPR.
1733 Info.setScratchRSrcReg(ReservedBufferReg);
1734
1735 if (HasStackObjects && !MFI.hasCalls()) {
1736 unsigned ScratchWaveOffsetReg = Info.getPreloadedReg(
1737 AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
1738 Info.setScratchWaveOffsetReg(ScratchWaveOffsetReg);
1739 } else {
1740 unsigned ReservedOffsetReg
1741 = TRI.reservedPrivateSegmentWaveByteOffsetReg(MF);
1742 Info.setScratchWaveOffsetReg(ReservedOffsetReg);
1743 }
1744 }
1745}
1746
1747bool SITargetLowering::supportSplitCSR(MachineFunction *MF) const {
1748 const SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
1749 return !Info->isEntryFunction();
1750}
1751
1752void SITargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {
1753
1754}
1755
1756void SITargetLowering::insertCopiesSplitCSR(
1757 MachineBasicBlock *Entry,
1758 const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
1759 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
1760
1761 const MCPhysReg *IStart = TRI->getCalleeSavedRegsViaCopy(Entry->getParent());
1762 if (!IStart)
1763 return;
1764
1765 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1766 MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();
1767 MachineBasicBlock::iterator MBBI = Entry->begin();
1768 for (const MCPhysReg *I = IStart; *I; ++I) {
1769 const TargetRegisterClass *RC = nullptr;
1770 if (AMDGPU::SReg_64RegClass.contains(*I))
1771 RC = &AMDGPU::SGPR_64RegClass;
1772 else if (AMDGPU::SReg_32RegClass.contains(*I))
1773 RC = &AMDGPU::SGPR_32RegClass;
1774 else
1775 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1775)
;
1776
1777 unsigned NewVR = MRI->createVirtualRegister(RC);
1778 // Create copy from CSR to a virtual register.
1779 Entry->addLiveIn(*I);
1780 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
1781 .addReg(*I);
1782
1783 // Insert the copy-back instructions right before the terminator.
1784 for (auto *Exit : Exits)
1785 BuildMI(*Exit, Exit->getFirstTerminator(), DebugLoc(),
1786 TII->get(TargetOpcode::COPY), *I)
1787 .addReg(NewVR);
1788 }
1789}
1790
1791SDValue SITargetLowering::LowerFormalArguments(
1792 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1793 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
1794 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1795 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
1796
1797 MachineFunction &MF = DAG.getMachineFunction();
1798 const Function &Fn = MF.getFunction();
1799 FunctionType *FType = MF.getFunction().getFunctionType();
1800 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
1801 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1802
1803 if (Subtarget->isAmdHsaOS() && AMDGPU::isShader(CallConv)) {
1804 DiagnosticInfoUnsupported NoGraphicsHSA(
1805 Fn, "unsupported non-compute shaders with HSA", DL.getDebugLoc());
1806 DAG.getContext()->diagnose(NoGraphicsHSA);
1807 return DAG.getEntryNode();
1808 }
1809
1810 // Create stack objects that are used for emitting debugger prologue if
1811 // "amdgpu-debugger-emit-prologue" attribute was specified.
1812 if (ST.debuggerEmitPrologue())
1813 createDebuggerPrologueStackObjects(MF);
1814
1815 SmallVector<ISD::InputArg, 16> Splits;
1816 SmallVector<CCValAssign, 16> ArgLocs;
1817 BitVector Skipped(Ins.size());
1818 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1819 *DAG.getContext());
1820
1821 bool IsShader = AMDGPU::isShader(CallConv);
1822 bool IsKernel = AMDGPU::isKernel(CallConv);
1823 bool IsEntryFunc = AMDGPU::isEntryFunctionCC(CallConv);
1824
1825 if (!IsEntryFunc) {
1826 // 4 bytes are reserved at offset 0 for the emergency stack slot. Skip over
1827 // this when allocating argument fixed offsets.
1828 CCInfo.AllocateStack(4, 4);
1829 }
1830
1831 if (IsShader) {
1832 processShaderInputArgs(Splits, CallConv, Ins, Skipped, FType, Info);
1833
1834 // At least one interpolation mode must be enabled or else the GPU will
1835 // hang.
1836 //
1837 // Check PSInputAddr instead of PSInputEnable. The idea is that if the user
1838 // set PSInputAddr, the user wants to enable some bits after the compilation
1839 // based on run-time states. Since we can't know what the final PSInputEna
1840 // will look like, so we shouldn't do anything here and the user should take
1841 // responsibility for the correct programming.
1842 //
1843 // Otherwise, the following restrictions apply:
1844 // - At least one of PERSP_* (0xF) or LINEAR_* (0x70) must be enabled.
1845 // - If POS_W_FLOAT (11) is enabled, at least one of PERSP_* must be
1846 // enabled too.
1847 if (CallConv == CallingConv::AMDGPU_PS) {
1848 if ((Info->getPSInputAddr() & 0x7F) == 0 ||
1849 ((Info->getPSInputAddr() & 0xF) == 0 &&
1850 Info->isPSInputAllocated(11))) {
1851 CCInfo.AllocateReg(AMDGPU::VGPR0);
1852 CCInfo.AllocateReg(AMDGPU::VGPR1);
1853 Info->markPSInputAllocated(0);
1854 Info->markPSInputEnabled(0);
1855 }
1856 if (Subtarget->isAmdPalOS()) {
1857 // For isAmdPalOS, the user does not enable some bits after compilation
1858 // based on run-time states; the register values being generated here are
1859 // the final ones set in hardware. Therefore we need to apply the
1860 // workaround to PSInputAddr and PSInputEnable together. (The case where
1861 // a bit is set in PSInputAddr but not PSInputEnable is where the
1862 // frontend set up an input arg for a particular interpolation mode, but
1863 // nothing uses that input arg. Really we should have an earlier pass
1864 // that removes such an arg.)
1865 unsigned PsInputBits = Info->getPSInputAddr() & Info->getPSInputEnable();
1866 if ((PsInputBits & 0x7F) == 0 ||
1867 ((PsInputBits & 0xF) == 0 &&
1868 (PsInputBits >> 11 & 1)))
1869 Info->markPSInputEnabled(
1870 countTrailingZeros(Info->getPSInputAddr(), ZB_Undefined));
1871 }
1872 }
1873
1874 assert(!Info->hasDispatchPtr() &&((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && !Info->hasFlatScratchInit() && !Info
->hasWorkGroupIDX() && !Info->hasWorkGroupIDY()
&& !Info->hasWorkGroupIDZ() && !Info->
hasWorkGroupInfo() && !Info->hasWorkItemIDX() &&
!Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ
()) ? static_cast<void> (0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1879, __PRETTY_FUNCTION__))
1875 !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() &&((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && !Info->hasFlatScratchInit() && !Info
->hasWorkGroupIDX() && !Info->hasWorkGroupIDY()
&& !Info->hasWorkGroupIDZ() && !Info->
hasWorkGroupInfo() && !Info->hasWorkItemIDX() &&
!Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ
()) ? static_cast<void> (0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1879, __PRETTY_FUNCTION__))
1876 !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && !Info->hasFlatScratchInit() && !Info
->hasWorkGroupIDX() && !Info->hasWorkGroupIDY()
&& !Info->hasWorkGroupIDZ() && !Info->
hasWorkGroupInfo() && !Info->hasWorkItemIDX() &&
!Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ
()) ? static_cast<void> (0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1879, __PRETTY_FUNCTION__))
1877 !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() &&((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && !Info->hasFlatScratchInit() && !Info
->hasWorkGroupIDX() && !Info->hasWorkGroupIDY()
&& !Info->hasWorkGroupIDZ() && !Info->
hasWorkGroupInfo() && !Info->hasWorkItemIDX() &&
!Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ
()) ? static_cast<void> (0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1879, __PRETTY_FUNCTION__))
1878 !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() &&((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && !Info->hasFlatScratchInit() && !Info
->hasWorkGroupIDX() && !Info->hasWorkGroupIDY()
&& !Info->hasWorkGroupIDZ() && !Info->
hasWorkGroupInfo() && !Info->hasWorkItemIDX() &&
!Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ
()) ? static_cast<void> (0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1879, __PRETTY_FUNCTION__))
1879 !Info->hasWorkItemIDZ())((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && !Info->hasFlatScratchInit() && !Info
->hasWorkGroupIDX() && !Info->hasWorkGroupIDY()
&& !Info->hasWorkGroupIDZ() && !Info->
hasWorkGroupInfo() && !Info->hasWorkItemIDX() &&
!Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ
()) ? static_cast<void> (0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1879, __PRETTY_FUNCTION__))
;
1880 } else if (IsKernel) {
1881 assert(Info->hasWorkGroupIDX() && Info->hasWorkItemIDX())((Info->hasWorkGroupIDX() && Info->hasWorkItemIDX
()) ? static_cast<void> (0) : __assert_fail ("Info->hasWorkGroupIDX() && Info->hasWorkItemIDX()"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1881, __PRETTY_FUNCTION__))
;
1882 } else {
1883 Splits.append(Ins.begin(), Ins.end());
1884 }
1885
1886 if (IsEntryFunc) {
1887 allocateSpecialEntryInputVGPRs(CCInfo, MF, *TRI, *Info);
1888 allocateHSAUserSGPRs(CCInfo, MF, *TRI, *Info);
1889 }
1890
1891 if (IsKernel) {
1892 analyzeFormalArgumentsCompute(CCInfo, Ins);
1893 } else {
1894 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, isVarArg);
1895 CCInfo.AnalyzeFormalArguments(Splits, AssignFn);
1896 }
1897
1898 SmallVector<SDValue, 16> Chains;
1899
1900 // FIXME: This is the minimum kernel argument alignment. We should improve
1901 // this to the maximum alignment of the arguments.
1902 //
1903 // FIXME: Alignment of explicit arguments totally broken with non-0 explicit
1904 // kern arg offset.
1905 const unsigned KernelArgBaseAlign = 16;
1906
1907 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
1908 const ISD::InputArg &Arg = Ins[i];
1909 if (Arg.isOrigArg() && Skipped[Arg.getOrigArgIndex()]) {
1910 InVals.push_back(DAG.getUNDEF(Arg.VT));
1911 continue;
1912 }
1913
1914 CCValAssign &VA = ArgLocs[ArgIdx++];
1915 MVT VT = VA.getLocVT();
1916
1917 if (IsEntryFunc && VA.isMemLoc()) {
1918 VT = Ins[i].VT;
1919 EVT MemVT = VA.getLocVT();
1920
1921 const uint64_t Offset = VA.getLocMemOffset();
1922 unsigned Align = MinAlign(KernelArgBaseAlign, Offset);
1923
1924 SDValue Arg = lowerKernargMemParameter(
1925 DAG, VT, MemVT, DL, Chain, Offset, Align, Ins[i].Flags.isSExt(), &Ins[i]);
1926 Chains.push_back(Arg.getValue(1));
1927
1928 auto *ParamTy =
1929 dyn_cast<PointerType>(FType->getParamType(Ins[i].getOrigArgIndex()));
1930 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
1931 ParamTy && ParamTy->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
1932 // On SI local pointers are just offsets into LDS, so they are always
1933 // less than 16-bits. On CI and newer they could potentially be
1934 // real pointers, so we can't guarantee their size.
1935 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
1936 DAG.getValueType(MVT::i16));
1937 }
1938
1939 InVals.push_back(Arg);
1940 continue;
1941 } else if (!IsEntryFunc && VA.isMemLoc()) {
1942 SDValue Val = lowerStackParameter(DAG, VA, DL, Chain, Arg);
1943 InVals.push_back(Val);
1944 if (!Arg.Flags.isByVal())
1945 Chains.push_back(Val.getValue(1));
1946 continue;
1947 }
1948
1949 assert(VA.isRegLoc() && "Parameter must be in a register!")((VA.isRegLoc() && "Parameter must be in a register!"
) ? static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Parameter must be in a register!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1949, __PRETTY_FUNCTION__))
;
1950
1951 unsigned Reg = VA.getLocReg();
1952 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
1953 EVT ValVT = VA.getValVT();
1954
1955 Reg = MF.addLiveIn(Reg, RC);
1956 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
1957
1958 if (Arg.Flags.isSRet() && !getSubtarget()->enableHugePrivateBuffer()) {
1959 // The return object should be reasonably addressable.
1960
1961 // FIXME: This helps when the return is a real sret. If it is a
1962 // automatically inserted sret (i.e. CanLowerReturn returns false), an
1963 // extra copy is inserted in SelectionDAGBuilder which obscures this.
1964 unsigned NumBits = 32 - AssumeFrameIndexHighZeroBits;
1965 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val,
1966 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), NumBits)));
1967 }
1968
1969 // If this is an 8 or 16-bit value, it is really passed promoted
1970 // to 32 bits. Insert an assert[sz]ext to capture this, then
1971 // truncate to the right size.
1972 switch (VA.getLocInfo()) {
1973 case CCValAssign::Full:
1974 break;
1975 case CCValAssign::BCvt:
1976 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
1977 break;
1978 case CCValAssign::SExt:
1979 Val = DAG.getNode(ISD::AssertSext, DL, VT, Val,
1980 DAG.getValueType(ValVT));
1981 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
1982 break;
1983 case CCValAssign::ZExt:
1984 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val,
1985 DAG.getValueType(ValVT));
1986 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
1987 break;
1988 case CCValAssign::AExt:
1989 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
1990 break;
1991 default:
1992 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1992)
;
1993 }
1994
1995 InVals.push_back(Val);
1996 }
1997
1998 if (!IsEntryFunc) {
1999 // Special inputs come after user arguments.
2000 allocateSpecialInputVGPRs(CCInfo, MF, *TRI, *Info);
2001 }
2002
2003 // Start adding system SGPRs.
2004 if (IsEntryFunc) {
2005 allocateSystemSGPRs(CCInfo, MF, *Info, CallConv, IsShader);
2006 } else {
2007 CCInfo.AllocateReg(Info->getScratchRSrcReg());
2008 CCInfo.AllocateReg(Info->getScratchWaveOffsetReg());
2009 CCInfo.AllocateReg(Info->getFrameOffsetReg());
2010 allocateSpecialInputSGPRs(CCInfo, MF, *TRI, *Info);
2011 }
2012
2013 auto &ArgUsageInfo =
2014 DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
2015 ArgUsageInfo.setFuncArgInfo(Fn, Info->getArgInfo());
2016
2017 unsigned StackArgSize = CCInfo.getNextStackOffset();
2018 Info->setBytesInStackArgArea(StackArgSize);
2019
2020 return Chains.empty() ? Chain :
2021 DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
2022}
2023
2024// TODO: If return values can't fit in registers, we should return as many as
2025// possible in registers before passing on stack.
2026bool SITargetLowering::CanLowerReturn(
2027 CallingConv::ID CallConv,
2028 MachineFunction &MF, bool IsVarArg,
2029 const SmallVectorImpl<ISD::OutputArg> &Outs,
2030 LLVMContext &Context) const {
2031 // Replacing returns with sret/stack usage doesn't make sense for shaders.
2032 // FIXME: Also sort of a workaround for custom vector splitting in LowerReturn
2033 // for shaders. Vector types should be explicitly handled by CC.
2034 if (AMDGPU::isEntryFunctionCC(CallConv))
2035 return true;
2036
2037 SmallVector<CCValAssign, 16> RVLocs;
2038 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
2039 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg));
2040}
2041
2042SDValue
2043SITargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2044 bool isVarArg,
2045 const SmallVectorImpl<ISD::OutputArg> &Outs,
2046 const SmallVectorImpl<SDValue> &OutVals,
2047 const SDLoc &DL, SelectionDAG &DAG) const {
2048 MachineFunction &MF = DAG.getMachineFunction();
2049 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
2050
2051 if (AMDGPU::isKernel(CallConv)) {
2052 return AMDGPUTargetLowering::LowerReturn(Chain, CallConv, isVarArg, Outs,
2053 OutVals, DL, DAG);
2054 }
2055
2056 bool IsShader = AMDGPU::isShader(CallConv);
2057
2058 Info->setIfReturnsVoid(Outs.empty());
2059 bool IsWaveEnd = Info->returnsVoid() && IsShader;
2060
2061 // CCValAssign - represent the assignment of the return value to a location.
2062 SmallVector<CCValAssign, 48> RVLocs;
2063 SmallVector<ISD::OutputArg, 48> Splits;
2064
2065 // CCState - Info about the registers and stack slots.
2066 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2067 *DAG.getContext());
2068
2069 // Analyze outgoing return values.
2070 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2071
2072 SDValue Flag;
2073 SmallVector<SDValue, 48> RetOps;
2074 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2075
2076 // Add return address for callable functions.
2077 if (!Info->isEntryFunction()) {
2078 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2079 SDValue ReturnAddrReg = CreateLiveInRegister(
2080 DAG, &AMDGPU::SReg_64RegClass, TRI->getReturnAddressReg(MF), MVT::i64);
2081
2082 // FIXME: Should be able to use a vreg here, but need a way to prevent it
2083 // from being allcoated to a CSR.
2084
2085 SDValue PhysReturnAddrReg = DAG.getRegister(TRI->getReturnAddressReg(MF),
2086 MVT::i64);
2087
2088 Chain = DAG.getCopyToReg(Chain, DL, PhysReturnAddrReg, ReturnAddrReg, Flag);
2089 Flag = Chain.getValue(1);
2090
2091 RetOps.push_back(PhysReturnAddrReg);
2092 }
2093
2094 // Copy the result values into the output registers.
2095 for (unsigned I = 0, RealRVLocIdx = 0, E = RVLocs.size(); I != E;
2096 ++I, ++RealRVLocIdx) {
2097 CCValAssign &VA = RVLocs[I];
2098 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2098, __PRETTY_FUNCTION__))
;
2099 // TODO: Partially return in registers if return values don't fit.
2100 SDValue Arg = OutVals[RealRVLocIdx];
2101
2102 // Copied from other backends.
2103 switch (VA.getLocInfo()) {
2104 case CCValAssign::Full:
2105 break;
2106 case CCValAssign::BCvt:
2107 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2108 break;
2109 case CCValAssign::SExt:
2110 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2111 break;
2112 case CCValAssign::ZExt:
2113 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2114 break;
2115 case CCValAssign::AExt:
2116 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2117 break;
2118 default:
2119 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2119)
;
2120 }
2121
2122 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2123 Flag = Chain.getValue(1);
2124 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2125 }
2126
2127 // FIXME: Does sret work properly?
2128 if (!Info->isEntryFunction()) {
2129 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
2130 const MCPhysReg *I =
2131 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
2132 if (I) {
2133 for (; *I; ++I) {
2134 if (AMDGPU::SReg_64RegClass.contains(*I))
2135 RetOps.push_back(DAG.getRegister(*I, MVT::i64));
2136 else if (AMDGPU::SReg_32RegClass.contains(*I))
2137 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
2138 else
2139 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2139)
;
2140 }
2141 }
2142 }
2143
2144 // Update chain and glue.
2145 RetOps[0] = Chain;
2146 if (Flag.getNode())
2147 RetOps.push_back(Flag);
2148
2149 unsigned Opc = AMDGPUISD::ENDPGM;
2150 if (!IsWaveEnd)
2151 Opc = IsShader ? AMDGPUISD::RETURN_TO_EPILOG : AMDGPUISD::RET_FLAG;
2152 return DAG.getNode(Opc, DL, MVT::Other, RetOps);
2153}
2154
2155SDValue SITargetLowering::LowerCallResult(
2156 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
2157 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
2158 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool IsThisReturn,
2159 SDValue ThisVal) const {
2160 CCAssignFn *RetCC = CCAssignFnForReturn(CallConv, IsVarArg);
2161
2162 // Assign locations to each value returned by this call.
2163 SmallVector<CCValAssign, 16> RVLocs;
2164 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2165 *DAG.getContext());
2166 CCInfo.AnalyzeCallResult(Ins, RetCC);
2167
2168 // Copy all of the result registers out of their specified physreg.
2169 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2170 CCValAssign VA = RVLocs[i];
2171 SDValue Val;
2172
2173 if (VA.isRegLoc()) {
2174 Val = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2175 Chain = Val.getValue(1);
2176 InFlag = Val.getValue(2);
2177 } else if (VA.isMemLoc()) {
2178 report_fatal_error("TODO: return values in memory");
2179 } else
2180 llvm_unreachable("unknown argument location type")::llvm::llvm_unreachable_internal("unknown argument location type"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2180)
;
2181
2182 switch (VA.getLocInfo()) {
2183 case CCValAssign::Full:
2184 break;
2185 case CCValAssign::BCvt:
2186 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2187 break;
2188 case CCValAssign::ZExt:
2189 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
2190 DAG.getValueType(VA.getValVT()));
2191 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2192 break;
2193 case CCValAssign::SExt:
2194 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
2195 DAG.getValueType(VA.getValVT()));
2196 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2197 break;
2198 case CCValAssign::AExt:
2199 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2200 break;
2201 default:
2202 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2202)
;
2203 }
2204
2205 InVals.push_back(Val);
2206 }
2207
2208 return Chain;
2209}
2210
2211// Add code to pass special inputs required depending on used features separate
2212// from the explicit user arguments present in the IR.
2213void SITargetLowering::passSpecialInputs(
2214 CallLoweringInfo &CLI,
2215 CCState &CCInfo,
2216 const SIMachineFunctionInfo &Info,
2217 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
2218 SmallVectorImpl<SDValue> &MemOpChains,
2219 SDValue Chain) const {
2220 // If we don't have a call site, this was a call inserted by
2221 // legalization. These can never use special inputs.
2222 if (!CLI.CS)
2223 return;
2224
2225 const Function *CalleeFunc = CLI.CS.getCalledFunction();
2226 assert(CalleeFunc)((CalleeFunc) ? static_cast<void> (0) : __assert_fail (
"CalleeFunc", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2226, __PRETTY_FUNCTION__))
;
2227
2228 SelectionDAG &DAG = CLI.DAG;
2229 const SDLoc &DL = CLI.DL;
2230
2231 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
2232
2233 auto &ArgUsageInfo =
2234 DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
2235 const AMDGPUFunctionArgInfo &CalleeArgInfo
2236 = ArgUsageInfo.lookupFuncArgInfo(*CalleeFunc);
2237
2238 const AMDGPUFunctionArgInfo &CallerArgInfo = Info.getArgInfo();
2239
2240 // TODO: Unify with private memory register handling. This is complicated by
2241 // the fact that at least in kernels, the input argument is not necessarily
2242 // in the same location as the input.
2243 AMDGPUFunctionArgInfo::PreloadedValue InputRegs[] = {
2244 AMDGPUFunctionArgInfo::DISPATCH_PTR,
2245 AMDGPUFunctionArgInfo::QUEUE_PTR,
2246 AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR,
2247 AMDGPUFunctionArgInfo::DISPATCH_ID,
2248 AMDGPUFunctionArgInfo::WORKGROUP_ID_X,
2249 AMDGPUFunctionArgInfo::WORKGROUP_ID_Y,
2250 AMDGPUFunctionArgInfo::WORKGROUP_ID_Z,
2251 AMDGPUFunctionArgInfo::WORKITEM_ID_X,
2252 AMDGPUFunctionArgInfo::WORKITEM_ID_Y,
2253 AMDGPUFunctionArgInfo::WORKITEM_ID_Z,
2254 AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR
2255 };
2256
2257 for (auto InputID : InputRegs) {
2258 const ArgDescriptor *OutgoingArg;
2259 const TargetRegisterClass *ArgRC;
2260
2261 std::tie(OutgoingArg, ArgRC) = CalleeArgInfo.getPreloadedValue(InputID);
2262 if (!OutgoingArg)
2263 continue;
2264
2265 const ArgDescriptor *IncomingArg;
2266 const TargetRegisterClass *IncomingArgRC;
2267 std::tie(IncomingArg, IncomingArgRC)
2268 = CallerArgInfo.getPreloadedValue(InputID);
2269 assert(IncomingArgRC == ArgRC)((IncomingArgRC == ArgRC) ? static_cast<void> (0) : __assert_fail
("IncomingArgRC == ArgRC", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2269, __PRETTY_FUNCTION__))
;
2270
2271 // All special arguments are ints for now.
2272 EVT ArgVT = TRI->getSpillSize(*ArgRC) == 8 ? MVT::i64 : MVT::i32;
2273 SDValue InputReg;
2274
2275 if (IncomingArg) {
2276 InputReg = loadInputValue(DAG, ArgRC, ArgVT, DL, *IncomingArg);
2277 } else {
2278 // The implicit arg ptr is special because it doesn't have a corresponding
2279 // input for kernels, and is computed from the kernarg segment pointer.
2280 assert(InputID == AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR)((InputID == AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR) ? static_cast
<void> (0) : __assert_fail ("InputID == AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2280, __PRETTY_FUNCTION__))
;
2281 InputReg = getImplicitArgPtr(DAG, DL);
2282 }
2283
2284 if (OutgoingArg->isRegister()) {
2285 RegsToPass.emplace_back(OutgoingArg->getRegister(), InputReg);
2286 } else {
2287 unsigned SpecialArgOffset = CCInfo.AllocateStack(ArgVT.getStoreSize(), 4);
2288 SDValue ArgStore = storeStackInputValue(DAG, DL, Chain, InputReg,
2289 SpecialArgOffset);
2290 MemOpChains.push_back(ArgStore);
2291 }
2292 }
2293}
2294
2295static bool canGuaranteeTCO(CallingConv::ID CC) {
2296 return CC == CallingConv::Fast;
2297}
2298
2299/// Return true if we might ever do TCO for calls with this calling convention.
2300static bool mayTailCallThisCC(CallingConv::ID CC) {
2301 switch (CC) {
2302 case CallingConv::C:
2303 return true;
2304 default:
2305 return canGuaranteeTCO(CC);
2306 }
2307}
2308
2309bool SITargetLowering::isEligibleForTailCallOptimization(
2310 SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg,
2311 const SmallVectorImpl<ISD::OutputArg> &Outs,
2312 const SmallVectorImpl<SDValue> &OutVals,
2313 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2314 if (!mayTailCallThisCC(CalleeCC))
2315 return false;
2316
2317 MachineFunction &MF = DAG.getMachineFunction();
2318 const Function &CallerF = MF.getFunction();
2319 CallingConv::ID CallerCC = CallerF.getCallingConv();
2320 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2321 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2322
2323 // Kernels aren't callable, and don't have a live in return address so it
2324 // doesn't make sense to do a tail call with entry functions.
2325 if (!CallerPreserved)
2326 return false;
2327
2328 bool CCMatch = CallerCC == CalleeCC;
2329
2330 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
2331 if (canGuaranteeTCO(CalleeCC) && CCMatch)
2332 return true;
2333 return false;
2334 }
2335
2336 // TODO: Can we handle var args?
2337 if (IsVarArg)
2338 return false;
2339
2340 for (const Argument &Arg : CallerF.args()) {
2341 if (Arg.hasByValAttr())
2342 return false;
2343 }
2344
2345 LLVMContext &Ctx = *DAG.getContext();
2346
2347 // Check that the call results are passed in the same way.
2348 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, Ctx, Ins,
2349 CCAssignFnForCall(CalleeCC, IsVarArg),
2350 CCAssignFnForCall(CallerCC, IsVarArg)))
2351 return false;
2352
2353 // The callee has to preserve all registers the caller needs to preserve.
2354 if (!CCMatch) {
2355 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2356 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2357 return false;
2358 }
2359
2360 // Nothing more to check if the callee is taking no arguments.
2361 if (Outs.empty())
2362 return true;
2363
2364 SmallVector<CCValAssign, 16> ArgLocs;
2365 CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, Ctx);
2366
2367 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, IsVarArg));
2368
2369 const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
2370 // If the stack arguments for this call do not fit into our own save area then
2371 // the call cannot be made tail.
2372 // TODO: Is this really necessary?
2373 if (CCInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea())
2374 return false;
2375
2376 const MachineRegisterInfo &MRI = MF.getRegInfo();
2377 return parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals);
2378}
2379
2380bool SITargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2381 if (!CI->isTailCall())
2382 return false;
2383
2384 const Function *ParentFn = CI->getParent()->getParent();
2385 if (AMDGPU::isEntryFunctionCC(ParentFn->getCallingConv()))
2386 return false;
2387
2388 auto Attr = ParentFn->getFnAttribute("disable-tail-calls");
2389 return (Attr.getValueAsString() != "true");
2390}
2391
2392// The wave scratch offset register is used as the global base pointer.
2393SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
2394 SmallVectorImpl<SDValue> &InVals) const {
2395 SelectionDAG &DAG = CLI.DAG;
2396 const SDLoc &DL = CLI.DL;
2397 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2398 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2399 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2400 SDValue Chain = CLI.Chain;
2401 SDValue Callee = CLI.Callee;
2402 bool &IsTailCall = CLI.IsTailCall;
2403 CallingConv::ID CallConv = CLI.CallConv;
2404 bool IsVarArg = CLI.IsVarArg;
2405 bool IsSibCall = false;
2406 bool IsThisReturn = false;
2407 MachineFunction &MF = DAG.getMachineFunction();
2408
2409 if (IsVarArg) {
2410 return lowerUnhandledCall(CLI, InVals,
2411 "unsupported call to variadic function ");
2412 }
2413
2414 if (!CLI.CS.getInstruction())
2415 report_fatal_error("unsupported libcall legalization");
2416
2417 if (!CLI.CS.getCalledFunction()) {
2418 return lowerUnhandledCall(CLI, InVals,
2419 "unsupported indirect call to function ");
2420 }
2421
2422 if (IsTailCall && MF.getTarget().Options.GuaranteedTailCallOpt) {
2423 return lowerUnhandledCall(CLI, InVals,
2424 "unsupported required tail call to function ");
2425 }
2426
2427 if (AMDGPU::isShader(MF.getFunction().getCallingConv())) {
2428 // Note the issue is with the CC of the calling function, not of the call
2429 // itself.
2430 return lowerUnhandledCall(CLI, InVals,
2431 "unsupported call from graphics shader of function ");
2432 }
2433
2434 // The first 4 bytes are reserved for the callee's emergency stack slot.
2435 if (IsTailCall) {
2436 IsTailCall = isEligibleForTailCallOptimization(
2437 Callee, CallConv, IsVarArg, Outs, OutVals, Ins, DAG);
2438 if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall()) {
2439 report_fatal_error("failed to perform tail call elimination on a call "
2440 "site marked musttail");
2441 }
2442
2443 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2444
2445 // A sibling call is one where we're under the usual C ABI and not planning
2446 // to change that but can still do a tail call:
2447 if (!TailCallOpt && IsTailCall)
2448 IsSibCall = true;
2449
2450 if (IsTailCall)
2451 ++NumTailCalls;
2452 }
2453
2454 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
2455
2456 // Analyze operands of the call, assigning locations to each operand.
2457 SmallVector<CCValAssign, 16> ArgLocs;
2458 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
2459 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, IsVarArg);
2460
2461 // The first 4 bytes are reserved for the callee's emergency stack slot.
2462 CCInfo.AllocateStack(4, 4);
2463
2464 CCInfo.AnalyzeCallOperands(Outs, AssignFn);
2465
2466 // Get a count of how many bytes are to be pushed on the stack.
2467 unsigned NumBytes = CCInfo.getNextStackOffset();
2468
2469 if (IsSibCall) {
2470 // Since we're not changing the ABI to make this a tail call, the memory
2471 // operands are already available in the caller's incoming argument space.
2472 NumBytes = 0;
2473 }
2474
2475 // FPDiff is the byte offset of the call's argument area from the callee's.
2476 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2477 // by this amount for a tail call. In a sibling call it must be 0 because the
2478 // caller will deallocate the entire stack and the callee still expects its
2479 // arguments to begin at SP+0. Completely unused for non-tail calls.
2480 int32_t FPDiff = 0;
2481 MachineFrameInfo &MFI = MF.getFrameInfo();
2482 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2483
2484 SDValue CallerSavedFP;
2485
2486 // Adjust the stack pointer for the new arguments...
2487 // These operations are automatically eliminated by the prolog/epilog pass
2488 if (!IsSibCall) {
2489 Chain = DAG.getCALLSEQ_START(Chain, 0, 0, DL);
2490
2491 unsigned OffsetReg = Info->getScratchWaveOffsetReg();
2492
2493 // In the HSA case, this should be an identity copy.
2494 SDValue ScratchRSrcReg
2495 = DAG.getCopyFromReg(Chain, DL, Info->getScratchRSrcReg(), MVT::v4i32);
2496 RegsToPass.emplace_back(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, ScratchRSrcReg);
2497
2498 // TODO: Don't hardcode these registers and get from the callee function.
2499 SDValue ScratchWaveOffsetReg
2500 = DAG.getCopyFromReg(Chain, DL, OffsetReg, MVT::i32);
2501 RegsToPass.emplace_back(AMDGPU::SGPR4, ScratchWaveOffsetReg);
2502
2503 if (!Info->isEntryFunction()) {
2504 // Avoid clobbering this function's FP value. In the current convention
2505 // callee will overwrite this, so do save/restore around the call site.
2506 CallerSavedFP = DAG.getCopyFromReg(Chain, DL,
2507 Info->getFrameOffsetReg(), MVT::i32);
2508 }
2509 }
2510
2511 SmallVector<SDValue, 8> MemOpChains;
2512 MVT PtrVT = MVT::i32;
2513
2514 // Walk the register/memloc assignments, inserting copies/loads.
2515 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2516 ++i, ++realArgIdx) {
2517 CCValAssign &VA = ArgLocs[i];
2518 SDValue Arg = OutVals[realArgIdx];
2519
2520 // Promote the value if needed.
2521 switch (VA.getLocInfo()) {
2522 case CCValAssign::Full:
2523 break;
2524 case CCValAssign::BCvt:
2525 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2526 break;
2527 case CCValAssign::ZExt:
2528 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2529 break;
2530 case CCValAssign::SExt:
2531 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2532 break;
2533 case CCValAssign::AExt:
2534 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2535 break;
2536 case CCValAssign::FPExt:
2537 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2538 break;
2539 default:
2540 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2540)
;
2541 }
2542
2543 if (VA.isRegLoc()) {
2544 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2545 } else {
2546 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2546, __PRETTY_FUNCTION__))
;
2547
2548 SDValue DstAddr;
2549 MachinePointerInfo DstInfo;
2550
2551 unsigned LocMemOffset = VA.getLocMemOffset();
2552 int32_t Offset = LocMemOffset;
2553
2554 SDValue PtrOff = DAG.getConstant(Offset, DL, PtrVT);
2555 unsigned Align = 0;
2556
2557 if (IsTailCall) {
2558 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2559 unsigned OpSize = Flags.isByVal() ?
2560 Flags.getByValSize() : VA.getValVT().getStoreSize();
2561
2562 // FIXME: We can have better than the minimum byval required alignment.
2563 Align = Flags.isByVal() ? Flags.getByValAlign() :
2564 MinAlign(Subtarget->getStackAlignment(), Offset);
2565
2566 Offset = Offset + FPDiff;
2567 int FI = MFI.CreateFixedObject(OpSize, Offset, true);
2568
2569 DstAddr = DAG.getFrameIndex(FI, PtrVT);
2570 DstInfo = MachinePointerInfo::getFixedStack(MF, FI);
2571
2572 // Make sure any stack arguments overlapping with where we're storing
2573 // are loaded before this eventual operation. Otherwise they'll be
2574 // clobbered.
2575
2576 // FIXME: Why is this really necessary? This seems to just result in a
2577 // lot of code to copy the stack and write them back to the same
2578 // locations, which are supposed to be immutable?
2579 Chain = addTokenForArgument(Chain, DAG, MFI, FI);
2580 } else {
2581 DstAddr = PtrOff;
2582 DstInfo = MachinePointerInfo::getStack(MF, LocMemOffset);
2583 Align = MinAlign(Subtarget->getStackAlignment(), LocMemOffset);
2584 }
2585
2586 if (Outs[i].Flags.isByVal()) {
2587 SDValue SizeNode =
2588 DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i32);
2589 SDValue Cpy = DAG.getMemcpy(
2590 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2591 /*isVol = */ false, /*AlwaysInline = */ true,
2592 /*isTailCall = */ false, DstInfo,
2593 MachinePointerInfo(UndefValue::get(Type::getInt8PtrTy(
2594 *DAG.getContext(), AMDGPUAS::PRIVATE_ADDRESS))));
2595
2596 MemOpChains.push_back(Cpy);
2597 } else {
2598 SDValue Store = DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, Align);
2599 MemOpChains.push_back(Store);
2600 }
2601 }
2602 }
2603
2604 // Copy special input registers after user input arguments.
2605 passSpecialInputs(CLI, CCInfo, *Info, RegsToPass, MemOpChains, Chain);
2606
2607 if (!MemOpChains.empty())
2608 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2609
2610 // Build a sequence of copy-to-reg nodes chained together with token chain
2611 // and flag operands which copy the outgoing args into the appropriate regs.
2612 SDValue InFlag;
2613 for (auto &RegToPass : RegsToPass) {
2614 Chain = DAG.getCopyToReg(Chain, DL, RegToPass.first,
2615 RegToPass.second, InFlag);
2616 InFlag = Chain.getValue(1);
2617 }
2618
2619
2620 SDValue PhysReturnAddrReg;
2621 if (IsTailCall) {
2622 // Since the return is being combined with the call, we need to pass on the
2623 // return address.
2624
2625 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2626 SDValue ReturnAddrReg = CreateLiveInRegister(
2627 DAG, &AMDGPU::SReg_64RegClass, TRI->getReturnAddressReg(MF), MVT::i64);
2628
2629 PhysReturnAddrReg = DAG.getRegister(TRI->getReturnAddressReg(MF),
2630 MVT::i64);
2631 Chain = DAG.getCopyToReg(Chain, DL, PhysReturnAddrReg, ReturnAddrReg, InFlag);
2632 InFlag = Chain.getValue(1);
2633 }
2634
2635 // We don't usually want to end the call-sequence here because we would tidy
2636 // the frame up *after* the call, however in the ABI-changing tail-call case
2637 // we've carefully laid out the parameters so that when sp is reset they'll be
2638 // in the correct location.
2639 if (IsTailCall && !IsSibCall) {
2640 Chain = DAG.getCALLSEQ_END(Chain,
2641 DAG.getTargetConstant(NumBytes, DL, MVT::i32),
2642 DAG.getTargetConstant(0, DL, MVT::i32),
2643 InFlag, DL);
2644 InFlag = Chain.getValue(1);
2645 }
2646
2647 std::vector<SDValue> Ops;
2648 Ops.push_back(Chain);
2649 Ops.push_back(Callee);
2650
2651 if (IsTailCall) {
2652 // Each tail call may have to adjust the stack by a different amount, so
2653 // this information must travel along with the operation for eventual
2654 // consumption by emitEpilogue.
2655 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32));
2656
2657 Ops.push_back(PhysReturnAddrReg);
2658 }
2659
2660 // Add argument registers to the end of the list so that they are known live
2661 // into the call.
2662 for (auto &RegToPass : RegsToPass) {
2663 Ops.push_back(DAG.getRegister(RegToPass.first,
2664 RegToPass.second.getValueType()));
2665 }
2666
2667 // Add a register mask operand representing the call-preserved registers.
2668
2669 auto *TRI = static_cast<const SIRegisterInfo*>(Subtarget->getRegisterInfo());
2670 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
2671 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2671, __PRETTY_FUNCTION__))
;
2672 Ops.push_back(DAG.getRegisterMask(Mask));
2673
2674 if (InFlag.getNode())
2675 Ops.push_back(InFlag);
2676
2677 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2678
2679 // If we're doing a tall call, use a TC_RETURN here rather than an
2680 // actual call instruction.
2681 if (IsTailCall) {
2682 MFI.setHasTailCall();
2683 return DAG.getNode(AMDGPUISD::TC_RETURN, DL, NodeTys, Ops);
2684 }
2685
2686 // Returns a chain and a flag for retval copy to use.
2687 SDValue Call = DAG.getNode(AMDGPUISD::CALL, DL, NodeTys, Ops);
2688 Chain = Call.getValue(0);
2689 InFlag = Call.getValue(1);
2690
2691 if (CallerSavedFP) {
2692 SDValue FPReg = DAG.getRegister(Info->getFrameOffsetReg(), MVT::i32);
2693 Chain = DAG.getCopyToReg(Chain, DL, FPReg, CallerSavedFP, InFlag);
2694 InFlag = Chain.getValue(1);
2695 }
2696
2697 uint64_t CalleePopBytes = NumBytes;
2698 Chain = DAG.getCALLSEQ_END(Chain, DAG.getTargetConstant(0, DL, MVT::i32),
2699 DAG.getTargetConstant(CalleePopBytes, DL, MVT::i32),
2700 InFlag, DL);
2701 if (!Ins.empty())
2702 InFlag = Chain.getValue(1);
2703
2704 // Handle result values, copying them out of physregs into vregs that we
2705 // return.
2706 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2707 InVals, IsThisReturn,
2708 IsThisReturn ? OutVals[0] : SDValue());
2709}
2710
2711unsigned SITargetLowering::getRegisterByName(const char* RegName, EVT VT,
2712 SelectionDAG &DAG) const {
2713 unsigned Reg = StringSwitch<unsigned>(RegName)
2714 .Case("m0", AMDGPU::M0)
2715 .Case("exec", AMDGPU::EXEC)
2716 .Case("exec_lo", AMDGPU::EXEC_LO)
2717 .Case("exec_hi", AMDGPU::EXEC_HI)
2718 .Case("flat_scratch", AMDGPU::FLAT_SCR)
2719 .Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)
2720 .Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI)
2721 .Default(AMDGPU::NoRegister);
2722
2723 if (Reg == AMDGPU::NoRegister) {
2724 report_fatal_error(Twine("invalid register name \""
2725 + StringRef(RegName) + "\"."));
2726
2727 }
2728
2729 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
2730 Subtarget->getRegisterInfo()->regsOverlap(Reg, AMDGPU::FLAT_SCR)) {
2731 report_fatal_error(Twine("invalid register \""
2732 + StringRef(RegName) + "\" for subtarget."));
2733 }
2734
2735 switch (Reg) {
2736 case AMDGPU::M0:
2737 case AMDGPU::EXEC_LO:
2738 case AMDGPU::EXEC_HI:
2739 case AMDGPU::FLAT_SCR_LO:
2740 case AMDGPU::FLAT_SCR_HI:
2741 if (VT.getSizeInBits() == 32)
2742 return Reg;
2743 break;
2744 case AMDGPU::EXEC:
2745 case AMDGPU::FLAT_SCR:
2746 if (VT.getSizeInBits() == 64)
2747 return Reg;
2748 break;
2749 default:
2750 llvm_unreachable("missing register type checking")::llvm::llvm_unreachable_internal("missing register type checking"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2750)
;
2751 }
2752
2753 report_fatal_error(Twine("invalid type for register \""
2754 + StringRef(RegName) + "\"."));
2755}
2756
2757// If kill is not the last instruction, split the block so kill is always a
2758// proper terminator.
2759MachineBasicBlock *SITargetLowering::splitKillBlock(MachineInstr &MI,
2760 MachineBasicBlock *BB) const {
2761 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
2762
2763 MachineBasicBlock::iterator SplitPoint(&MI);
2764 ++SplitPoint;
2765
2766 if (SplitPoint == BB->end()) {
2767 // Don't bother with a new block.
2768 MI.setDesc(TII->getKillTerminatorFromPseudo(MI.getOpcode()));
2769 return BB;
2770 }
2771
2772 MachineFunction *MF = BB->getParent();
2773 MachineBasicBlock *SplitBB
2774 = MF->CreateMachineBasicBlock(BB->getBasicBlock());
2775
2776 MF->insert(++MachineFunction::iterator(BB), SplitBB);
2777 SplitBB->splice(SplitBB->begin(), BB, SplitPoint, BB->end());
2778
2779 SplitBB->transferSuccessorsAndUpdatePHIs(BB);
2780 BB->addSuccessor(SplitBB);
2781
2782 MI.setDesc(TII->getKillTerminatorFromPseudo(MI.getOpcode()));
2783 return SplitBB;
2784}
2785
2786// Do a v_movrels_b32 or v_movreld_b32 for each unique value of \p IdxReg in the
2787// wavefront. If the value is uniform and just happens to be in a VGPR, this
2788// will only do one iteration. In the worst case, this will loop 64 times.
2789//
2790// TODO: Just use v_readlane_b32 if we know the VGPR has a uniform value.
2791static MachineBasicBlock::iterator emitLoadM0FromVGPRLoop(
2792 const SIInstrInfo *TII,
2793 MachineRegisterInfo &MRI,
2794 MachineBasicBlock &OrigBB,
2795 MachineBasicBlock &LoopBB,
2796 const DebugLoc &DL,
2797 const MachineOperand &IdxReg,
2798 unsigned InitReg,
2799 unsigned ResultReg,
2800 unsigned PhiReg,
2801 unsigned InitSaveExecReg,
2802 int Offset,
2803 bool UseGPRIdxMode,
2804 bool IsIndirectSrc) {
2805 MachineBasicBlock::iterator I = LoopBB.begin();
2806
2807 unsigned PhiExec = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
2808 unsigned NewExec = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
2809 unsigned CurrentIdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2810 unsigned CondReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
2811
2812 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiReg)
2813 .addReg(InitReg)
2814 .addMBB(&OrigBB)
2815 .addReg(ResultReg)
2816 .addMBB(&LoopBB);
2817
2818 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiExec)
2819 .addReg(InitSaveExecReg)
2820 .addMBB(&OrigBB)
2821 .addReg(NewExec)
2822 .addMBB(&LoopBB);
2823
2824 // Read the next variant <- also loop target.
2825 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), CurrentIdxReg)
2826 .addReg(IdxReg.getReg(), getUndefRegState(IdxReg.isUndef()));
2827
2828 // Compare the just read M0 value to all possible Idx values.
2829 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e64), CondReg)
2830 .addReg(CurrentIdxReg)
2831 .addReg(IdxReg.getReg(), 0, IdxReg.getSubReg());
2832
2833 // Update EXEC, save the original EXEC value to VCC.
2834 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), NewExec)
2835 .addReg(CondReg, RegState::Kill);
2836
2837 MRI.setSimpleHint(NewExec, CondReg);
2838
2839 if (UseGPRIdxMode) {
2840 unsigned IdxReg;
2841 if (Offset == 0) {
2842 IdxReg = CurrentIdxReg;
2843 } else {
2844 IdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2845 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), IdxReg)
2846 .addReg(CurrentIdxReg, RegState::Kill)
2847 .addImm(Offset);
2848 }
2849 unsigned IdxMode = IsIndirectSrc ?
2850 VGPRIndexMode::SRC0_ENABLE : VGPRIndexMode::DST_ENABLE;
2851 MachineInstr *SetOn =
2852 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
2853 .addReg(IdxReg, RegState::Kill)
2854 .addImm(IdxMode);
2855 SetOn->getOperand(3).setIsUndef();
2856 } else {
2857 // Move index from VCC into M0
2858 if (Offset == 0) {
2859 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
2860 .addReg(CurrentIdxReg, RegState::Kill);
2861 } else {
2862 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
2863 .addReg(CurrentIdxReg, RegState::Kill)
2864 .addImm(Offset);
2865 }
2866 }
2867
2868 // Update EXEC, switch all done bits to 0 and all todo bits to 1.
2869 MachineInstr *InsertPt =
2870 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
2871 .addReg(AMDGPU::EXEC)
2872 .addReg(NewExec);
2873
2874 // XXX - s_xor_b64 sets scc to 1 if the result is nonzero, so can we use
2875 // s_cbranch_scc0?
2876
2877 // Loop back to V_READFIRSTLANE_B32 if there are still variants to cover.
2878 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
2879 .addMBB(&LoopBB);
2880
2881 return InsertPt->getIterator();
2882}
2883
2884// This has slightly sub-optimal regalloc when the source vector is killed by
2885// the read. The register allocator does not understand that the kill is
2886// per-workitem, so is kept alive for the whole loop so we end up not re-using a
2887// subregister from it, using 1 more VGPR than necessary. This was saved when
2888// this was expanded after register allocation.
2889static MachineBasicBlock::iterator loadM0FromVGPR(const SIInstrInfo *TII,
2890 MachineBasicBlock &MBB,
2891 MachineInstr &MI,
2892 unsigned InitResultReg,
2893 unsigned PhiReg,
2894 int Offset,
2895 bool UseGPRIdxMode,
2896 bool IsIndirectSrc) {
2897 MachineFunction *MF = MBB.getParent();
2898 MachineRegisterInfo &MRI = MF->getRegInfo();
2899 const DebugLoc &DL = MI.getDebugLoc();
2900 MachineBasicBlock::iterator I(&MI);
2901
2902 unsigned DstReg = MI.getOperand(0).getReg();
2903 unsigned SaveExec = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
2904 unsigned TmpExec = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
2905
2906 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), TmpExec);
2907
2908 // Save the EXEC mask
2909 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B64), SaveExec)
2910 .addReg(AMDGPU::EXEC);
2911
2912 // To insert the loop we need to split the block. Move everything after this
2913 // point to a new block, and insert a new empty block between the two.
2914 MachineBasicBlock *LoopBB = MF->CreateMachineBasicBlock();
2915 MachineBasicBlock *RemainderBB = MF->CreateMachineBasicBlock();
2916 MachineFunction::iterator MBBI(MBB);
2917 ++MBBI;
2918
2919 MF->insert(MBBI, LoopBB);
2920 MF->insert(MBBI, RemainderBB);
2921
2922 LoopBB->addSuccessor(LoopBB);
2923 LoopBB->addSuccessor(RemainderBB);
2924
2925 // Move the rest of the block into a new block.
2926 RemainderBB->transferSuccessorsAndUpdatePHIs(&MBB);
2927 RemainderBB->splice(RemainderBB->begin(), &MBB, I, MBB.end());
2928
2929 MBB.addSuccessor(LoopBB);
2930
2931 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
2932
2933 auto InsPt = emitLoadM0FromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, *Idx,
2934 InitResultReg, DstReg, PhiReg, TmpExec,
2935 Offset, UseGPRIdxMode, IsIndirectSrc);
2936
2937 MachineBasicBlock::iterator First = RemainderBB->begin();
2938 BuildMI(*RemainderBB, First, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
2939 .addReg(SaveExec);
2940
2941 return InsPt;
2942}
2943
2944// Returns subreg index, offset
2945static std::pair<unsigned, int>
2946computeIndirectRegAndOffset(const SIRegisterInfo &TRI,
2947 const TargetRegisterClass *SuperRC,
2948 unsigned VecReg,
2949 int Offset) {
2950 int NumElts = TRI.getRegSizeInBits(*SuperRC) / 32;
2951
2952 // Skip out of bounds offsets, or else we would end up using an undefined
2953 // register.
2954 if (Offset >= NumElts || Offset < 0)
2955 return std::make_pair(AMDGPU::sub0, Offset);
2956
2957 return std::make_pair(AMDGPU::sub0 + Offset, 0);
2958}
2959
2960// Return true if the index is an SGPR and was set.
2961static bool setM0ToIndexFromSGPR(const SIInstrInfo *TII,
2962 MachineRegisterInfo &MRI,
2963 MachineInstr &MI,
2964 int Offset,
2965 bool UseGPRIdxMode,
2966 bool IsIndirectSrc) {
2967 MachineBasicBlock *MBB = MI.getParent();
2968 const DebugLoc &DL = MI.getDebugLoc();
2969 MachineBasicBlock::iterator I(&MI);
2970
2971 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
2972 const TargetRegisterClass *IdxRC = MRI.getRegClass(Idx->getReg());
2973
2974 assert(Idx->getReg() != AMDGPU::NoRegister)((Idx->getReg() != AMDGPU::NoRegister) ? static_cast<void
> (0) : __assert_fail ("Idx->getReg() != AMDGPU::NoRegister"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2974, __PRETTY_FUNCTION__))
;
2975
2976 if (!TII->getRegisterInfo().isSGPRClass(IdxRC))
2977 return false;
2978
2979 if (UseGPRIdxMode) {
2980 unsigned IdxMode = IsIndirectSrc ?
2981 VGPRIndexMode::SRC0_ENABLE : VGPRIndexMode::DST_ENABLE;
2982 if (Offset == 0) {
2983 MachineInstr *SetOn =
2984 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
2985 .add(*Idx)
2986 .addImm(IdxMode);
2987
2988 SetOn->getOperand(3).setIsUndef();
2989 } else {
2990 unsigned Tmp = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
2991 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), Tmp)
2992 .add(*Idx)
2993 .addImm(Offset);
2994 MachineInstr *SetOn =
2995 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
2996 .addReg(Tmp, RegState::Kill)
2997 .addImm(IdxMode);
2998
2999 SetOn->getOperand(3).setIsUndef();
3000 }
3001
3002 return true;
3003 }
3004
3005 if (Offset == 0) {
3006 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3007 .add(*Idx);
3008 } else {
3009 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
3010 .add(*Idx)
3011 .addImm(Offset);
3012 }
3013
3014 return true;
3015}
3016
3017// Control flow needs to be inserted if indexing with a VGPR.
3018static MachineBasicBlock *emitIndirectSrc(MachineInstr &MI,
3019 MachineBasicBlock &MBB,
3020 const GCNSubtarget &ST) {
3021 const SIInstrInfo *TII = ST.getInstrInfo();
3022 const SIRegisterInfo &TRI = TII->getRegisterInfo();
3023 MachineFunction *MF = MBB.getParent();
3024 MachineRegisterInfo &MRI = MF->getRegInfo();
3025
3026 unsigned Dst = MI.getOperand(0).getReg();
3027 unsigned SrcReg = TII->getNamedOperand(MI, AMDGPU::OpName::src)->getReg();
3028 int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
3029
3030 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg);
3031
3032 unsigned SubReg;
3033 std::tie(SubReg, Offset)
3034 = computeIndirectRegAndOffset(TRI, VecRC, SrcReg, Offset);
3035
3036 bool UseGPRIdxMode = ST.useVGPRIndexMode(EnableVGPRIndexMode);
3037
3038 if (setM0ToIndexFromSGPR(TII, MRI, MI, Offset, UseGPRIdxMode, true)) {
3039 MachineBasicBlock::iterator I(&MI);
3040 const DebugLoc &DL = MI.getDebugLoc();
3041
3042 if (UseGPRIdxMode) {
3043 // TODO: Look at the uses to avoid the copy. This may require rescheduling
3044 // to avoid interfering with other uses, so probably requires a new
3045 // optimization pass.
3046 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
3047 .addReg(SrcReg, RegState::Undef, SubReg)
3048 .addReg(SrcReg, RegState::Implicit)
3049 .addReg(AMDGPU::M0, RegState::Implicit);
3050 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3051 } else {
3052 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
3053 .addReg(SrcReg, RegState::Undef, SubReg)
3054 .addReg(SrcReg, RegState::Implicit);
3055 }
3056
3057 MI.eraseFromParent();
3058
3059 return &MBB;
3060 }
3061
3062 const DebugLoc &DL = MI.getDebugLoc();
3063 MachineBasicBlock::iterator I(&MI);
3064
3065 unsigned PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3066 unsigned InitReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3067
3068 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), InitReg);
3069
3070 auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg,
3071 Offset, UseGPRIdxMode, true);
3072 MachineBasicBlock *LoopBB = InsPt->getParent();
3073
3074 if (UseGPRIdxMode) {
3075 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
3076 .addReg(SrcReg, RegState::Undef, SubReg)
3077 .addReg(SrcReg, RegState::Implicit)
3078 .addReg(AMDGPU::M0, RegState::Implicit);
3079 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3080 } else {
3081 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
3082 .addReg(SrcReg, RegState::Undef, SubReg)
3083 .addReg(SrcReg, RegState::Implicit);
3084 }
3085
3086 MI.eraseFromParent();
3087
3088 return LoopBB;
3089}
3090
3091static unsigned getMOVRELDPseudo(const SIRegisterInfo &TRI,
3092 const TargetRegisterClass *VecRC) {
3093 switch (TRI.getRegSizeInBits(*VecRC)) {
3094 case 32: // 4 bytes
3095 return AMDGPU::V_MOVRELD_B32_V1;
3096 case 64: // 8 bytes
3097 return AMDGPU::V_MOVRELD_B32_V2;
3098 case 128: // 16 bytes
3099 return AMDGPU::V_MOVRELD_B32_V4;
3100 case 256: // 32 bytes
3101 return AMDGPU::V_MOVRELD_B32_V8;
3102 case 512: // 64 bytes
3103 return AMDGPU::V_MOVRELD_B32_V16;
3104 default:
3105 llvm_unreachable("unsupported size for MOVRELD pseudos")::llvm::llvm_unreachable_internal("unsupported size for MOVRELD pseudos"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3105)
;
3106 }
3107}
3108
3109static MachineBasicBlock *emitIndirectDst(MachineInstr &MI,
3110 MachineBasicBlock &MBB,
3111 const GCNSubtarget &ST) {
3112 const SIInstrInfo *TII = ST.getInstrInfo();
3113 const SIRegisterInfo &TRI = TII->getRegisterInfo();
3114 MachineFunction *MF = MBB.getParent();
3115 MachineRegisterInfo &MRI = MF->getRegInfo();
3116
3117 unsigned Dst = MI.getOperand(0).getReg();
3118 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src);
3119 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3120 const MachineOperand *Val = TII->getNamedOperand(MI, AMDGPU::OpName::val);
3121 int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
3122 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg());
3123
3124 // This can be an immediate, but will be folded later.
3125 assert(Val->getReg())((Val->getReg()) ? static_cast<void> (0) : __assert_fail
("Val->getReg()", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3125, __PRETTY_FUNCTION__))
;
3126
3127 unsigned SubReg;
3128 std::tie(SubReg, Offset) = computeIndirectRegAndOffset(TRI, VecRC,
3129 SrcVec->getReg(),
3130 Offset);
3131 bool UseGPRIdxMode = ST.useVGPRIndexMode(EnableVGPRIndexMode);
3132
3133 if (Idx->getReg() == AMDGPU::NoRegister) {
3134 MachineBasicBlock::iterator I(&MI);
3135 const DebugLoc &DL = MI.getDebugLoc();
3136
3137 assert(Offset == 0)((Offset == 0) ? static_cast<void> (0) : __assert_fail (
"Offset == 0", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3137, __PRETTY_FUNCTION__))
;
3138
3139 BuildMI(MBB, I, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dst)
3140 .add(*SrcVec)
3141 .add(*Val)
3142 .addImm(SubReg);
3143
3144 MI.eraseFromParent();
3145 return &MBB;
3146 }
3147
3148 if (setM0ToIndexFromSGPR(TII, MRI, MI, Offset, UseGPRIdxMode, false)) {
3149 MachineBasicBlock::iterator I(&MI);
3150 const DebugLoc &DL = MI.getDebugLoc();
3151
3152 if (UseGPRIdxMode) {
3153 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_indirect))
3154 .addReg(SrcVec->getReg(), RegState::Undef, SubReg) // vdst
3155 .add(*Val)
3156 .addReg(Dst, RegState::ImplicitDefine)
3157 .addReg(SrcVec->getReg(), RegState::Implicit)
3158 .addReg(AMDGPU::M0, RegState::Implicit);
3159
3160 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3161 } else {
3162 const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(TRI, VecRC));
3163
3164 BuildMI(MBB, I, DL, MovRelDesc)
3165 .addReg(Dst, RegState::Define)
3166 .addReg(SrcVec->getReg())
3167 .add(*Val)
3168 .addImm(SubReg - AMDGPU::sub0);
3169 }
3170
3171 MI.eraseFromParent();
3172 return &MBB;
3173 }
3174
3175 if (Val->isReg())
3176 MRI.clearKillFlags(Val->getReg());
3177
3178 const DebugLoc &DL = MI.getDebugLoc();
3179
3180 unsigned PhiReg = MRI.createVirtualRegister(VecRC);
3181
3182 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg,
3183 Offset, UseGPRIdxMode, false);
3184 MachineBasicBlock *LoopBB = InsPt->getParent();
3185
3186 if (UseGPRIdxMode) {
3187 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOV_B32_indirect))
3188 .addReg(PhiReg, RegState::Undef, SubReg) // vdst
3189 .add(*Val) // src0
3190 .addReg(Dst, RegState::ImplicitDefine)
3191 .addReg(PhiReg, RegState::Implicit)
3192 .addReg(AMDGPU::M0, RegState::Implicit);
3193 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3194 } else {
3195 const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(TRI, VecRC));
3196
3197 BuildMI(*LoopBB, InsPt, DL, MovRelDesc)
3198 .addReg(Dst, RegState::Define)
3199 .addReg(PhiReg)
3200 .add(*Val)
3201 .addImm(SubReg - AMDGPU::sub0);
3202 }
3203
3204 MI.eraseFromParent();
3205
3206 return LoopBB;
3207}
3208
3209MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
3210 MachineInstr &MI, MachineBasicBlock *BB) const {
3211
3212 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3213 MachineFunction *MF = BB->getParent();
3214 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
3215
3216 if (TII->isMIMG(MI)) {
3217 if (MI.memoperands_empty() && MI.mayLoadOrStore()) {
3218 report_fatal_error("missing mem operand from MIMG instruction");
3219 }
3220 // Add a memoperand for mimg instructions so that they aren't assumed to
3221 // be ordered memory instuctions.
3222
3223 return BB;
3224 }
3225
3226 switch (MI.getOpcode()) {
3227 case AMDGPU::S_ADD_U64_PSEUDO:
3228 case AMDGPU::S_SUB_U64_PSEUDO: {
3229 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
3230 const DebugLoc &DL = MI.getDebugLoc();
3231
3232 MachineOperand &Dest = MI.getOperand(0);
3233 MachineOperand &Src0 = MI.getOperand(1);
3234 MachineOperand &Src1 = MI.getOperand(2);
3235
3236 unsigned DestSub0 = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3237 unsigned DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3238
3239 MachineOperand Src0Sub0 = TII->buildExtractSubRegOrImm(MI, MRI,
3240 Src0, &AMDGPU::SReg_64RegClass, AMDGPU::sub0,
3241 &AMDGPU::SReg_32_XM0RegClass);
3242 MachineOperand Src0Sub1 = TII->buildExtractSubRegOrImm(MI, MRI,
3243 Src0, &AMDGPU::SReg_64RegClass, AMDGPU::sub1,
3244 &AMDGPU::SReg_32_XM0RegClass);
3245
3246 MachineOperand Src1Sub0 = TII->buildExtractSubRegOrImm(MI, MRI,
3247 Src1, &AMDGPU::SReg_64RegClass, AMDGPU::sub0,
3248 &AMDGPU::SReg_32_XM0RegClass);
3249 MachineOperand Src1Sub1 = TII->buildExtractSubRegOrImm(MI, MRI,
3250 Src1, &AMDGPU::SReg_64RegClass, AMDGPU::sub1,
3251 &AMDGPU::SReg_32_XM0RegClass);
3252
3253 bool IsAdd = (MI.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO);
3254
3255 unsigned LoOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
3256 unsigned HiOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
3257 BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0)
3258 .add(Src0Sub0)
3259 .add(Src1Sub0);
3260 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1)
3261 .add(Src0Sub1)
3262 .add(Src1Sub1);
3263 BuildMI(*BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest.getReg())
3264 .addReg(DestSub0)
3265 .addImm(AMDGPU::sub0)
3266 .addReg(DestSub1)
3267 .addImm(AMDGPU::sub1);
3268 MI.eraseFromParent();
3269 return BB;
3270 }
3271 case AMDGPU::SI_INIT_M0: {
3272 BuildMI(*BB, MI.getIterator(), MI.getDebugLoc(),
3273 TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3274 .add(MI.getOperand(0));
3275 MI.eraseFromParent();
3276 return BB;
3277 }
3278 case AMDGPU::SI_INIT_EXEC:
3279 // This should be before all vector instructions.
3280 BuildMI(*BB, &*BB->begin(), MI.getDebugLoc(), TII->get(AMDGPU::S_MOV_B64),
3281 AMDGPU::EXEC)
3282 .addImm(MI.getOperand(0).getImm());
3283 MI.eraseFromParent();
3284 return BB;
3285
3286 case AMDGPU::SI_INIT_EXEC_FROM_INPUT: {
3287 // Extract the thread count from an SGPR input and set EXEC accordingly.
3288 // Since BFM can't shift by 64, handle that case with CMP + CMOV.
3289 //
3290 // S_BFE_U32 count, input, {shift, 7}
3291 // S_BFM_B64 exec, count, 0
3292 // S_CMP_EQ_U32 count, 64
3293 // S_CMOV_B64 exec, -1
3294 MachineInstr *FirstMI = &*BB->begin();
3295 MachineRegisterInfo &MRI = MF->getRegInfo();
3296 unsigned InputReg = MI.getOperand(0).getReg();
3297 unsigned CountReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3298 bool Found = false;
3299
3300 // Move the COPY of the input reg to the beginning, so that we can use it.
3301 for (auto I = BB->begin(); I != &MI; I++) {
3302 if (I->getOpcode() != TargetOpcode::COPY ||
3303 I->getOperand(0).getReg() != InputReg)
3304 continue;
3305
3306 if (I == FirstMI) {
3307 FirstMI = &*++BB->begin();
3308 } else {
3309 I->removeFromParent();
3310 BB->insert(FirstMI, &*I);
3311 }
3312 Found = true;
3313 break;
3314 }
3315 assert(Found)((Found) ? static_cast<void> (0) : __assert_fail ("Found"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3315, __PRETTY_FUNCTION__))
;
3316 (void)Found;
3317
3318 // This should be before all vector instructions.
3319 BuildMI(*BB, FirstMI, DebugLoc(), TII->get(AMDGPU::S_BFE_U32), CountReg)
3320 .addReg(InputReg)
3321 .addImm((MI.getOperand(1).getImm() & 0x7f) | 0x70000);
3322 BuildMI(*BB, FirstMI, DebugLoc(), TII->get(AMDGPU::S_BFM_B64),
3323 AMDGPU::EXEC)
3324 .addReg(CountReg)
3325 .addImm(0);
3326 BuildMI(*BB, FirstMI, DebugLoc(), TII->get(AMDGPU::S_CMP_EQ_U32))
3327 .addReg(CountReg, RegState::Kill)
3328 .addImm(64);
3329 BuildMI(*BB, FirstMI, DebugLoc(), TII->get(AMDGPU::S_CMOV_B64),
3330 AMDGPU::EXEC)
3331 .addImm(-1);
3332 MI.eraseFromParent();
3333 return BB;
3334 }
3335
3336 case AMDGPU::GET_GROUPSTATICSIZE: {
3337 DebugLoc DL = MI.getDebugLoc();
3338 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_MOV_B32))
3339 .add(MI.getOperand(0))
3340 .addImm(MFI->getLDSSize());
3341 MI.eraseFromParent();
3342 return BB;
3343 }
3344 case AMDGPU::SI_INDIRECT_SRC_V1:
3345 case AMDGPU::SI_INDIRECT_SRC_V2:
3346 case AMDGPU::SI_INDIRECT_SRC_V4:
3347 case AMDGPU::SI_INDIRECT_SRC_V8:
3348 case AMDGPU::SI_INDIRECT_SRC_V16:
3349 return emitIndirectSrc(MI, *BB, *getSubtarget());
3350 case AMDGPU::SI_INDIRECT_DST_V1:
3351 case AMDGPU::SI_INDIRECT_DST_V2:
3352 case AMDGPU::SI_INDIRECT_DST_V4:
3353 case AMDGPU::SI_INDIRECT_DST_V8:
3354 case AMDGPU::SI_INDIRECT_DST_V16:
3355 return emitIndirectDst(MI, *BB, *getSubtarget());
3356 case AMDGPU::SI_KILL_F32_COND_IMM_PSEUDO:
3357 case AMDGPU::SI_KILL_I1_PSEUDO:
3358 return splitKillBlock(MI, BB);
3359 case AMDGPU::V_CNDMASK_B64_PSEUDO: {
3360 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
3361
3362 unsigned Dst = MI.getOperand(0).getReg();
3363 unsigned Src0 = MI.getOperand(1).getReg();
3364 unsigned Src1 = MI.getOperand(2).getReg();
3365 const DebugLoc &DL = MI.getDebugLoc();
3366 unsigned SrcCond = MI.getOperand(3).getReg();
3367
3368 unsigned DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3369 unsigned DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3370 unsigned SrcCondCopy = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
3371
3372 BuildMI(*BB, MI, DL, TII->get(AMDGPU::COPY), SrcCondCopy)
3373 .addReg(SrcCond);
3374 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
3375 .addReg(Src0, 0, AMDGPU::sub0)
3376 .addReg(Src1, 0, AMDGPU::sub0)
3377 .addReg(SrcCondCopy);
3378 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
3379 .addReg(Src0, 0, AMDGPU::sub1)
3380 .addReg(Src1, 0, AMDGPU::sub1)
3381 .addReg(SrcCondCopy);
3382
3383 BuildMI(*BB, MI, DL, TII->get(AMDGPU::REG_SEQUENCE), Dst)
3384 .addReg(DstLo)
3385 .addImm(AMDGPU::sub0)
3386 .addReg(DstHi)
3387 .addImm(AMDGPU::sub1);
3388 MI.eraseFromParent();
3389 return BB;
3390 }
3391 case AMDGPU::SI_BR_UNDEF: {
3392 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3393 const DebugLoc &DL = MI.getDebugLoc();
3394 MachineInstr *Br = BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
3395 .add(MI.getOperand(0));
3396 Br->getOperand(1).setIsUndef(true); // read undef SCC
3397 MI.eraseFromParent();
3398 return BB;
3399 }
3400 case AMDGPU::ADJCALLSTACKUP:
3401 case AMDGPU::ADJCALLSTACKDOWN: {
3402 const SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
3403 MachineInstrBuilder MIB(*MF, &MI);
3404
3405 // Add an implicit use of the frame offset reg to prevent the restore copy
3406 // inserted after the call from being reorderd after stack operations in the
3407 // the caller's frame.
3408 MIB.addReg(Info->getStackPtrOffsetReg(), RegState::ImplicitDefine)
3409 .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit)
3410 .addReg(Info->getFrameOffsetReg(), RegState::Implicit);
3411 return BB;
3412 }
3413 case AMDGPU::SI_CALL_ISEL:
3414 case AMDGPU::SI_TCRETURN_ISEL: {
3415 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3416 const DebugLoc &DL = MI.getDebugLoc();
3417 unsigned ReturnAddrReg = TII->getRegisterInfo().getReturnAddressReg(*MF);
3418
3419 MachineRegisterInfo &MRI = MF->getRegInfo();
3420 unsigned GlobalAddrReg = MI.getOperand(0).getReg();
3421 MachineInstr *PCRel = MRI.getVRegDef(GlobalAddrReg);
3422 assert(PCRel->getOpcode() == AMDGPU::SI_PC_ADD_REL_OFFSET)((PCRel->getOpcode() == AMDGPU::SI_PC_ADD_REL_OFFSET) ? static_cast
<void> (0) : __assert_fail ("PCRel->getOpcode() == AMDGPU::SI_PC_ADD_REL_OFFSET"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3422, __PRETTY_FUNCTION__))
;
3423
3424 const GlobalValue *G = PCRel->getOperand(1).getGlobal();
3425
3426 MachineInstrBuilder MIB;
3427 if (MI.getOpcode() == AMDGPU::SI_CALL_ISEL) {
3428 MIB = BuildMI(*BB, MI, DL, TII->get(AMDGPU::SI_CALL), ReturnAddrReg)
3429 .add(MI.getOperand(0))
3430 .addGlobalAddress(G);
3431 } else {
3432 MIB = BuildMI(*BB, MI, DL, TII->get(AMDGPU::SI_TCRETURN))
3433 .add(MI.getOperand(0))
3434 .addGlobalAddress(G);
3435
3436 // There is an additional imm operand for tcreturn, but it should be in the
3437 // right place already.
3438 }
3439
3440 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
3441 MIB.add(MI.getOperand(I));
3442
3443 MIB.cloneMemRefs(MI);
3444 MI.eraseFromParent();
3445 return BB;
3446 }
3447 default:
3448 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
3449 }
3450}
3451
3452bool SITargetLowering::hasBitPreservingFPLogic(EVT VT) const {
3453 return isTypeLegal(VT.getScalarType());
3454}
3455
3456bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {
3457 // This currently forces unfolding various combinations of fsub into fma with
3458 // free fneg'd operands. As long as we have fast FMA (controlled by
3459 // isFMAFasterThanFMulAndFAdd), we should perform these.
3460
3461 // When fma is quarter rate, for f64 where add / sub are at best half rate,
3462 // most of these combines appear to be cycle neutral but save on instruction
3463 // count / code size.
3464 return true;
3465}
3466
3467EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
3468 EVT VT) const {
3469 if (!VT.isVector()) {
3470 return MVT::i1;
3471 }
3472 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
3473}
3474
3475MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT VT) const {
3476 // TODO: Should i16 be used always if legal? For now it would force VALU
3477 // shifts.
3478 return (VT == MVT::i16) ? MVT::i16 : MVT::i32;
3479}
3480
3481// Answering this is somewhat tricky and depends on the specific device which
3482// have different rates for fma or all f64 operations.
3483//
3484// v_fma_f64 and v_mul_f64 always take the same number of cycles as each other
3485// regardless of which device (although the number of cycles differs between
3486// devices), so it is always profitable for f64.
3487//
3488// v_fma_f32 takes 4 or 16 cycles depending on the device, so it is profitable
3489// only on full rate devices. Normally, we should prefer selecting v_mad_f32
3490// which we can always do even without fused FP ops since it returns the same
3491// result as the separate operations and since it is always full
3492// rate. Therefore, we lie and report that it is not faster for f32. v_mad_f32
3493// however does not support denormals, so we do report fma as faster if we have
3494// a fast fma device and require denormals.
3495//
3496bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
3497 VT = VT.getScalarType();
3498
3499 switch (VT.getSimpleVT().SimpleTy) {
3500 case MVT::f32: {
3501 // This is as fast on some subtargets. However, we always have full rate f32
3502 // mad available which returns the same result as the separate operations
3503 // which we should prefer over fma. We can't use this if we want to support
3504 // denormals, so only report this in these cases.
3505 if (Subtarget->hasFP32Denormals())
3506 return Subtarget->hasFastFMAF32() || Subtarget->hasDLInsts();
3507
3508 // If the subtarget has v_fmac_f32, that's just as good as v_mac_f32.
3509 return Subtarget->hasFastFMAF32() && Subtarget->hasDLInsts();
3510 }
3511 case MVT::f64:
3512 return true;
3513 case MVT::f16:
3514 return Subtarget->has16BitInsts() && Subtarget->hasFP16Denormals();
3515 default:
3516 break;
3517 }
3518
3519 return false;
3520}
3521
3522//===----------------------------------------------------------------------===//
3523// Custom DAG Lowering Operations
3524//===----------------------------------------------------------------------===//
3525
3526// Work around LegalizeDAG doing the wrong thing and fully scalarizing if the
3527// wider vector type is legal.
3528SDValue SITargetLowering::splitUnaryVectorOp(SDValue Op,
3529 SelectionDAG &DAG) const {
3530 unsigned Opc = Op.getOpcode();
3531 EVT VT = Op.getValueType();
3532 assert(VT == MVT::v4f16)((VT == MVT::v4f16) ? static_cast<void> (0) : __assert_fail
("VT == MVT::v4f16", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3532, __PRETTY_FUNCTION__))
;
3533
3534 SDValue Lo, Hi;
3535 std::tie(Lo, Hi) = DAG.SplitVectorOperand(Op.getNode(), 0);
3536
3537 SDLoc SL(Op);
3538 SDValue OpLo = DAG.getNode(Opc, SL, Lo.getValueType(), Lo,
3539 Op->getFlags());
3540 SDValue OpHi = DAG.getNode(Opc, SL, Hi.getValueType(), Hi,
3541 Op->getFlags());
3542
3543 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
3544}
3545
3546// Work around LegalizeDAG doing the wrong thing and fully scalarizing if the
3547// wider vector type is legal.
3548SDValue SITargetLowering::splitBinaryVectorOp(SDValue Op,
3549 SelectionDAG &DAG) const {
3550 unsigned Opc = Op.getOpcode();
3551 EVT VT = Op.getValueType();
3552 assert(VT == MVT::v4i16 || VT == MVT::v4f16)((VT == MVT::v4i16 || VT == MVT::v4f16) ? static_cast<void
> (0) : __assert_fail ("VT == MVT::v4i16 || VT == MVT::v4f16"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3552, __PRETTY_FUNCTION__))
;
3553
3554 SDValue Lo0, Hi0;
3555 std::tie(Lo0, Hi0) = DAG.SplitVectorOperand(Op.getNode(), 0);
3556 SDValue Lo1, Hi1;
3557 std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1);
3558
3559 SDLoc SL(Op);
3560
3561 SDValue OpLo = DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1,
3562 Op->getFlags());
3563 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1,
3564 Op->getFlags());
3565
3566 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
3567}
3568
3569SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3570 switch (Op.getOpcode()) {
3571 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
3572 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
3573 case ISD::LOAD: {
3574 SDValue Result = LowerLOAD(Op, DAG);
3575 assert((!Result.getNode() ||(((!Result.getNode() || Result.getNode()->getNumValues() ==
2) && "Load should return a value and a chain") ? static_cast
<void> (0) : __assert_fail ("(!Result.getNode() || Result.getNode()->getNumValues() == 2) && \"Load should return a value and a chain\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3577, __PRETTY_FUNCTION__))
3576 Result.getNode()->getNumValues() == 2) &&(((!Result.getNode() || Result.getNode()->getNumValues() ==
2) && "Load should return a value and a chain") ? static_cast
<void> (0) : __assert_fail ("(!Result.getNode() || Result.getNode()->getNumValues() == 2) && \"Load should return a value and a chain\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3577, __PRETTY_FUNCTION__))
3577 "Load should return a value and a chain")(((!Result.getNode() || Result.getNode()->getNumValues() ==
2) && "Load should return a value and a chain") ? static_cast
<void> (0) : __assert_fail ("(!Result.getNode() || Result.getNode()->getNumValues() == 2) && \"Load should return a value and a chain\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3577, __PRETTY_FUNCTION__))
;
3578 return Result;
3579 }
3580
3581 case ISD::FSIN:
3582 case ISD::FCOS:
3583 return LowerTrig(Op, DAG);
3584 case ISD::SELECT: return LowerSELECT(Op, DAG);
3585 case ISD::FDIV: return LowerFDIV(Op, DAG);
3586 case ISD::ATOMIC_CMP_SWAP: return LowerATOMIC_CMP_SWAP(Op, DAG);
3587 case ISD::STORE: return LowerSTORE(Op, DAG);
3588 case ISD::GlobalAddress: {
3589 MachineFunction &MF = DAG.getMachineFunction();
3590 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
3591 return LowerGlobalAddress(MFI, Op, DAG);
3592 }
3593 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3594 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
3595 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
3596 case ISD::ADDRSPACECAST: return lowerADDRSPACECAST(Op, DAG);
3597 case ISD::INSERT_VECTOR_ELT:
3598 return lowerINSERT_VECTOR_ELT(Op, DAG);
3599 case ISD::EXTRACT_VECTOR_ELT:
3600 return lowerEXTRACT_VECTOR_ELT(Op, DAG);
3601 case ISD::BUILD_VECTOR:
3602 return lowerBUILD_VECTOR(Op, DAG);
3603 case ISD::FP_ROUND:
3604 return lowerFP_ROUND(Op, DAG);
3605 case ISD::TRAP:
3606 return lowerTRAP(Op, DAG);
3607 case ISD::DEBUGTRAP:
3608 return lowerDEBUGTRAP(Op, DAG);
3609 case ISD::FABS:
3610 case ISD::FNEG:
3611 case ISD::FCANONICALIZE:
3612 return splitUnaryVectorOp(Op, DAG);
3613 case ISD::FMINNUM:
3614 case ISD::FMAXNUM:
3615 return lowerFMINNUM_FMAXNUM(Op, DAG);
3616 case ISD::SHL:
3617 case ISD::SRA:
3618 case ISD::SRL:
3619 case ISD::ADD:
3620 case ISD::SUB:
3621 case ISD::MUL:
3622 case ISD::SMIN:
3623 case ISD::SMAX:
3624 case ISD::UMIN:
3625 case ISD::UMAX:
3626 case ISD::FADD:
3627 case ISD::FMUL:
3628 case ISD::FMINNUM_IEEE:
3629 case ISD::FMAXNUM_IEEE:
3630 return splitBinaryVectorOp(Op, DAG);
3631 }
3632 return SDValue();
3633}
3634
3635static SDValue adjustLoadValueTypeImpl(SDValue Result, EVT LoadVT,
3636 const SDLoc &DL,
3637 SelectionDAG &DAG, bool Unpacked) {
3638 if (!LoadVT.isVector())
3639 return Result;
3640
3641 if (Unpacked) { // From v2i32/v4i32 back to v2f16/v4f16.
3642 // Truncate to v2i16/v4i16.
3643 EVT IntLoadVT = LoadVT.changeTypeToInteger();
3644
3645 // Workaround legalizer not scalarizing truncate after vector op
3646 // legalization byt not creating intermediate vector trunc.
3647 SmallVector<SDValue, 4> Elts;
3648 DAG.ExtractVectorElements(Result, Elts);
3649 for (SDValue &Elt : Elts)
3650 Elt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Elt);
3651
3652 Result = DAG.getBuildVector(IntLoadVT, DL, Elts);
3653
3654 // Bitcast to original type (v2f16/v4f16).
3655 return DAG.getNode(ISD::BITCAST, DL, LoadVT, Result);
3656 }
3657
3658 // Cast back to the original packed type.
3659 return DAG.getNode(ISD::BITCAST, DL, LoadVT, Result);
3660}
3661
3662SDValue SITargetLowering::adjustLoadValueType(unsigned Opcode,
3663 MemSDNode *M,
3664 SelectionDAG &DAG,
3665 ArrayRef<SDValue> Ops,
3666 bool IsIntrinsic) const {
3667 SDLoc DL(M);
3668
3669 bool Unpacked = Subtarget->hasUnpackedD16VMem();
3670 EVT LoadVT = M->getValueType(0);
3671
3672 EVT EquivLoadVT = LoadVT;
3673 if (Unpacked && LoadVT.isVector()) {
3674 EquivLoadVT = LoadVT.isVector() ?
3675 EVT::getVectorVT(*DAG.getContext(), MVT::i32,
3676 LoadVT.getVectorNumElements()) : LoadVT;
3677 }
3678
3679 // Change from v4f16/v2f16 to EquivLoadVT.
3680 SDVTList VTList = DAG.getVTList(EquivLoadVT, MVT::Other);
3681
3682 SDValue Load
3683 = DAG.getMemIntrinsicNode(
3684 IsIntrinsic ? (unsigned)ISD::INTRINSIC_W_CHAIN : Opcode, DL,
3685 VTList, Ops, M->getMemoryVT(),
3686 M->getMemOperand());
3687 if (!Unpacked) // Just adjusted the opcode.
3688 return Load;
3689
3690 SDValue Adjusted = adjustLoadValueTypeImpl(Load, LoadVT, DL, DAG, Unpacked);
3691
3692 return DAG.getMergeValues({ Adjusted, Load.getValue(1) }, DL);
3693}
3694
3695static SDValue lowerICMPIntrinsic(const SITargetLowering &TLI,
3696 SDNode *N, SelectionDAG &DAG) {
3697 EVT VT = N->getValueType(0);
3698 const auto *CD = dyn_cast<ConstantSDNode>(N->getOperand(3));
3699 if (!CD)
3700 return DAG.getUNDEF(VT);
3701
3702 int CondCode = CD->getSExtValue();
3703 if (CondCode < ICmpInst::Predicate::FIRST_ICMP_PREDICATE ||
3704 CondCode > ICmpInst::Predicate::LAST_ICMP_PREDICATE)
3705 return DAG.getUNDEF(VT);
3706
3707 ICmpInst::Predicate IcInput = static_cast<ICmpInst::Predicate>(CondCode);
3708
3709
3710 SDValue LHS = N->getOperand(1);
3711 SDValue RHS = N->getOperand(2);
3712
3713 SDLoc DL(N);
3714
3715 EVT CmpVT = LHS.getValueType();
3716 if (CmpVT == MVT::i16 && !TLI.isTypeLegal(MVT::i16)) {
3717 unsigned PromoteOp = ICmpInst::isSigned(IcInput) ?
3718 ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3719 LHS = DAG.getNode(PromoteOp, DL, MVT::i32, LHS);
3720 RHS = DAG.getNode(PromoteOp, DL, MVT::i32, RHS);
3721 }
3722
3723 ISD::CondCode CCOpcode = getICmpCondCode(IcInput);
3724
3725 return DAG.getNode(AMDGPUISD::SETCC, DL, VT, LHS, RHS,
3726 DAG.getCondCode(CCOpcode));
3727}
3728
3729static SDValue lowerFCMPIntrinsic(const SITargetLowering &TLI,
3730 SDNode *N, SelectionDAG &DAG) {
3731 EVT VT = N->getValueType(0);
3732 const auto *CD = dyn_cast<ConstantSDNode>(N->getOperand(3));
3733 if (!CD)
3734 return DAG.getUNDEF(VT);
3735
3736 int CondCode = CD->getSExtValue();
3737 if (CondCode < FCmpInst::Predicate::FIRST_FCMP_PREDICATE ||
3738 CondCode > FCmpInst::Predicate::LAST_FCMP_PREDICATE) {
3739 return DAG.getUNDEF(VT);
3740 }
3741
3742 SDValue Src0 = N->getOperand(1);
3743 SDValue Src1 = N->getOperand(2);
3744 EVT CmpVT = Src0.getValueType();
3745 SDLoc SL(N);
3746
3747 if (CmpVT == MVT::f16 && !TLI.isTypeLegal(CmpVT)) {
3748 Src0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
3749 Src1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1);
3750 }
3751
3752 FCmpInst::Predicate IcInput = static_cast<FCmpInst::Predicate>(CondCode);
3753 ISD::CondCode CCOpcode = getFCmpCondCode(IcInput);
3754 return DAG.getNode(AMDGPUISD::SETCC, SL, VT, Src0,
3755 Src1, DAG.getCondCode(CCOpcode));
3756}
3757
3758void SITargetLowering::ReplaceNodeResults(SDNode *N,
3759 SmallVectorImpl<SDValue> &Results,
3760 SelectionDAG &DAG) const {
3761 switch (N->getOpcode()) {
3762 case ISD::INSERT_VECTOR_ELT: {
3763 if (SDValue Res = lowerINSERT_VECTOR_ELT(SDValue(N, 0), DAG))
3764 Results.push_back(Res);
3765 return;
3766 }
3767 case ISD::EXTRACT_VECTOR_ELT: {
3768 if (SDValue Res = lowerEXTRACT_VECTOR_ELT(SDValue(N, 0), DAG))
3769 Results.push_back(Res);
3770 return;
3771 }
3772 case ISD::INTRINSIC_WO_CHAIN: {
3773 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3774 switch (IID) {
3775 case Intrinsic::amdgcn_cvt_pkrtz: {
3776 SDValue Src0 = N->getOperand(1);
3777 SDValue Src1 = N->getOperand(2);
3778 SDLoc SL(N);
3779 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_PKRTZ_F16_F32, SL, MVT::i32,
3780 Src0, Src1);
3781 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Cvt));
3782 return;
3783 }
3784 case Intrinsic::amdgcn_cvt_pknorm_i16:
3785 case Intrinsic::amdgcn_cvt_pknorm_u16:
3786 case Intrinsic::amdgcn_cvt_pk_i16:
3787 case Intrinsic::amdgcn_cvt_pk_u16: {
3788 SDValue Src0 = N->getOperand(1);
3789 SDValue Src1 = N->getOperand(2);
3790 SDLoc SL(N);
3791 unsigned Opcode;
3792
3793 if (IID == Intrinsic::amdgcn_cvt_pknorm_i16)
3794 Opcode = AMDGPUISD::CVT_PKNORM_I16_F32;
3795 else if (IID == Intrinsic::amdgcn_cvt_pknorm_u16)
3796 Opcode = AMDGPUISD::CVT_PKNORM_U16_F32;
3797 else if (IID == Intrinsic::amdgcn_cvt_pk_i16)
3798 Opcode = AMDGPUISD::CVT_PK_I16_I32;
3799 else
3800 Opcode = AMDGPUISD::CVT_PK_U16_U32;
3801
3802 EVT VT = N->getValueType(0);
3803 if (isTypeLegal(VT))
3804 Results.push_back(DAG.getNode(Opcode, SL, VT, Src0, Src1));
3805 else {
3806 SDValue Cvt = DAG.getNode(Opcode, SL, MVT::i32, Src0, Src1);
3807 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, Cvt));
3808 }
3809 return;
3810 }
3811 }
3812 break;
3813 }
3814 case ISD::INTRINSIC_W_CHAIN: {
3815 if (SDValue Res = LowerINTRINSIC_W_CHAIN(SDValue(N, 0), DAG)) {
3816 Results.push_back(Res);
3817 Results.push_back(Res.getValue(1));
3818 return;
3819 }
3820
3821 break;
3822 }
3823 case ISD::SELECT: {
3824 SDLoc SL(N);
3825 EVT VT = N->getValueType(0);
3826 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
3827 SDValue LHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(1));
3828 SDValue RHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(2));
3829
3830 EVT SelectVT = NewVT;
3831 if (NewVT.bitsLT(MVT::i32)) {
3832 LHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, LHS);
3833 RHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, RHS);
3834 SelectVT = MVT::i32;
3835 }
3836
3837 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, SelectVT,
3838 N->getOperand(0), LHS, RHS);
3839
3840 if (NewVT != SelectVT)
3841 NewSelect = DAG.getNode(ISD::TRUNCATE, SL, NewVT, NewSelect);
3842 Results.push_back(DAG.getNode(ISD::BITCAST, SL, VT, NewSelect));
3843 return;
3844 }
3845 case ISD::FNEG: {
3846 if (N->getValueType(0) != MVT::v2f16)
3847 break;
3848
3849 SDLoc SL(N);
3850 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, N->getOperand(0));
3851
3852 SDValue Op = DAG.getNode(ISD::XOR, SL, MVT::i32,
3853 BC,
3854 DAG.getConstant(0x80008000, SL, MVT::i32));
3855 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Op));
3856 return;
3857 }
3858 case ISD::FABS: {
3859 if (N->getValueType(0) != MVT::v2f16)
3860 break;
3861
3862 SDLoc SL(N);
3863 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, N->getOperand(0));
3864
3865 SDValue Op = DAG.getNode(ISD::AND, SL, MVT::i32,
3866 BC,
3867 DAG.getConstant(0x7fff7fff, SL, MVT::i32));
3868 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Op));
3869 return;
3870 }
3871 default:
3872 break;
3873 }
3874}
3875
3876/// Helper function for LowerBRCOND
3877static SDNode *findUser(SDValue Value, unsigned Opcode) {
3878
3879 SDNode *Parent = Value.getNode();
3880 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
3881 I != E; ++I) {
3882
3883 if (I.getUse().get() != Value)
3884 continue;
3885
3886 if (I->getOpcode() == Opcode)
3887 return *I;
3888 }
3889 return nullptr;
3890}
3891
3892unsigned SITargetLowering::isCFIntrinsic(const SDNode *Intr) const {
3893 if (Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
3894 switch (cast<ConstantSDNode>(Intr->getOperand(1))->getZExtValue()) {
3895 case Intrinsic::amdgcn_if:
3896 return AMDGPUISD::IF;
3897 case Intrinsic::amdgcn_else:
3898 return AMDGPUISD::ELSE;
3899 case Intrinsic::amdgcn_loop:
3900 return AMDGPUISD::LOOP;
3901 case Intrinsic::amdgcn_end_cf:
3902 llvm_unreachable("should not occur")::llvm::llvm_unreachable_internal("should not occur", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3902)
;
3903 default:
3904 return 0;
3905 }
3906 }
3907
3908 // break, if_break, else_break are all only used as inputs to loop, not
3909 // directly as branch conditions.
3910 return 0;
3911}
3912
3913void SITargetLowering::createDebuggerPrologueStackObjects(
3914 MachineFunction &MF) const {
3915 // Create stack objects that are used for emitting debugger prologue.
3916 //
3917 // Debugger prologue writes work group IDs and work item IDs to scratch memory
3918 // at fixed location in the following format:
3919 // offset 0: work group ID x
3920 // offset 4: work group ID y
3921 // offset 8: work group ID z
3922 // offset 16: work item ID x
3923 // offset 20: work item ID y
3924 // offset 24: work item ID z
3925 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
3926 int ObjectIdx = 0;
3927
3928 // For each dimension:
3929 for (unsigned i = 0; i < 3; ++i) {
3930 // Create fixed stack object for work group ID.
3931 ObjectIdx = MF.getFrameInfo().CreateFixedObject(4, i * 4, true);
3932 Info->setDebuggerWorkGroupIDStackObjectIndex(i, ObjectIdx);
3933 // Create fixed stack object for work item ID.
3934 ObjectIdx = MF.getFrameInfo().CreateFixedObject(4, i * 4 + 16, true);
3935 Info->setDebuggerWorkItemIDStackObjectIndex(i, ObjectIdx);
3936 }
3937}
3938
3939bool SITargetLowering::shouldEmitFixup(const GlobalValue *GV) const {
3940 const Triple &TT = getTargetMachine().getTargetTriple();
3941 return (GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
3942 GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
3943 AMDGPU::shouldEmitConstantsToTextSection(TT);
3944}
3945
3946bool SITargetLowering::shouldEmitGOTReloc(const GlobalValue *GV) const {
3947 return (GV->getType()->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS ||
3948 GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
3949 GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
3950 !shouldEmitFixup(GV) &&
3951 !getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
3952}
3953
3954bool SITargetLowering::shouldEmitPCReloc(const GlobalValue *GV) const {
3955 return !shouldEmitFixup(GV) && !shouldEmitGOTReloc(GV);
3956}
3957
3958/// This transforms the control flow intrinsics to get the branch destination as
3959/// last parameter, also switches branch target with BR if the need arise
3960SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
3961 SelectionDAG &DAG) const {
3962 SDLoc DL(BRCOND);
3963
3964 SDNode *Intr = BRCOND.getOperand(1).getNode();
3965 SDValue Target = BRCOND.getOperand(2);
3966 SDNode *BR = nullptr;
3967 SDNode *SetCC = nullptr;
3968
3969 if (Intr->getOpcode() == ISD::SETCC) {
3970 // As long as we negate the condition everything is fine
3971 SetCC = Intr;
3972 Intr = SetCC->getOperand(0).getNode();
3973
3974 } else {
3975 // Get the target from BR if we don't negate the condition
3976 BR = findUser(BRCOND, ISD::BR);
3977 Target = BR->getOperand(1);
3978 }
3979
3980 // FIXME: This changes the types of the intrinsics instead of introducing new
3981 // nodes with the correct types.
3982 // e.g. llvm.amdgcn.loop
3983
3984 // eg: i1,ch = llvm.amdgcn.loop t0, TargetConstant:i32<6271>, t3
3985 // => t9: ch = llvm.amdgcn.loop t0, TargetConstant:i32<6271>, t3, BasicBlock:ch<bb1 0x7fee5286d088>
3986
3987 unsigned CFNode = isCFIntrinsic(Intr);
3988 if (CFNode == 0) {
3989 // This is a uniform branch so we don't need to legalize.
3990 return BRCOND;
3991 }
3992
3993 bool HaveChain = Intr->getOpcode() == ISD::INTRINSIC_VOID ||
3994 Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN;
3995
3996 assert(!SetCC ||((!SetCC || (SetCC->getConstantOperandVal(1) == 1 &&
cast<CondCodeSDNode>(SetCC->getOperand(2).getNode()
)->get() == ISD::SETNE)) ? static_cast<void> (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3999, __PRETTY_FUNCTION__))
3997 (SetCC->getConstantOperandVal(1) == 1 &&((!SetCC || (SetCC->getConstantOperandVal(1) == 1 &&
cast<CondCodeSDNode>(SetCC->getOperand(2).getNode()
)->get() == ISD::SETNE)) ? static_cast<void> (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3999, __PRETTY_FUNCTION__))
3998 cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==((!SetCC || (SetCC->getConstantOperandVal(1) == 1 &&
cast<CondCodeSDNode>(SetCC->getOperand(2).getNode()
)->get() == ISD::SETNE)) ? static_cast<void> (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3999, __PRETTY_FUNCTION__))
3999 ISD::SETNE))((!SetCC || (SetCC->getConstantOperandVal(1) == 1 &&
cast<CondCodeSDNode>(SetCC->getOperand(2).getNode()
)->get() == ISD::SETNE)) ? static_cast<void> (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3999, __PRETTY_FUNCTION__))
;
4000
4001 // operands of the new intrinsic call
4002 SmallVector<SDValue, 4> Ops;
4003 if (HaveChain)
4004 Ops.push_back(BRCOND.getOperand(0));
4005
4006 Ops.append(Intr->op_begin() + (HaveChain ? 2 : 1), Intr->op_end());
4007 Ops.push_back(Target);
4008
4009 ArrayRef<EVT> Res(Intr->value_begin() + 1, Intr->value_end());
4010
4011 // build the new intrinsic call
4012 SDNode *Result = DAG.getNode(CFNode, DL, DAG.getVTList(Res), Ops).getNode();
4013
4014 if (!HaveChain) {
4015 SDValue Ops[] = {
4016 SDValue(Result, 0),
4017 BRCOND.getOperand(0)
4018 };
4019
4020 Result = DAG.getMergeValues(Ops, DL).getNode();
4021 }
4022
4023 if (BR) {
4024 // Give the branch instruction our target
4025 SDValue Ops[] = {
4026 BR->getOperand(0),
4027 BRCOND.getOperand(2)
4028 };
4029 SDValue NewBR = DAG.getNode(ISD::BR, DL, BR->getVTList(), Ops);
4030 DAG.ReplaceAllUsesWith(BR, NewBR.getNode());
4031 BR = NewBR.getNode();
4032 }
4033
4034 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
4035
4036 // Copy the intrinsic results to registers
4037 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
4038 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
4039 if (!CopyToReg)
4040 continue;
4041
4042 Chain = DAG.getCopyToReg(
4043 Chain, DL,
4044 CopyToReg->getOperand(1),
4045 SDValue(Result, i - 1),
4046 SDValue());
4047
4048 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
4049 }
4050
4051 // Remove the old intrinsic from the chain
4052 DAG.ReplaceAllUsesOfValueWith(
4053 SDValue(Intr, Intr->getNumValues() - 1),
4054 Intr->getOperand(0));
4055
4056 return Chain;
4057}
4058
4059SDValue SITargetLowering::getFPExtOrFPTrunc(SelectionDAG &DAG,
4060 SDValue Op,
4061 const SDLoc &DL,
4062 EVT VT) const {
4063 return Op.getValueType().bitsLE(VT) ?
4064 DAG.getNode(ISD::FP_EXTEND, DL, VT, Op) :
4065 DAG.getNode(ISD::FTRUNC, DL, VT, Op);
4066}
4067
4068SDValue SITargetLowering::lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
4069 assert(Op.getValueType() == MVT::f16 &&((Op.getValueType() == MVT::f16 && "Do not know how to custom lower FP_ROUND for non-f16 type"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::f16 && \"Do not know how to custom lower FP_ROUND for non-f16 type\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4070, __PRETTY_FUNCTION__))
4070 "Do not know how to custom lower FP_ROUND for non-f16 type")((Op.getValueType() == MVT::f16 && "Do not know how to custom lower FP_ROUND for non-f16 type"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::f16 && \"Do not know how to custom lower FP_ROUND for non-f16 type\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4070, __PRETTY_FUNCTION__))
;
4071
4072 SDValue Src = Op.getOperand(0);
4073 EVT SrcVT = Src.getValueType();
4074 if (SrcVT != MVT::f64)
4075 return Op;
4076
4077 SDLoc DL(Op);
4078
4079 SDValue FpToFp16 = DAG.getNode(ISD::FP_TO_FP16, DL, MVT::i32, Src);
4080 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FpToFp16);
4081 return DAG.getNode(ISD::BITCAST, DL, MVT::f16, Trunc);
4082}
4083
4084SDValue SITargetLowering::lowerFMINNUM_FMAXNUM(SDValue Op,
4085 SelectionDAG &DAG) const {
4086 EVT VT = Op.getValueType();
4087 bool IsIEEEMode = Subtarget->enableIEEEBit(DAG.getMachineFunction());
4088
4089 // FIXME: Assert during eslection that this is only selected for
4090 // ieee_mode. Currently a combine can produce the ieee version for non-ieee
4091 // mode functions, but this happens to be OK since it's only done in cases
4092 // where there is known no sNaN.
4093 if (IsIEEEMode)
4094 return expandFMINNUM_FMAXNUM(Op.getNode(), DAG);
4095
4096 if (VT == MVT::v4f16)
4097 return splitBinaryVectorOp(Op, DAG);
4098 return Op;
4099}
4100
4101SDValue SITargetLowering::lowerTRAP(SDValue Op, SelectionDAG &DAG) const {
4102 SDLoc SL(Op);
4103 SDValue Chain = Op.getOperand(0);
4104
4105 if (Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbiHsa ||
4106 !Subtarget->isTrapHandlerEnabled())
4107 return DAG.getNode(AMDGPUISD::ENDPGM, SL, MVT::Other, Chain);
4108
4109 MachineFunction &MF = DAG.getMachineFunction();
4110 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
4111 unsigned UserSGPR = Info->getQueuePtrUserSGPR();
4112 assert(UserSGPR != AMDGPU::NoRegister)((UserSGPR != AMDGPU::NoRegister) ? static_cast<void> (
0) : __assert_fail ("UserSGPR != AMDGPU::NoRegister", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4112, __PRETTY_FUNCTION__))
;
4113 SDValue QueuePtr = CreateLiveInRegister(
4114 DAG, &AMDGPU::SReg_64RegClass, UserSGPR, MVT::i64);
4115 SDValue SGPR01 = DAG.getRegister(AMDGPU::SGPR0_SGPR1, MVT::i64);
4116 SDValue ToReg = DAG.getCopyToReg(Chain, SL, SGPR01,
4117 QueuePtr, SDValue());
4118 SDValue Ops[] = {
4119 ToReg,
4120 DAG.getTargetConstant(GCNSubtarget::TrapIDLLVMTrap, SL, MVT::i16),
4121 SGPR01,
4122 ToReg.getValue(1)
4123 };
4124 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops);
4125}
4126
4127SDValue SITargetLowering::lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const {
4128 SDLoc SL(Op);
4129 SDValue Chain = Op.getOperand(0);
4130 MachineFunction &MF = DAG.getMachineFunction();
4131
4132 if (Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbiHsa ||
4133 !Subtarget->isTrapHandlerEnabled()) {
4134 DiagnosticInfoUnsupported NoTrap(MF.getFunction(),
4135 "debugtrap handler not supported",
4136 Op.getDebugLoc(),
4137 DS_Warning);
4138 LLVMContext &Ctx = MF.getFunction().getContext();
4139 Ctx.diagnose(NoTrap);
4140 return Chain;
4141 }
4142
4143 SDValue Ops[] = {
4144 Chain,
4145 DAG.getTargetConstant(GCNSubtarget::TrapIDLLVMDebugTrap, SL, MVT::i16)
4146 };
4147 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops);
4148}
4149
4150SDValue SITargetLowering::getSegmentAperture(unsigned AS, const SDLoc &DL,
4151 SelectionDAG &DAG) const {
4152 // FIXME: Use inline constants (src_{shared, private}_base) instead.
4153 if (Subtarget->hasApertureRegs()) {
4154 unsigned Offset = AS == AMDGPUAS::LOCAL_ADDRESS ?
4155 AMDGPU::Hwreg::OFFSET_SRC_SHARED_BASE :
4156 AMDGPU::Hwreg::OFFSET_SRC_PRIVATE_BASE;
4157 unsigned WidthM1 = AS == AMDGPUAS::LOCAL_ADDRESS ?
4158 AMDGPU::Hwreg::WIDTH_M1_SRC_SHARED_BASE :
4159 AMDGPU::Hwreg::WIDTH_M1_SRC_PRIVATE_BASE;
4160 unsigned Encoding =
4161 AMDGPU::Hwreg::ID_MEM_BASES << AMDGPU::Hwreg::ID_SHIFT_ |
4162 Offset << AMDGPU::Hwreg::OFFSET_SHIFT_ |
4163 WidthM1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_;
4164
4165 SDValue EncodingImm = DAG.getTargetConstant(Encoding, DL, MVT::i16);
4166 SDValue ApertureReg = SDValue(
4167 DAG.getMachineNode(AMDGPU::S_GETREG_B32, DL, MVT::i32, EncodingImm), 0);
4168 SDValue ShiftAmount = DAG.getTargetConstant(WidthM1 + 1, DL, MVT::i32);
4169 return DAG.getNode(ISD::SHL, DL, MVT::i32, ApertureReg, ShiftAmount);
4170 }
4171
4172 MachineFunction &MF = DAG.getMachineFunction();
4173 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
4174 unsigned UserSGPR = Info->getQueuePtrUserSGPR();
4175 assert(UserSGPR != AMDGPU::NoRegister)((UserSGPR != AMDGPU::NoRegister) ? static_cast<void> (
0) : __assert_fail ("UserSGPR != AMDGPU::NoRegister", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4175, __PRETTY_FUNCTION__))
;
4176
4177 SDValue QueuePtr = CreateLiveInRegister(
4178 DAG, &AMDGPU::SReg_64RegClass, UserSGPR, MVT::i64);
4179
4180 // Offset into amd_queue_t for group_segment_aperture_base_hi /
4181 // private_segment_aperture_base_hi.
4182 uint32_t StructOffset = (AS == AMDGPUAS::LOCAL_ADDRESS) ? 0x40 : 0x44;
4183
4184 SDValue Ptr = DAG.getObjectPtrOffset(DL, QueuePtr, StructOffset);
4185
4186 // TODO: Use custom target PseudoSourceValue.
4187 // TODO: We should use the value from the IR intrinsic call, but it might not
4188 // be available and how do we get it?
4189 Value *V = UndefValue::get(PointerType::get(Type::getInt8Ty(*DAG.getContext()),
4190 AMDGPUAS::CONSTANT_ADDRESS));
4191
4192 MachinePointerInfo PtrInfo(V, StructOffset);
4193 return DAG.getLoad(MVT::i32, DL, QueuePtr.getValue(1), Ptr, PtrInfo,
4194 MinAlign(64, StructOffset),
4195 MachineMemOperand::MODereferenceable |
4196 MachineMemOperand::MOInvariant);
4197}
4198
4199SDValue SITargetLowering::lowerADDRSPACECAST(SDValue Op,
4200 SelectionDAG &DAG) const {
4201 SDLoc SL(Op);
4202 const AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(Op);
4203
4204 SDValue Src = ASC->getOperand(0);
4205 SDValue FlatNullPtr = DAG.getConstant(0, SL, MVT::i64);
4206
4207 const AMDGPUTargetMachine &TM =
4208 static_cast<const AMDGPUTargetMachine &>(getTargetMachine());
4209
4210 // flat -> local/private
4211 if (ASC->getSrcAddressSpace() == AMDGPUAS::FLAT_ADDRESS) {
4212 unsigned DestAS = ASC->getDestAddressSpace();
4213
4214 if (DestAS == AMDGPUAS::LOCAL_ADDRESS ||
4215 DestAS == AMDGPUAS::PRIVATE_ADDRESS) {
4216 unsigned NullVal = TM.getNullPointerValue(DestAS);
4217 SDValue SegmentNullPtr = DAG.getConstant(NullVal, SL, MVT::i32);
4218 SDValue NonNull = DAG.getSetCC(SL, MVT::i1, Src, FlatNullPtr, ISD::SETNE);
4219 SDValue Ptr = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Src);
4220
4221 return DAG.getNode(ISD::SELECT, SL, MVT::i32,
4222 NonNull, Ptr, SegmentNullPtr);
4223 }
4224 }
4225
4226 // local/private -> flat
4227 if (ASC->getDestAddressSpace() == AMDGPUAS::FLAT_ADDRESS) {
4228 unsigned SrcAS = ASC->getSrcAddressSpace();
4229
4230 if (SrcAS == AMDGPUAS::LOCAL_ADDRESS ||
4231 SrcAS == AMDGPUAS::PRIVATE_ADDRESS) {
4232 unsigned NullVal = TM.getNullPointerValue(SrcAS);
4233 SDValue SegmentNullPtr = DAG.getConstant(NullVal, SL, MVT::i32);
4234
4235 SDValue NonNull
4236 = DAG.getSetCC(SL, MVT::i1, Src, SegmentNullPtr, ISD::SETNE);
4237
4238 SDValue Aperture = getSegmentAperture(ASC->getSrcAddressSpace(), SL, DAG);
4239 SDValue CvtPtr
4240 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Src, Aperture);
4241
4242 return DAG.getNode(ISD::SELECT, SL, MVT::i64, NonNull,
4243 DAG.getNode(ISD::BITCAST, SL, MVT::i64, CvtPtr),
4244 FlatNullPtr);
4245 }
4246 }
4247
4248 // global <-> flat are no-ops and never emitted.
4249
4250 const MachineFunction &MF = DAG.getMachineFunction();
4251 DiagnosticInfoUnsupported InvalidAddrSpaceCast(
4252 MF.getFunction(), "invalid addrspacecast", SL.getDebugLoc());
4253 DAG.getContext()->diagnose(InvalidAddrSpaceCast);
4254
4255 return DAG.getUNDEF(ASC->getValueType(0));
4256}
4257
4258SDValue SITargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
4259 SelectionDAG &DAG) const {
4260 SDValue Vec = Op.getOperand(0);
4261 SDValue InsVal = Op.getOperand(1);
4262 SDValue Idx = Op.getOperand(2);
4263 EVT VecVT = Vec.getValueType();
4264 EVT EltVT = VecVT.getVectorElementType();
4265 unsigned VecSize = VecVT.getSizeInBits();
4266 unsigned EltSize = EltVT.getSizeInBits();
4267
4268
4269 assert(VecSize <= 64)((VecSize <= 64) ? static_cast<void> (0) : __assert_fail
("VecSize <= 64", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4269, __PRETTY_FUNCTION__))
;
4270
4271 unsigned NumElts = VecVT.getVectorNumElements();
4272 SDLoc SL(Op);
4273 auto KIdx = dyn_cast<ConstantSDNode>(Idx);
4274
4275 if (NumElts == 4 && EltSize == 16 && KIdx) {
4276 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Vec);
4277
4278 SDValue LoHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec,
4279 DAG.getConstant(0, SL, MVT::i32));
4280 SDValue HiHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec,
4281 DAG.getConstant(1, SL, MVT::i32));
4282
4283 SDValue LoVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, LoHalf);
4284 SDValue HiVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, HiHalf);
4285
4286 unsigned Idx = KIdx->getZExtValue();
4287 bool InsertLo = Idx < 2;
4288 SDValue InsHalf = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, MVT::v2i16,
4289 InsertLo ? LoVec : HiVec,
4290 DAG.getNode(ISD::BITCAST, SL, MVT::i16, InsVal),
4291 DAG.getConstant(InsertLo ? Idx : (Idx - 2), SL, MVT::i32));
4292
4293 InsHalf = DAG.getNode(ISD::BITCAST, SL, MVT::i32, InsHalf);
4294
4295 SDValue Concat = InsertLo ?
4296 DAG.getBuildVector(MVT::v2i32, SL, { InsHalf, HiHalf }) :
4297 DAG.getBuildVector(MVT::v2i32, SL, { LoHalf, InsHalf });
4298
4299 return DAG.getNode(ISD::BITCAST, SL, VecVT, Concat);
4300 }
4301
4302 if (isa<ConstantSDNode>(Idx))
4303 return SDValue();
4304
4305 MVT IntVT = MVT::getIntegerVT(VecSize);
4306
4307 // Avoid stack access for dynamic indexing.
4308 SDValue Val = InsVal;
4309 if (InsVal.getValueType() == MVT::f16)
4310 Val = DAG.getNode(ISD::BITCAST, SL, MVT::i16, InsVal);
4311
4312 // v_bfi_b32 (v_bfm_b32 16, (shl idx, 16)), val, vec
4313 SDValue ExtVal = DAG.getNode(ISD::ZERO_EXTEND, SL, IntVT, Val);
4314
4315 assert(isPowerOf2_32(EltSize))((isPowerOf2_32(EltSize)) ? static_cast<void> (0) : __assert_fail
("isPowerOf2_32(EltSize)", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4315, __PRETTY_FUNCTION__))
;
4316 SDValue ScaleFactor = DAG.getConstant(Log2_32(EltSize), SL, MVT::i32);
4317
4318 // Convert vector index to bit-index.
4319 SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor);
4320
4321 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec);
4322 SDValue BFM = DAG.getNode(ISD::SHL, SL, IntVT,
4323 DAG.getConstant(0xffff, SL, IntVT),
4324 ScaledIdx);
4325
4326 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal);
4327 SDValue RHS = DAG.getNode(ISD::AND, SL, IntVT,
4328 DAG.getNOT(SL, BFM, IntVT), BCVec);
4329
4330 SDValue BFI = DAG.getNode(ISD::OR, SL, IntVT, LHS, RHS);
4331 return DAG.getNode(ISD::BITCAST, SL, VecVT, BFI);
4332}
4333
4334SDValue SITargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
4335 SelectionDAG &DAG) const {
4336 SDLoc SL(Op);
4337
4338 EVT ResultVT = Op.getValueType();
4339 SDValue Vec = Op.getOperand(0);
4340 SDValue Idx = Op.getOperand(1);
4341 EVT VecVT = Vec.getValueType();
4342 unsigned VecSize = VecVT.getSizeInBits();
4343 EVT EltVT = VecVT.getVectorElementType();
4344 assert(VecSize <= 64)((VecSize <= 64) ? static_cast<void> (0) : __assert_fail
("VecSize <= 64", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4344, __PRETTY_FUNCTION__))
;
4345
4346 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr);
4347
4348 // Make sure we do any optimizations that will make it easier to fold
4349 // source modifiers before obscuring it with bit operations.
4350
4351 // XXX - Why doesn't this get called when vector_shuffle is expanded?
4352 if (SDValue Combined = performExtractVectorEltCombine(Op.getNode(), DCI))
4353 return Combined;
4354
4355 unsigned EltSize = EltVT.getSizeInBits();
4356 assert(isPowerOf2_32(EltSize))((isPowerOf2_32(EltSize)) ? static_cast<void> (0) : __assert_fail
("isPowerOf2_32(EltSize)", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4356, __PRETTY_FUNCTION__))
;
4357
4358 MVT IntVT = MVT::getIntegerVT(VecSize);
4359 SDValue ScaleFactor = DAG.getConstant(Log2_32(EltSize), SL, MVT::i32);
4360
4361 // Convert vector index to bit-index (* EltSize)
4362 SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor);
4363
4364 SDValue BC = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec);
4365 SDValue Elt = DAG.getNode(ISD::SRL, SL, IntVT, BC, ScaledIdx);
4366
4367 if (ResultVT == MVT::f16) {
4368 SDValue Result = DAG.getNode(ISD::TRUNCATE, SL, MVT::i16, Elt);
4369 return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result);
4370 }
4371
4372 return DAG.getAnyExtOrTrunc(Elt, SL, ResultVT);
4373}
4374
4375SDValue SITargetLowering::lowerBUILD_VECTOR(SDValue Op,
4376 SelectionDAG &DAG) const {
4377 SDLoc SL(Op);
4378 EVT VT = Op.getValueType();
4379
4380 if (VT == MVT::v4i16 || VT == MVT::v4f16) {
4381 EVT HalfVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(), 2);
4382
4383 // Turn into pair of packed build_vectors.
4384 // TODO: Special case for constants that can be materialized with s_mov_b64.
4385 SDValue Lo = DAG.getBuildVector(HalfVT, SL,
4386 { Op.getOperand(0), Op.getOperand(1) });
4387 SDValue Hi = DAG.getBuildVector(HalfVT, SL,
4388 { Op.getOperand(2), Op.getOperand(3) });
4389
4390 SDValue CastLo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Lo);
4391 SDValue CastHi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Hi);
4392
4393 SDValue Blend = DAG.getBuildVector(MVT::v2i32, SL, { CastLo, CastHi });
4394 return DAG.getNode(ISD::BITCAST, SL, VT, Blend);
4395 }
4396
4397 assert(VT == MVT::v2f16 || VT == MVT::v2i16)((VT == MVT::v2f16 || VT == MVT::v2i16) ? static_cast<void
> (0) : __assert_fail ("VT == MVT::v2f16 || VT == MVT::v2i16"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4397, __PRETTY_FUNCTION__))
;
4398 assert(!Subtarget->hasVOP3PInsts() && "this should be legal")((!Subtarget->hasVOP3PInsts() && "this should be legal"
) ? static_cast<void> (0) : __assert_fail ("!Subtarget->hasVOP3PInsts() && \"this should be legal\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4398, __PRETTY_FUNCTION__))
;
4399
4400 SDValue Lo = Op.getOperand(0);
4401 SDValue Hi = Op.getOperand(1);
4402
4403 // Avoid adding defined bits with the zero_extend.
4404 if (Hi.isUndef()) {
4405 Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Lo);
4406 SDValue ExtLo = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, Lo);
4407 return DAG.getNode(ISD::BITCAST, SL, VT, ExtLo);
4408 }
4409
4410 Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Hi);
4411 Hi = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Hi);
4412
4413 SDValue ShlHi = DAG.getNode(ISD::SHL, SL, MVT::i32, Hi,
4414 DAG.getConstant(16, SL, MVT::i32));
4415 if (Lo.isUndef())
4416 return DAG.getNode(ISD::BITCAST, SL, VT, ShlHi);
4417
4418 Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Lo);
4419 Lo = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Lo);
4420
4421 SDValue Or = DAG.getNode(ISD::OR, SL, MVT::i32, Lo, ShlHi);
4422 return DAG.getNode(ISD::BITCAST, SL, VT, Or);
4423}
4424
4425bool
4426SITargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4427 // We can fold offsets for anything that doesn't require a GOT relocation.
4428 return (GA->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS ||
4429 GA->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
4430 GA->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
4431 !shouldEmitGOTReloc(GA->getGlobal());
4432}
4433
4434static SDValue
4435buildPCRelGlobalAddress(SelectionDAG &DAG, const GlobalValue *GV,
4436 const SDLoc &DL, unsigned Offset, EVT PtrVT,
4437 unsigned GAFlags = SIInstrInfo::MO_NONE) {
4438 // In order to support pc-relative addressing, the PC_ADD_REL_OFFSET SDNode is
4439 // lowered to the following code sequence:
4440 //
4441 // For constant address space:
4442 // s_getpc_b64 s[0:1]
4443 // s_add_u32 s0, s0, $symbol
4444 // s_addc_u32 s1, s1, 0
4445 //
4446 // s_getpc_b64 returns the address of the s_add_u32 instruction and then
4447 // a fixup or relocation is emitted to replace $symbol with a literal
4448 // constant, which is a pc-relative offset from the encoding of the $symbol
4449 // operand to the global variable.
4450 //
4451 // For global address space:
4452 // s_getpc_b64 s[0:1]
4453 // s_add_u32 s0, s0, $symbol@{gotpc}rel32@lo
4454 // s_addc_u32 s1, s1, $symbol@{gotpc}rel32@hi
4455 //
4456 // s_getpc_b64 returns the address of the s_add_u32 instruction and then
4457 // fixups or relocations are emitted to replace $symbol@*@lo and
4458 // $symbol@*@hi with lower 32 bits and higher 32 bits of a literal constant,
4459 // which is a 64-bit pc-relative offset from the encoding of the $symbol
4460 // operand to the global variable.
4461 //
4462 // What we want here is an offset from the value returned by s_getpc
4463 // (which is the address of the s_add_u32 instruction) to the global
4464 // variable, but since the encoding of $symbol starts 4 bytes after the start
4465 // of the s_add_u32 instruction, we end up with an offset that is 4 bytes too
4466 // small. This requires us to add 4 to the global variable offset in order to
4467 // compute the correct address.
4468 SDValue PtrLo = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 4,
4469 GAFlags);
4470 SDValue PtrHi = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 4,
4471 GAFlags == SIInstrInfo::MO_NONE ?
4472 GAFlags : GAFlags + 1);
4473 return DAG.getNode(AMDGPUISD::PC_ADD_REL_OFFSET, DL, PtrVT, PtrLo, PtrHi);
4474}
4475
4476SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
4477 SDValue Op,
4478 SelectionDAG &DAG) const {
4479 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
4480 const GlobalValue *GV = GSD->getGlobal();
4481 if (GSD->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
4482 GSD->getAddressSpace() == AMDGPUAS::REGION_ADDRESS ||
4483 GSD->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS)
4484 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
4485
4486 SDLoc DL(GSD);
4487 EVT PtrVT = Op.getValueType();
4488
4489 // FIXME: Should not make address space based decisions here.
4490 if (shouldEmitFixup(GV))
4491 return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT);
4492 else if (shouldEmitPCReloc(GV))
4493 return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT,
4494 SIInstrInfo::MO_REL32);
4495
4496 SDValue GOTAddr = buildPCRelGlobalAddress(DAG, GV, DL, 0, PtrVT,
4497 SIInstrInfo::MO_GOTPCREL32);
4498
4499 Type *Ty = PtrVT.getTypeForEVT(*DAG.getContext());
4500 PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
4501 const DataLayout &DataLayout = DAG.getDataLayout();
4502 unsigned Align = DataLayout.getABITypeAlignment(PtrTy);
4503 MachinePointerInfo PtrInfo
4504 = MachinePointerInfo::getGOT(DAG.getMachineFunction());
4505
4506 return DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), GOTAddr, PtrInfo, Align,
4507 MachineMemOperand::MODereferenceable |
4508 MachineMemOperand::MOInvariant);
4509}
4510
4511SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain,
4512 const SDLoc &DL, SDValue V) const {
4513 // We can't use S_MOV_B32 directly, because there is no way to specify m0 as
4514 // the destination register.
4515 //
4516 // We can't use CopyToReg, because MachineCSE won't combine COPY instructions,
4517 // so we will end up with redundant moves to m0.
4518 //
4519 // We use a pseudo to ensure we emit s_mov_b32 with m0 as the direct result.
4520
4521 // A Null SDValue creates a glue result.
4522 SDNode *M0 = DAG.getMachineNode(AMDGPU::SI_INIT_M0, DL, MVT::Other, MVT::Glue,
4523 V, Chain);
4524 return SDValue(M0, 0);
4525}
4526
4527SDValue SITargetLowering::lowerImplicitZextParam(SelectionDAG &DAG,
4528 SDValue Op,
4529 MVT VT,
4530 unsigned Offset) const {
4531 SDLoc SL(Op);
4532 SDValue Param = lowerKernargMemParameter(DAG, MVT::i32, MVT::i32, SL,
4533 DAG.getEntryNode(), Offset, 4, false);
4534 // The local size values will have the hi 16-bits as zero.
4535 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param,
4536 DAG.getValueType(VT));
4537}
4538
4539static SDValue emitNonHSAIntrinsicError(SelectionDAG &DAG, const SDLoc &DL,
4540 EVT VT) {
4541 DiagnosticInfoUnsupported BadIntrin(DAG.getMachineFunction().getFunction(),
4542 "non-hsa intrinsic with hsa target",
4543 DL.getDebugLoc());
4544 DAG.getContext()->diagnose(BadIntrin);
4545 return DAG.getUNDEF(VT);
4546}
4547
4548static SDValue emitRemovedIntrinsicError(SelectionDAG &DAG, const SDLoc &DL,
4549 EVT VT) {
4550 DiagnosticInfoUnsupported BadIntrin(DAG.getMachineFunction().getFunction(),
4551 "intrinsic not supported on subtarget",
4552 DL.getDebugLoc());
4553 DAG.getContext()->diagnose(BadIntrin);
4554 return DAG.getUNDEF(VT);
4555}
4556
4557static SDValue getBuildDwordsVector(SelectionDAG &DAG, SDLoc DL,
4558 ArrayRef<SDValue> Elts) {
4559 assert(!Elts.empty())((!Elts.empty()) ? static_cast<void> (0) : __assert_fail
("!Elts.empty()", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4559, __PRETTY_FUNCTION__))
;
4560 MVT Type;
4561 unsigned NumElts;
4562
4563 if (Elts.size() == 1) {
4564 Type = MVT::f32;
4565 NumElts = 1;
4566 } else if (Elts.size() == 2) {
4567 Type = MVT::v2f32;
4568 NumElts = 2;
4569 } else if (Elts.size() <= 4) {
4570 Type = MVT::v4f32;
4571 NumElts = 4;
4572 } else if (Elts.size() <= 8) {
4573 Type = MVT::v8f32;
4574 NumElts = 8;
4575 } else {
4576 assert(Elts.size() <= 16)((Elts.size() <= 16) ? static_cast<void> (0) : __assert_fail
("Elts.size() <= 16", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4576, __PRETTY_FUNCTION__))
;
4577 Type = MVT::v16f32;
4578 NumElts = 16;
4579 }
4580
4581 SmallVector<SDValue, 16> VecElts(NumElts);
4582 for (unsigned i = 0; i < Elts.size(); ++i) {
4583 SDValue Elt = Elts[i];
4584 if (Elt.getValueType() != MVT::f32)
4585 Elt = DAG.getBitcast(MVT::f32, Elt);
4586 VecElts[i] = Elt;
4587 }
4588 for (unsigned i = Elts.size(); i < NumElts; ++i)
4589 VecElts[i] = DAG.getUNDEF(MVT::f32);
4590
4591 if (NumElts == 1)
4592 return VecElts[0];
4593 return DAG.getBuildVector(Type, DL, VecElts);
4594}
4595
4596static bool parseCachePolicy(SDValue CachePolicy, SelectionDAG &DAG,
4597 SDValue *GLC, SDValue *SLC) {
4598 auto CachePolicyConst = dyn_cast<ConstantSDNode>(CachePolicy.getNode());
4599 if (!CachePolicyConst)
4600 return false;
4601
4602 uint64_t Value = CachePolicyConst->getZExtValue();
4603 SDLoc DL(CachePolicy);
4604 if (GLC) {
4605 *GLC = DAG.getTargetConstant((Value & 0x1) ? 1 : 0, DL, MVT::i32);
4606 Value &= ~(uint64_t)0x1;
4607 }
4608 if (SLC) {
4609 *SLC = DAG.getTargetConstant((Value & 0x2) ? 1 : 0, DL, MVT::i32);
4610 Value &= ~(uint64_t)0x2;
4611 }
4612
4613 return Value == 0;
4614}
4615
4616SDValue SITargetLowering::lowerImage(SDValue Op,
4617 const AMDGPU::ImageDimIntrinsicInfo *Intr,
4618 SelectionDAG &DAG) const {
4619 SDLoc DL(Op);
4620 MachineFunction &MF = DAG.getMachineFunction();
4621 const GCNSubtarget* ST = &MF.getSubtarget<GCNSubtarget>();
4622 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
4623 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode);
4624 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfo(Intr->Dim);
4625 const AMDGPU::MIMGLZMappingInfo *LZMappingInfo =
4626 AMDGPU::getMIMGLZMappingInfo(Intr->BaseOpcode);
4627 unsigned IntrOpcode = Intr->BaseOpcode;
4628
4629 SmallVector<EVT, 2> ResultTypes(Op->value_begin(), Op->value_end());
4630 bool IsD16 = false;
4631 bool IsA16 = false;
4632 SDValue VData;
4633 int NumVDataDwords;
4634 unsigned AddrIdx; // Index of first address argument
4635 unsigned DMask;
4636
4637 if (BaseOpcode->Atomic) {
4638 VData = Op.getOperand(2);
4639
4640 bool Is64Bit = VData.getValueType() == MVT::i64;
4641 if (BaseOpcode->AtomicX2) {
4642 SDValue VData2 = Op.getOperand(3);
4643 VData = DAG.getBuildVector(Is64Bit ? MVT::v2i64 : MVT::v2i32, DL,
4644 {VData, VData2});
4645 if (Is64Bit)
4646 VData = DAG.getBitcast(MVT::v4i32, VData);
4647
4648 ResultTypes[0] = Is64Bit ? MVT::v2i64 : MVT::v2i32;
4649 DMask = Is64Bit ? 0xf : 0x3;
4650 NumVDataDwords = Is64Bit ? 4 : 2;
4651 AddrIdx = 4;
4652 } else {
4653 DMask = Is64Bit ? 0x3 : 0x1;
4654 NumVDataDwords = Is64Bit ? 2 : 1;
4655 AddrIdx = 3;
4656 }
4657 } else {
4658 unsigned DMaskIdx;
4659
4660 if (BaseOpcode->Store) {
4661 VData = Op.getOperand(2);
4662
4663 MVT StoreVT = VData.getSimpleValueType();
4664 if (StoreVT.getScalarType() == MVT::f16) {
4665 if (Subtarget->getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS ||
4666 !BaseOpcode->HasD16)
4667 return Op; // D16 is unsupported for this instruction
4668
4669 IsD16 = true;
4670 VData = handleD16VData(VData, DAG);
4671 }
4672
4673 NumVDataDwords = (VData.getValueType().getSizeInBits() + 31) / 32;
4674 DMaskIdx = 3;
4675 } else {
4676 MVT LoadVT = Op.getSimpleValueType();
4677 if (LoadVT.getScalarType() == MVT::f16) {
4678 if (Subtarget->getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS ||
4679 !BaseOpcode->HasD16)
4680 return Op; // D16 is unsupported for this instruction
4681
4682 IsD16 = true;
4683 if (LoadVT.isVector() && Subtarget->hasUnpackedD16VMem())
4684 ResultTypes[0] = (LoadVT == MVT::v2f16) ? MVT::v2i32 : MVT::v4i32;
4685 }
4686
4687 NumVDataDwords = (ResultTypes[0].getSizeInBits() + 31) / 32;
4688 DMaskIdx = isa<MemSDNode>(Op) ? 2 : 1;
4689 }
4690
4691 auto DMaskConst = dyn_cast<ConstantSDNode>(Op.getOperand(DMaskIdx));
4692 if (!DMaskConst)
4693 return Op;
4694
4695 AddrIdx = DMaskIdx + 1;
4696 DMask = DMaskConst->getZExtValue();
4697 if (!DMask && !BaseOpcode->Store) {
4698 // Eliminate no-op loads. Stores with dmask == 0 are *not* no-op: they
4699 // store the channels' default values.
4700 SDValue Undef = DAG.getUNDEF(Op.getValueType());
4701 if (isa<MemSDNode>(Op))
4702 return DAG.getMergeValues({Undef, Op.getOperand(0)}, DL);
4703 return Undef;
4704 }
4705 }
4706
4707 unsigned NumGradients = BaseOpcode->Gradients ? DimInfo->NumGradients : 0;
4708 unsigned NumCoords = BaseOpcode->Coordinates ? DimInfo->NumCoords : 0;
4709 unsigned NumLCM = BaseOpcode->LodOrClampOrMip ? 1 : 0;
4710 unsigned NumVAddrs = BaseOpcode->NumExtraArgs + NumGradients +
4711 NumCoords + NumLCM;
4712 unsigned NumMIVAddrs = NumVAddrs;
4713
4714 SmallVector<SDValue, 4> VAddrs;
4715
4716 // Optimize _L to _LZ when _L is zero
4717 if (LZMappingInfo) {
4718 if (auto ConstantLod =
4719 dyn_cast<ConstantFPSDNode>(Op.getOperand(AddrIdx+NumVAddrs-1))) {
4720 if (ConstantLod->isZero() || ConstantLod->isNegative()) {
4721 IntrOpcode = LZMappingInfo->LZ; // set new opcode to _lz variant of _l
4722 NumMIVAddrs--; // remove 'lod'
4723 }
4724 }
4725 }
4726
4727 // Check for 16 bit addresses and pack if true.
4728 unsigned DimIdx = AddrIdx + BaseOpcode->NumExtraArgs;
4729 MVT VAddrVT = Op.getOperand(DimIdx).getSimpleValueType();
4730 const MVT VAddrScalarVT = VAddrVT.getScalarType();
4731 if (((VAddrScalarVT == MVT::f16) || (VAddrScalarVT == MVT::i16)) &&
4732 ST->hasFeature(AMDGPU::FeatureR128A16)) {
4733 IsA16 = true;
4734 const MVT VectorVT = VAddrScalarVT == MVT::f16 ? MVT::v2f16 : MVT::v2i16;
4735 for (unsigned i = AddrIdx; i < (AddrIdx + NumMIVAddrs); ++i) {
4736 SDValue AddrLo, AddrHi;
4737 // Push back extra arguments.
4738 if (i < DimIdx) {
4739 AddrLo = Op.getOperand(i);
4740 } else {
4741 AddrLo = Op.getOperand(i);
4742 // Dz/dh, dz/dv and the last odd coord are packed with undef. Also,
4743 // in 1D, derivatives dx/dh and dx/dv are packed with undef.
4744 if (((i + 1) >= (AddrIdx + NumMIVAddrs)) ||
4745 ((NumGradients / 2) % 2 == 1 &&
4746 (i == DimIdx + (NumGradients / 2) - 1 ||
4747 i == DimIdx + NumGradients - 1))) {
4748 AddrHi = DAG.getUNDEF(MVT::f16);
4749 } else {
4750 AddrHi = Op.getOperand(i + 1);
4751 i++;
4752 }
4753 AddrLo = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VectorVT,
4754 {AddrLo, AddrHi});
4755 AddrLo = DAG.getBitcast(MVT::i32, AddrLo);
4756 }
4757 VAddrs.push_back(AddrLo);
4758 }
4759 } else {
4760 for (unsigned i = 0; i < NumMIVAddrs; ++i)
4761 VAddrs.push_back(Op.getOperand(AddrIdx + i));
4762 }
4763
4764 SDValue VAddr = getBuildDwordsVector(DAG, DL, VAddrs);
4765
4766 SDValue True = DAG.getTargetConstant(1, DL, MVT::i1);
4767 SDValue False = DAG.getTargetConstant(0, DL, MVT::i1);
4768 unsigned CtrlIdx; // Index of texfailctrl argument
4769 SDValue Unorm;
4770 if (!BaseOpcode->Sampler) {
4771 Unorm = True;
4772 CtrlIdx = AddrIdx + NumVAddrs + 1;
4773 } else {
4774 auto UnormConst =
4775 dyn_cast<ConstantSDNode>(Op.getOperand(AddrIdx + NumVAddrs + 2));
4776 if (!UnormConst)
4777 return Op;
4778
4779 Unorm = UnormConst->getZExtValue() ? True : False;
4780 CtrlIdx = AddrIdx + NumVAddrs + 3;
4781 }
4782
4783 SDValue TexFail = Op.getOperand(CtrlIdx);
4784 auto TexFailConst = dyn_cast<ConstantSDNode>(TexFail.getNode());
4785 if (!TexFailConst || TexFailConst->getZExtValue() != 0)
4786 return Op;
4787
4788 SDValue GLC;
4789 SDValue SLC;
4790 if (BaseOpcode->Atomic) {
4791 GLC = True; // TODO no-return optimization
4792 if (!parseCachePolicy(Op.getOperand(CtrlIdx + 1), DAG, nullptr, &SLC))
4793 return Op;
4794 } else {
4795 if (!parseCachePolicy(Op.getOperand(CtrlIdx + 1), DAG, &GLC, &SLC))
4796 return Op;
4797 }
4798
4799 SmallVector<SDValue, 14> Ops;
4800 if (BaseOpcode->Store || BaseOpcode->Atomic)
4801 Ops.push_back(VData); // vdata
4802 Ops.push_back(VAddr);
4803 Ops.push_back(Op.getOperand(AddrIdx + NumVAddrs)); // rsrc
4804 if (BaseOpcode->Sampler)
4805 Ops.push_back(Op.getOperand(AddrIdx + NumVAddrs + 1)); // sampler
4806 Ops.push_back(DAG.getTargetConstant(DMask, DL, MVT::i32));
4807 Ops.push_back(Unorm);
4808 Ops.push_back(GLC);
4809 Ops.push_back(SLC);
4810 Ops.push_back(IsA16 && // a16 or r128
4811 ST->hasFeature(AMDGPU::FeatureR128A16) ? True : False);
4812 Ops.push_back(False); // tfe
4813 Ops.push_back(False); // lwe
4814 Ops.push_back(DimInfo->DA ? True : False);
4815 if (BaseOpcode->HasD16)
4816 Ops.push_back(IsD16 ? True : False);
4817 if (isa<MemSDNode>(Op))
4818 Ops.push_back(Op.getOperand(0)); // chain
4819
4820 int NumVAddrDwords = VAddr.getValueType().getSizeInBits() / 32;
4821 int Opcode = -1;
4822
4823 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
4824 Opcode = AMDGPU::getMIMGOpcode(IntrOpcode, AMDGPU::MIMGEncGfx8,
4825 NumVDataDwords, NumVAddrDwords);
4826 if (Opcode == -1)
4827 Opcode = AMDGPU::getMIMGOpcode(IntrOpcode, AMDGPU::MIMGEncGfx6,
4828 NumVDataDwords, NumVAddrDwords);
4829 assert(Opcode != -1)((Opcode != -1) ? static_cast<void> (0) : __assert_fail
("Opcode != -1", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4829, __PRETTY_FUNCTION__))
;
4830
4831 MachineSDNode *NewNode = DAG.getMachineNode(Opcode, DL, ResultTypes, Ops);
4832 if (auto MemOp = dyn_cast<MemSDNode>(Op)) {
4833 MachineMemOperand *MemRef = MemOp->getMemOperand();
4834 DAG.setNodeMemRefs(NewNode, {MemRef});
4835 }
4836
4837 if (BaseOpcode->AtomicX2) {
4838 SmallVector<SDValue, 1> Elt;
4839 DAG.ExtractVectorElements(SDValue(NewNode, 0), Elt, 0, 1);
4840 return DAG.getMergeValues({Elt[0], SDValue(NewNode, 1)}, DL);
4841 } else if (IsD16 && !BaseOpcode->Store) {
4842 MVT LoadVT = Op.getSimpleValueType();
4843 SDValue Adjusted = adjustLoadValueTypeImpl(
4844 SDValue(NewNode, 0), LoadVT, DL, DAG, Subtarget->hasUnpackedD16VMem());
4845 return DAG.getMergeValues({Adjusted, SDValue(NewNode, 1)}, DL);
4846 }
4847
4848 return SDValue(NewNode, 0);
4849}
4850
4851SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc,
4852 SDValue Offset, SDValue GLC,
4853 SelectionDAG &DAG) const {
4854 MachineFunction &MF = DAG.getMachineFunction();
4855 MachineMemOperand *MMO = MF.getMachineMemOperand(
4856 MachinePointerInfo(),
4857 MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable |
4858 MachineMemOperand::MOInvariant,
4859 VT.getStoreSize(), VT.getStoreSize());
4860
4861 if (!Offset->isDivergent()) {
4862 SDValue Ops[] = {
4863 Rsrc,
4864 Offset, // Offset
4865 GLC // glc
4866 };
4867 return DAG.getMemIntrinsicNode(AMDGPUISD::SBUFFER_LOAD, DL,
4868 DAG.getVTList(VT), Ops, VT, MMO);
4869 }
4870
4871 // We have a divergent offset. Emit a MUBUF buffer load instead. We can
4872 // assume that the buffer is unswizzled.
4873 SmallVector<SDValue, 4> Loads;
4874 unsigned NumLoads = 1;
4875 MVT LoadVT = VT.getSimpleVT();
4876 unsigned NumElts = LoadVT.isVector() ? LoadVT.getVectorNumElements() : 1;
4877 assert((LoadVT.getScalarType() == MVT::i32 ||(((LoadVT.getScalarType() == MVT::i32 || LoadVT.getScalarType
() == MVT::f32) && isPowerOf2_32(NumElts)) ? static_cast
<void> (0) : __assert_fail ("(LoadVT.getScalarType() == MVT::i32 || LoadVT.getScalarType() == MVT::f32) && isPowerOf2_32(NumElts)"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4879, __PRETTY_FUNCTION__))
4878 LoadVT.getScalarType() == MVT::f32) &&(((LoadVT.getScalarType() == MVT::i32 || LoadVT.getScalarType
() == MVT::f32) && isPowerOf2_32(NumElts)) ? static_cast
<void> (0) : __assert_fail ("(LoadVT.getScalarType() == MVT::i32 || LoadVT.getScalarType() == MVT::f32) && isPowerOf2_32(NumElts)"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4879, __PRETTY_FUNCTION__))
4879 isPowerOf2_32(NumElts))(((LoadVT.getScalarType() == MVT::i32 || LoadVT.getScalarType
() == MVT::f32) && isPowerOf2_32(NumElts)) ? static_cast
<void> (0) : __assert_fail ("(LoadVT.getScalarType() == MVT::i32 || LoadVT.getScalarType() == MVT::f32) && isPowerOf2_32(NumElts)"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4879, __PRETTY_FUNCTION__))
;
4880
4881 if (NumElts == 8 || NumElts == 16) {
4882 NumLoads = NumElts == 16 ? 4 : 2;
4883 LoadVT = MVT::v4i32;
4884 }
4885
4886 SDVTList VTList = DAG.getVTList({LoadVT, MVT::Glue});
4887 unsigned CachePolicy = cast<ConstantSDNode>(GLC)->getZExtValue();
4888 SDValue Ops[] = {
4889 DAG.getEntryNode(), // Chain
4890 Rsrc, // rsrc
4891 DAG.getConstant(0, DL, MVT::i32), // vindex
4892 {}, // voffset
4893 {}, // soffset
4894 {}, // offset
4895 DAG.getConstant(CachePolicy, DL, MVT::i32), // cachepolicy
4896 DAG.getConstant(0, DL, MVT::i1), // idxen
4897 };
4898
4899 // Use the alignment to ensure that the required offsets will fit into the
4900 // immediate offsets.
4901 setBufferOffsets(Offset, DAG, &Ops[3], NumLoads > 1 ? 16 * NumLoads : 4);
4902
4903 uint64_t InstOffset = cast<ConstantSDNode>(Ops[5])->getZExtValue();
4904 for (unsigned i = 0; i < NumLoads; ++i) {
4905 Ops[5] = DAG.getConstant(InstOffset + 16 * i, DL, MVT::i32);
4906 Loads.push_back(DAG.getMemIntrinsicNode(AMDGPUISD::BUFFER_LOAD, DL, VTList,
4907 Ops, LoadVT, MMO));
4908 }
4909
4910 if (VT == MVT::v8i32 || VT == MVT::v16i32)
4911 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Loads);
4912
4913 return Loads[0];
4914}
4915
4916SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
4917 SelectionDAG &DAG) const {
4918 MachineFunction &MF = DAG.getMachineFunction();
4919 auto MFI = MF.getInfo<SIMachineFunctionInfo>();
4920
4921 EVT VT = Op.getValueType();
4922 SDLoc DL(Op);
4923 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4924
4925 // TODO: Should this propagate fast-math-flags?
4926
4927 switch (IntrinsicID) {
4928 case Intrinsic::amdgcn_implicit_buffer_ptr: {
4929 if (getSubtarget()->isAmdHsaOrMesa(MF.getFunction()))
4930 return emitNonHSAIntrinsicError(DAG, DL, VT);
4931 return getPreloadedValue(DAG, *MFI, VT,
4932 AMDGPUFunctionArgInfo::IMPLICIT_BUFFER_PTR);
4933 }
4934 case Intrinsic::amdgcn_dispatch_ptr:
4935 case Intrinsic::amdgcn_queue_ptr: {
4936 if (!Subtarget->isAmdHsaOrMesa(MF.getFunction())) {
4937 DiagnosticInfoUnsupported BadIntrin(
4938 MF.getFunction(), "unsupported hsa intrinsic without hsa target",
4939 DL.getDebugLoc());
4940 DAG.getContext()->diagnose(BadIntrin);
4941 return DAG.getUNDEF(VT);
4942 }
4943
4944 auto RegID = IntrinsicID == Intrinsic::amdgcn_dispatch_ptr ?
4945 AMDGPUFunctionArgInfo::DISPATCH_PTR : AMDGPUFunctionArgInfo::QUEUE_PTR;
4946 return getPreloadedValue(DAG, *MFI, VT, RegID);
4947 }
4948 case Intrinsic::amdgcn_implicitarg_ptr: {
4949 if (MFI->isEntryFunction())
4950 return getImplicitArgPtr(DAG, DL);
4951 return getPreloadedValue(DAG, *MFI, VT,
4952 AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR);
4953 }
4954 case Intrinsic::amdgcn_kernarg_segment_ptr: {
4955 return getPreloadedValue(DAG, *MFI, VT,
4956 AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR);
4957 }
4958 case Intrinsic::amdgcn_dispatch_id: {
4959 return getPreloadedValue(DAG, *MFI, VT, AMDGPUFunctionArgInfo::DISPATCH_ID);
4960 }
4961 case Intrinsic::amdgcn_rcp:
4962 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
4963 case Intrinsic::amdgcn_rsq:
4964 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
4965 case Intrinsic::amdgcn_rsq_legacy:
4966 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
4967 return emitRemovedIntrinsicError(DAG, DL, VT);
4968
4969 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
4970 case Intrinsic::amdgcn_rcp_legacy:
4971 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
4972 return emitRemovedIntrinsicError(DAG, DL, VT);
4973 return DAG.getNode(AMDGPUISD::RCP_LEGACY, DL, VT, Op.getOperand(1));
4974 case Intrinsic::amdgcn_rsq_clamp: {
4975 if (Subtarget->getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS)
4976 return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1));
4977
4978 Type *Type = VT.getTypeForEVT(*DAG.getContext());
4979 APFloat Max = APFloat::getLargest(Type->getFltSemantics());
4980 APFloat Min = APFloat::getLargest(Type->getFltSemantics(), true);
4981
4982 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
4983 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
4984 DAG.getConstantFP(Max, DL, VT));
4985 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
4986 DAG.getConstantFP(Min, DL, VT));
4987 }
4988 case Intrinsic::r600_read_ngroups_x:
4989 if (Subtarget->isAmdHsaOS())
4990 return emitNonHSAIntrinsicError(DAG, DL, VT);
4991
4992 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
4993 SI::KernelInputOffsets::NGROUPS_X, 4, false);
4994 case Intrinsic::r600_read_ngroups_y:
4995 if (Subtarget->isAmdHsaOS())
4996 return emitNonHSAIntrinsicError(DAG, DL, VT);
4997
4998 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
4999 SI::KernelInputOffsets::NGROUPS_Y, 4, false);
5000 case Intrinsic::r600_read_ngroups_z:
5001 if (Subtarget->isAmdHsaOS())
5002 return emitNonHSAIntrinsicError(DAG, DL, VT);
5003
5004 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
5005 SI::KernelInputOffsets::NGROUPS_Z, 4, false);
5006 case Intrinsic::r600_read_global_size_x:
5007 if (Subtarget->isAmdHsaOS())
5008 return emitNonHSAIntrinsicError(DAG, DL, VT);
5009
5010 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
5011 SI::KernelInputOffsets::GLOBAL_SIZE_X, 4, false);
5012 case Intrinsic::r600_read_global_size_y:
5013 if (Subtarget->isAmdHsaOS())
5014 return emitNonHSAIntrinsicError(DAG, DL, VT);
5015
5016 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
5017 SI::KernelInputOffsets::GLOBAL_SIZE_Y, 4, false);
5018 case Intrinsic::r600_read_global_size_z:
5019 if (Subtarget->isAmdHsaOS())
5020 return emitNonHSAIntrinsicError(DAG, DL, VT);
5021
5022 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
5023 SI::KernelInputOffsets::GLOBAL_SIZE_Z, 4, false);
5024 case Intrinsic::r600_read_local_size_x:
5025 if (Subtarget->isAmdHsaOS())
5026 return emitNonHSAIntrinsicError(DAG, DL, VT);
5027
5028 return lowerImplicitZextParam(DAG, Op, MVT::i16,
5029 SI::KernelInputOffsets::LOCAL_SIZE_X);
5030 case Intrinsic::r600_read_local_size_y:
5031 if (Subtarget->isAmdHsaOS())
5032 return emitNonHSAIntrinsicError(DAG, DL, VT);
5033
5034 return lowerImplicitZextParam(DAG, Op, MVT::i16,
5035 SI::KernelInputOffsets::LOCAL_SIZE_Y);
5036 case Intrinsic::r600_read_local_size_z:
5037 if (Subtarget->isAmdHsaOS())
5038 return emitNonHSAIntrinsicError(DAG, DL, VT);
5039
5040 return lowerImplicitZextParam(DAG, Op, MVT::i16,
5041 SI::KernelInputOffsets::LOCAL_SIZE_Z);
5042 case Intrinsic::amdgcn_workgroup_id_x:
5043 case Intrinsic::r600_read_tgid_x:
5044 return getPreloadedValue(DAG, *MFI, VT,
5045 AMDGPUFunctionArgInfo::WORKGROUP_ID_X);
5046 case Intrinsic::amdgcn_workgroup_id_y:
5047 case Intrinsic::r600_read_tgid_y:
5048 return getPreloadedValue(DAG, *MFI, VT,
5049 AMDGPUFunctionArgInfo::WORKGROUP_ID_Y);
5050 case Intrinsic::amdgcn_workgroup_id_z:
5051 case Intrinsic::r600_read_tgid_z:
5052 return getPreloadedValue(DAG, *MFI, VT,
5053 AMDGPUFunctionArgInfo::WORKGROUP_ID_Z);
5054 case Intrinsic::amdgcn_workitem_id_x:
5055 case Intrinsic::r600_read_tidig_x:
5056 return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
5057 SDLoc(DAG.getEntryNode()),
5058 MFI->getArgInfo().WorkItemIDX);
5059 case Intrinsic::amdgcn_workitem_id_y:
5060 case Intrinsic::r600_read_tidig_y:
5061 return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
5062 SDLoc(DAG.getEntryNode()),
5063 MFI->getArgInfo().WorkItemIDY);
5064 case Intrinsic::amdgcn_workitem_id_z:
5065 case Intrinsic::r600_read_tidig_z:
5066 return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
5067 SDLoc(DAG.getEntryNode()),
5068 MFI->getArgInfo().WorkItemIDZ);
5069 case SIIntrinsic::SI_load_const: {
5070 SDValue Load =
5071 lowerSBuffer(MVT::i32, DL, Op.getOperand(1), Op.getOperand(2),
5072 DAG.getTargetConstant(0, DL, MVT::i1), DAG);
5073 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Load);
5074 }
5075 case Intrinsic::amdgcn_s_buffer_load: {
5076 unsigned Cache = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
5077 return lowerSBuffer(VT, DL, Op.getOperand(1), Op.getOperand(2),
5078 DAG.getTargetConstant(Cache & 1, DL, MVT::i1), DAG);
5079 }
5080 case Intrinsic::amdgcn_fdiv_fast:
5081 return lowerFDIV_FAST(Op, DAG);
5082 case Intrinsic::amdgcn_interp_mov: {
5083 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(4));
5084 SDValue Glue = M0.getValue(1);
5085 return DAG.getNode(AMDGPUISD::INTERP_MOV, DL, MVT::f32, Op.getOperand(1),
5086 Op.getOperand(2), Op.getOperand(3), Glue);
5087 }
5088 case Intrinsic::amdgcn_interp_p1: {
5089 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(4));
5090 SDValue Glue = M0.getValue(1);
5091 return DAG.getNode(AMDGPUISD::INTERP_P1, DL, MVT::f32, Op.getOperand(1),
5092 Op.getOperand(2), Op.getOperand(3), Glue);
5093 }
5094 case Intrinsic::amdgcn_interp_p2: {
5095 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(5));
5096 SDValue Glue = SDValue(M0.getNode(), 1);
5097 return DAG.getNode(AMDGPUISD::INTERP_P2, DL, MVT::f32, Op.getOperand(1),
5098 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4),
5099 Glue);
5100 }
5101 case Intrinsic::amdgcn_sin:
5102 return DAG.getNode(AMDGPUISD::SIN_HW, DL, VT, Op.getOperand(1));
5103
5104 case Intrinsic::amdgcn_cos:
5105 return DAG.getNode(AMDGPUISD::COS_HW, DL, VT, Op.getOperand(1));
5106
5107 case Intrinsic::amdgcn_log_clamp: {
5108 if (Subtarget->getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS)
5109 return SDValue();
5110
5111 DiagnosticInfoUnsupported BadIntrin(
5112 MF.getFunction(), "intrinsic not supported on subtarget",
5113 DL.getDebugLoc());
5114 DAG.getContext()->diagnose(BadIntrin);
5115 return DAG.getUNDEF(VT);
5116 }
5117 case Intrinsic::amdgcn_ldexp:
5118 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT,
5119 Op.getOperand(1), Op.getOperand(2));
5120
5121 case Intrinsic::amdgcn_fract:
5122 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
5123
5124 case Intrinsic::amdgcn_class:
5125 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, VT,
5126 Op.getOperand(1), Op.getOperand(2));
5127 case Intrinsic::amdgcn_div_fmas:
5128 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
5129 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
5130 Op.getOperand(4));
5131
5132 case Intrinsic::amdgcn_div_fixup:
5133 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
5134 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
5135
5136 case Intrinsic::amdgcn_trig_preop:
5137 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
5138 Op.getOperand(1), Op.getOperand(2));
5139 case Intrinsic::amdgcn_div_scale: {
5140 // 3rd parameter required to be a constant.
5141 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
5142 if (!Param)
5143 return DAG.getMergeValues({ DAG.getUNDEF(VT), DAG.getUNDEF(MVT::i1) }, DL);
5144
5145 // Translate to the operands expected by the machine instruction. The
5146 // first parameter must be the same as the first instruction.
5147 SDValue Numerator = Op.getOperand(1);
5148 SDValue Denominator = Op.getOperand(2);
5149
5150 // Note this order is opposite of the machine instruction's operations,
5151 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
5152 // intrinsic has the numerator as the first operand to match a normal
5153 // division operation.
5154
5155 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
5156
5157 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
5158 Denominator, Numerator);
5159 }
5160 case Intrinsic::amdgcn_icmp: {
5161 return lowerICMPIntrinsic(*this, Op.getNode(), DAG);
5162 }
5163 case Intrinsic::amdgcn_fcmp: {
5164 return lowerFCMPIntrinsic(*this, Op.getNode(), DAG);
5165 }
5166 case Intrinsic::amdgcn_fmed3:
5167 return DAG.getNode(AMDGPUISD::FMED3, DL, VT,
5168 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
5169 case Intrinsic::amdgcn_fdot2:
5170 return DAG.getNode(AMDGPUISD::FDOT2, DL, VT,
5171 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
5172 Op.getOperand(4));
5173 case Intrinsic::amdgcn_fmul_legacy:
5174 return DAG.getNode(AMDGPUISD::FMUL_LEGACY, DL, VT,
5175 Op.getOperand(1), Op.getOperand(2));
5176 case Intrinsic::amdgcn_sffbh:
5177 return DAG.getNode(AMDGPUISD::FFBH_I32, DL, VT, Op.getOperand(1));
5178 case Intrinsic::amdgcn_sbfe:
5179 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
5180 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
5181 case Intrinsic::amdgcn_ubfe:
5182 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
5183 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
5184 case Intrinsic::amdgcn_cvt_pkrtz:
5185 case Intrinsic::amdgcn_cvt_pknorm_i16:
5186 case Intrinsic::amdgcn_cvt_pknorm_u16:
5187 case Intrinsic::amdgcn_cvt_pk_i16:
5188 case Intrinsic::amdgcn_cvt_pk_u16: {
5189 // FIXME: Stop adding cast if v2f16/v2i16 are legal.
5190 EVT VT = Op.getValueType();
5191 unsigned Opcode;
5192
5193 if (IntrinsicID == Intrinsic::amdgcn_cvt_pkrtz)
5194 Opcode = AMDGPUISD::CVT_PKRTZ_F16_F32;
5195 else if (IntrinsicID == Intrinsic::amdgcn_cvt_pknorm_i16)
5196 Opcode = AMDGPUISD::CVT_PKNORM_I16_F32;
5197 else if (IntrinsicID == Intrinsic::amdgcn_cvt_pknorm_u16)
5198 Opcode = AMDGPUISD::CVT_PKNORM_U16_F32;
5199 else if (IntrinsicID == Intrinsic::amdgcn_cvt_pk_i16)
5200 Opcode = AMDGPUISD::CVT_PK_I16_I32;
5201 else
5202 Opcode = AMDGPUISD::CVT_PK_U16_U32;
5203
5204 if (isTypeLegal(VT))
5205 return DAG.getNode(Opcode, DL, VT, Op.getOperand(1), Op.getOperand(2));
5206
5207 SDValue Node = DAG.getNode(Opcode, DL, MVT::i32,
5208 Op.getOperand(1), Op.getOperand(2));
5209 return DAG.getNode(ISD::BITCAST, DL, VT, Node);
5210 }
5211 case Intrinsic::amdgcn_wqm: {
5212 SDValue Src = Op.getOperand(1);
5213 return SDValue(DAG.getMachineNode(AMDGPU::WQM, DL, Src.getValueType(), Src),
5214 0);
5215 }
5216 case Intrinsic::amdgcn_wwm: {
5217 SDValue Src = Op.getOperand(1);
5218 return SDValue(DAG.getMachineNode(AMDGPU::WWM, DL, Src.getValueType(), Src),
5219 0);
5220 }
5221 case Intrinsic::amdgcn_fmad_ftz:
5222 return DAG.getNode(AMDGPUISD::FMAD_FTZ, DL, VT, Op.getOperand(1),
5223 Op.getOperand(2), Op.getOperand(3));
5224 default:
5225 if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr =
5226 AMDGPU::getImageDimIntrinsicInfo(IntrinsicID))
5227 return lowerImage(Op, ImageDimIntr, DAG);
5228
5229 return Op;
5230 }
5231}
5232
5233SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
5234 SelectionDAG &DAG) const {
5235 unsigned IntrID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5236 SDLoc DL(Op);
5237
5238 switch (IntrID) {
5239 case Intrinsic::amdgcn_atomic_inc:
5240 case Intrinsic::amdgcn_atomic_dec:
5241 case Intrinsic::amdgcn_ds_fadd:
5242 case Intrinsic::amdgcn_ds_fmin:
5243 case Intrinsic::amdgcn_ds_fmax: {
5244 MemSDNode *M = cast<MemSDNode>(Op);
5245 unsigned Opc;
5246 switch (IntrID) {
5247 case Intrinsic::amdgcn_atomic_inc:
5248 Opc = AMDGPUISD::ATOMIC_INC;
5249 break;
5250 case Intrinsic::amdgcn_atomic_dec:
5251 Opc = AMDGPUISD::ATOMIC_DEC;
5252 break;
5253 case Intrinsic::amdgcn_ds_fadd:
5254 Opc = AMDGPUISD::ATOMIC_LOAD_FADD;
5255 break;
5256 case Intrinsic::amdgcn_ds_fmin:
5257 Opc = AMDGPUISD::ATOMIC_LOAD_FMIN;
5258 break;
5259 case Intrinsic::amdgcn_ds_fmax:
5260 Opc = AMDGPUISD::ATOMIC_LOAD_FMAX;
5261 break;
5262 default:
5263 llvm_unreachable("Unknown intrinsic!")::llvm::llvm_unreachable_internal("Unknown intrinsic!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5263)
;
5264 }
5265 SDValue Ops[] = {
5266 M->getOperand(0), // Chain
5267 M->getOperand(2), // Ptr
5268 M->getOperand(3) // Value
5269 };
5270
5271 return DAG.getMemIntrinsicNode(Opc, SDLoc(Op), M->getVTList(), Ops,
5272 M->getMemoryVT(), M->getMemOperand());
5273 }
5274 case Intrinsic::amdgcn_buffer_load:
5275 case Intrinsic::amdgcn_buffer_load_format: {
5276 unsigned Glc = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
5277 unsigned Slc = cast<ConstantSDNode>(Op.getOperand(6))->getZExtValue();
5278 unsigned IdxEn = 1;
5279 if (auto Idx = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
5280 IdxEn = Idx->getZExtValue() != 0;
5281 SDValue Ops[] = {
5282 Op.getOperand(0), // Chain
5283 Op.getOperand(2), // rsrc
5284 Op.getOperand(3), // vindex
5285 SDValue(), // voffset -- will be set by setBufferOffsets
5286 SDValue(), // soffset -- will be set by setBufferOffsets
5287 SDValue(), // offset -- will be set by setBufferOffsets
5288 DAG.getConstant(Glc | (Slc << 1), DL, MVT::i32), // cachepolicy
5289 DAG.getConstant(IdxEn, DL, MVT::i1), // idxen
5290 };
5291
5292 setBufferOffsets(Op.getOperand(4), DAG, &Ops[3]);
5293 unsigned Opc = (IntrID == Intrinsic::amdgcn_buffer_load) ?
5294 AMDGPUISD::BUFFER_LOAD : AMDGPUISD::BUFFER_LOAD_FORMAT;
5295
5296 EVT VT = Op.getValueType();
5297 EVT IntVT = VT.changeTypeToInteger();
5298 auto *M = cast<MemSDNode>(Op);
5299 EVT LoadVT = Op.getValueType();
5300
5301 if (LoadVT.getScalarType() == MVT::f16)
5302 return adjustLoadValueType(AMDGPUISD::BUFFER_LOAD_FORMAT_D16,
5303 M, DAG, Ops);
5304 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops, IntVT,
5305 M->getMemOperand());
5306 }
5307 case Intrinsic::amdgcn_raw_buffer_load:
5308 case Intrinsic::amdgcn_raw_buffer_load_format: {
5309 auto Offsets = splitBufferOffsets(Op.getOperand(3), DAG);
5310 SDValue Ops[] = {
5311 Op.getOperand(0), // Chain
5312 Op.getOperand(2), // rsrc
5313 DAG.getConstant(0, DL, MVT::i32), // vindex
5314 Offsets.first, // voffset
5315 Op.getOperand(4), // soffset
5316 Offsets.second, // offset
5317 Op.getOperand(5), // cachepolicy
5318 DAG.getConstant(0, DL, MVT::i1), // idxen
5319 };
5320
5321 unsigned Opc = (IntrID == Intrinsic::amdgcn_raw_buffer_load) ?
5322 AMDGPUISD::BUFFER_LOAD : AMDGPUISD::BUFFER_LOAD_FORMAT;
5323
5324 EVT VT = Op.getValueType();
5325 EVT IntVT = VT.changeTypeToInteger();
5326 auto *M = cast<MemSDNode>(Op);
5327 EVT LoadVT = Op.getValueType();
5328
5329 if (LoadVT.getScalarType() == MVT::f16)
5330 return adjustLoadValueType(AMDGPUISD::BUFFER_LOAD_FORMAT_D16,
5331 M, DAG, Ops);
5332 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops, IntVT,
5333 M->getMemOperand());
5334 }
5335 case Intrinsic::amdgcn_struct_buffer_load:
5336 case Intrinsic::amdgcn_struct_buffer_load_format: {
5337 auto Offsets = splitBufferOffsets(Op.getOperand(4), DAG);
5338 SDValue Ops[] = {
5339 Op.getOperand(0), // Chain
5340 Op.getOperand(2), // rsrc
5341 Op.getOperand(3), // vindex
5342 Offsets.first, // voffset
5343 Op.getOperand(5), // soffset
5344 Offsets.second, // offset
5345 Op.getOperand(6), // cachepolicy
5346 DAG.getConstant(1, DL, MVT::i1), // idxen
5347 };
5348
5349 unsigned Opc = (IntrID == Intrinsic::amdgcn_struct_buffer_load) ?
5350 AMDGPUISD::BUFFER_LOAD : AMDGPUISD::BUFFER_LOAD_FORMAT;
5351
5352 EVT VT = Op.getValueType();
5353 EVT IntVT = VT.changeTypeToInteger();
5354 auto *M = cast<MemSDNode>(Op);
5355 EVT LoadVT = Op.getValueType();
5356
5357 if (LoadVT.getScalarType() == MVT::f16)
5358 return adjustLoadValueType(AMDGPUISD::BUFFER_LOAD_FORMAT_D16,
5359 M, DAG, Ops);
5360 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops, IntVT,
5361 M->getMemOperand());
5362 }
5363 case Intrinsic::amdgcn_tbuffer_load: {
5364 MemSDNode *M = cast<MemSDNode>(Op);
5365 EVT LoadVT = Op.getValueType();
5366
5367 unsigned Dfmt = cast<ConstantSDNode>(Op.getOperand(7))->getZExtValue();
5368 unsigned Nfmt = cast<ConstantSDNode>(Op.getOperand(8))->getZExtValue();
5369 unsigned Glc = cast<ConstantSDNode>(Op.getOperand(9))->getZExtValue();
5370 unsigned Slc = cast<ConstantSDNode>(Op.getOperand(10))->getZExtValue();
5371 unsigned IdxEn = 1;
5372 if (auto Idx = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
5373 IdxEn = Idx->getZExtValue() != 0;
5374 SDValue Ops[] = {
5375 Op.getOperand(0), // Chain
5376 Op.getOperand(2), // rsrc
5377 Op.getOperand(3), // vindex
5378 Op.getOperand(4), // voffset
5379 Op.getOperand(5), // soffset
5380 Op.getOperand(6), // offset
5381 DAG.getConstant(Dfmt | (Nfmt << 4), DL, MVT::i32), // format
5382 DAG.getConstant(Glc | (Slc << 1), DL, MVT::i32), // cachepolicy
5383 DAG.getConstant(IdxEn, DL, MVT::i1), // idxen
5384 };
5385
5386 if (LoadVT.getScalarType() == MVT::f16)
5387 return adjustLoadValueType(AMDGPUISD::TBUFFER_LOAD_FORMAT_D16,
5388 M, DAG, Ops);
5389 return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_LOAD_FORMAT, DL,
5390 Op->getVTList(), Ops, LoadVT,
5391 M->getMemOperand());
5392 }
5393 case Intrinsic::amdgcn_raw_tbuffer_load: {
5394 MemSDNode *M = cast<MemSDNode>(Op);
5395 EVT LoadVT = Op.getValueType();
5396 auto Offsets = splitBufferOffsets(Op.getOperand(3), DAG);
5397
5398 SDValue Ops[] = {
5399 Op.getOperand(0), // Chain
5400 Op.getOperand(2), // rsrc
5401 DAG.getConstant(0, DL, MVT::i32), // vindex
5402 Offsets.first, // voffset
5403 Op.getOperand(4), // soffset
5404 Offsets.second, // offset
5405 Op.getOperand(5), // format
5406 Op.getOperand(6), // cachepolicy
5407 DAG.getConstant(0, DL, MVT::i1), // idxen
5408 };
5409
5410 if (LoadVT.getScalarType() == MVT::f16)
5411 return adjustLoadValueType(AMDGPUISD::TBUFFER_LOAD_FORMAT_D16,
5412 M, DAG, Ops);
5413 return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_LOAD_FORMAT, DL,
5414 Op->getVTList(), Ops, LoadVT,
5415 M->getMemOperand());
5416 }
5417 case Intrinsic::amdgcn_struct_tbuffer_load: {
5418 MemSDNode *M = cast<MemSDNode>(Op);
5419 EVT LoadVT = Op.getValueType();
5420 auto Offsets = splitBufferOffsets(Op.getOperand(4), DAG);
5421
5422 SDValue Ops[] = {
5423 Op.getOperand(0), // Chain
5424 Op.getOperand(2), // rsrc
5425 Op.getOperand(3), // vindex
5426 Offsets.first, // voffset
5427 Op.getOperand(5), // soffset
5428 Offsets.second, // offset
5429 Op.getOperand(6), // format
5430 Op.getOperand(7), // cachepolicy
5431 DAG.getConstant(1, DL, MVT::i1), // idxen
5432 };
5433
5434 if (LoadVT.getScalarType() == MVT::f16)
5435 return adjustLoadValueType(AMDGPUISD::TBUFFER_LOAD_FORMAT_D16,
5436 M, DAG, Ops);
5437 return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_LOAD_FORMAT, DL,
5438 Op->getVTList(), Ops, LoadVT,
5439 M->getMemOperand());
5440 }
5441 case Intrinsic::amdgcn_buffer_atomic_swap:
5442 case Intrinsic::amdgcn_buffer_atomic_add:
5443 case Intrinsic::amdgcn_buffer_atomic_sub:
5444 case Intrinsic::amdgcn_buffer_atomic_smin:
5445 case Intrinsic::amdgcn_buffer_atomic_umin:
5446 case Intrinsic::amdgcn_buffer_atomic_smax:
5447 case Intrinsic::amdgcn_buffer_atomic_umax:
5448 case Intrinsic::amdgcn_buffer_atomic_and:
5449 case Intrinsic::amdgcn_buffer_atomic_or:
5450 case Intrinsic::amdgcn_buffer_atomic_xor: {
5451 unsigned Slc = cast<ConstantSDNode>(Op.getOperand(6))->getZExtValue();
5452 unsigned IdxEn = 1;
5453 if (auto Idx = dyn_cast<ConstantSDNode>(Op.getOperand(4)))
5454 IdxEn = Idx->getZExtValue() != 0;
5455 SDValue Ops[] = {
5456 Op.getOperand(0), // Chain
5457 Op.getOperand(2), // vdata
5458 Op.getOperand(3), // rsrc
5459 Op.getOperand(4), // vindex
5460 SDValue(), // voffset -- will be set by setBufferOffsets
5461 SDValue(), // soffset -- will be set by setBufferOffsets
5462 SDValue(), // offset -- will be set by setBufferOffsets
5463 DAG.getConstant(Slc << 1, DL, MVT::i32), // cachepolicy
5464 DAG.getConstant(IdxEn, DL, MVT::i1), // idxen
5465 };
5466 setBufferOffsets(Op.getOperand(5), DAG, &Ops[4]);
5467 EVT VT = Op.getValueType();
5468
5469 auto *M = cast<MemSDNode>(Op);
5470 unsigned Opcode = 0;
5471
5472 switch (IntrID) {
5473 case Intrinsic::amdgcn_buffer_atomic_swap:
5474 Opcode = AMDGPUISD::BUFFER_ATOMIC_SWAP;
5475 break;
5476 case Intrinsic::amdgcn_buffer_atomic_add:
5477 Opcode = AMDGPUISD::BUFFER_ATOMIC_ADD;
5478 break;
5479 case Intrinsic::amdgcn_buffer_atomic_sub:
5480 Opcode = AMDGPUISD::BUFFER_ATOMIC_SUB;
5481 break;
5482 case Intrinsic::amdgcn_buffer_atomic_smin:
5483 Opcode = AMDGPUISD::BUFFER_ATOMIC_SMIN;
5484 break;
5485 case Intrinsic::amdgcn_buffer_atomic_umin:
5486 Opcode = AMDGPUISD::BUFFER_ATOMIC_UMIN;
5487 break;
5488 case Intrinsic::amdgcn_buffer_atomic_smax:
5489 Opcode = AMDGPUISD::BUFFER_ATOMIC_SMAX;
5490 break;
5491 case Intrinsic::amdgcn_buffer_atomic_umax:
5492 Opcode = AMDGPUISD::BUFFER_ATOMIC_UMAX;
5493 break;
5494 case Intrinsic::amdgcn_buffer_atomic_and:
5495 Opcode = AMDGPUISD::BUFFER_ATOMIC_AND;
5496 break;
5497 case Intrinsic::amdgcn_buffer_atomic_or:
5498 Opcode = AMDGPUISD::BUFFER_ATOMIC_OR;
5499 break;
5500 case Intrinsic::amdgcn_buffer_atomic_xor:
5501 Opcode = AMDGPUISD::BUFFER_ATOMIC_XOR;
5502 break;
5503 default:
5504 llvm_unreachable("unhandled atomic opcode")::llvm::llvm_unreachable_internal("unhandled atomic opcode", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5504)
;
5505 }
5506
5507 return DAG.getMemIntrinsicNode(Opcode, DL, Op->getVTList(), Ops, VT,
5508 M->getMemOperand());
5509 }
5510 case Intrinsic::amdgcn_raw_buffer_atomic_swap:
5511 case Intrinsic::amdgcn_raw_buffer_atomic_add:
5512 case Intrinsic::amdgcn_raw_buffer_atomic_sub:
5513 case Intrinsic::amdgcn_raw_buffer_atomic_smin:
5514 case Intrinsic::amdgcn_raw_buffer_atomic_umin:
5515 case Intrinsic::amdgcn_raw_buffer_atomic_smax:
5516 case Intrinsic::amdgcn_raw_buffer_atomic_umax:
5517 case Intrinsic::amdgcn_raw_buffer_atomic_and:
5518 case Intrinsic::amdgcn_raw_buffer_atomic_or:
5519 case Intrinsic::amdgcn_raw_buffer_atomic_xor: {
5520 auto Offsets = splitBufferOffsets(Op.getOperand(4), DAG);
5521 SDValue Ops[] = {
5522 Op.getOperand(0), // Chain
5523 Op.getOperand(2), // vdata
5524 Op.getOperand(3), // rsrc
5525 DAG.getConstant(0, DL, MVT::i32), // vindex
5526 Offsets.first, // voffset
5527 Op.getOperand(5), // soffset
5528 Offsets.second, // offset
5529 Op.getOperand(6), // cachepolicy
5530 DAG.getConstant(0, DL, MVT::i1), // idxen
5531 };
5532 EVT VT = Op.getValueType();
5533
5534 auto *M = cast<MemSDNode>(Op);
5535 unsigned Opcode = 0;
5536
5537 switch (IntrID) {
5538 case Intrinsic::amdgcn_raw_buffer_atomic_swap:
5539 Opcode = AMDGPUISD::BUFFER_ATOMIC_SWAP;
5540 break;
5541 case Intrinsic::amdgcn_raw_buffer_atomic_add:
5542 Opcode = AMDGPUISD::BUFFER_ATOMIC_ADD;
5543 break;
5544 case Intrinsic::amdgcn_raw_buffer_atomic_sub:
5545 Opcode = AMDGPUISD::BUFFER_ATOMIC_SUB;
5546 break;
5547 case Intrinsic::amdgcn_raw_buffer_atomic_smin:
5548 Opcode = AMDGPUISD::BUFFER_ATOMIC_SMIN;
5549 break;
5550 case Intrinsic::amdgcn_raw_buffer_atomic_umin:
5551 Opcode = AMDGPUISD::BUFFER_ATOMIC_UMIN;
5552 break;
5553 case Intrinsic::amdgcn_raw_buffer_atomic_smax:
5554 Opcode = AMDGPUISD::BUFFER_ATOMIC_SMAX;
5555 break;
5556 case Intrinsic::amdgcn_raw_buffer_atomic_umax:
5557 Opcode = AMDGPUISD::BUFFER_ATOMIC_UMAX;
5558 break;
5559 case Intrinsic::amdgcn_raw_buffer_atomic_and:
5560 Opcode = AMDGPUISD::BUFFER_ATOMIC_AND;
5561 break;
5562 case Intrinsic::amdgcn_raw_buffer_atomic_or:
5563 Opcode = AMDGPUISD::BUFFER_ATOMIC_OR;
5564 break;
5565 case Intrinsic::amdgcn_raw_buffer_atomic_xor:
5566 Opcode = AMDGPUISD::BUFFER_ATOMIC_XOR;
5567 break;
5568 default:
5569 llvm_unreachable("unhandled atomic opcode")::llvm::llvm_unreachable_internal("unhandled atomic opcode", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5569)
;
5570 }
5571
5572 return DAG.getMemIntrinsicNode(Opcode, DL, Op->getVTList(), Ops, VT,
5573 M->getMemOperand());
5574 }
5575 case Intrinsic::amdgcn_struct_buffer_atomic_swap:
5576 case Intrinsic::amdgcn_struct_buffer_atomic_add:
5577 case Intrinsic::amdgcn_struct_buffer_atomic_sub:
5578 case Intrinsic::amdgcn_struct_buffer_atomic_smin:
5579 case Intrinsic::amdgcn_struct_buffer_atomic_umin:
5580 case Intrinsic::amdgcn_struct_buffer_atomic_smax:
5581 case Intrinsic::amdgcn_struct_buffer_atomic_umax:
5582 case Intrinsic::amdgcn_struct_buffer_atomic_and:
5583 case Intrinsic::amdgcn_struct_buffer_atomic_or:
5584 case Intrinsic::amdgcn_struct_buffer_atomic_xor: {
5585 auto Offsets = splitBufferOffsets(Op.getOperand(5), DAG);
5586 SDValue Ops[] = {
5587 Op.getOperand(0), // Chain
5588 Op.getOperand(2), // vdata
5589 Op.getOperand(3), // rsrc
5590 Op.getOperand(4), // vindex
5591 Offsets.first, // voffset
5592 Op.getOperand(6), // soffset
5593 Offsets.second, // offset
5594 Op.getOperand(7), // cachepolicy
5595 DAG.getConstant(1, DL, MVT::i1), // idxen
5596 };
5597 EVT VT = Op.getValueType();
5598
5599 auto *M = cast<MemSDNode>(Op);
5600 unsigned Opcode = 0;
5601
5602 switch (IntrID) {
5603 case Intrinsic::amdgcn_struct_buffer_atomic_swap:
5604 Opcode = AMDGPUISD::BUFFER_ATOMIC_SWAP;
5605 break;
5606 case Intrinsic::amdgcn_struct_buffer_atomic_add:
5607 Opcode = AMDGPUISD::BUFFER_ATOMIC_ADD;
5608 break;
5609 case Intrinsic::amdgcn_struct_buffer_atomic_sub:
5610 Opcode = AMDGPUISD::BUFFER_ATOMIC_SUB;
5611 break;
5612 case Intrinsic::amdgcn_struct_buffer_atomic_smin:
5613 Opcode = AMDGPUISD::BUFFER_ATOMIC_SMIN;
5614 break;
5615 case Intrinsic::amdgcn_struct_buffer_atomic_umin:
5616 Opcode = AMDGPUISD::BUFFER_ATOMIC_UMIN;
5617 break;
5618 case Intrinsic::amdgcn_struct_buffer_atomic_smax:
5619 Opcode = AMDGPUISD::BUFFER_ATOMIC_SMAX;
5620 break;
5621 case Intrinsic::amdgcn_struct_buffer_atomic_umax:
5622 Opcode = AMDGPUISD::BUFFER_ATOMIC_UMAX;
5623 break;
5624 case Intrinsic::amdgcn_struct_buffer_atomic_and:
5625 Opcode = AMDGPUISD::BUFFER_ATOMIC_AND;
5626 break;
5627 case Intrinsic::amdgcn_struct_buffer_atomic_or:
5628 Opcode = AMDGPUISD::BUFFER_ATOMIC_OR;
5629 break;
5630 case Intrinsic::amdgcn_struct_buffer_atomic_xor:
5631 Opcode = AMDGPUISD::BUFFER_ATOMIC_XOR;
5632 break;
5633 default:
5634 llvm_unreachable("unhandled atomic opcode")::llvm::llvm_unreachable_internal("unhandled atomic opcode", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5634)
;
5635 }
5636
5637 return DAG.getMemIntrinsicNode(Opcode, DL, Op->getVTList(), Ops, VT,
5638 M->getMemOperand());
5639 }
5640 case Intrinsic::amdgcn_buffer_atomic_cmpswap: {
5641 unsigned Slc = cast<ConstantSDNode>(Op.getOperand(7))->getZExtValue();
5642 unsigned IdxEn = 1;
5643 if (auto Idx = dyn_cast<ConstantSDNode>(Op.getOperand(5)))
5644 IdxEn = Idx->getZExtValue() != 0;
5645 SDValue Ops[] = {
5646 Op.getOperand(0), // Chain
5647 Op.getOperand(2), // src
5648 Op.getOperand(3), // cmp
5649 Op.getOperand(4), // rsrc
5650 Op.getOperand(5), // vindex
5651 SDValue(), // voffset -- will be set by setBufferOffsets
5652 SDValue(), // soffset -- will be set by setBufferOffsets
5653 SDValue(), // offset -- will be set by setBufferOffsets
5654 DAG.getConstant(Slc << 1, DL, MVT::i32), // cachepolicy
5655 DAG.getConstant(IdxEn, DL, MVT::i1), // idxen
5656 };
5657 setBufferOffsets(Op.getOperand(6), DAG, &Ops[5]);
5658 EVT VT = Op.getValueType();
5659 auto *M = cast<MemSDNode>(Op);
5660
5661 return DAG.getMemIntrinsicNode(AMDGPUISD::BUFFER_ATOMIC_CMPSWAP, DL,
5662 Op->getVTList(), Ops, VT, M->getMemOperand());
5663 }
5664 case Intrinsic::amdgcn_raw_buffer_atomic_cmpswap: {
5665 auto Offsets = splitBufferOffsets(Op.getOperand(5), DAG);
5666 SDValue Ops[] = {
5667 Op.getOperand(0), // Chain
5668 Op.getOperand(2), // src
5669 Op.getOperand(3), // cmp
5670 Op.getOperand(4), // rsrc
5671 DAG.getConstant(0, DL, MVT::i32), // vindex
5672 Offsets.first, // voffset
5673 Op.getOperand(6), // soffset
5674 Offsets.second, // offset
5675 Op.getOperand(7), // cachepolicy
5676 DAG.getConstant(0, DL, MVT::i1), // idxen
5677 };
5678 EVT VT = Op.getValueType();
5679 auto *M = cast<MemSDNode>(Op);
5680
5681 return DAG.getMemIntrinsicNode(AMDGPUISD::BUFFER_ATOMIC_CMPSWAP, DL,
5682 Op->getVTList(), Ops, VT, M->getMemOperand());
5683 }
5684 case Intrinsic::amdgcn_struct_buffer_atomic_cmpswap: {
5685 auto Offsets = splitBufferOffsets(Op.getOperand(6), DAG);
5686 SDValue Ops[] = {
5687 Op.getOperand(0), // Chain
5688 Op.getOperand(2), // src
5689 Op.getOperand(3), // cmp
5690 Op.getOperand(4), // rsrc
5691 Op.getOperand(5), // vindex
5692 Offsets.first, // voffset
5693 Op.getOperand(7), // soffset
5694 Offsets.second, // offset
5695 Op.getOperand(8), // cachepolicy
5696 DAG.getConstant(1, DL, MVT::i1), // idxen
5697 };
5698 EVT VT = Op.getValueType();
5699 auto *M = cast<MemSDNode>(Op);
5700
5701 return DAG.getMemIntrinsicNode(AMDGPUISD::BUFFER_ATOMIC_CMPSWAP, DL,
5702 Op->getVTList(), Ops, VT, M->getMemOperand());
5703 }
5704
5705 default:
5706 if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr =
5707 AMDGPU::getImageDimIntrinsicInfo(IntrID))
5708 return lowerImage(Op, ImageDimIntr, DAG);
5709
5710 return SDValue();
5711 }
5712}
5713
5714SDValue SITargetLowering::handleD16VData(SDValue VData,
5715 SelectionDAG &DAG) const {
5716 EVT StoreVT = VData.getValueType();
5717
5718 // No change for f16 and legal vector D16 types.
5719 if (!StoreVT.isVector())
5720 return VData;
5721
5722 SDLoc DL(VData);
5723 assert((StoreVT.getVectorNumElements() != 3) && "Handle v3f16")(((StoreVT.getVectorNumElements() != 3) && "Handle v3f16"
) ? static_cast<void> (0) : __assert_fail ("(StoreVT.getVectorNumElements() != 3) && \"Handle v3f16\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5723, __PRETTY_FUNCTION__))
;
5724
5725 if (Subtarget->hasUnpackedD16VMem()) {
5726 // We need to unpack the packed data to store.
5727 EVT IntStoreVT = StoreVT.changeTypeToInteger();
5728 SDValue IntVData = DAG.getNode(ISD::BITCAST, DL, IntStoreVT, VData);
5729
5730 EVT EquivStoreVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
5731 StoreVT.getVectorNumElements());
5732 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, EquivStoreVT, IntVData);
5733 return DAG.UnrollVectorOp(ZExt.getNode());
5734 }
5735
5736 assert(isTypeLegal(StoreVT))((isTypeLegal(StoreVT)) ? static_cast<void> (0) : __assert_fail
("isTypeLegal(StoreVT)", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5736, __PRETTY_FUNCTION__))
;
5737 return VData;
5738}
5739
5740SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
5741 SelectionDAG &DAG) const {
5742 SDLoc DL(Op);
5743 SDValue Chain = Op.getOperand(0);
5744 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5745 MachineFunction &MF = DAG.getMachineFunction();
5746
5747 switch (IntrinsicID) {
5748 case Intrinsic::amdgcn_exp: {
5749 const ConstantSDNode *Tgt = cast<ConstantSDNode>(Op.getOperand(2));
5750 const ConstantSDNode *En = cast<ConstantSDNode>(Op.getOperand(3));
5751 const ConstantSDNode *Done = cast<ConstantSDNode>(Op.getOperand(8));
5752 const ConstantSDNode *VM = cast<ConstantSDNode>(Op.getOperand(9));
5753
5754 const SDValue Ops[] = {
5755 Chain,
5756 DAG.getTargetConstant(Tgt->getZExtValue(), DL, MVT::i8), // tgt
5757 DAG.getTargetConstant(En->getZExtValue(), DL, MVT::i8), // en
5758 Op.getOperand(4), // src0
5759 Op.getOperand(5), // src1
5760 Op.getOperand(6), // src2
5761 Op.getOperand(7), // src3
5762 DAG.getTargetConstant(0, DL, MVT::i1), // compr
5763 DAG.getTargetConstant(VM->getZExtValue(), DL, MVT::i1)
5764 };
5765
5766 unsigned Opc = Done->isNullValue() ?
5767 AMDGPUISD::EXPORT : AMDGPUISD::EXPORT_DONE;
5768 return DAG.getNode(Opc, DL, Op->getVTList(), Ops);
5769 }
5770 case Intrinsic::amdgcn_exp_compr: {
5771 const ConstantSDNode *Tgt = cast<ConstantSDNode>(Op.getOperand(2));
5772 const ConstantSDNode *En = cast<ConstantSDNode>(Op.getOperand(3));
5773 SDValue Src0 = Op.getOperand(4);
5774 SDValue Src1 = Op.getOperand(5);
5775 const ConstantSDNode *Done = cast<ConstantSDNode>(Op.getOperand(6));
5776 const ConstantSDNode *VM = cast<ConstantSDNode>(Op.getOperand(7));
5777
5778 SDValue Undef = DAG.getUNDEF(MVT::f32);
5779 const SDValue Ops[] = {
5780 Chain,
5781 DAG.getTargetConstant(Tgt->getZExtValue(), DL, MVT::i8), // tgt
5782 DAG.getTargetConstant(En->getZExtValue(), DL, MVT::i8), // en
5783 DAG.getNode(ISD::BITCAST, DL, MVT::f32, Src0),
5784 DAG.getNode(ISD::BITCAST, DL, MVT::f32, Src1),
5785 Undef, // src2
5786 Undef, // src3
5787 DAG.getTargetConstant(1, DL, MVT::i1), // compr
5788 DAG.getTargetConstant(VM->getZExtValue(), DL, MVT::i1)
5789 };
5790
5791 unsigned Opc = Done->isNullValue() ?
5792 AMDGPUISD::EXPORT : AMDGPUISD::EXPORT_DONE;
5793 return DAG.getNode(Opc, DL, Op->getVTList(), Ops);
5794 }
5795 case Intrinsic::amdgcn_s_sendmsg:
5796 case Intrinsic::amdgcn_s_sendmsghalt: {
5797 unsigned NodeOp = (IntrinsicID == Intrinsic::amdgcn_s_sendmsg) ?
5798 AMDGPUISD::SENDMSG : AMDGPUISD::SENDMSGHALT;
5799 Chain = copyToM0(DAG, Chain, DL, Op.getOperand(3));
5800 SDValue Glue = Chain.getValue(1);
5801 return DAG.getNode(NodeOp, DL, MVT::Other, Chain,
5802 Op.getOperand(2), Glue);
5803 }
5804 case Intrinsic::amdgcn_init_exec: {
5805 return DAG.getNode(AMDGPUISD::INIT_EXEC, DL, MVT::Other, Chain,
5806 Op.getOperand(2));
5807 }
5808 case Intrinsic::amdgcn_init_exec_from_input: {
5809 return DAG.getNode(AMDGPUISD::INIT_EXEC_FROM_INPUT, DL, MVT::Other, Chain,
5810 Op.getOperand(2), Op.getOperand(3));
5811 }
5812 case Intrinsic::amdgcn_s_barrier: {
5813 if (getTargetMachine().getOptLevel() > CodeGenOpt::None) {
5814 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
5815 unsigned WGSize = ST.getFlatWorkGroupSizes(MF.getFunction()).second;
5816 if (WGSize <= ST.getWavefrontSize())
5817 return SDValue(DAG.getMachineNode(AMDGPU::WAVE_BARRIER, DL, MVT::Other,
5818 Op.getOperand(0)), 0);
5819 }
5820 return SDValue();
5821 };
5822 case Intrinsic::amdgcn_tbuffer_store: {
5823 SDValue VData = Op.getOperand(2);
5824 bool IsD16 = (VData.getValueType().getScalarType() == MVT::f16);
5825 if (IsD16)
5826 VData = handleD16VData(VData, DAG);
5827 unsigned Dfmt = cast<ConstantSDNode>(Op.getOperand(8))->getZExtValue();
5828 unsigned Nfmt = cast<ConstantSDNode>(Op.getOperand(9))->getZExtValue();
5829 unsigned Glc = cast<ConstantSDNode>(Op.getOperand(10))->getZExtValue();
5830 unsigned Slc = cast<ConstantSDNode>(Op.getOperand(11))->getZExtValue();
5831 unsigned IdxEn = 1;
5832 if (auto Idx = dyn_cast<ConstantSDNode>(Op.getOperand(4)))
5833 IdxEn = Idx->getZExtValue() != 0;
5834 SDValue Ops[] = {
5835 Chain,
5836 VData, // vdata
5837 Op.getOperand(3), // rsrc
5838 Op.getOperand(4), // vindex
5839 Op.getOperand(5), // voffset
5840 Op.getOperand(6), // soffset
5841 Op.getOperand(7), // offset
5842 DAG.getConstant(Dfmt | (Nfmt << 4), DL, MVT::i32), // format
5843 DAG.getConstant(Glc | (Slc << 1), DL, MVT::i32), // cachepolicy
5844 DAG.getConstant(IdxEn, DL, MVT::i1), // idexen
5845 };
5846 unsigned Opc = IsD16 ? AMDGPUISD::TBUFFER_STORE_FORMAT_D16 :
5847 AMDGPUISD::TBUFFER_STORE_FORMAT;
5848 MemSDNode *M = cast<MemSDNode>(Op);
5849 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
5850 M->getMemoryVT(), M->getMemOperand());
5851 }
5852
5853 case Intrinsic::amdgcn_struct_tbuffer_store: {
5854 SDValue VData = Op.getOperand(2);
5855 bool IsD16 = (VData.getValueType().getScalarType() == MVT::f16);
5856 if (IsD16)
5857 VData = handleD16VData(VData, DAG);
5858 auto Offsets = splitBufferOffsets(Op.getOperand(5), DAG);
5859 SDValue Ops[] = {
5860 Chain,
5861 VData, // vdata
5862 Op.getOperand(3), // rsrc
5863 Op.getOperand(4), // vindex
5864 Offsets.first, // voffset
5865 Op.getOperand(6), // soffset
5866 Offsets.second, // offset
5867 Op.getOperand(7), // format
5868 Op.getOperand(8), // cachepolicy
5869 DAG.getConstant(1, DL, MVT::i1), // idexen
5870 };
5871 unsigned Opc = IsD16 ? AMDGPUISD::TBUFFER_STORE_FORMAT_D16 :
5872 AMDGPUISD::TBUFFER_STORE_FORMAT;
5873 MemSDNode *M = cast<MemSDNode>(Op);
5874 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
5875 M->getMemoryVT(), M->getMemOperand());
5876 }
5877
5878 case Intrinsic::amdgcn_raw_tbuffer_store: {
5879 SDValue VData = Op.getOperand(2);
5880 bool IsD16 = (VData.getValueType().getScalarType() == MVT::f16);
5881 if (IsD16)
5882 VData = handleD16VData(VData, DAG);
5883 auto Offsets = splitBufferOffsets(Op.getOperand(4), DAG);
5884 SDValue Ops[] = {
5885 Chain,
5886 VData, // vdata
5887 Op.getOperand(3), // rsrc
5888 DAG.getConstant(0, DL, MVT::i32), // vindex
5889 Offsets.first, // voffset
5890 Op.getOperand(5), // soffset
5891 Offsets.second, // offset
5892 Op.getOperand(6), // format
5893 Op.getOperand(7), // cachepolicy
5894 DAG.getConstant(0, DL, MVT::i1), // idexen
5895 };
5896 unsigned Opc = IsD16 ? AMDGPUISD::TBUFFER_STORE_FORMAT_D16 :
5897 AMDGPUISD::TBUFFER_STORE_FORMAT;
5898 MemSDNode *M = cast<MemSDNode>(Op);
5899 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
5900 M->getMemoryVT(), M->getMemOperand());
5901 }
5902
5903 case Intrinsic::amdgcn_buffer_store:
5904 case Intrinsic::amdgcn_buffer_store_format: {
5905 SDValue VData = Op.getOperand(2);
5906 bool IsD16 = (VData.getValueType().getScalarType() == MVT::f16);
5907 if (IsD16)
5908 VData = handleD16VData(VData, DAG);
5909 unsigned Glc = cast<ConstantSDNode>(Op.getOperand(6))->getZExtValue();
5910 unsigned Slc = cast<ConstantSDNode>(Op.getOperand(7))->getZExtValue();
5911 unsigned IdxEn = 1;
5912 if (auto Idx = dyn_cast<ConstantSDNode>(Op.getOperand(4)))
5913 IdxEn = Idx->getZExtValue() != 0;
5914 SDValue Ops[] = {
5915 Chain,
5916 VData,
5917 Op.getOperand(3), // rsrc
5918 Op.getOperand(4), // vindex
5919 SDValue(), // voffset -- will be set by setBufferOffsets
5920 SDValue(), // soffset -- will be set by setBufferOffsets
5921 SDValue(), // offset -- will be set by setBufferOffsets
5922 DAG.getConstant(Glc | (Slc << 1), DL, MVT::i32), // cachepolicy
5923 DAG.getConstant(IdxEn, DL, MVT::i1), // idxen
5924 };
5925 setBufferOffsets(Op.getOperand(5), DAG, &Ops[4]);
5926 unsigned Opc = IntrinsicID == Intrinsic::amdgcn_buffer_store ?
5927 AMDGPUISD::BUFFER_STORE : AMDGPUISD::BUFFER_STORE_FORMAT;
5928 Opc = IsD16 ? AMDGPUISD::BUFFER_STORE_FORMAT_D16 : Opc;
5929 MemSDNode *M = cast<MemSDNode>(Op);
5930 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
5931 M->getMemoryVT(), M->getMemOperand());
5932 }
5933
5934 case Intrinsic::amdgcn_raw_buffer_store:
5935 case Intrinsic::amdgcn_raw_buffer_store_format: {
5936 SDValue VData = Op.getOperand(2);
5937 bool IsD16 = (VData.getValueType().getScalarType() == MVT::f16);
5938 if (IsD16)
5939 VData = handleD16VData(VData, DAG);
5940 auto Offsets = splitBufferOffsets(Op.getOperand(4), DAG);
5941 SDValue Ops[] = {
5942 Chain,
5943 VData,
5944 Op.getOperand(3), // rsrc
5945 DAG.getConstant(0, DL, MVT::i32), // vindex
5946 Offsets.first, // voffset
5947 Op.getOperand(5), // soffset
5948 Offsets.second, // offset
5949 Op.getOperand(6), // cachepolicy
5950 DAG.getConstant(0, DL, MVT::i1), // idxen
5951 };
5952 unsigned Opc = IntrinsicID == Intrinsic::amdgcn_raw_buffer_store ?
5953 AMDGPUISD::BUFFER_STORE : AMDGPUISD::BUFFER_STORE_FORMAT;
5954 Opc = IsD16 ? AMDGPUISD::BUFFER_STORE_FORMAT_D16 : Opc;
5955 MemSDNode *M = cast<MemSDNode>(Op);
5956 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
5957 M->getMemoryVT(), M->getMemOperand());
5958 }
5959
5960 case Intrinsic::amdgcn_struct_buffer_store:
5961 case Intrinsic::amdgcn_struct_buffer_store_format: {
5962 SDValue VData = Op.getOperand(2);
5963 bool IsD16 = (VData.getValueType().getScalarType() == MVT::f16);
5964 if (IsD16)
5965 VData = handleD16VData(VData, DAG);
5966 auto Offsets = splitBufferOffsets(Op.getOperand(5), DAG);
5967 SDValue Ops[] = {
5968 Chain,
5969 VData,
5970 Op.getOperand(3), // rsrc
5971 Op.getOperand(4), // vindex
5972 Offsets.first, // voffset
5973 Op.getOperand(6), // soffset
5974 Offsets.second, // offset
5975 Op.getOperand(7), // cachepolicy
5976 DAG.getConstant(1, DL, MVT::i1), // idxen
5977 };
5978 unsigned Opc = IntrinsicID == Intrinsic::amdgcn_struct_buffer_store ?
5979 AMDGPUISD::BUFFER_STORE : AMDGPUISD::BUFFER_STORE_FORMAT;
5980 Opc = IsD16 ? AMDGPUISD::BUFFER_STORE_FORMAT_D16 : Opc;
5981 MemSDNode *M = cast<MemSDNode>(Op);
5982 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
5983 M->getMemoryVT(), M->getMemOperand());
5984 }
5985
5986 default: {
5987 if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr =
5988 AMDGPU::getImageDimIntrinsicInfo(IntrinsicID))
5989 return lowerImage(Op, ImageDimIntr, DAG);
5990
5991 return Op;
5992 }
5993 }
5994}
5995
5996// The raw.(t)buffer and struct.(t)buffer intrinsics have two offset args:
5997// offset (the offset that is included in bounds checking and swizzling, to be
5998// split between the instruction's voffset and immoffset fields) and soffset
5999// (the offset that is excluded from bounds checking and swizzling, to go in
6000// the instruction's soffset field). This function takes the first kind of
6001// offset and figures out how to split it between voffset and immoffset.
6002std::pair<SDValue, SDValue> SITargetLowering::splitBufferOffsets(
6003 SDValue Offset, SelectionDAG &DAG) const {
6004 SDLoc DL(Offset);
6005 const unsigned MaxImm = 4095;
6006 SDValue N0 = Offset;
6007 ConstantSDNode *C1 = nullptr;
6008 if (N0.getOpcode() == ISD::ADD) {
6009 if ((C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))))
6010 N0 = N0.getOperand(0);
6011 } else if ((C1 = dyn_cast<ConstantSDNode>(N0)))
6012 N0 = SDValue();
6013
6014 if (C1) {
6015 unsigned ImmOffset = C1->getZExtValue();
6016 // If the immediate value is too big for the immoffset field, put the value
6017 // and -4096 into the immoffset field so that the value that is copied/added
6018 // for the voffset field is a multiple of 4096, and it stands more chance
6019 // of being CSEd with the copy/add for another similar load/store.
6020 // However, do not do that rounding down to a multiple of 4096 if that is a
6021 // negative number, as it appears to be illegal to have a negative offset
6022 // in the vgpr, even if adding the immediate offset makes it positive.
6023 unsigned Overflow = ImmOffset & ~MaxImm;
6024 ImmOffset -= Overflow;
6025 if ((int32_t)Overflow < 0) {
6026 Overflow += ImmOffset;
6027 ImmOffset = 0;
6028 }
6029 C1 = cast<ConstantSDNode>(DAG.getConstant(ImmOffset, DL, MVT::i32));
6030 if (Overflow) {
6031 auto OverflowVal = DAG.getConstant(Overflow, DL, MVT::i32);
6032 if (!N0)
6033 N0 = OverflowVal;
6034 else {
6035 SDValue Ops[] = { N0, OverflowVal };
6036 N0 = DAG.getNode(ISD::ADD, DL, MVT::i32, Ops);
6037 }
6038 }
6039 }
6040 if (!N0)
6041 N0 = DAG.getConstant(0, DL, MVT::i32);
6042 if (!C1)
6043 C1 = cast<ConstantSDNode>(DAG.getConstant(0, DL, MVT::i32));
6044 return {N0, SDValue(C1, 0)};
6045}
6046
6047// Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the
6048// three offsets (voffset, soffset and instoffset) into the SDValue[3] array
6049// pointed to by Offsets.
6050void SITargetLowering::setBufferOffsets(SDValue CombinedOffset,
6051 SelectionDAG &DAG, SDValue *Offsets,
6052 unsigned Align) const {
6053 SDLoc DL(CombinedOffset);
6054 if (auto C = dyn_cast<ConstantSDNode>(CombinedOffset)) {
6055 uint32_t Imm = C->getZExtValue();
6056 uint32_t SOffset, ImmOffset;
6057 if (AMDGPU::splitMUBUFOffset(Imm, SOffset, ImmOffset, Subtarget, Align)) {
6058 Offsets[0] = DAG.getConstant(0, DL, MVT::i32);
6059 Offsets[1] = DAG.getConstant(SOffset, DL, MVT::i32);
6060 Offsets[2] = DAG.getConstant(ImmOffset, DL, MVT::i32);
6061 return;
6062 }
6063 }
6064 if (DAG.isBaseWithConstantOffset(CombinedOffset)) {
6065 SDValue N0 = CombinedOffset.getOperand(0);
6066 SDValue N1 = CombinedOffset.getOperand(1);
6067 uint32_t SOffset, ImmOffset;
6068 int Offset = cast<ConstantSDNode>(N1)->getSExtValue();
6069 if (Offset >= 0 && AMDGPU::splitMUBUFOffset(Offset, SOffset, ImmOffset,
6070 Subtarget, Align)) {
6071 Offsets[0] = N0;
6072 Offsets[1] = DAG.getConstant(SOffset, DL, MVT::i32);
6073 Offsets[2] = DAG.getConstant(ImmOffset, DL, MVT::i32);
6074 return;
6075 }
6076 }
6077 Offsets[0] = CombinedOffset;
6078 Offsets[1] = DAG.getConstant(0, DL, MVT::i32);
6079 Offsets[2] = DAG.getConstant(0, DL, MVT::i32);
6080}
6081
6082static SDValue getLoadExtOrTrunc(SelectionDAG &DAG,
6083 ISD::LoadExtType ExtType, SDValue Op,
6084 const SDLoc &SL, EVT VT) {
6085 if (VT.bitsLT(Op.getValueType()))
6086 return DAG.getNode(ISD::TRUNCATE, SL, VT, Op);
6087
6088 switch (ExtType) {
6089 case ISD::SEXTLOAD:
6090 return DAG.getNode(ISD::SIGN_EXTEND, SL, VT, Op);
6091 case ISD::ZEXTLOAD:
6092 return DAG.getNode(ISD::ZERO_EXTEND, SL, VT, Op);
6093 case ISD::EXTLOAD:
6094 return DAG.getNode(ISD::ANY_EXTEND, SL, VT, Op);
6095 case ISD::NON_EXTLOAD:
6096 return Op;
6097 }
6098
6099 llvm_unreachable("invalid ext type")::llvm::llvm_unreachable_internal("invalid ext type", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6099)
;
6100}
6101
6102SDValue SITargetLowering::widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const {
6103 SelectionDAG &DAG = DCI.DAG;
6104 if (Ld->getAlignment() < 4 || Ld->isDivergent())
6105 return SDValue();
6106
6107 // FIXME: Constant loads should all be marked invariant.
6108 unsigned AS = Ld->getAddressSpace();
6109 if (AS != AMDGPUAS::CONSTANT_ADDRESS &&
6110 AS != AMDGPUAS::CONSTANT_ADDRESS_32BIT &&
6111 (AS != AMDGPUAS::GLOBAL_ADDRESS || !Ld->isInvariant()))
6112 return SDValue();
6113
6114 // Don't do this early, since it may interfere with adjacent load merging for
6115 // illegal types. We can avoid losing alignment information for exotic types
6116 // pre-legalize.
6117 EVT MemVT = Ld->getMemoryVT();
6118 if ((MemVT.isSimple() && !DCI.isAfterLegalizeDAG()) ||
6119 MemVT.getSizeInBits() >= 32)
6120 return SDValue();
6121
6122 SDLoc SL(Ld);
6123
6124 assert((!MemVT.isVector() || Ld->getExtensionType() == ISD::NON_EXTLOAD) &&(((!MemVT.isVector() || Ld->getExtensionType() == ISD::NON_EXTLOAD
) && "unexpected vector extload") ? static_cast<void
> (0) : __assert_fail ("(!MemVT.isVector() || Ld->getExtensionType() == ISD::NON_EXTLOAD) && \"unexpected vector extload\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6125, __PRETTY_FUNCTION__))
6125 "unexpected vector extload")(((!MemVT.isVector() || Ld->getExtensionType() == ISD::NON_EXTLOAD
) && "unexpected vector extload") ? static_cast<void
> (0) : __assert_fail ("(!MemVT.isVector() || Ld->getExtensionType() == ISD::NON_EXTLOAD) && \"unexpected vector extload\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6125, __PRETTY_FUNCTION__))
;
6126
6127 // TODO: Drop only high part of range.
6128 SDValue Ptr = Ld->getBasePtr();
6129 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
6130 MVT::i32, SL, Ld->getChain(), Ptr,
6131 Ld->getOffset(),
6132 Ld->getPointerInfo(), MVT::i32,
6133 Ld->getAlignment(),
6134 Ld->getMemOperand()->getFlags(),
6135 Ld->getAAInfo(),
6136 nullptr); // Drop ranges
6137
6138 EVT TruncVT = EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits());
6139 if (MemVT.isFloatingPoint()) {
6140 assert(Ld->getExtensionType() == ISD::NON_EXTLOAD &&((Ld->getExtensionType() == ISD::NON_EXTLOAD && "unexpected fp extload"
) ? static_cast<void> (0) : __assert_fail ("Ld->getExtensionType() == ISD::NON_EXTLOAD && \"unexpected fp extload\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6141, __PRETTY_FUNCTION__))
6141 "unexpected fp extload")((Ld->getExtensionType() == ISD::NON_EXTLOAD && "unexpected fp extload"
) ? static_cast<void> (0) : __assert_fail ("Ld->getExtensionType() == ISD::NON_EXTLOAD && \"unexpected fp extload\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6141, __PRETTY_FUNCTION__))
;
6142 TruncVT = MemVT.changeTypeToInteger();
6143 }
6144
6145 SDValue Cvt = NewLoad;
6146 if (Ld->getExtensionType() == ISD::SEXTLOAD) {
6147 Cvt = DAG.getNode(ISD::SIGN_EXTEND_INREG, SL, MVT::i32, NewLoad,
6148 DAG.getValueType(TruncVT));
6149 } else if (Ld->getExtensionType() == ISD::ZEXTLOAD ||
6150 Ld->getExtensionType() == ISD::NON_EXTLOAD) {
6151 Cvt = DAG.getZeroExtendInReg(NewLoad, SL, TruncVT);
6152 } else {
6153 assert(Ld->getExtensionType() == ISD::EXTLOAD)((Ld->getExtensionType() == ISD::EXTLOAD) ? static_cast<
void> (0) : __assert_fail ("Ld->getExtensionType() == ISD::EXTLOAD"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6153, __PRETTY_FUNCTION__))
;
6154 }
6155
6156 EVT VT = Ld->getValueType(0);
6157 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
6158
6159 DCI.AddToWorklist(Cvt.getNode());
6160
6161 // We may need to handle exotic cases, such as i16->i64 extloads, so insert
6162 // the appropriate extension from the 32-bit load.
6163 Cvt = getLoadExtOrTrunc(DAG, Ld->getExtensionType(), Cvt, SL, IntVT);
6164 DCI.AddToWorklist(Cvt.getNode());
6165
6166 // Handle conversion back to floating point if necessary.
6167 Cvt = DAG.getNode(ISD::BITCAST, SL, VT, Cvt);
6168
6169 return DAG.getMergeValues({ Cvt, NewLoad.getValue(1) }, SL);
6170}
6171
6172SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
6173 SDLoc DL(Op);
6174 LoadSDNode *Load = cast<LoadSDNode>(Op);
6175 ISD::LoadExtType ExtType = Load->getExtensionType();
6176 EVT MemVT = Load->getMemoryVT();
6177
6178 if (ExtType == ISD::NON_EXTLOAD && MemVT.getSizeInBits() < 32) {
6179 if (MemVT == MVT::i16 && isTypeLegal(MVT::i16))
6180 return SDValue();
6181
6182 // FIXME: Copied from PPC
6183 // First, load into 32 bits, then truncate to 1 bit.
6184
6185 SDValue Chain = Load->getChain();
6186 SDValue BasePtr = Load->getBasePtr();
6187 MachineMemOperand *MMO = Load->getMemOperand();
6188
6189 EVT RealMemVT = (MemVT == MVT::i1) ? MVT::i8 : MVT::i16;
6190
6191 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
6192 BasePtr, RealMemVT, MMO);
6193
6194 SDValue Ops[] = {
6195 DAG.getNode(ISD::TRUNCATE, DL, MemVT, NewLD),
6196 NewLD.getValue(1)
6197 };
6198
6199 return DAG.getMergeValues(Ops, DL);
6200 }
6201
6202 if (!MemVT.isVector())
6203 return SDValue();
6204
6205 assert(Op.getValueType().getVectorElementType() == MVT::i32 &&((Op.getValueType().getVectorElementType() == MVT::i32 &&
"Custom lowering for non-i32 vectors hasn't been implemented."
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType().getVectorElementType() == MVT::i32 && \"Custom lowering for non-i32 vectors hasn't been implemented.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6206, __PRETTY_FUNCTION__))
6206 "Custom lowering for non-i32 vectors hasn't been implemented.")((Op.getValueType().getVectorElementType() == MVT::i32 &&
"Custom lowering for non-i32 vectors hasn't been implemented."
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType().getVectorElementType() == MVT::i32 && \"Custom lowering for non-i32 vectors hasn't been implemented.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6206, __PRETTY_FUNCTION__))
;
6207
6208 unsigned Alignment = Load->getAlignment();
6209 unsigned AS = Load->getAddressSpace();
6210 if (!allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT,
6211 AS, Alignment)) {
6212 SDValue Ops[2];
6213 std::tie(Ops[0], Ops[1]) = expandUnalignedLoad(Load, DAG);
6214 return DAG.getMergeValues(Ops, DL);
6215 }
6216
6217 MachineFunction &MF = DAG.getMachineFunction();
6218 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
6219 // If there is a possibilty that flat instruction access scratch memory
6220 // then we need to use the same legalization rules we use for private.
6221 if (AS == AMDGPUAS::FLAT_ADDRESS)
6222 AS = MFI->hasFlatScratchInit() ?
6223 AMDGPUAS::PRIVATE_ADDRESS : AMDGPUAS::GLOBAL_ADDRESS;
6224
6225 unsigned NumElements = MemVT.getVectorNumElements();
6226
6227 if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
6228 AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT) {
6229 if (!Op->isDivergent() && Alignment >= 4 && NumElements < 32)
6230 return SDValue();
6231 // Non-uniform loads will be selected to MUBUF instructions, so they
6232 // have the same legalization requirements as global and private
6233 // loads.
6234 //
6235 }
6236
6237 if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
6238 AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
6239 AS == AMDGPUAS::GLOBAL_ADDRESS) {
6240 if (Subtarget->getScalarizeGlobalBehavior() && !Op->isDivergent() &&
6241 !Load->isVolatile() && isMemOpHasNoClobberedMemOperand(Load) &&
6242 Alignment >= 4 && NumElements < 32)
6243 return SDValue();
6244 // Non-uniform loads will be selected to MUBUF instructions, so they
6245 // have the same legalization requirements as global and private
6246 // loads.
6247 //
6248 }
6249 if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
6250 AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
6251 AS == AMDGPUAS::GLOBAL_ADDRESS ||
6252 AS == AMDGPUAS::FLAT_ADDRESS) {
6253 if (NumElements > 4)
6254 return SplitVectorLoad(Op, DAG);
6255 // v4 loads are supported for private and global memory.
6256 return SDValue();
6257 }
6258 if (AS == AMDGPUAS::PRIVATE_ADDRESS) {
6259 // Depending on the setting of the private_element_size field in the
6260 // resource descriptor, we can only make private accesses up to a certain
6261 // size.
6262 switch (Subtarget->getMaxPrivateElementSize()) {
6263 case 4:
6264 return scalarizeVectorLoad(Load, DAG);
6265 case 8:
6266 if (NumElements > 2)
6267 return SplitVectorLoad(Op, DAG);
6268 return SDValue();
6269 case 16:
6270 // Same as global/flat
6271 if (NumElements > 4)
6272 return SplitVectorLoad(Op, DAG);
6273 return SDValue();
6274 default:
6275 llvm_unreachable("unsupported private_element_size")::llvm::llvm_unreachable_internal("unsupported private_element_size"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6275)
;
6276 }
6277 } else if (AS == AMDGPUAS::LOCAL_ADDRESS) {
6278 // Use ds_read_b128 if possible.
6279 if (Subtarget->useDS128() && Load->getAlignment() >= 16 &&
6280 MemVT.getStoreSize() == 16)
6281 return SDValue();
6282
6283 if (NumElements > 2)
6284 return SplitVectorLoad(Op, DAG);
6285
6286 // SI has a hardware bug in the LDS / GDS boounds checking: if the base
6287 // address is negative, then the instruction is incorrectly treated as
6288 // out-of-bounds even if base + offsets is in bounds. Split vectorized
6289 // loads here to avoid emitting ds_read2_b32. We may re-combine the
6290 // load later in the SILoadStoreOptimizer.
6291 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
6292 NumElements == 2 && MemVT.getStoreSize() == 8 &&
6293 Load->getAlignment() < 8) {
6294 return SplitVectorLoad(Op, DAG);
6295 }
6296 }
6297 return SDValue();
6298}
6299
6300SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
6301 EVT VT = Op.getValueType();
6302 assert(VT.getSizeInBits() == 64)((VT.getSizeInBits() == 64) ? static_cast<void> (0) : __assert_fail
("VT.getSizeInBits() == 64", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6302, __PRETTY_FUNCTION__))
;
6303
6304 SDLoc DL(Op);
6305 SDValue Cond = Op.getOperand(0);
6306
6307 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
6308 SDValue One = DAG.getConstant(1, DL, MVT::i32);
6309
6310 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
6311 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
6312
6313 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero);
6314 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero);
6315
6316 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1);
6317
6318 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One);
6319 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One);
6320
6321 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
6322
6323 SDValue Res = DAG.getBuildVector(MVT::v2i32, DL, {Lo, Hi});
6324 return DAG.getNode(ISD::BITCAST, DL, VT, Res);
6325}
6326
6327// Catch division cases where we can use shortcuts with rcp and rsq
6328// instructions.
6329SDValue SITargetLowering::lowerFastUnsafeFDIV(SDValue Op,
6330 SelectionDAG &DAG) const {
6331 SDLoc SL(Op);
6332 SDValue LHS = Op.getOperand(0);
6333 SDValue RHS = Op.getOperand(1);
6334 EVT VT = Op.getValueType();
6335 const SDNodeFlags Flags = Op->getFlags();
6336 bool Unsafe = DAG.getTarget().Options.UnsafeFPMath || Flags.hasAllowReciprocal();
6337
6338 if (!Unsafe && VT == MVT::f32 && Subtarget->hasFP32Denormals())
6339 return SDValue();
6340
6341 if (const ConstantFPSDNode *CLHS = dyn_cast<ConstantFPSDNode>(LHS)) {
6342 if (Unsafe || VT == MVT::f32 || VT == MVT::f16) {
6343 if (CLHS->isExactlyValue(1.0)) {
6344 // v_rcp_f32 and v_rsq_f32 do not support denormals, and according to
6345 // the CI documentation has a worst case error of 1 ulp.
6346 // OpenCL requires <= 2.5 ulp for 1.0 / x, so it should always be OK to
6347 // use it as long as we aren't trying to use denormals.
6348 //
6349 // v_rcp_f16 and v_rsq_f16 DO support denormals.
6350
6351 // 1.0 / sqrt(x) -> rsq(x)
6352
6353 // XXX - Is UnsafeFPMath sufficient to do this for f64? The maximum ULP
6354 // error seems really high at 2^29 ULP.
6355 if (RHS.getOpcode() == ISD::FSQRT)
6356 return DAG.getNode(AMDGPUISD::RSQ, SL, VT, RHS.getOperand(0));
6357
6358 // 1.0 / x -> rcp(x)
6359 return DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
6360 }
6361
6362 // Same as for 1.0, but expand the sign out of the constant.
6363 if (CLHS->isExactlyValue(-1.0)) {
6364 // -1.0 / x -> rcp (fneg x)
6365 SDValue FNegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
6366 return DAG.getNode(AMDGPUISD::RCP, SL, VT, FNegRHS);
6367 }
6368 }
6369 }
6370
6371 if (Unsafe) {
6372 // Turn into multiply by the reciprocal.
6373 // x / y -> x * (1.0 / y)
6374 SDValue Recip = DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
6375 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip, Flags);
6376 }
6377
6378 return SDValue();
6379}
6380
6381static SDValue getFPBinOp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &SL,
6382 EVT VT, SDValue A, SDValue B, SDValue GlueChain) {
6383 if (GlueChain->getNumValues() <= 1) {
6384 return DAG.getNode(Opcode, SL, VT, A, B);
6385 }
6386
6387 assert(GlueChain->getNumValues() == 3)((GlueChain->getNumValues() == 3) ? static_cast<void>
(0) : __assert_fail ("GlueChain->getNumValues() == 3", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6387, __PRETTY_FUNCTION__))
;
6388
6389 SDVTList VTList = DAG.getVTList(VT, MVT::Other, MVT::Glue);
6390 switch (Opcode) {
6391 default: llvm_unreachable("no chain equivalent for opcode")::llvm::llvm_unreachable_internal("no chain equivalent for opcode"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6391)
;
6392 case ISD::FMUL:
6393 Opcode = AMDGPUISD::FMUL_W_CHAIN;
6394 break;
6395 }
6396
6397 return DAG.getNode(Opcode, SL, VTList, GlueChain.getValue(1), A, B,
6398 GlueChain.getValue(2));
6399}
6400
6401static SDValue getFPTernOp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &SL,
6402 EVT VT, SDValue A, SDValue B, SDValue C,
6403 SDValue GlueChain) {
6404 if (GlueChain->getNumValues() <= 1) {
6405 return DAG.getNode(Opcode, SL, VT, A, B, C);
6406 }
6407
6408 assert(GlueChain->getNumValues() == 3)((GlueChain->getNumValues() == 3) ? static_cast<void>
(0) : __assert_fail ("GlueChain->getNumValues() == 3", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6408, __PRETTY_FUNCTION__))
;
6409
6410 SDVTList VTList = DAG.getVTList(VT, MVT::Other, MVT::Glue);
6411 switch (Opcode) {
6412 default: llvm_unreachable("no chain equivalent for opcode")::llvm::llvm_unreachable_internal("no chain equivalent for opcode"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6412)
;
6413 case ISD::FMA:
6414 Opcode = AMDGPUISD::FMA_W_CHAIN;
6415 break;
6416 }
6417
6418 return DAG.getNode(Opcode, SL, VTList, GlueChain.getValue(1), A, B, C,
6419 GlueChain.getValue(2));
6420}
6421
6422SDValue SITargetLowering::LowerFDIV16(SDValue Op, SelectionDAG &DAG) const {
6423 if (SDValue FastLowered = lowerFastUnsafeFDIV(Op, DAG))
6424 return FastLowered;
6425
6426 SDLoc SL(Op);
6427 SDValue Src0 = Op.getOperand(0);
6428 SDValue Src1 = Op.getOperand(1);
6429
6430 SDValue CvtSrc0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
6431 SDValue CvtSrc1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1);
6432
6433 SDValue RcpSrc1 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, CvtSrc1);
6434 SDValue Quot = DAG.getNode(ISD::FMUL, SL, MVT::f32, CvtSrc0, RcpSrc1);
6435
6436 SDValue FPRoundFlag = DAG.getTargetConstant(0, SL, MVT::i32);
6437 SDValue BestQuot = DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Quot, FPRoundFlag);
6438
6439 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f16, BestQuot, Src1, Src0);
6440}
6441
6442// Faster 2.5 ULP division that does not support denormals.
6443SDValue SITargetLowering::lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const {
6444 SDLoc SL(Op);
6445 SDValue LHS = Op.getOperand(1);
6446 SDValue RHS = Op.getOperand(2);
6447
6448 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
6449
6450 const APFloat K0Val(BitsToFloat(0x6f800000));
6451 const SDValue K0 = DAG.getConstantFP(K0Val, SL, MVT::f32);
6452
6453 const APFloat K1Val(BitsToFloat(0x2f800000));
6454 const SDValue K1 = DAG.getConstantFP(K1Val, SL, MVT::f32);
6455
6456 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
6457
6458 EVT SetCCVT =
6459 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
6460
6461 SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);
6462
6463 SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
6464
6465 // TODO: Should this propagate fast-math-flags?
6466 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
6467
6468 // rcp does not support denormals.
6469 SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1);
6470
6471 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
6472
6473 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
6474}
6475
6476SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
6477 if (SDValue FastLowered = lowerFastUnsafeFDIV(Op, DAG))
6478 return FastLowered;
6479
6480 SDLoc SL(Op);
6481 SDValue LHS = Op.getOperand(0);
6482 SDValue RHS = Op.getOperand(1);
6483
6484 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
6485
6486 SDVTList ScaleVT = DAG.getVTList(MVT::f32, MVT::i1);
6487
6488 SDValue DenominatorScaled = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT,
6489 RHS, RHS, LHS);
6490 SDValue NumeratorScaled = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT,
6491 LHS, RHS, LHS);
6492
6493 // Denominator is scaled to not be denormal, so using rcp is ok.
6494 SDValue ApproxRcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32,
6495 DenominatorScaled);
6496 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f32,
6497 DenominatorScaled);
6498
6499 const unsigned Denorm32Reg = AMDGPU::Hwreg::ID_MODE |
6500 (4 << AMDGPU::Hwreg::OFFSET_SHIFT_) |
6501 (1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_);
6502
6503 const SDValue BitField = DAG.getTargetConstant(Denorm32Reg, SL, MVT::i16);
6504
6505 if (!Subtarget->hasFP32Denormals()) {
6506 SDVTList BindParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
6507 const SDValue EnableDenormValue = DAG.getConstant(FP_DENORM_FLUSH_NONE3,
6508 SL, MVT::i32);
6509 SDValue EnableDenorm = DAG.getNode(AMDGPUISD::SETREG, SL, BindParamVTs,
6510 DAG.getEntryNode(),
6511 EnableDenormValue, BitField);
6512 SDValue Ops[3] = {
6513 NegDivScale0,
6514 EnableDenorm.getValue(0),
6515 EnableDenorm.getValue(1)
6516 };
6517
6518 NegDivScale0 = DAG.getMergeValues(Ops, SL);
6519 }
6520
6521 SDValue Fma0 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0,
6522 ApproxRcp, One, NegDivScale0);
6523
6524 SDValue Fma1 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, Fma0, ApproxRcp,
6525 ApproxRcp, Fma0);
6526
6527 SDValue Mul = getFPBinOp(DAG, ISD::FMUL, SL, MVT::f32, NumeratorScaled,
6528 Fma1, Fma1);
6529
6530 SDValue Fma2 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Mul,
6531 NumeratorScaled, Mul);
6532
6533 SDValue Fma3 = getFPTernOp(DAG, ISD::FMA,SL, MVT::f32, Fma2, Fma1, Mul, Fma2);
6534
6535 SDValue Fma4 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Fma3,
6536 NumeratorScaled, Fma3);
6537
6538 if (!Subtarget->hasFP32Denormals()) {
6539 const SDValue DisableDenormValue =
6540 DAG.getConstant(FP_DENORM_FLUSH_IN_FLUSH_OUT0, SL, MVT::i32);
6541 SDValue DisableDenorm = DAG.getNode(AMDGPUISD::SETREG, SL, MVT::Other,
6542 Fma4.getValue(1),
6543 DisableDenormValue,
6544 BitField,
6545 Fma4.getValue(2));
6546
6547 SDValue OutputChain = DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
6548 DisableDenorm, DAG.getRoot());
6549 DAG.setRoot(OutputChain);
6550 }
6551
6552 SDValue Scale = NumeratorScaled.getValue(1);
6553 SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f32,
6554 Fma4, Fma1, Fma3, Scale);
6555
6556 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f32, Fmas, RHS, LHS);
6557}
6558
6559SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
6560 if (DAG.getTarget().Options.UnsafeFPMath)
6561 return lowerFastUnsafeFDIV(Op, DAG);
6562
6563 SDLoc SL(Op);
6564 SDValue X = Op.getOperand(0);
6565 SDValue Y = Op.getOperand(1);
6566
6567 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
6568
6569 SDVTList ScaleVT = DAG.getVTList(MVT::f64, MVT::i1);
6570
6571 SDValue DivScale0 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, Y, Y, X);
6572
6573 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f64, DivScale0);
6574
6575 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0);
6576
6577 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One);
6578
6579 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp);
6580
6581 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One);
6582
6583 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X);
6584
6585 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1);
6586 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3);
6587
6588 SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f64,
6589 NegDivScale0, Mul, DivScale1);
6590
6591 SDValue Scale;
6592
6593 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) {
6594 // Workaround a hardware bug on SI where the condition output from div_scale
6595 // is not usable.
6596
6597 const SDValue Hi = DAG.getConstant(1, SL, MVT::i32);
6598
6599 // Figure out if the scale to use for div_fmas.
6600 SDValue NumBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
6601 SDValue DenBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Y);
6602 SDValue Scale0BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale0);
6603 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1);
6604
6605 SDValue NumHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, NumBC, Hi);
6606 SDValue DenHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, DenBC, Hi);
6607
6608 SDValue Scale0Hi
6609 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale0BC, Hi);
6610 SDValue Scale1Hi
6611 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale1BC, Hi);
6612
6613 SDValue CmpDen = DAG.getSetCC(SL, MVT::i1, DenHi, Scale0Hi, ISD::SETEQ);
6614 SDValue CmpNum = DAG.getSetCC(SL, MVT::i1, NumHi, Scale1Hi, ISD::SETEQ);
6615 Scale = DAG.getNode(ISD::XOR, SL, MVT::i1, CmpNum, CmpDen);
6616 } else {
6617 Scale = DivScale1.getValue(1);
6618 }
6619
6620 SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f64,
6621 Fma4, Fma3, Mul, Scale);
6622
6623 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f64, Fmas, Y, X);
6624}
6625
6626SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
6627 EVT VT = Op.getValueType();
6628
6629 if (VT == MVT::f32)
6630 return LowerFDIV32(Op, DAG);
6631
6632 if (VT == MVT::f64)
6633 return LowerFDIV64(Op, DAG);
6634
6635 if (VT == MVT::f16)
6636 return LowerFDIV16(Op, DAG);
6637
6638 llvm_unreachable("Unexpected type for fdiv")::llvm::llvm_unreachable_internal("Unexpected type for fdiv",
"/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6638)
;
6639}
6640
6641SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
6642 SDLoc DL(Op);
6643 StoreSDNode *Store = cast<StoreSDNode>(Op);
6644 EVT VT = Store->getMemoryVT();
6645
6646 if (VT == MVT::i1) {
6647 return DAG.getTruncStore(Store->getChain(), DL,
6648 DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32),
6649 Store->getBasePtr(), MVT::i1, Store->getMemOperand());
6650 }
6651
6652 assert(VT.isVector() &&((VT.isVector() && Store->getValue().getValueType(
).getScalarType() == MVT::i32) ? static_cast<void> (0) :
__assert_fail ("VT.isVector() && Store->getValue().getValueType().getScalarType() == MVT::i32"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6653, __PRETTY_FUNCTION__))
6653 Store->getValue().getValueType().getScalarType() == MVT::i32)((VT.isVector() && Store->getValue().getValueType(
).getScalarType() == MVT::i32) ? static_cast<void> (0) :
__assert_fail ("VT.isVector() && Store->getValue().getValueType().getScalarType() == MVT::i32"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6653, __PRETTY_FUNCTION__))
;
6654
6655 unsigned AS = Store->getAddressSpace();
6656 if (!allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
6657 AS, Store->getAlignment())) {
6658 return expandUnalignedStore(Store, DAG);
6659 }
6660
6661 MachineFunction &MF = DAG.getMachineFunction();
6662 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
6663 // If there is a possibilty that flat instruction access scratch memory
6664 // then we need to use the same legalization rules we use for private.
6665 if (AS == AMDGPUAS::FLAT_ADDRESS)
6666 AS = MFI->hasFlatScratchInit() ?
6667 AMDGPUAS::PRIVATE_ADDRESS : AMDGPUAS::GLOBAL_ADDRESS;
6668
6669 unsigned NumElements = VT.getVectorNumElements();
6670 if (AS == AMDGPUAS::GLOBAL_ADDRESS ||
6671 AS == AMDGPUAS::FLAT_ADDRESS) {
6672 if (NumElements > 4)
6673 return SplitVectorStore(Op, DAG);
6674 return SDValue();
6675 } else if (AS == AMDGPUAS::PRIVATE_ADDRESS) {
6676 switch (Subtarget->getMaxPrivateElementSize()) {
6677 case 4:
6678 return scalarizeVectorStore(Store, DAG);
6679 case 8:
6680 if (NumElements > 2)
6681 return SplitVectorStore(Op, DAG);
6682 return SDValue();
6683 case 16:
6684 if (NumElements > 4)
6685 return SplitVectorStore(Op, DAG);
6686 return SDValue();
6687 default:
6688 llvm_unreachable("unsupported private_element_size")::llvm::llvm_unreachable_internal("unsupported private_element_size"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6688)
;
6689 }
6690 } else if (AS == AMDGPUAS::LOCAL_ADDRESS) {
6691 // Use ds_write_b128 if possible.
6692 if (Subtarget->useDS128() && Store->getAlignment() >= 16 &&
6693 VT.getStoreSize() == 16)
6694 return SDValue();
6695
6696 if (NumElements > 2)
6697 return SplitVectorStore(Op, DAG);
6698
6699 // SI has a hardware bug in the LDS / GDS boounds checking: if the base
6700 // address is negative, then the instruction is incorrectly treated as
6701 // out-of-bounds even if base + offsets is in bounds. Split vectorized
6702 // stores here to avoid emitting ds_write2_b32. We may re-combine the
6703 // store later in the SILoadStoreOptimizer.
6704 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
6705 NumElements == 2 && VT.getStoreSize() == 8 &&
6706 Store->getAlignment() < 8) {
6707 return SplitVectorStore(Op, DAG);
6708 }
6709
6710 return SDValue();
6711 } else {
6712 llvm_unreachable("unhandled address space")::llvm::llvm_unreachable_internal("unhandled address space", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6712)
;
6713 }
6714}
6715
6716SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
6717 SDLoc DL(Op);
6718 EVT VT = Op.getValueType();
6719 SDValue Arg = Op.getOperand(0);
6720 SDValue TrigVal;
6721
6722 // TODO: Should this propagate fast-math-flags?
6723
6724 SDValue OneOver2Pi = DAG.getConstantFP(0.5 / M_PI3.14159265358979323846, DL, VT);
6725
6726 if (Subtarget->hasTrigReducedRange()) {
6727 SDValue MulVal = DAG.getNode(ISD::FMUL, DL, VT, Arg, OneOver2Pi);
6728 TrigVal = DAG.getNode(AMDGPUISD::FRACT, DL, VT, MulVal);
6729 } else {
6730 TrigVal = DAG.getNode(ISD::FMUL, DL, VT, Arg, OneOver2Pi);
6731 }
6732
6733 switch (Op.getOpcode()) {
6734 case ISD::FCOS:
6735 return DAG.getNode(AMDGPUISD::COS_HW, SDLoc(Op), VT, TrigVal);
6736 case ISD::FSIN:
6737 return DAG.getNode(AMDGPUISD::SIN_HW, SDLoc(Op), VT, TrigVal);
6738 default:
6739 llvm_unreachable("Wrong trig opcode")::llvm::llvm_unreachable_internal("Wrong trig opcode", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6739)
;
6740 }
6741}
6742
6743SDValue SITargetLowering::LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
6744 AtomicSDNode *AtomicNode = cast<AtomicSDNode>(Op);
6745 assert(AtomicNode->isCompareAndSwap())((AtomicNode->isCompareAndSwap()) ? static_cast<void>
(0) : __assert_fail ("AtomicNode->isCompareAndSwap()", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6745, __PRETTY_FUNCTION__))
;
6746 unsigned AS = AtomicNode->getAddressSpace();
6747
6748 // No custom lowering required for local address space
6749 if (!isFlatGlobalAddrSpace(AS))
6750 return Op;
6751
6752 // Non-local address space requires custom lowering for atomic compare
6753 // and swap; cmp and swap should be in a v2i32 or v2i64 in case of _X2
6754 SDLoc DL(Op);
6755 SDValue ChainIn = Op.getOperand(0);
6756 SDValue Addr = Op.getOperand(1);
6757 SDValue Old = Op.getOperand(2);
6758 SDValue New = Op.getOperand(3);
6759 EVT VT = Op.getValueType();
6760 MVT SimpleVT = VT.getSimpleVT();
6761 MVT VecType = MVT::getVectorVT(SimpleVT, 2);
6762
6763 SDValue NewOld = DAG.getBuildVector(VecType, DL, {New, Old});
6764 SDValue Ops[] = { ChainIn, Addr, NewOld };
6765
6766 return DAG.getMemIntrinsicNode(AMDGPUISD::ATOMIC_CMP_SWAP, DL, Op->getVTList(),
6767 Ops, VT, AtomicNode->getMemOperand());
6768}
6769
6770//===----------------------------------------------------------------------===//
6771// Custom DAG optimizations
6772//===----------------------------------------------------------------------===//
6773
6774SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
6775 DAGCombinerInfo &DCI) const {
6776 EVT VT = N->getValueType(0);
6777 EVT ScalarVT = VT.getScalarType();
6778 if (ScalarVT != MVT::f32)
6779 return SDValue();
6780
6781 SelectionDAG &DAG = DCI.DAG;
6782 SDLoc DL(N);
6783
6784 SDValue Src = N->getOperand(0);
6785 EVT SrcVT = Src.getValueType();
6786
6787 // TODO: We could try to match extracting the higher bytes, which would be
6788 // easier if i8 vectors weren't promoted to i32 vectors, particularly after
6789 // types are legalized. v4i8 -> v4f32 is probably the only case to worry
6790 // about in practice.
6791 if (DCI.isAfterLegalizeDAG() && SrcVT == MVT::i32) {
6792 if (DAG.MaskedValueIsZero(Src, APInt::getHighBitsSet(32, 24))) {
6793 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Src);
6794 DCI.AddToWorklist(Cvt.getNode());
6795 return Cvt;
6796 }
6797 }
6798
6799 return SDValue();
6800}
6801
6802// (shl (add x, c1), c2) -> add (shl x, c2), (shl c1, c2)
6803
6804// This is a variant of
6805// (mul (add x, c1), c2) -> add (mul x, c2), (mul c1, c2),
6806//
6807// The normal DAG combiner will do this, but only if the add has one use since
6808// that would increase the number of instructions.
6809//
6810// This prevents us from seeing a constant offset that can be folded into a
6811// memory instruction's addressing mode. If we know the resulting add offset of
6812// a pointer can be folded into an addressing offset, we can replace the pointer
6813// operand with the add of new constant offset. This eliminates one of the uses,
6814// and may allow the remaining use to also be simplified.
6815//
6816SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,
6817 unsigned AddrSpace,
6818 EVT MemVT,
6819 DAGCombinerInfo &DCI) const {
6820 SDValue N0 = N->getOperand(0);
6821 SDValue N1 = N->getOperand(1);
6822
6823 // We only do this to handle cases where it's profitable when there are
6824 // multiple uses of the add, so defer to the standard combine.
6825 if ((N0.getOpcode() != ISD::ADD && N0.getOpcode() != ISD::OR) ||
6826 N0->hasOneUse())
6827 return SDValue();
6828
6829 const ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(N1);
6830 if (!CN1)
6831 return SDValue();
6832
6833 const ConstantSDNode *CAdd = dyn_cast<ConstantSDNode>(N0.getOperand(1));
6834 if (!CAdd)
6835 return SDValue();
6836
6837 // If the resulting offset is too large, we can't fold it into the addressing
6838 // mode offset.
6839 APInt Offset = CAdd->getAPIntValue() << CN1->getAPIntValue();
6840 Type *Ty = MemVT.getTypeForEVT(*DCI.DAG.getContext());
6841
6842 AddrMode AM;
6843 AM.HasBaseReg = true;
6844 AM.BaseOffs = Offset.getSExtValue();
6845 if (!isLegalAddressingMode(DCI.DAG.getDataLayout(), AM, Ty, AddrSpace))
6846 return SDValue();
6847
6848 SelectionDAG &DAG = DCI.DAG;
6849 SDLoc SL(N);
6850 EVT VT = N->getValueType(0);
6851
6852 SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1);
6853 SDValue COffset = DAG.getConstant(Offset, SL, MVT::i32);
6854
6855 SDNodeFlags Flags;
6856 Flags.setNoUnsignedWrap(N->getFlags().hasNoUnsignedWrap() &&
6857 (N0.getOpcode() == ISD::OR ||
6858 N0->getFlags().hasNoUnsignedWrap()));
6859
6860 return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset, Flags);
6861}
6862
6863SDValue SITargetLowering::performMemSDNodeCombine(MemSDNode *N,
6864 DAGCombinerInfo &DCI) const {
6865 SDValue Ptr = N->getBasePtr();
6866 SelectionDAG &DAG = DCI.DAG;
6867 SDLoc SL(N);
6868
6869 // TODO: We could also do this for multiplies.
6870 if (Ptr.getOpcode() == ISD::SHL) {
6871 SDValue NewPtr = performSHLPtrCombine(Ptr.getNode(), N->getAddressSpace(),
6872 N->getMemoryVT(), DCI);
6873 if (NewPtr) {
6874 SmallVector<SDValue, 8> NewOps(N->op_begin(), N->op_end());
6875
6876 NewOps[N->getOpcode() == ISD::STORE ? 2 : 1] = NewPtr;
6877 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
6878 }
6879 }
6880
6881 return SDValue();
6882}
6883
6884static bool bitOpWithConstantIsReducible(unsigned Opc, uint32_t Val) {
6885 return (Opc == ISD::AND && (Val == 0 || Val == 0xffffffff)) ||
6886 (Opc == ISD::OR && (Val == 0xffffffff || Val == 0)) ||
6887 (Opc == ISD::XOR && Val == 0);
6888}
6889
6890// Break up 64-bit bit operation of a constant into two 32-bit and/or/xor. This
6891// will typically happen anyway for a VALU 64-bit and. This exposes other 32-bit
6892// integer combine opportunities since most 64-bit operations are decomposed
6893// this way. TODO: We won't want this for SALU especially if it is an inline
6894// immediate.
6895SDValue SITargetLowering::splitBinaryBitConstantOp(
6896 DAGCombinerInfo &DCI,
6897 const SDLoc &SL,
6898 unsigned Opc, SDValue LHS,
6899 const ConstantSDNode *CRHS) const {
6900 uint64_t Val = CRHS->getZExtValue();
6901 uint32_t ValLo = Lo_32(Val);
6902 uint32_t ValHi = Hi_32(Val);
6903 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
6904
6905 if ((bitOpWithConstantIsReducible(Opc, ValLo) ||
6906 bitOpWithConstantIsReducible(Opc, ValHi)) ||
6907 (CRHS->hasOneUse() && !TII->isInlineConstant(CRHS->getAPIntValue()))) {
6908 // If we need to materialize a 64-bit immediate, it will be split up later
6909 // anyway. Avoid creating the harder to understand 64-bit immediate
6910 // materialization.
6911 return splitBinaryBitConstantOpImpl(DCI, SL, Opc, LHS, ValLo, ValHi);
6912 }
6913
6914 return SDValue();
6915}
6916
6917// Returns true if argument is a boolean value which is not serialized into
6918// memory or argument and does not require v_cmdmask_b32 to be deserialized.
6919static bool isBoolSGPR(SDValue V) {
6920 if (V.getValueType() != MVT::i1)
6921 return false;
6922 switch (V.getOpcode()) {
6923 default: break;
6924 case ISD::SETCC:
6925 case ISD::AND:
6926 case ISD::OR:
6927 case ISD::XOR:
6928 case AMDGPUISD::FP_CLASS:
6929 return true;
6930 }
6931 return false;
6932}
6933
6934// If a constant has all zeroes or all ones within each byte return it.
6935// Otherwise return 0.
6936static uint32_t getConstantPermuteMask(uint32_t C) {
6937 // 0xff for any zero byte in the mask
6938 uint32_t ZeroByteMask = 0;
6939 if (!(C & 0x000000ff)) ZeroByteMask |= 0x000000ff;
6940 if (!(C & 0x0000ff00)) ZeroByteMask |= 0x0000ff00;
6941 if (!(C & 0x00ff0000)) ZeroByteMask |= 0x00ff0000;
6942 if (!(C & 0xff000000)) ZeroByteMask |= 0xff000000;
6943 uint32_t NonZeroByteMask = ~ZeroByteMask; // 0xff for any non-zero byte
6944 if ((NonZeroByteMask & C) != NonZeroByteMask)
6945 return 0; // Partial bytes selected.
6946 return C;
6947}
6948
6949// Check if a node selects whole bytes from its operand 0 starting at a byte
6950// boundary while masking the rest. Returns select mask as in the v_perm_b32
6951// or -1 if not succeeded.
6952// Note byte select encoding:
6953// value 0-3 selects corresponding source byte;
6954// value 0xc selects zero;
6955// value 0xff selects 0xff.
6956static uint32_t getPermuteMask(SelectionDAG &DAG, SDValue V) {
6957 assert(V.getValueSizeInBits() == 32)((V.getValueSizeInBits() == 32) ? static_cast<void> (0)
: __assert_fail ("V.getValueSizeInBits() == 32", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6957, __PRETTY_FUNCTION__))
;
6958
6959 if (V.getNumOperands() != 2)
6960 return ~0;
6961
6962 ConstantSDNode *N1 = dyn_cast<ConstantSDNode>(V.getOperand(1));
6963 if (!N1)
6964 return ~0;
6965
6966 uint32_t C = N1->getZExtValue();
6967
6968 switch (V.getOpcode()) {
6969 default:
6970 break;
6971 case ISD::AND:
6972 if (uint32_t ConstMask = getConstantPermuteMask(C)) {
6973 return (0x03020100 & ConstMask) | (0x0c0c0c0c & ~ConstMask);
6974 }
6975 break;
6976
6977 case ISD::OR:
6978 if (uint32_t ConstMask = getConstantPermuteMask(C)) {
6979 return (0x03020100 & ~ConstMask) | ConstMask;
6980 }
6981 break;
6982
6983 case ISD::SHL:
6984 if (C % 8)
6985 return ~0;
6986
6987 return uint32_t((0x030201000c0c0c0cull << C) >> 32);
6988
6989 case ISD::SRL:
6990 if (C % 8)
6991 return ~0;
6992
6993 return uint32_t(0x0c0c0c0c03020100ull >> C);
6994 }
6995
6996 return ~0;
6997}
6998
6999SDValue SITargetLowering::performAndCombine(SDNode *N,
7000 DAGCombinerInfo &DCI) const {
7001 if (DCI.isBeforeLegalize())
7002 return SDValue();
7003
7004 SelectionDAG &DAG = DCI.DAG;
7005 EVT VT = N->getValueType(0);
7006 SDValue LHS = N->getOperand(0);
7007 SDValue RHS = N->getOperand(1);
7008
7009
7010 const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS);
7011 if (VT == MVT::i64 && CRHS) {
7012 if (SDValue Split
7013 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::AND, LHS, CRHS))
7014 return Split;
7015 }
7016
7017 if (CRHS && VT == MVT::i32) {
7018 // and (srl x, c), mask => shl (bfe x, nb + c, mask >> nb), nb
7019 // nb = number of trailing zeroes in mask
7020 // It can be optimized out using SDWA for GFX8+ in the SDWA peephole pass,
7021 // given that we are selecting 8 or 16 bit fields starting at byte boundary.
7022 uint64_t Mask = CRHS->getZExtValue();
7023 unsigned Bits = countPopulation(Mask);
7024 if (getSubtarget()->hasSDWA() && LHS->getOpcode() == ISD::SRL &&
7025 (Bits == 8 || Bits == 16) && isShiftedMask_64(Mask) && !(Mask & 1)) {
7026 if (auto *CShift = dyn_cast<ConstantSDNode>(LHS->getOperand(1))) {
7027 unsigned Shift = CShift->getZExtValue();
7028 unsigned NB = CRHS->getAPIntValue().countTrailingZeros();
7029 unsigned Offset = NB + Shift;
7030 if ((Offset & (Bits - 1)) == 0) { // Starts at a byte or word boundary.
7031 SDLoc SL(N);
7032 SDValue BFE = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
7033 LHS->getOperand(0),
7034 DAG.getConstant(Offset, SL, MVT::i32),
7035 DAG.getConstant(Bits, SL, MVT::i32));
7036 EVT NarrowVT = EVT::getIntegerVT(*DAG.getContext(), Bits);
7037 SDValue Ext = DAG.getNode(ISD::AssertZext, SL, VT, BFE,
7038 DAG.getValueType(NarrowVT));
7039 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(LHS), VT, Ext,
7040 DAG.getConstant(NB, SDLoc(CRHS), MVT::i32));
7041 return Shl;
7042 }
7043 }
7044 }
7045
7046 // and (perm x, y, c1), c2 -> perm x, y, permute_mask(c1, c2)
7047 if (LHS.hasOneUse() && LHS.getOpcode() == AMDGPUISD::PERM &&
7048 isa<ConstantSDNode>(LHS.getOperand(2))) {
7049 uint32_t Sel = getConstantPermuteMask(Mask);
7050 if (!Sel)
7051 return SDValue();
7052
7053 // Select 0xc for all zero bytes
7054 Sel = (LHS.getConstantOperandVal(2) & Sel) | (~Sel & 0x0c0c0c0c);
7055 SDLoc DL(N);
7056 return DAG.getNode(AMDGPUISD::PERM, DL, MVT::i32, LHS.getOperand(0),
7057 LHS.getOperand(1), DAG.getConstant(Sel, DL, MVT::i32));
7058 }
7059 }
7060
7061 // (and (fcmp ord x, x), (fcmp une (fabs x), inf)) ->
7062 // fp_class x, ~(s_nan | q_nan | n_infinity | p_infinity)
7063 if (LHS.getOpcode() == ISD::SETCC && RHS.getOpcode() == ISD::SETCC) {
7064 ISD::CondCode LCC = cast<CondCodeSDNode>(LHS.getOperand(2))->get();
7065 ISD::CondCode RCC = cast<CondCodeSDNode>(RHS.getOperand(2))->get();
7066
7067 SDValue X = LHS.getOperand(0);
7068 SDValue Y = RHS.getOperand(0);
7069 if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X)
7070 return SDValue();
7071
7072 if (LCC == ISD::SETO) {
7073 if (X != LHS.getOperand(1))
7074 return SDValue();
7075
7076 if (RCC == ISD::SETUNE) {
7077 const ConstantFPSDNode *C1 = dyn_cast<ConstantFPSDNode>(RHS.getOperand(1));
7078 if (!C1 || !C1->isInfinity() || C1->isNegative())
7079 return SDValue();
7080
7081 const uint32_t Mask = SIInstrFlags::N_NORMAL |
7082 SIInstrFlags::N_SUBNORMAL |
7083 SIInstrFlags::N_ZERO |
7084 SIInstrFlags::P_ZERO |
7085 SIInstrFlags::P_SUBNORMAL |
7086 SIInstrFlags::P_NORMAL;
7087
7088 static_assert(((~(SIInstrFlags::S_NAN |
7089 SIInstrFlags::Q_NAN |
7090 SIInstrFlags::N_INFINITY |
7091 SIInstrFlags::P_INFINITY)) & 0x3ff) == Mask,
7092 "mask not equal");
7093
7094 SDLoc DL(N);
7095 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1,
7096 X, DAG.getConstant(Mask, DL, MVT::i32));
7097 }
7098 }
7099 }
7100
7101 if (RHS.getOpcode() == ISD::SETCC && LHS.getOpcode() == AMDGPUISD::FP_CLASS)
7102 std::swap(LHS, RHS);
7103
7104 if (LHS.getOpcode() == ISD::SETCC && RHS.getOpcode() == AMDGPUISD::FP_CLASS &&
7105 RHS.hasOneUse()) {
7106 ISD::CondCode LCC = cast<CondCodeSDNode>(LHS.getOperand(2))->get();
7107 // and (fcmp seto), (fp_class x, mask) -> fp_class x, mask & ~(p_nan | n_nan)
7108 // and (fcmp setuo), (fp_class x, mask) -> fp_class x, mask & (p_nan | n_nan)
7109 const ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(RHS.getOperand(1));
7110 if ((LCC == ISD::SETO || LCC == ISD::SETUO) && Mask &&
7111 (RHS.getOperand(0) == LHS.getOperand(0) &&
7112 LHS.getOperand(0) == LHS.getOperand(1))) {
7113 const unsigned OrdMask = SIInstrFlags::S_NAN | SIInstrFlags::Q_NAN;
7114 unsigned NewMask = LCC == ISD::SETO ?
7115 Mask->getZExtValue() & ~OrdMask :
7116 Mask->getZExtValue() & OrdMask;
7117
7118 SDLoc DL(N);
7119 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1, RHS.getOperand(0),
7120 DAG.getConstant(NewMask, DL, MVT::i32));
7121 }
7122 }
7123
7124 if (VT == MVT::i32 &&
7125 (RHS.getOpcode() == ISD::SIGN_EXTEND || LHS.getOpcode() == ISD::SIGN_EXTEND)) {
7126 // and x, (sext cc from i1) => select cc, x, 0
7127 if (RHS.getOpcode() != ISD::SIGN_EXTEND)
7128 std::swap(LHS, RHS);
7129 if (isBoolSGPR(RHS.getOperand(0)))
7130 return DAG.getSelect(SDLoc(N), MVT::i32, RHS.getOperand(0),
7131 LHS, DAG.getConstant(0, SDLoc(N), MVT::i32));
7132 }
7133
7134 // and (op x, c1), (op y, c2) -> perm x, y, permute_mask(c1, c2)
7135 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
7136 if (VT == MVT::i32 && LHS.hasOneUse() && RHS.hasOneUse() &&
7137 N->isDivergent() && TII->pseudoToMCOpcode(AMDGPU::V_PERM_B32) != -1) {
7138 uint32_t LHSMask = getPermuteMask(DAG, LHS);
7139 uint32_t RHSMask = getPermuteMask(DAG, RHS);
7140 if (LHSMask != ~0u && RHSMask != ~0u) {
7141 // Canonicalize the expression in an attempt to have fewer unique masks
7142 // and therefore fewer registers used to hold the masks.
7143 if (LHSMask > RHSMask) {
7144 std::swap(LHSMask, RHSMask);
7145 std::swap(LHS, RHS);
7146 }
7147
7148 // Select 0xc for each lane used from source operand. Zero has 0xc mask
7149 // set, 0xff have 0xff in the mask, actual lanes are in the 0-3 range.
7150 uint32_t LHSUsedLanes = ~(LHSMask & 0x0c0c0c0c) & 0x0c0c0c0c;
7151 uint32_t RHSUsedLanes = ~(RHSMask & 0x0c0c0c0c) & 0x0c0c0c0c;
7152
7153 // Check of we need to combine values from two sources within a byte.
7154 if (!(LHSUsedLanes & RHSUsedLanes) &&
7155 // If we select high and lower word keep it for SDWA.
7156 // TODO: teach SDWA to work with v_perm_b32 and remove the check.
7157 !(LHSUsedLanes == 0x0c0c0000 && RHSUsedLanes == 0x00000c0c)) {
7158 // Each byte in each mask is either selector mask 0-3, or has higher
7159 // bits set in either of masks, which can be 0xff for 0xff or 0x0c for
7160 // zero. If 0x0c is in either mask it shall always be 0x0c. Otherwise
7161 // mask which is not 0xff wins. By anding both masks we have a correct
7162 // result except that 0x0c shall be corrected to give 0x0c only.
7163 uint32_t Mask = LHSMask & RHSMask;
7164 for (unsigned I = 0; I < 32; I += 8) {
7165 uint32_t ByteSel = 0xff << I;
7166 if ((LHSMask & ByteSel) == 0x0c || (RHSMask & ByteSel) == 0x0c)
7167 Mask &= (0x0c << I) & 0xffffffff;
7168 }
7169
7170 // Add 4 to each active LHS lane. It will not affect any existing 0xff
7171 // or 0x0c.
7172 uint32_t Sel = Mask | (LHSUsedLanes & 0x04040404);
7173 SDLoc DL(N);
7174
7175 return DAG.getNode(AMDGPUISD::PERM, DL, MVT::i32,
7176 LHS.getOperand(0), RHS.getOperand(0),
7177 DAG.getConstant(Sel, DL, MVT::i32));
7178 }
7179 }
7180 }
7181
7182 return SDValue();
7183}
7184
7185SDValue SITargetLowering::performOrCombine(SDNode *N,
7186 DAGCombinerInfo &DCI) const {
7187 SelectionDAG &DAG = DCI.DAG;
7188 SDValue LHS = N->getOperand(0);
7189 SDValue RHS = N->getOperand(1);
7190
7191 EVT VT = N->getValueType(0);
7192 if (VT == MVT::i1) {
7193 // or (fp_class x, c1), (fp_class x, c2) -> fp_class x, (c1 | c2)
7194 if (LHS.getOpcode() == AMDGPUISD::FP_CLASS &&
7195 RHS.getOpcode() == AMDGPUISD::FP_CLASS) {
7196 SDValue Src = LHS.getOperand(0);
7197 if (Src != RHS.getOperand(0))
7198 return SDValue();
7199
7200 const ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(LHS.getOperand(1));
7201 const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS.getOperand(1));
7202 if (!CLHS || !CRHS)
7203 return SDValue();
7204
7205 // Only 10 bits are used.
7206 static const uint32_t MaxMask = 0x3ff;
7207
7208 uint32_t NewMask = (CLHS->getZExtValue() | CRHS->getZExtValue()) & MaxMask;
7209 SDLoc DL(N);
7210 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1,
7211 Src, DAG.getConstant(NewMask, DL, MVT::i32));
7212 }
7213
7214 return SDValue();
7215 }
7216
7217 // or (perm x, y, c1), c2 -> perm x, y, permute_mask(c1, c2)
7218 if (isa<ConstantSDNode>(RHS) && LHS.hasOneUse() &&
7219 LHS.getOpcode() == AMDGPUISD::PERM &&
7220 isa<ConstantSDNode>(LHS.getOperand(2))) {
7221 uint32_t Sel = getConstantPermuteMask(N->getConstantOperandVal(1));
7222 if (!Sel)
7223 return SDValue();
7224
7225 Sel |= LHS.getConstantOperandVal(2);
7226 SDLoc DL(N);
7227 return DAG.getNode(AMDGPUISD::PERM, DL, MVT::i32, LHS.getOperand(0),
7228 LHS.getOperand(1), DAG.getConstant(Sel, DL, MVT::i32));
7229 }
7230
7231 // or (op x, c1), (op y, c2) -> perm x, y, permute_mask(c1, c2)
7232 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
7233 if (VT == MVT::i32 && LHS.hasOneUse() && RHS.hasOneUse() &&
7234 N->isDivergent() && TII->pseudoToMCOpcode(AMDGPU::V_PERM_B32) != -1) {
7235 uint32_t LHSMask = getPermuteMask(DAG, LHS);
7236 uint32_t RHSMask = getPermuteMask(DAG, RHS);
7237 if (LHSMask != ~0u && RHSMask != ~0u) {
7238 // Canonicalize the expression in an attempt to have fewer unique masks
7239 // and therefore fewer registers used to hold the masks.
7240 if (LHSMask > RHSMask) {
7241 std::swap(LHSMask, RHSMask);
7242 std::swap(LHS, RHS);
7243 }
7244
7245 // Select 0xc for each lane used from source operand. Zero has 0xc mask
7246 // set, 0xff have 0xff in the mask, actual lanes are in the 0-3 range.
7247 uint32_t LHSUsedLanes = ~(LHSMask & 0x0c0c0c0c) & 0x0c0c0c0c;
7248 uint32_t RHSUsedLanes = ~(RHSMask & 0x0c0c0c0c) & 0x0c0c0c0c;
7249
7250 // Check of we need to combine values from two sources within a byte.
7251 if (!(LHSUsedLanes & RHSUsedLanes) &&
7252 // If we select high and lower word keep it for SDWA.
7253 // TODO: teach SDWA to work with v_perm_b32 and remove the check.
7254 !(LHSUsedLanes == 0x0c0c0000 && RHSUsedLanes == 0x00000c0c)) {
7255 // Kill zero bytes selected by other mask. Zero value is 0xc.
7256 LHSMask &= ~RHSUsedLanes;
7257 RHSMask &= ~LHSUsedLanes;
7258 // Add 4 to each active LHS lane
7259 LHSMask |= LHSUsedLanes & 0x04040404;
7260 // Combine masks
7261 uint32_t Sel = LHSMask | RHSMask;
7262 SDLoc DL(N);
7263
7264 return DAG.getNode(AMDGPUISD::PERM, DL, MVT::i32,
7265 LHS.getOperand(0), RHS.getOperand(0),
7266 DAG.getConstant(Sel, DL, MVT::i32));
7267 }
7268 }
7269 }
7270
7271 if (VT != MVT::i64)
7272 return SDValue();
7273
7274 // TODO: This could be a generic combine with a predicate for extracting the
7275 // high half of an integer being free.
7276
7277 // (or i64:x, (zero_extend i32:y)) ->
7278 // i64 (bitcast (v2i32 build_vector (or i32:y, lo_32(x)), hi_32(x)))
7279 if (LHS.getOpcode() == ISD::ZERO_EXTEND &&
7280 RHS.getOpcode() != ISD::ZERO_EXTEND)
7281 std::swap(LHS, RHS);
7282
7283 if (RHS.getOpcode() == ISD::ZERO_EXTEND) {
7284 SDValue ExtSrc = RHS.getOperand(0);
7285 EVT SrcVT = ExtSrc.getValueType();
7286 if (SrcVT == MVT::i32) {
7287 SDLoc SL(N);
7288 SDValue LowLHS, HiBits;
7289 std::tie(LowLHS, HiBits) = split64BitValue(LHS, DAG);
7290 SDValue LowOr = DAG.getNode(ISD::OR, SL, MVT::i32, LowLHS, ExtSrc);
7291
7292 DCI.AddToWorklist(LowOr.getNode());
7293 DCI.AddToWorklist(HiBits.getNode());
7294
7295 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
7296 LowOr, HiBits);
7297 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
7298 }
7299 }
7300
7301 const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
7302 if (CRHS) {
7303 if (SDValue Split
7304 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::OR, LHS, CRHS))
7305 return Split;
7306 }
7307
7308 return SDValue();
7309}
7310
7311SDValue SITargetLowering::performXorCombine(SDNode *N,
7312 DAGCombinerInfo &DCI) const {
7313 EVT VT = N->getValueType(0);
7314 if (VT != MVT::i64)
7315 return SDValue();
7316
7317 SDValue LHS = N->getOperand(0);
7318 SDValue RHS = N->getOperand(1);
7319
7320 const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS);
7321 if (CRHS) {
7322 if (SDValue Split
7323 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::XOR, LHS, CRHS))
7324 return Split;
7325 }
7326
7327 return SDValue();
7328}
7329
7330// Instructions that will be lowered with a final instruction that zeros the
7331// high result bits.
7332// XXX - probably only need to list legal operations.
7333static bool fp16SrcZerosHighBits(unsigned Opc) {
7334 switch (Opc) {
7335 case ISD::FADD:
7336 case ISD::FSUB:
7337 case ISD::FMUL:
7338 case ISD::FDIV:
7339 case ISD::FREM:
7340 case ISD::FMA:
7341 case ISD::FMAD:
7342 case ISD::FCANONICALIZE:
7343 case ISD::FP_ROUND:
7344 case ISD::UINT_TO_FP:
7345 case ISD::SINT_TO_FP:
7346 case ISD::FABS:
7347 // Fabs is lowered to a bit operation, but it's an and which will clear the
7348 // high bits anyway.
7349 case ISD::FSQRT:
7350 case ISD::FSIN:
7351 case ISD::FCOS:
7352 case ISD::FPOWI:
7353 case ISD::FPOW:
7354 case ISD::FLOG:
7355 case ISD::FLOG2:
7356 case ISD::FLOG10:
7357 case ISD::FEXP:
7358 case ISD::FEXP2:
7359 case ISD::FCEIL:
7360 case ISD::FTRUNC:
7361 case ISD::FRINT:
7362 case ISD::FNEARBYINT:
7363 case ISD::FROUND:
7364 case ISD::FFLOOR:
7365 case ISD::FMINNUM:
7366 case ISD::FMAXNUM:
7367 case AMDGPUISD::FRACT:
7368 case AMDGPUISD::CLAMP:
7369 case AMDGPUISD::COS_HW:
7370 case AMDGPUISD::SIN_HW:
7371 case AMDGPUISD::FMIN3:
7372 case AMDGPUISD::FMAX3:
7373 case AMDGPUISD::FMED3:
7374 case AMDGPUISD::FMAD_FTZ:
7375 case AMDGPUISD::RCP:
7376 case AMDGPUISD::RSQ:
7377 case AMDGPUISD::RCP_IFLAG:
7378 case AMDGPUISD::LDEXP:
7379 return true;
7380 default:
7381 // fcopysign, select and others may be lowered to 32-bit bit operations
7382 // which don't zero the high bits.
7383 return false;
7384 }
7385}
7386
7387SDValue SITargetLowering::performZeroExtendCombine(SDNode *N,
7388 DAGCombinerInfo &DCI) const {
7389 if (!Subtarget->has16BitInsts() ||
7390 DCI.getDAGCombineLevel() < AfterLegalizeDAG)
7391 return SDValue();
7392
7393 EVT VT = N->getValueType(0);
7394 if (VT != MVT::i32)
7395 return SDValue();
7396
7397 SDValue Src = N->getOperand(0);
7398 if (Src.getValueType() != MVT::i16)
7399 return SDValue();
7400
7401 // (i32 zext (i16 (bitcast f16:$src))) -> fp16_zext $src
7402 // FIXME: It is not universally true that the high bits are zeroed on gfx9.
7403 if (Src.getOpcode() == ISD::BITCAST) {
7404 SDValue BCSrc = Src.getOperand(0);
7405 if (BCSrc.getValueType() == MVT::f16 &&
7406 fp16SrcZerosHighBits(BCSrc.getOpcode()))
7407 return DCI.DAG.getNode(AMDGPUISD::FP16_ZEXT, SDLoc(N), VT, BCSrc);
7408 }
7409
7410 return SDValue();
7411}
7412
7413SDValue SITargetLowering::performClassCombine(SDNode *N,
7414 DAGCombinerInfo &DCI) const {
7415 SelectionDAG &DAG = DCI.DAG;
7416 SDValue Mask = N->getOperand(1);
7417
7418 // fp_class x, 0 -> false
7419 if (const ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Mask)) {
7420 if (CMask->isNullValue())
7421 return DAG.getConstant(0, SDLoc(N), MVT::i1);
7422 }
7423
7424 if (N->getOperand(0).isUndef())
7425 return DAG.getUNDEF(MVT::i1);
7426
7427 return SDValue();
7428}
7429
7430SDValue SITargetLowering::performRcpCombine(SDNode *N,
7431 DAGCombinerInfo &DCI) const {
7432 EVT VT = N->getValueType(0);
7433 SDValue N0 = N->getOperand(0);
7434
7435 if (N0.isUndef())
7436 return N0;
7437
7438 if (VT == MVT::f32 && (N0.getOpcode() == ISD::UINT_TO_FP ||
7439 N0.getOpcode() == ISD::SINT_TO_FP)) {
7440 return DCI.DAG.getNode(AMDGPUISD::RCP_IFLAG, SDLoc(N), VT, N0,
7441 N->getFlags());
7442 }
7443
7444 return AMDGPUTargetLowering::performRcpCombine(N, DCI);
7445}
7446
7447bool SITargetLowering::isCanonicalized(SelectionDAG &DAG, SDValue Op,
7448 unsigned MaxDepth) const {
7449 unsigned Opcode = Op.getOpcode();
7450 if (Opcode == ISD::FCANONICALIZE)
7451 return true;
7452
7453 if (auto *CFP = dyn_cast<ConstantFPSDNode>(Op)) {
7454 auto F = CFP->getValueAPF();
7455 if (F.isNaN() && F.isSignaling())
7456 return false;
7457 return !F.isDenormal() || denormalsEnabledForType(Op.getValueType());
7458 }
7459
7460 // If source is a result of another standard FP operation it is already in
7461 // canonical form.
7462 if (MaxDepth == 0)
7463 return false;
7464
7465 switch (Opcode) {
7466 // These will flush denorms if required.
7467 case ISD::FADD:
7468 case ISD::FSUB:
7469 case ISD::FMUL:
7470 case ISD::FCEIL:
7471 case ISD::FFLOOR:
7472 case ISD::FMA:
7473 case ISD::FMAD:
7474 case ISD::FSQRT:
7475 case ISD::FDIV:
7476 case ISD::FREM:
7477 case ISD::FP_ROUND:
7478 case ISD::FP_EXTEND:
7479 case AMDGPUISD::FMUL_LEGACY:
7480 case AMDGPUISD::FMAD_FTZ:
7481 case AMDGPUISD::RCP:
7482 case AMDGPUISD::RSQ:
7483 case AMDGPUISD::RSQ_CLAMP:
7484 case AMDGPUISD::RCP_LEGACY:
7485 case AMDGPUISD::RSQ_LEGACY:
7486 case AMDGPUISD::RCP_IFLAG:
7487 case AMDGPUISD::TRIG_PREOP:
7488 case AMDGPUISD::DIV_SCALE:
7489 case AMDGPUISD::DIV_FMAS:
7490 case AMDGPUISD::DIV_FIXUP:
7491 case AMDGPUISD::FRACT:
7492 case AMDGPUISD::LDEXP:
7493 case AMDGPUISD::CVT_PKRTZ_F16_F32:
7494 case AMDGPUISD::CVT_F32_UBYTE0:
7495 case AMDGPUISD::CVT_F32_UBYTE1:
7496 case AMDGPUISD::CVT_F32_UBYTE2:
7497 case AMDGPUISD::CVT_F32_UBYTE3:
7498 return true;
7499
7500 // It can/will be lowered or combined as a bit operation.
7501 // Need to check their input recursively to handle.
7502 case ISD::FNEG:
7503 case ISD::FABS:
7504 case ISD::FCOPYSIGN:
7505 return isCanonicalized(DAG, Op.getOperand(0), MaxDepth - 1);
7506
7507 case ISD::FSIN:
7508 case ISD::FCOS:
7509 case ISD::FSINCOS:
7510 return Op.getValueType().getScalarType() != MVT::f16;
7511
7512 case ISD::FMINNUM:
7513 case ISD::FMAXNUM:
7514 case ISD::FMINNUM_IEEE:
7515 case ISD::FMAXNUM_IEEE:
7516 case AMDGPUISD::CLAMP:
7517 case AMDGPUISD::FMED3:
7518 case AMDGPUISD::FMAX3:
7519 case AMDGPUISD::FMIN3: {
7520 // FIXME: Shouldn't treat the generic operations different based these.
7521 // However, we aren't really required to flush the result from
7522 // minnum/maxnum..
7523
7524 // snans will be quieted, so we only need to worry about denormals.
7525 if (Subtarget->supportsMinMaxDenormModes() ||
7526 denormalsEnabledForType(Op.getValueType()))
7527 return true;
7528
7529 // Flushing may be required.
7530 // In pre-GFX9 targets V_MIN_F32 and others do not flush denorms. For such
7531 // targets need to check their input recursively.
7532
7533 // FIXME: Does this apply with clamp? It's implemented with max.
7534 for (unsigned I = 0, E = Op.getNumOperands(); I != E; ++I) {
7535 if (!isCanonicalized(DAG, Op.getOperand(I), MaxDepth - 1))
7536 return false;
7537 }
7538
7539 return true;
7540 }
7541 case ISD::SELECT: {
7542 return isCanonicalized(DAG, Op.getOperand(1), MaxDepth - 1) &&
7543 isCanonicalized(DAG, Op.getOperand(2), MaxDepth - 1);
7544 }
7545 case ISD::BUILD_VECTOR: {
7546 for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
7547 SDValue SrcOp = Op.getOperand(i);
7548 if (!isCanonicalized(DAG, SrcOp, MaxDepth - 1))
7549 return false;
7550 }
7551
7552 return true;
7553 }
7554 case ISD::EXTRACT_VECTOR_ELT:
7555 case ISD::EXTRACT_SUBVECTOR: {
7556 return isCanonicalized(DAG, Op.getOperand(0), MaxDepth - 1);
7557 }
7558 case ISD::INSERT_VECTOR_ELT: {
7559 return isCanonicalized(DAG, Op.getOperand(0), MaxDepth - 1) &&
7560 isCanonicalized(DAG, Op.getOperand(1), MaxDepth - 1);
7561 }
7562 case ISD::UNDEF:
7563 // Could be anything.
7564 return false;
7565
7566 case ISD::BITCAST: {
7567 // Hack round the mess we make when legalizing extract_vector_elt
7568 SDValue Src = Op.getOperand(0);
7569 if (Src.getValueType() == MVT::i16 &&
7570 Src.getOpcode() == ISD::TRUNCATE) {
7571 SDValue TruncSrc = Src.getOperand(0);
7572 if (TruncSrc.getValueType() == MVT::i32 &&
7573 TruncSrc.getOpcode() == ISD::BITCAST &&
7574 TruncSrc.getOperand(0).getValueType() == MVT::v2f16) {
7575 return isCanonicalized(DAG, TruncSrc.getOperand(0), MaxDepth - 1);
7576 }
7577 }
7578
7579 return false;
7580 }
7581 case ISD::INTRINSIC_WO_CHAIN: {
7582 unsigned IntrinsicID
7583 = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7584 // TODO: Handle more intrinsics
7585 switch (IntrinsicID) {
7586 case Intrinsic::amdgcn_cvt_pkrtz:
7587 case Intrinsic::amdgcn_cubeid:
7588 case Intrinsic::amdgcn_frexp_mant:
7589 case Intrinsic::amdgcn_fdot2:
7590 return true;
7591 default:
7592 break;
7593 }
7594
7595 LLVM_FALLTHROUGH[[clang::fallthrough]];
7596 }
7597 default:
7598 return denormalsEnabledForType(Op.getValueType()) &&
7599 DAG.isKnownNeverSNaN(Op);
7600 }
7601
7602 llvm_unreachable("invalid operation")::llvm::llvm_unreachable_internal("invalid operation", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 7602)
;
7603}
7604
7605// Constant fold canonicalize.
7606SDValue SITargetLowering::getCanonicalConstantFP(
7607 SelectionDAG &DAG, const SDLoc &SL, EVT VT, const APFloat &C) const {
7608 // Flush denormals to 0 if not enabled.
7609 if (C.isDenormal() && !denormalsEnabledForType(VT))
7610 return DAG.getConstantFP(0.0, SL, VT);
7611
7612 if (C.isNaN()) {
7613 APFloat CanonicalQNaN = APFloat::getQNaN(C.getSemantics());
7614 if (C.isSignaling()) {
7615 // Quiet a signaling NaN.
7616 // FIXME: Is this supposed to preserve payload bits?
7617 return DAG.getConstantFP(CanonicalQNaN, SL, VT);
7618 }
7619
7620 // Make sure it is the canonical NaN bitpattern.
7621 //
7622 // TODO: Can we use -1 as the canonical NaN value since it's an inline
7623 // immediate?
7624 if (C.bitcastToAPInt() != CanonicalQNaN.bitcastToAPInt())
7625 return DAG.getConstantFP(CanonicalQNaN, SL, VT);
7626 }
7627
7628 // Already canonical.
7629 return DAG.getConstantFP(C, SL, VT);
7630}
7631
7632static bool vectorEltWillFoldAway(SDValue Op) {
7633 return Op.isUndef() || isa<ConstantFPSDNode>(Op);
7634}
7635
7636SDValue SITargetLowering::performFCanonicalizeCombine(
7637 SDNode *N,
7638 DAGCombinerInfo &DCI) const {
7639 SelectionDAG &DAG = DCI.DAG;
7640 SDValue N0 = N->getOperand(0);
7641 EVT VT = N->getValueType(0);
7642
7643 // fcanonicalize undef -> qnan
7644 if (N0.isUndef()) {
7645 APFloat QNaN = APFloat::getQNaN(SelectionDAG::EVTToAPFloatSemantics(VT));
7646 return DAG.getConstantFP(QNaN, SDLoc(N), VT);
7647 }
7648
7649 if (ConstantFPSDNode *CFP = isConstOrConstSplatFP(N0)) {
7650 EVT VT = N->getValueType(0);
7651 return getCanonicalConstantFP(DAG, SDLoc(N), VT, CFP->getValueAPF());
7652 }
7653
7654 // fcanonicalize (build_vector x, k) -> build_vector (fcanonicalize x),
7655 // (fcanonicalize k)
7656 //
7657 // fcanonicalize (build_vector x, undef) -> build_vector (fcanonicalize x), 0
7658
7659 // TODO: This could be better with wider vectors that will be split to v2f16,
7660 // and to consider uses since there aren't that many packed operations.
7661 if (N0.getOpcode() == ISD::BUILD_VECTOR && VT == MVT::v2f16 &&
7662 isTypeLegal(MVT::v2f16)) {
7663 SDLoc SL(N);
7664 SDValue NewElts[2];
7665 SDValue Lo = N0.getOperand(0);
7666 SDValue Hi = N0.getOperand(1);
7667 EVT EltVT = Lo.getValueType();
7668
7669 if (vectorEltWillFoldAway(Lo) || vectorEltWillFoldAway(Hi)) {
7670 for (unsigned I = 0; I != 2; ++I) {
7671 SDValue Op = N0.getOperand(I);
7672 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) {
7673 NewElts[I] = getCanonicalConstantFP(DAG, SL, EltVT,
7674 CFP->getValueAPF());
7675 } else if (Op.isUndef()) {
7676 // Handled below based on what the other operand is.
7677 NewElts[I] = Op;
7678 } else {
7679 NewElts[I] = DAG.getNode(ISD::FCANONICALIZE, SL, EltVT, Op);
7680 }
7681 }
7682
7683 // If one half is undef, and one is constant, perfer a splat vector rather
7684 // than the normal qNaN. If it's a register, prefer 0.0 since that's
7685 // cheaper to use and may be free with a packed operation.
7686 if (NewElts[0].isUndef()) {
7687 if (isa<ConstantFPSDNode>(NewElts[1]))
7688 NewElts[0] = isa<ConstantFPSDNode>(NewElts[1]) ?
7689 NewElts[1]: DAG.getConstantFP(0.0f, SL, EltVT);
7690 }
7691
7692 if (NewElts[1].isUndef()) {
7693 NewElts[1] = isa<ConstantFPSDNode>(NewElts[0]) ?
7694 NewElts[0] : DAG.getConstantFP(0.0f, SL, EltVT);
7695 }
7696
7697 return DAG.getBuildVector(VT, SL, NewElts);
7698 }
7699 }
7700
7701 unsigned SrcOpc = N0.getOpcode();
7702
7703 // If it's free to do so, push canonicalizes further up the source, which may
7704 // find a canonical source.
7705 //
7706 // TODO: More opcodes. Note this is unsafe for the the _ieee minnum/maxnum for
7707 // sNaNs.
7708 if (SrcOpc == ISD::FMINNUM || SrcOpc == ISD::FMAXNUM) {
7709 auto *CRHS = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
7710 if (CRHS && N0.hasOneUse()) {
7711 SDLoc SL(N);
7712 SDValue Canon0 = DAG.getNode(ISD::FCANONICALIZE, SL, VT,
7713 N0.getOperand(0));
7714 SDValue Canon1 = getCanonicalConstantFP(DAG, SL, VT, CRHS->getValueAPF());
7715 DCI.AddToWorklist(Canon0.getNode());
7716
7717 return DAG.getNode(N0.getOpcode(), SL, VT, Canon0, Canon1);
7718 }
7719 }
7720
7721 return isCanonicalized(DAG, N0) ? N0 : SDValue();
7722}
7723
7724static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc) {
7725 switch (Opc) {
7726 case ISD::FMAXNUM:
7727 case ISD::FMAXNUM_IEEE:
7728 return AMDGPUISD::FMAX3;
7729 case ISD::SMAX:
7730 return AMDGPUISD::SMAX3;
7731 case ISD::UMAX:
7732 return AMDGPUISD::UMAX3;
7733 case ISD::FMINNUM:
7734 case ISD::FMINNUM_IEEE:
7735 return AMDGPUISD::FMIN3;
7736 case ISD::SMIN:
7737 return AMDGPUISD::SMIN3;
7738 case ISD::UMIN:
7739 return AMDGPUISD::UMIN3;
7740 default:
7741 llvm_unreachable("Not a min/max opcode")::llvm::llvm_unreachable_internal("Not a min/max opcode", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 7741)
;
7742 }
7743}
7744
7745SDValue SITargetLowering::performIntMed3ImmCombine(
7746 SelectionDAG &DAG, const SDLoc &SL,
7747 SDValue Op0, SDValue Op1, bool Signed) const {
7748 ConstantSDNode *K1 = dyn_cast<ConstantSDNode>(Op1);
7749 if (!K1)
7750 return SDValue();
7751
7752 ConstantSDNode *K0 = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
7753 if (!K0)
7754 return SDValue();
7755
7756 if (Signed) {
7757 if (K0->getAPIntValue().sge(K1->getAPIntValue()))
7758 return SDValue();
7759 } else {
7760 if (K0->getAPIntValue().uge(K1->getAPIntValue()))
7761 return SDValue();
7762 }
7763
7764 EVT VT = K0->getValueType(0);
7765 unsigned Med3Opc = Signed ? AMDGPUISD::SMED3 : AMDGPUISD::UMED3;
7766 if (VT == MVT::i32 || (VT == MVT::i16 && Subtarget->hasMed3_16())) {
7767 return DAG.getNode(Med3Opc, SL, VT,
7768 Op0.getOperand(0), SDValue(K0, 0), SDValue(K1, 0));
7769 }
7770
7771 // If there isn't a 16-bit med3 operation, convert to 32-bit.
7772 MVT NVT = MVT::i32;
7773 unsigned ExtOp = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
7774
7775 SDValue Tmp1 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(0));
7776 SDValue Tmp2 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(1));
7777 SDValue Tmp3 = DAG.getNode(ExtOp, SL, NVT, Op1);
7778
7779 SDValue Med3 = DAG.getNode(Med3Opc, SL, NVT, Tmp1, Tmp2, Tmp3);
7780 return DAG.getNode(ISD::TRUNCATE, SL, VT, Med3);
7781}
7782
7783static ConstantFPSDNode *getSplatConstantFP(SDValue Op) {
7784 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Op))
7785 return C;
7786
7787 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op)) {
7788 if (ConstantFPSDNode *C = BV->getConstantFPSplatNode())
7789 return C;
7790 }
7791
7792 return nullptr;
7793}
7794
7795SDValue SITargetLowering::performFPMed3ImmCombine(SelectionDAG &DAG,
7796 const SDLoc &SL,
7797 SDValue Op0,
7798 SDValue Op1) const {
7799 ConstantFPSDNode *K1 = getSplatConstantFP(Op1);
7800 if (!K1)
7801 return SDValue();
7802
7803 ConstantFPSDNode *K0 = getSplatConstantFP(Op0.getOperand(1));
7804 if (!K0)
7805 return SDValue();
7806
7807 // Ordered >= (although NaN inputs should have folded away by now).
7808 APFloat::cmpResult Cmp = K0->getValueAPF().compare(K1->getValueAPF());
7809 if (Cmp == APFloat::cmpGreaterThan)
7810 return SDValue();
7811
7812 // TODO: Check IEEE bit enabled?
7813 EVT VT = Op0.getValueType();
7814 if (Subtarget->enableDX10Clamp()) {
7815 // If dx10_clamp is enabled, NaNs clamp to 0.0. This is the same as the
7816 // hardware fmed3 behavior converting to a min.
7817 // FIXME: Should this be allowing -0.0?
7818 if (K1->isExactlyValue(1.0) && K0->isExactlyValue(0.0))
7819 return DAG.getNode(AMDGPUISD::CLAMP, SL, VT, Op0.getOperand(0));
7820 }
7821
7822 // med3 for f16 is only available on gfx9+, and not available for v2f16.
7823 if (VT == MVT::f32 || (VT == MVT::f16 && Subtarget->hasMed3_16())) {
7824 // This isn't safe with signaling NaNs because in IEEE mode, min/max on a
7825 // signaling NaN gives a quiet NaN. The quiet NaN input to the min would
7826 // then give the other result, which is different from med3 with a NaN
7827 // input.
7828 SDValue Var = Op0.getOperand(0);
7829 if (!DAG.isKnownNeverSNaN(Var))
7830 return SDValue();
7831
7832 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
7833
7834 if ((!K0->hasOneUse() ||
7835 TII->isInlineConstant(K0->getValueAPF().bitcastToAPInt())) &&
7836 (!K1->hasOneUse() ||
7837 TII->isInlineConstant(K1->getValueAPF().bitcastToAPInt()))) {
7838 return DAG.getNode(AMDGPUISD::FMED3, SL, K0->getValueType(0),
7839 Var, SDValue(K0, 0), SDValue(K1, 0));
7840 }
7841 }
7842
7843 return SDValue();
7844}
7845
7846SDValue SITargetLowering::performMinMaxCombine(SDNode *N,
7847 DAGCombinerInfo &DCI) const {
7848 SelectionDAG &DAG = DCI.DAG;
7849
7850 EVT VT = N->getValueType(0);
7851 unsigned Opc = N->getOpcode();
7852 SDValue Op0 = N->getOperand(0);
7853 SDValue Op1 = N->getOperand(1);
7854
7855 // Only do this if the inner op has one use since this will just increases
7856 // register pressure for no benefit.
7857
7858
7859 if (Opc != AMDGPUISD::FMIN_LEGACY && Opc != AMDGPUISD::FMAX_LEGACY &&
7860 !VT.isVector() && VT != MVT::f64 &&
7861 ((VT != MVT::f16 && VT != MVT::i16) || Subtarget->hasMin3Max3_16())) {
7862 // max(max(a, b), c) -> max3(a, b, c)
7863 // min(min(a, b), c) -> min3(a, b, c)
7864 if (Op0.getOpcode() == Opc && Op0.hasOneUse()) {
7865 SDLoc DL(N);
7866 return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
7867 DL,
7868 N->getValueType(0),
7869 Op0.getOperand(0),
7870 Op0.getOperand(1),
7871 Op1);
7872 }
7873
7874 // Try commuted.
7875 // max(a, max(b, c)) -> max3(a, b, c)
7876 // min(a, min(b, c)) -> min3(a, b, c)
7877 if (Op1.getOpcode() == Opc && Op1.hasOneUse()) {
7878 SDLoc DL(N);
7879 return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
7880 DL,
7881 N->getValueType(0),
7882 Op0,
7883 Op1.getOperand(0),
7884 Op1.getOperand(1));
7885 }
7886 }
7887
7888 // min(max(x, K0), K1), K0 < K1 -> med3(x, K0, K1)
7889 if (Opc == ISD::SMIN && Op0.getOpcode() == ISD::SMAX && Op0.hasOneUse()) {
7890 if (SDValue Med3 = performIntMed3ImmCombine(DAG, SDLoc(N), Op0, Op1, true))
7891 return Med3;
7892 }
7893
7894 if (Opc == ISD::UMIN && Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) {
7895 if (SDValue Med3 = performIntMed3ImmCombine(DAG, SDLoc(N), Op0, Op1, false))
7896 return Med3;
7897 }
7898
7899 // fminnum(fmaxnum(x, K0), K1), K0 < K1 && !is_snan(x) -> fmed3(x, K0, K1)
7900 if (((Opc == ISD::FMINNUM && Op0.getOpcode() == ISD::FMAXNUM) ||
7901 (Opc == ISD::FMINNUM_IEEE && Op0.getOpcode() == ISD::FMAXNUM_IEEE) ||
7902 (Opc == AMDGPUISD::FMIN_LEGACY &&
7903 Op0.getOpcode() == AMDGPUISD::FMAX_LEGACY)) &&
7904 (VT == MVT::f32 || VT == MVT::f64 ||
7905 (VT == MVT::f16 && Subtarget->has16BitInsts()) ||
7906 (VT == MVT::v2f16 && Subtarget->hasVOP3PInsts())) &&
7907 Op0.hasOneUse()) {
7908 if (SDValue Res = performFPMed3ImmCombine(DAG, SDLoc(N), Op0, Op1))
7909 return Res;
7910 }
7911
7912 return SDValue();
7913}
7914
7915static bool isClampZeroToOne(SDValue A, SDValue B) {
7916 if (ConstantFPSDNode *CA = dyn_cast<ConstantFPSDNode>(A)) {
7917 if (ConstantFPSDNode *CB = dyn_cast<ConstantFPSDNode>(B)) {
7918 // FIXME: Should this be allowing -0.0?
7919 return (CA->isExactlyValue(0.0) && CB->isExactlyValue(1.0)) ||
7920 (CA->isExactlyValue(1.0) && CB->isExactlyValue(0.0));
7921 }
7922 }
7923
7924 return false;
7925}
7926
7927// FIXME: Should only worry about snans for version with chain.
7928SDValue SITargetLowering::performFMed3Combine(SDNode *N,
7929 DAGCombinerInfo &DCI) const {
7930 EVT VT = N->getValueType(0);
7931 // v_med3_f32 and v_max_f32 behave identically wrt denorms, exceptions and
7932 // NaNs. With a NaN input, the order of the operands may change the result.
7933
7934 SelectionDAG &DAG = DCI.DAG;
7935 SDLoc SL(N);
7936
7937 SDValue Src0 = N->getOperand(0);
7938 SDValue Src1 = N->getOperand(1);
7939 SDValue Src2 = N->getOperand(2);
7940
7941 if (isClampZeroToOne(Src0, Src1)) {
7942 // const_a, const_b, x -> clamp is safe in all cases including signaling
7943 // nans.
7944 // FIXME: Should this be allowing -0.0?
7945 return DAG.getNode(AMDGPUISD::CLAMP, SL, VT, Src2);
7946 }
7947
7948 // FIXME: dx10_clamp behavior assumed in instcombine. Should we really bother
7949 // handling no dx10-clamp?
7950 if (Subtarget->enableDX10Clamp()) {
7951 // If NaNs is clamped to 0, we are free to reorder the inputs.
7952
7953 if (isa<ConstantFPSDNode>(Src0) && !isa<ConstantFPSDNode>(Src1))
7954 std::swap(Src0, Src1);
7955
7956 if (isa<ConstantFPSDNode>(Src1) && !isa<ConstantFPSDNode>(Src2))
7957 std::swap(Src1, Src2);
7958
7959 if (isa<ConstantFPSDNode>(Src0) && !isa<ConstantFPSDNode>(Src1))
7960 std::swap(Src0, Src1);
7961
7962 if (isClampZeroToOne(Src1, Src2))
7963 return DAG.getNode(AMDGPUISD::CLAMP, SL, VT, Src0);
7964 }
7965
7966 return SDValue();
7967}
7968
7969SDValue SITargetLowering::performCvtPkRTZCombine(SDNode *N,
7970 DAGCombinerInfo &DCI) const {
7971 SDValue Src0 = N->getOperand(0);
7972 SDValue Src1 = N->getOperand(1);
7973 if (Src0.isUndef() && Src1.isUndef())
7974 return DCI.DAG.getUNDEF(N->getValueType(0));
7975 return SDValue();
7976}
7977
7978SDValue SITargetLowering::performExtractVectorEltCombine(
7979 SDNode *N, DAGCombinerInfo &DCI) const {
7980 SDValue Vec = N->getOperand(0);
7981 SelectionDAG &DAG = DCI.DAG;
7982
7983 EVT VecVT = Vec.getValueType();
7984 EVT EltVT = VecVT.getVectorElementType();
7985
7986 if ((Vec.getOpcode() == ISD::FNEG ||
7987 Vec.getOpcode() == ISD::FABS) && allUsesHaveSourceMods(N)) {
7988 SDLoc SL(N);
7989 EVT EltVT = N->getValueType(0);
7990 SDValue Idx = N->getOperand(1);
7991 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
7992 Vec.getOperand(0), Idx);
7993 return DAG.getNode(Vec.getOpcode(), SL, EltVT, Elt);
7994 }
7995
7996 // ScalarRes = EXTRACT_VECTOR_ELT ((vector-BINOP Vec1, Vec2), Idx)
7997 // =>
7998 // Vec1Elt = EXTRACT_VECTOR_ELT(Vec1, Idx)
7999 // Vec2Elt = EXTRACT_VECTOR_ELT(Vec2, Idx)
8000 // ScalarRes = scalar-BINOP Vec1Elt, Vec2Elt
8001 if (Vec.hasOneUse() && DCI.isBeforeLegalize()) {
8002 SDLoc SL(N);
8003 EVT EltVT = N->getValueType(0);
8004 SDValue Idx = N->getOperand(1);
8005 unsigned Opc = Vec.getOpcode();
8006
8007 switch(Opc) {
8008 default:
8009 break;
8010 // TODO: Support other binary operations.
8011 case ISD::FADD:
8012 case ISD::FSUB:
8013 case ISD::FMUL:
8014 case ISD::ADD:
8015 case ISD::UMIN:
8016 case ISD::UMAX:
8017 case ISD::SMIN:
8018 case ISD::SMAX:
8019 case ISD::FMAXNUM:
8020 case ISD::FMINNUM:
8021 case ISD::FMAXNUM_IEEE:
8022 case ISD::FMINNUM_IEEE: {
8023 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
8024 Vec.getOperand(0), Idx);
8025 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
8026 Vec.getOperand(1), Idx);
8027
8028 DCI.AddToWorklist(Elt0.getNode());
8029 DCI.AddToWorklist(Elt1.getNode());
8030 return DAG.getNode(Opc, SL, EltVT, Elt0, Elt1, Vec->getFlags());
8031 }
8032 }
8033 }
8034
8035 unsigned VecSize = VecVT.getSizeInBits();
8036 unsigned EltSize = EltVT.getSizeInBits();
8037
8038 // EXTRACT_VECTOR_ELT (<n x e>, var-idx) => n x select (e, const-idx)
8039 // This elminates non-constant index and subsequent movrel or scratch access.
8040 // Sub-dword vectors of size 2 dword or less have better implementation.
8041 // Vectors of size bigger than 8 dwords would yield too many v_cndmask_b32
8042 // instructions.
8043 if (VecSize <= 256 && (VecSize > 64 || EltSize >= 32) &&
8044 !isa<ConstantSDNode>(N->getOperand(1))) {
8045 SDLoc SL(N);
8046 SDValue Idx = N->getOperand(1);
8047 EVT IdxVT = Idx.getValueType();
8048 SDValue V;
8049 for (unsigned I = 0, E = VecVT.getVectorNumElements(); I < E; ++I) {
8050 SDValue IC = DAG.getConstant(I, SL, IdxVT);
8051 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Vec, IC);
8052 if (I == 0)
8053 V = Elt;
8054 else
8055 V = DAG.getSelectCC(SL, Idx, IC, Elt, V, ISD::SETEQ);
8056 }
8057 return V;
8058 }
8059
8060 if (!DCI.isBeforeLegalize())
8061 return SDValue();
8062
8063 // Try to turn sub-dword accesses of vectors into accesses of the same 32-bit
8064 // elements. This exposes more load reduction opportunities by replacing
8065 // multiple small extract_vector_elements with a single 32-bit extract.
8066 auto *Idx = dyn_cast<ConstantSDNode>(N->getOperand(1));
8067 if (isa<MemSDNode>(Vec) &&
8068 EltSize <= 16 &&
8069 EltVT.isByteSized() &&
8070 VecSize > 32 &&
8071 VecSize % 32 == 0 &&
8072 Idx) {
8073 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VecVT);
8074
8075 unsigned BitIndex = Idx->getZExtValue() * EltSize;
8076 unsigned EltIdx = BitIndex / 32;
8077 unsigned LeftoverBitIdx = BitIndex % 32;
8078 SDLoc SL(N);
8079
8080 SDValue Cast = DAG.getNode(ISD::BITCAST, SL, NewVT, Vec);
8081 DCI.AddToWorklist(Cast.getNode());
8082
8083 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Cast,
8084 DAG.getConstant(EltIdx, SL, MVT::i32));
8085 DCI.AddToWorklist(Elt.getNode());
8086 SDValue Srl = DAG.getNode(ISD::SRL, SL, MVT::i32, Elt,
8087 DAG.getConstant(LeftoverBitIdx, SL, MVT::i32));
8088 DCI.AddToWorklist(Srl.getNode());
8089
8090 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, EltVT.changeTypeToInteger(), Srl);
8091 DCI.AddToWorklist(Trunc.getNode());
8092 return DAG.getNode(ISD::BITCAST, SL, EltVT, Trunc);
8093 }
8094
8095 return SDValue();
8096}
8097
8098SDValue
8099SITargetLowering::performInsertVectorEltCombine(SDNode *N,
8100 DAGCombinerInfo &DCI) const {
8101 SDValue Vec = N->getOperand(0);
8102 SDValue Idx = N->getOperand(2);
8103 EVT VecVT = Vec.getValueType();
8104 EVT EltVT = VecVT.getVectorElementType();
8105 unsigned VecSize = VecVT.getSizeInBits();
8106 unsigned EltSize = EltVT.getSizeInBits();
8107
8108 // INSERT_VECTOR_ELT (<n x e>, var-idx)
8109 // => BUILD_VECTOR n x select (e, const-idx)
8110 // This elminates non-constant index and subsequent movrel or scratch access.
8111 // Sub-dword vectors of size 2 dword or less have better implementation.
8112 // Vectors of size bigger than 8 dwords would yield too many v_cndmask_b32
8113 // instructions.
8114 if (isa<ConstantSDNode>(Idx) ||
8115 VecSize > 256 || (VecSize <= 64 && EltSize < 32))
8116 return SDValue();
8117
8118 SelectionDAG &DAG = DCI.DAG;
8119 SDLoc SL(N);
8120 SDValue Ins = N->getOperand(1);
8121 EVT IdxVT = Idx.getValueType();
8122
8123 SmallVector<SDValue, 16> Ops;
8124 for (unsigned I = 0, E = VecVT.getVectorNumElements(); I < E; ++I) {
8125 SDValue IC = DAG.getConstant(I, SL, IdxVT);
8126 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Vec, IC);
8127 SDValue V = DAG.getSelectCC(SL, Idx, IC, Ins, Elt, ISD::SETEQ);
8128 Ops.push_back(V);
8129 }
8130
8131 return DAG.getBuildVector(VecVT, SL, Ops);
8132}
8133
8134unsigned SITargetLowering::getFusedOpcode(const SelectionDAG &DAG,
8135 const SDNode *N0,
8136 const SDNode *N1) const {
8137 EVT VT = N0->getValueType(0);
8138
8139 // Only do this if we are not trying to support denormals. v_mad_f32 does not
8140 // support denormals ever.
8141 if ((VT == MVT::f32 && !Subtarget->hasFP32Denormals()) ||
8142 (VT == MVT::f16 && !Subtarget->hasFP16Denormals()))
8143 return ISD::FMAD;
8144
8145 const TargetOptions &Options = DAG.getTarget().Options;
8146 if ((Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath ||
8147 (N0->getFlags().hasAllowContract() &&
8148 N1->getFlags().hasAllowContract())) &&
8149 isFMAFasterThanFMulAndFAdd(VT)) {
8150 return ISD::FMA;
8151 }
8152
8153 return 0;
8154}
8155
8156static SDValue getMad64_32(SelectionDAG &DAG, const SDLoc &SL,
8157 EVT VT,
8158 SDValue N0, SDValue N1, SDValue N2,
8159 bool Signed) {
8160 unsigned MadOpc = Signed ? AMDGPUISD::MAD_I64_I32 : AMDGPUISD::MAD_U64_U32;
8161 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i1);
8162 SDValue Mad = DAG.getNode(MadOpc, SL, VTs, N0, N1, N2);
8163 return DAG.getNode(ISD::TRUNCATE, SL, VT, Mad);
8164}
8165
8166SDValue SITargetLowering::performAddCombine(SDNode *N,
8167 DAGCombinerInfo &DCI) const {
8168 SelectionDAG &DAG = DCI.DAG;
8169 EVT VT = N->getValueType(0);
8170 SDLoc SL(N);
8171 SDValue LHS = N->getOperand(0);
8172 SDValue RHS = N->getOperand(1);
8173
8174 if ((LHS.getOpcode() == ISD::MUL || RHS.getOpcode() == ISD::MUL)
8175 && Subtarget->hasMad64_32() &&
8176 !VT.isVector() && VT.getScalarSizeInBits() > 32 &&
8177 VT.getScalarSizeInBits() <= 64) {
8178 if (LHS.getOpcode() != ISD::MUL)
8179 std::swap(LHS, RHS);
8180
8181 SDValue MulLHS = LHS.getOperand(0);
8182 SDValue MulRHS = LHS.getOperand(1);
8183 SDValue AddRHS = RHS;
8184
8185 // TODO: Maybe restrict if SGPR inputs.
8186 if (numBitsUnsigned(MulLHS, DAG) <= 32 &&
8187 numBitsUnsigned(MulRHS, DAG) <= 32) {
8188 MulLHS = DAG.getZExtOrTrunc(MulLHS, SL, MVT::i32);
8189 MulRHS = DAG.getZExtOrTrunc(MulRHS, SL, MVT::i32);
8190 AddRHS = DAG.getZExtOrTrunc(AddRHS, SL, MVT::i64);
8191 return getMad64_32(DAG, SL, VT, MulLHS, MulRHS, AddRHS, false);
8192 }
8193
8194 if (numBitsSigned(MulLHS, DAG) < 32 && numBitsSigned(MulRHS, DAG) < 32) {
8195 MulLHS = DAG.getSExtOrTrunc(MulLHS, SL, MVT::i32);
8196 MulRHS = DAG.getSExtOrTrunc(MulRHS, SL, MVT::i32);
8197 AddRHS = DAG.getSExtOrTrunc(AddRHS, SL, MVT::i64);
8198 return getMad64_32(DAG, SL, VT, MulLHS, MulRHS, AddRHS, true);
8199 }
8200
8201 return SDValue();
8202 }
8203
8204 if (VT != MVT::i32 || !DCI.isAfterLegalizeDAG())
8205 return SDValue();
8206
8207 // add x, zext (setcc) => addcarry x, 0, setcc
8208 // add x, sext (setcc) => subcarry x, 0, setcc
8209 unsigned Opc = LHS.getOpcode();
8210 if (Opc == ISD::ZERO_EXTEND || Opc == ISD::SIGN_EXTEND ||
8211 Opc == ISD::ANY_EXTEND || Opc == ISD::ADDCARRY)
8212 std::swap(RHS, LHS);
8213
8214 Opc = RHS.getOpcode();
8215 switch (Opc) {
8216 default: break;
8217 case ISD::ZERO_EXTEND:
8218 case ISD::SIGN_EXTEND:
8219 case ISD::ANY_EXTEND: {
8220 auto Cond = RHS.getOperand(0);
8221 if (!isBoolSGPR(Cond))
8222 break;
8223 SDVTList VTList = DAG.getVTList(MVT::i32, MVT::i1);
8224 SDValue Args[] = { LHS, DAG.getConstant(0, SL, MVT::i32), Cond };
8225 Opc = (Opc == ISD::SIGN_EXTEND) ? ISD::SUBCARRY : ISD::ADDCARRY;
8226 return DAG.getNode(Opc, SL, VTList, Args);
8227 }
8228 case ISD::ADDCARRY: {
8229 // add x, (addcarry y, 0, cc) => addcarry x, y, cc
8230 auto C = dyn_cast<ConstantSDNode>(RHS.getOperand(1));
8231 if (!C || C->getZExtValue() != 0) break;
8232 SDValue Args[] = { LHS, RHS.getOperand(0), RHS.getOperand(2) };
8233 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), RHS->getVTList(), Args);
8234 }
8235 }
8236 return SDValue();
8237}
8238
8239SDValue SITargetLowering::performSubCombine(SDNode *N,
8240 DAGCombinerInfo &DCI) const {
8241 SelectionDAG &DAG = DCI.DAG;
8242 EVT VT = N->getValueType(0);
8243
8244 if (VT != MVT::i32)
8245 return SDValue();
8246
8247 SDLoc SL(N);
8248 SDValue LHS = N->getOperand(0);
8249 SDValue RHS = N->getOperand(1);
8250
8251 unsigned Opc = LHS.getOpcode();
8252 if (Opc != ISD::SUBCARRY)
8253 std::swap(RHS, LHS);
8254
8255 if (LHS.getOpcode() == ISD::SUBCARRY) {
8256 // sub (subcarry x, 0, cc), y => subcarry x, y, cc
8257 auto C = dyn_cast<ConstantSDNode>(LHS.getOperand(1));
8258 if (!C || C->getZExtValue() != 0)
8259 return SDValue();
8260 SDValue Args[] = { LHS.getOperand(0), RHS, LHS.getOperand(2) };
8261 return DAG.getNode(ISD::SUBCARRY, SDLoc(N), LHS->getVTList(), Args);
8262 }
8263 return SDValue();
8264}
8265
8266SDValue SITargetLowering::performAddCarrySubCarryCombine(SDNode *N,
8267 DAGCombinerInfo &DCI) const {
8268
8269 if (N->getValueType(0) != MVT::i32)
8270 return SDValue();
8271
8272 auto C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8273 if (!C || C->getZExtValue() != 0)
8274 return SDValue();
8275
8276 SelectionDAG &DAG = DCI.DAG;
8277 SDValue LHS = N->getOperand(0);
8278
8279 // addcarry (add x, y), 0, cc => addcarry x, y, cc
8280 // subcarry (sub x, y), 0, cc => subcarry x, y, cc
8281 unsigned LHSOpc = LHS.getOpcode();
8282 unsigned Opc = N->getOpcode();
8283 if ((LHSOpc == ISD::ADD && Opc == ISD::ADDCARRY) ||
8284 (LHSOpc == ISD::SUB && Opc == ISD::SUBCARRY)) {
8285 SDValue Args[] = { LHS.getOperand(0), LHS.getOperand(1), N->getOperand(2) };
8286 return DAG.getNode(Opc, SDLoc(N), N->getVTList(), Args);
8287 }
8288 return SDValue();
8289}
8290
8291SDValue SITargetLowering::performFAddCombine(SDNode *N,
8292 DAGCombinerInfo &DCI) const {
8293 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
8294 return SDValue();
8295
8296 SelectionDAG &DAG = DCI.DAG;
8297 EVT VT = N->getValueType(0);
8298
8299 SDLoc SL(N);
8300 SDValue LHS = N->getOperand(0);
8301 SDValue RHS = N->getOperand(1);
8302
8303 // These should really be instruction patterns, but writing patterns with
8304 // source modiifiers is a pain.
8305
8306 // fadd (fadd (a, a), b) -> mad 2.0, a, b
8307 if (LHS.getOpcode() == ISD::FADD) {
8308 SDValue A = LHS.getOperand(0);
8309 if (A == LHS.getOperand(1)) {
8310 unsigned FusedOp = getFusedOpcode(DAG, N, LHS.getNode());
8311 if (FusedOp != 0) {
8312 const SDValue Two = DAG.getConstantFP(2.0, SL, VT);
8313 return DAG.getNode(FusedOp, SL, VT, A, Two, RHS);
8314 }
8315 }
8316 }
8317
8318 // fadd (b, fadd (a, a)) -> mad 2.0, a, b
8319 if (RHS.getOpcode() == ISD::FADD) {
8320 SDValue A = RHS.getOperand(0);
8321 if (A == RHS.getOperand(1)) {
8322 unsigned FusedOp = getFusedOpcode(DAG, N, RHS.getNode());
8323 if (FusedOp != 0) {
8324 const SDValue Two = DAG.getConstantFP(2.0, SL, VT);
8325 return DAG.getNode(FusedOp, SL, VT, A, Two, LHS);
8326 }
8327 }
8328 }
8329
8330 return SDValue();
8331}
8332
8333SDValue SITargetLowering::performFSubCombine(SDNode *N,
8334 DAGCombinerInfo &DCI) const {
8335 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
8336 return SDValue();
8337
8338 SelectionDAG &DAG = DCI.DAG;
8339 SDLoc SL(N);
8340 EVT VT = N->getValueType(0);
8341 assert(!VT.isVector())((!VT.isVector()) ? static_cast<void> (0) : __assert_fail
("!VT.isVector()", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 8341, __PRETTY_FUNCTION__))
;
8342
8343 // Try to get the fneg to fold into the source modifier. This undoes generic
8344 // DAG combines and folds them into the mad.
8345 //
8346 // Only do this if we are not trying to support denormals. v_mad_f32 does
8347 // not support denormals ever.
8348 SDValue LHS = N->getOperand(0);
8349 SDValue RHS = N->getOperand(1);
8350 if (LHS.getOpcode() == ISD::FADD) {
8351 // (fsub (fadd a, a), c) -> mad 2.0, a, (fneg c)
8352 SDValue A = LHS.getOperand(0);
8353 if (A == LHS.getOperand(1)) {
8354 unsigned FusedOp = getFusedOpcode(DAG, N, LHS.getNode());
8355 if (FusedOp != 0){
8356 const SDValue Two = DAG.getConstantFP(2.0, SL, VT);
8357 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
8358
8359 return DAG.getNode(FusedOp, SL, VT, A, Two, NegRHS);
8360 }
8361 }
8362 }
8363
8364 if (RHS.getOpcode() == ISD::FADD) {
8365 // (fsub c, (fadd a, a)) -> mad -2.0, a, c
8366
8367 SDValue A = RHS.getOperand(0);
8368 if (A == RHS.getOperand(1)) {
8369 unsigned FusedOp = getFusedOpcode(DAG, N, RHS.getNode());
8370 if (FusedOp != 0){
8371 const SDValue NegTwo = DAG.getConstantFP(-2.0, SL, VT);
8372 return DAG.getNode(FusedOp, SL, VT, A, NegTwo, LHS);
8373 }
8374 }
8375 }
8376
8377 return SDValue();
8378}
8379
8380SDValue SITargetLowering::performFMACombine(SDNode *N,
8381 DAGCombinerInfo &DCI) const {
8382 SelectionDAG &DAG = DCI.DAG;
8383 EVT VT = N->getValueType(0);
8384 SDLoc SL(N);
8385
8386 if (!Subtarget->hasDLInsts() || VT != MVT::f32)
8387 return SDValue();
8388
8389 // FMA((F32)S0.x, (F32)S1. x, FMA((F32)S0.y, (F32)S1.y, (F32)z)) ->
8390 // FDOT2((V2F16)S0, (V2F16)S1, (F32)z))
8391 SDValue Op1 = N->getOperand(0);
8392 SDValue Op2 = N->getOperand(1);
8393 SDValue FMA = N->getOperand(2);
8394
8395 if (FMA.getOpcode() != ISD::FMA ||
8396 Op1.getOpcode() != ISD::FP_EXTEND ||
8397 Op2.getOpcode() != ISD::FP_EXTEND)
8398 return SDValue();
8399
8400 // fdot2_f32_f16 always flushes fp32 denormal operand and output to zero,
8401 // regardless of the denorm mode setting. Therefore, unsafe-fp-math/fp-contract
8402 // is sufficient to allow generaing fdot2.
8403 const TargetOptions &Options = DAG.getTarget().Options;
8404 if (Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath ||
8405 (N->getFlags().hasAllowContract() &&
8406 FMA->getFlags().hasAllowContract())) {
8407 Op1 = Op1.getOperand(0);
8408 Op2 = Op2.getOperand(0);
8409 if (Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
8410 Op2.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8411 return SDValue();
8412
8413 SDValue Vec1 = Op1.getOperand(0);
8414 SDValue Idx1 = Op1.getOperand(1);
8415 SDValue Vec2 = Op2.getOperand(0);
8416
8417 SDValue FMAOp1 = FMA.getOperand(0);
8418 SDValue FMAOp2 = FMA.getOperand(1);
8419 SDValue FMAAcc = FMA.getOperand(2);
8420
8421 if (FMAOp1.getOpcode() != ISD::FP_EXTEND ||
8422 FMAOp2.getOpcode() != ISD::FP_EXTEND)
8423 return SDValue();
8424
8425 FMAOp1 = FMAOp1.getOperand(0);
8426 FMAOp2 = FMAOp2.getOperand(0);
8427 if (FMAOp1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
8428 FMAOp2.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8429 return SDValue();
8430
8431 SDValue Vec3 = FMAOp1.getOperand(0);
8432 SDValue Vec4 = FMAOp2.getOperand(0);
8433 SDValue Idx2 = FMAOp1.getOperand(1);
8434
8435 if (Idx1 != Op2.getOperand(1) || Idx2 != FMAOp2.getOperand(1) ||
8436 // Idx1 and Idx2 cannot be the same.
8437 Idx1 == Idx2)
8438 return SDValue();
8439
8440 if (Vec1 == Vec2 || Vec3 == Vec4)
8441 return SDValue();
8442
8443 if (Vec1.getValueType() != MVT::v2f16 || Vec2.getValueType() != MVT::v2f16)
8444 return SDValue();
8445
8446 if ((Vec1 == Vec3 && Vec2 == Vec4) ||
8447 (Vec1 == Vec4 && Vec2 == Vec3)) {
8448 return DAG.getNode(AMDGPUISD::FDOT2, SL, MVT::f32, Vec1, Vec2, FMAAcc,
8449 DAG.getTargetConstant(0, SL, MVT::i1));
8450 }
8451 }
8452 return SDValue();
8453}
8454
8455SDValue SITargetLowering::performSetCCCombine(SDNode *N,
8456 DAGCombinerInfo &DCI) const {
8457 SelectionDAG &DAG = DCI.DAG;
8458 SDLoc SL(N);
8459
8460 SDValue LHS = N->getOperand(0);
8461 SDValue RHS = N->getOperand(1);
8462 EVT VT = LHS.getValueType();
8463 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
8464
8465 auto CRHS = dyn_cast<ConstantSDNode>(RHS);
8466 if (!CRHS) {
8467 CRHS = dyn_cast<ConstantSDNode>(LHS);
8468 if (CRHS) {
8469 std::swap(LHS, RHS);
8470 CC = getSetCCSwappedOperands(CC);
8471 }
8472 }
8473
8474 if (CRHS) {
8475 if (VT == MVT::i32 && LHS.getOpcode() == ISD::SIGN_EXTEND &&
8476 isBoolSGPR(LHS.getOperand(0))) {
8477 // setcc (sext from i1 cc), -1, ne|sgt|ult) => not cc => xor cc, -1
8478 // setcc (sext from i1 cc), -1, eq|sle|uge) => cc
8479 // setcc (sext from i1 cc), 0, eq|sge|ule) => not cc => xor cc, -1
8480 // setcc (sext from i1 cc), 0, ne|ugt|slt) => cc
8481 if ((CRHS->isAllOnesValue() &&
8482 (CC == ISD::SETNE || CC == ISD::SETGT || CC == ISD::SETULT)) ||
8483 (CRHS->isNullValue() &&
8484 (CC == ISD::SETEQ || CC == ISD::SETGE || CC == ISD::SETULE)))
8485 return DAG.getNode(ISD::XOR, SL, MVT::i1, LHS.getOperand(0),
8486 DAG.getConstant(-1, SL, MVT::i1));
8487 if ((CRHS->isAllOnesValue() &&
8488 (CC == ISD::SETEQ || CC == ISD::SETLE || CC == ISD::SETUGE)) ||
8489 (CRHS->isNullValue() &&
8490 (CC == ISD::SETNE || CC == ISD::SETUGT || CC == ISD::SETLT)))
8491 return LHS.getOperand(0);
8492 }
8493
8494 uint64_t CRHSVal = CRHS->getZExtValue();
8495 if ((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8496 LHS.getOpcode() == ISD::SELECT &&
8497 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8498 isa<ConstantSDNode>(LHS.getOperand(2)) &&
8499 LHS.getConstantOperandVal(1) != LHS.getConstantOperandVal(2) &&
8500 isBoolSGPR(LHS.getOperand(0))) {
8501 // Given CT != FT:
8502 // setcc (select cc, CT, CF), CF, eq => xor cc, -1
8503 // setcc (select cc, CT, CF), CF, ne => cc
8504 // setcc (select cc, CT, CF), CT, ne => xor cc, -1
8505 // setcc (select cc, CT, CF), CT, eq => cc
8506 uint64_t CT = LHS.getConstantOperandVal(1);
8507 uint64_t CF = LHS.getConstantOperandVal(2);
8508
8509 if ((CF == CRHSVal && CC == ISD::SETEQ) ||
8510 (CT == CRHSVal && CC == ISD::SETNE))
8511 return DAG.getNode(ISD::XOR, SL, MVT::i1, LHS.getOperand(0),
8512 DAG.getConstant(-1, SL, MVT::i1));
8513 if ((CF == CRHSVal && CC == ISD::SETNE) ||
8514 (CT == CRHSVal && CC == ISD::SETEQ))
8515 return LHS.getOperand(0);
8516 }
8517 }
8518
8519 if (VT != MVT::f32 && VT != MVT::f64 && (Subtarget->has16BitInsts() &&
8520 VT != MVT::f16))
8521 return SDValue();
8522
8523 // Match isinf/isfinite pattern
8524 // (fcmp oeq (fabs x), inf) -> (fp_class x, (p_infinity | n_infinity))
8525 // (fcmp one (fabs x), inf) -> (fp_class x,
8526 // (p_normal | n_normal | p_subnormal | n_subnormal | p_zero | n_zero)
8527 if ((CC == ISD::SETOEQ || CC == ISD::SETONE) && LHS.getOpcode() == ISD::FABS) {
8528 const ConstantFPSDNode *CRHS = dyn_cast<ConstantFPSDNode>(RHS);
8529 if (!CRHS)
8530 return SDValue();
8531
8532 const APFloat &APF = CRHS->getValueAPF();
8533 if (APF.isInfinity() && !APF.isNegative()) {
8534 const unsigned IsInfMask = SIInstrFlags::P_INFINITY |
8535 SIInstrFlags::N_INFINITY;
8536 const unsigned IsFiniteMask = SIInstrFlags::N_ZERO |
8537 SIInstrFlags::P_ZERO |
8538 SIInstrFlags::N_NORMAL |
8539 SIInstrFlags::P_NORMAL |
8540 SIInstrFlags::N_SUBNORMAL |
8541 SIInstrFlags::P_SUBNORMAL;
8542 unsigned Mask = CC == ISD::SETOEQ ? IsInfMask : IsFiniteMask;
8543 return DAG.getNode(AMDGPUISD::FP_CLASS, SL, MVT::i1, LHS.getOperand(0),
8544 DAG.getConstant(Mask, SL, MVT::i32));
8545 }
8546 }
8547
8548 return SDValue();
8549}
8550
8551SDValue SITargetLowering::performCvtF32UByteNCombine(SDNode *N,
8552 DAGCombinerInfo &DCI) const {
8553 SelectionDAG &DAG = DCI.DAG;
8554 SDLoc SL(N);
8555 unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0;
8556
8557 SDValue Src = N->getOperand(0);
8558 SDValue Srl = N->getOperand(0);
8559 if (Srl.getOpcode() == ISD::ZERO_EXTEND)
8560 Srl = Srl.getOperand(0);
8561
8562 // TODO: Handle (or x, (srl y, 8)) pattern when known bits are zero.
8563 if (Srl.getOpcode() == ISD::SRL) {
8564 // cvt_f32_ubyte0 (srl x, 16) -> cvt_f32_ubyte2 x
8565 // cvt_f32_ubyte1 (srl x, 16) -> cvt_f32_ubyte3 x
8566 // cvt_f32_ubyte0 (srl x, 8) -> cvt_f32_ubyte1 x
8567
8568 if (const ConstantSDNode *C =
8569 dyn_cast<ConstantSDNode>(Srl.getOperand(1))) {
8570 Srl = DAG.getZExtOrTrunc(Srl.getOperand(0), SDLoc(Srl.getOperand(0)),
8571 EVT(MVT::i32));
8572
8573 unsigned SrcOffset = C->getZExtValue() + 8 * Offset;
8574 if (SrcOffset < 32 && SrcOffset % 8 == 0) {
8575 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0 + SrcOffset / 8, SL,
8576 MVT::f32, Srl);
8577 }
8578 }
8579 }
8580
8581 APInt Demanded = APInt::getBitsSet(32, 8 * Offset, 8 * Offset + 8);
8582
8583 KnownBits Known;
8584 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
8585 !DCI.isBeforeLegalizeOps());
8586 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8587 if (TLI.ShrinkDemandedConstant(Src, Demanded, TLO) ||
8588 TLI.SimplifyDemandedBits(Src, Demanded, Known, TLO)) {
8589 DCI.CommitTargetLoweringOpt(TLO);
8590 }
8591
8592 return SDValue();
8593}
8594
8595SDValue SITargetLowering::performClampCombine(SDNode *N,
8596 DAGCombinerInfo &DCI) const {
8597 ConstantFPSDNode *CSrc = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
8598 if (!CSrc)
8599 return SDValue();
8600
8601 const APFloat &F = CSrc->getValueAPF();
8602 APFloat Zero = APFloat::getZero(F.getSemantics());
8603 APFloat::cmpResult Cmp0 = F.compare(Zero);
8604 if (Cmp0 == APFloat::cmpLessThan ||
8605 (Cmp0 == APFloat::cmpUnordered && Subtarget->enableDX10Clamp())) {
8606 return DCI.DAG.getConstantFP(Zero, SDLoc(N), N->getValueType(0));
8607 }
8608
8609 APFloat One(F.getSemantics(), "1.0");
8610 APFloat::cmpResult Cmp1 = F.compare(One);
8611 if (Cmp1 == APFloat::cmpGreaterThan)
8612 return DCI.DAG.getConstantFP(One, SDLoc(N), N->getValueType(0));
8613
8614 return SDValue(CSrc, 0);
8615}
8616
8617
8618SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
8619 DAGCombinerInfo &DCI) const {
8620 if (getTargetMachine().getOptLevel() == CodeGenOpt::None)
8621 return SDValue();
8622
8623 switch (N->getOpcode()) {
8624 default:
8625 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
8626 case ISD::ADD:
8627 return performAddCombine(N, DCI);
8628 case ISD::SUB:
8629 return performSubCombine(N, DCI);
8630 case ISD::ADDCARRY:
8631 case ISD::SUBCARRY:
8632 return performAddCarrySubCarryCombine(N, DCI);
8633 case ISD::FADD:
8634 return performFAddCombine(N, DCI);
8635 case ISD::FSUB:
8636 return performFSubCombine(N, DCI);
8637 case ISD::SETCC:
8638 return performSetCCCombine(N, DCI);
8639 case ISD::FMAXNUM:
8640 case ISD::FMINNUM:
8641 case ISD::FMAXNUM_IEEE:
8642 case ISD::FMINNUM_IEEE:
8643 case ISD::SMAX:
8644 case ISD::SMIN:
8645 case ISD::UMAX:
8646 case ISD::UMIN:
8647 case AMDGPUISD::FMIN_LEGACY:
8648 case AMDGPUISD::FMAX_LEGACY:
8649 return performMinMaxCombine(N, DCI);
8650 case ISD::FMA:
8651 return performFMACombine(N, DCI);
8652 case ISD::LOAD: {
8653 if (SDValue Widended = widenLoad(cast<LoadSDNode>(N), DCI))
8654 return Widended;
8655 LLVM_FALLTHROUGH[[clang::fallthrough]];
8656 }
8657 case ISD::STORE:
8658 case ISD::ATOMIC_LOAD:
8659 case ISD::ATOMIC_STORE:
8660 case ISD::ATOMIC_CMP_SWAP:
8661 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
8662 case ISD::ATOMIC_SWAP:
8663 case ISD::ATOMIC_LOAD_ADD:
8664 case ISD::ATOMIC_LOAD_SUB:
8665 case ISD::ATOMIC_LOAD_AND:
8666 case ISD::ATOMIC_LOAD_OR:
8667 case ISD::ATOMIC_LOAD_XOR:
8668 case ISD::ATOMIC_LOAD_NAND:
8669 case ISD::ATOMIC_LOAD_MIN:
8670 case ISD::ATOMIC_LOAD_MAX:
8671 case ISD::ATOMIC_LOAD_UMIN:
8672 case ISD::ATOMIC_LOAD_UMAX:
8673 case AMDGPUISD::ATOMIC_INC:
8674 case AMDGPUISD::ATOMIC_DEC:
8675 case AMDGPUISD::ATOMIC_LOAD_FADD:
8676 case AMDGPUISD::ATOMIC_LOAD_FMIN:
8677 case AMDGPUISD::ATOMIC_LOAD_FMAX: // TODO: Target mem intrinsics.
8678 if (DCI.isBeforeLegalize())
8679 break;
8680 return performMemSDNodeCombine(cast<MemSDNode>(N), DCI);
8681 case ISD::AND:
8682 return performAndCombine(N, DCI);
8683 case ISD::OR:
8684 return performOrCombine(N, DCI);
8685 case ISD::XOR:
8686 return performXorCombine(N, DCI);
8687 case ISD::ZERO_EXTEND:
8688 return performZeroExtendCombine(N, DCI);
8689 case AMDGPUISD::FP_CLASS:
8690 return performClassCombine(N, DCI);
8691 case ISD::FCANONICALIZE:
8692 return performFCanonicalizeCombine(N, DCI);
8693 case AMDGPUISD::RCP:
8694 return performRcpCombine(N, DCI);
8695 case AMDGPUISD::FRACT:
8696 case AMDGPUISD::RSQ:
8697 case AMDGPUISD::RCP_LEGACY:
8698 case AMDGPUISD::RSQ_LEGACY:
8699 case AMDGPUISD::RCP_IFLAG:
8700 case AMDGPUISD::RSQ_CLAMP:
8701 case AMDGPUISD::LDEXP: {
8702 SDValue Src = N->getOperand(0);
8703 if (Src.isUndef())
8704 return Src;
8705 break;
8706 }
8707 case ISD::SINT_TO_FP:
8708 case ISD::UINT_TO_FP:
8709 return performUCharToFloatCombine(N, DCI);
8710 case AMDGPUISD::CVT_F32_UBYTE0:
8711 case AMDGPUISD::CVT_F32_UBYTE1:
8712 case AMDGPUISD::CVT_F32_UBYTE2:
8713 case AMDGPUISD::CVT_F32_UBYTE3:
8714 return performCvtF32UByteNCombine(N, DCI);
8715 case AMDGPUISD::FMED3:
8716 return performFMed3Combine(N, DCI);
8717 case AMDGPUISD::CVT_PKRTZ_F16_F32:
8718 return performCvtPkRTZCombine(N, DCI);
8719 case AMDGPUISD::CLAMP:
8720 return performClampCombine(N, DCI);
8721 case ISD::SCALAR_TO_VECTOR: {
8722 SelectionDAG &DAG = DCI.DAG;
8723 EVT VT = N->getValueType(0);
8724
8725 // v2i16 (scalar_to_vector i16:x) -> v2i16 (bitcast (any_extend i16:x))
8726 if (VT == MVT::v2i16 || VT == MVT::v2f16) {
8727 SDLoc SL(N);
8728 SDValue Src = N->getOperand(0);
8729 EVT EltVT = Src.getValueType();
8730 if (EltVT == MVT::f16)
8731 Src = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Src);
8732
8733 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, Src);
8734 return DAG.getNode(ISD::BITCAST, SL, VT, Ext);
8735 }
8736
8737 break;
8738 }
8739 case ISD::EXTRACT_VECTOR_ELT:
8740 return performExtractVectorEltCombine(N, DCI);
8741 case ISD::INSERT_VECTOR_ELT:
8742 return performInsertVectorEltCombine(N, DCI);
8743 }
8744 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
8745}
8746
8747/// Helper function for adjustWritemask
8748static unsigned SubIdx2Lane(unsigned Idx) {
8749 switch (Idx) {
8750 default: return 0;
8751 case AMDGPU::sub0: return 0;
8752 case AMDGPU::sub1: return 1;
8753 case AMDGPU::sub2: return 2;
8754 case AMDGPU::sub3: return 3;
8755 }
8756}
8757
8758/// Adjust the writemask of MIMG instructions
8759SDNode *SITargetLowering::adjustWritemask(MachineSDNode *&Node,
8760 SelectionDAG &DAG) const {
8761 unsigned Opcode = Node->getMachineOpcode();
8762
8763 // Subtract 1 because the vdata output is not a MachineSDNode operand.
8764 int D16Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::d16) - 1;
8765 if (D16Idx >= 0 && Node->getConstantOperandVal(D16Idx))
6
Assuming 'D16Idx' is < 0
8766 return Node; // not implemented for D16
8767
8768 SDNode *Users[4] = { nullptr };
7
Initializing to a null pointer value
8769 unsigned Lane = 0;
8770 unsigned DmaskIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::dmask) - 1;
8771 unsigned OldDmask = Node->getConstantOperandVal(DmaskIdx);
8772 unsigned NewDmask = 0;
8773 bool HasChain = Node->getNumValues() > 1;
8
Assuming the condition is false
8774
8775 if (OldDmask == 0) {
9
Assuming 'OldDmask' is not equal to 0
10
Taking false branch
8776 // These are folded out, but on the chance it happens don't assert.
8777 return Node;
8778 }
8779
8780 // Try to figure out the used register components
8781 for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
11
Loop condition is false. Execution continues on line 8815
8782 I != E; ++I) {
8783
8784 // Don't look at users of the chain.
8785 if (I.getUse().getResNo() != 0)
8786 continue;
8787
8788 // Abort if we can't understand the usage
8789 if (!I->isMachineOpcode() ||
8790 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
8791 return Node;
8792
8793 // Lane means which subreg of %vgpra_vgprb_vgprc_vgprd is used.
8794 // Note that subregs are packed, i.e. Lane==0 is the first bit set
8795 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
8796 // set, etc.
8797 Lane = SubIdx2Lane(I->getConstantOperandVal(1));
8798
8799 // Set which texture component corresponds to the lane.
8800 unsigned Comp;
8801 for (unsigned i = 0, Dmask = OldDmask; (i <= Lane) && (Dmask != 0); i++) {
8802 Comp = countTrailingZeros(Dmask);
8803 Dmask &= ~(1 << Comp);
8804 }
8805
8806 // Abort if we have more than one user per component
8807 if (Users[Lane])
8808 return Node;
8809
8810 Users[Lane] = *I;
8811 NewDmask |= 1 << Comp;
8812 }
8813
8814 // Abort if there's no change
8815 if (NewDmask == OldDmask)
12
Taking false branch
8816 return Node;
8817
8818 unsigned BitsSet = countPopulation(NewDmask);
8819
8820 int NewOpcode = AMDGPU::getMaskedMIMGOp(Node->getMachineOpcode(), BitsSet);
8821 assert(NewOpcode != -1 &&((NewOpcode != -1 && NewOpcode != static_cast<int>
(Node->getMachineOpcode()) && "failed to find equivalent MIMG op"
) ? static_cast<void> (0) : __assert_fail ("NewOpcode != -1 && NewOpcode != static_cast<int>(Node->getMachineOpcode()) && \"failed to find equivalent MIMG op\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 8823, __PRETTY_FUNCTION__))
13
Assuming the condition is true
14
'?' condition is true
8822 NewOpcode != static_cast<int>(Node->getMachineOpcode()) &&((NewOpcode != -1 && NewOpcode != static_cast<int>
(Node->getMachineOpcode()) && "failed to find equivalent MIMG op"
) ? static_cast<void> (0) : __assert_fail ("NewOpcode != -1 && NewOpcode != static_cast<int>(Node->getMachineOpcode()) && \"failed to find equivalent MIMG op\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 8823, __PRETTY_FUNCTION__))
8823 "failed to find equivalent MIMG op")((NewOpcode != -1 && NewOpcode != static_cast<int>
(Node->getMachineOpcode()) && "failed to find equivalent MIMG op"
) ? static_cast<void> (0) : __assert_fail ("NewOpcode != -1 && NewOpcode != static_cast<int>(Node->getMachineOpcode()) && \"failed to find equivalent MIMG op\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 8823, __PRETTY_FUNCTION__))
;
8824
8825 // Adjust the writemask in the node
8826 SmallVector<SDValue, 12> Ops;
8827 Ops.insert(Ops.end(), Node->op_begin(), Node->op_begin() + DmaskIdx);
8828 Ops.push_back(DAG.getTargetConstant(NewDmask, SDLoc(Node), MVT::i32));
8829 Ops.insert(Ops.end(), Node->op_begin() + DmaskIdx + 1, Node->op_end());
8830
8831 MVT SVT = Node->getValueType(0).getVectorElementType().getSimpleVT();
8832
8833 MVT ResultVT = BitsSet == 1 ?
15
Assuming 'BitsSet' is equal to 1
16
'?' condition is true
8834 SVT : MVT::getVectorVT(SVT, BitsSet == 3 ? 4 : BitsSet);
8835 SDVTList NewVTList = HasChain ?
17
'?' condition is false
8836 DAG.getVTList(ResultVT, MVT::Other) : DAG.getVTList(ResultVT);
8837
8838
8839 MachineSDNode *NewNode = DAG.getMachineNode(NewOpcode, SDLoc(Node),
8840 NewVTList, Ops);
8841
8842 if (HasChain) {
18
Taking false branch
8843 // Update chain.
8844 DAG.setNodeMemRefs(NewNode, Node->memoperands());
8845 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(NewNode, 1));
8846 }
8847
8848 if (BitsSet == 1) {
19
Taking true branch
8849 assert(Node->hasNUsesOfValue(1, 0))((Node->hasNUsesOfValue(1, 0)) ? static_cast<void> (
0) : __assert_fail ("Node->hasNUsesOfValue(1, 0)", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 8849, __PRETTY_FUNCTION__))
;
20
Assuming the condition is true
21
'?' condition is true
8850 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY,
8851 SDLoc(Node), Users[Lane]->getValueType(0),
22
Called C++ object pointer is null
8852 SDValue(NewNode, 0));
8853 DAG.ReplaceAllUsesWith(Users[Lane], Copy);
8854 return nullptr;
8855 }
8856
8857 // Update the users of the node with the new indices
8858 for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
8859 SDNode *User = Users[i];
8860 if (!User)
8861 continue;
8862
8863 SDValue Op = DAG.getTargetConstant(Idx, SDLoc(User), MVT::i32);
8864 DAG.UpdateNodeOperands(User, SDValue(NewNode, 0), Op);
8865
8866 switch (Idx) {
8867 default: break;
8868 case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
8869 case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
8870 case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
8871 }
8872 }
8873
8874 DAG.RemoveDeadNode(Node);
8875 return nullptr;
8876}
8877
8878static bool isFrameIndexOp(SDValue Op) {
8879 if (Op.getOpcode() == ISD::AssertZext)
8880 Op = Op.getOperand(0);
8881
8882 return isa<FrameIndexSDNode>(Op);
8883}
8884
8885/// Legalize target independent instructions (e.g. INSERT_SUBREG)
8886/// with frame index operands.
8887/// LLVM assumes that inputs are to these instructions are registers.
8888SDNode *SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
8889 SelectionDAG &DAG) const {
8890 if (Node->getOpcode() == ISD::CopyToReg) {
8891 RegisterSDNode *DestReg = cast<RegisterSDNode>(Node->getOperand(1));
8892 SDValue SrcVal = Node->getOperand(2);
8893
8894 // Insert a copy to a VReg_1 virtual register so LowerI1Copies doesn't have
8895 // to try understanding copies to physical registers.
8896 if (SrcVal.getValueType() == MVT::i1 &&
8897 TargetRegisterInfo::isPhysicalRegister(DestReg->getReg())) {
8898 SDLoc SL(Node);
8899 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
8900 SDValue VReg = DAG.getRegister(
8901 MRI.createVirtualRegister(&AMDGPU::VReg_1RegClass), MVT::i1);
8902
8903 SDNode *Glued = Node->getGluedNode();
8904 SDValue ToVReg
8905 = DAG.getCopyToReg(Node->getOperand(0), SL, VReg, SrcVal,
8906 SDValue(Glued, Glued ? Glued->getNumValues() - 1 : 0));
8907 SDValue ToResultReg
8908 = DAG.getCopyToReg(ToVReg, SL, SDValue(DestReg, 0),
8909 VReg, ToVReg.getValue(1));
8910 DAG.ReplaceAllUsesWith(Node, ToResultReg.getNode());
8911 DAG.RemoveDeadNode(Node);
8912 return ToResultReg.getNode();
8913 }
8914 }
8915
8916 SmallVector<SDValue, 8> Ops;
8917 for (unsigned i = 0; i < Node->getNumOperands(); ++i) {
8918 if (!isFrameIndexOp(Node->getOperand(i))) {
8919 Ops.push_back(Node->getOperand(i));
8920 continue;
8921 }
8922
8923 SDLoc DL(Node);
8924 Ops.push_back(SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL,
8925 Node->getOperand(i).getValueType(),
8926 Node->getOperand(i)), 0));
8927 }
8928
8929 return DAG.UpdateNodeOperands(Node, Ops);
8930}
8931
8932/// Fold the instructions after selecting them.
8933/// Returns null if users were already updated.
8934SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
8935 SelectionDAG &DAG) const {
8936 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
8937 unsigned Opcode = Node->getMachineOpcode();
8938
8939 if (TII->isMIMG(Opcode) && !TII->get(Opcode).mayStore() &&
1
Assuming the condition is true
2
Assuming the condition is true
4
Taking true branch
8940 !TII->isGather4(Opcode)) {
3
Assuming the condition is true
8941 return adjustWritemask(Node, DAG);
5
Calling 'SITargetLowering::adjustWritemask'
8942 }
8943
8944 if (Opcode == AMDGPU::INSERT_SUBREG ||
8945 Opcode == AMDGPU::REG_SEQUENCE) {
8946 legalizeTargetIndependentNode(Node, DAG);
8947 return Node;
8948 }
8949
8950 switch (Opcode) {
8951 case AMDGPU::V_DIV_SCALE_F32:
8952 case AMDGPU::V_DIV_SCALE_F64: {
8953 // Satisfy the operand register constraint when one of the inputs is
8954 // undefined. Ordinarily each undef value will have its own implicit_def of
8955 // a vreg, so force these to use a single register.
8956 SDValue Src0 = Node->getOperand(0);
8957 SDValue Src1 = Node->getOperand(1);
8958 SDValue Src2 = Node->getOperand(2);
8959
8960 if ((Src0.isMachineOpcode() &&
8961 Src0.getMachineOpcode() != AMDGPU::IMPLICIT_DEF) &&
8962 (Src0 == Src1 || Src0 == Src2))
8963 break;
8964
8965 MVT VT = Src0.getValueType().getSimpleVT();
8966 const TargetRegisterClass *RC = getRegClassFor(VT);
8967
8968 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
8969 SDValue UndefReg = DAG.getRegister(MRI.createVirtualRegister(RC), VT);
8970
8971 SDValue ImpDef = DAG.getCopyToReg(DAG.getEntryNode(), SDLoc(Node),
8972 UndefReg, Src0, SDValue());
8973
8974 // src0 must be the same register as src1 or src2, even if the value is
8975 // undefined, so make sure we don't violate this constraint.
8976 if (Src0.isMachineOpcode() &&
8977 Src0.getMachineOpcode() == AMDGPU::IMPLICIT_DEF) {
8978 if (Src1.isMachineOpcode() &&
8979 Src1.getMachineOpcode() != AMDGPU::IMPLICIT_DEF)
8980 Src0 = Src1;
8981 else if (Src2.isMachineOpcode() &&
8982 Src2.getMachineOpcode() != AMDGPU::IMPLICIT_DEF)
8983 Src0 = Src2;
8984 else {
8985 assert(Src1.getMachineOpcode() == AMDGPU::IMPLICIT_DEF)((Src1.getMachineOpcode() == AMDGPU::IMPLICIT_DEF) ? static_cast
<void> (0) : __assert_fail ("Src1.getMachineOpcode() == AMDGPU::IMPLICIT_DEF"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 8985, __PRETTY_FUNCTION__))
;
8986 Src0 = UndefReg;
8987 Src1 = UndefReg;
8988 }
8989 } else
8990 break;
8991
8992 SmallVector<SDValue, 4> Ops = { Src0, Src1, Src2 };
8993 for (unsigned I = 3, N = Node->getNumOperands(); I != N; ++I)
8994 Ops.push_back(Node->getOperand(I));
8995
8996 Ops.push_back(ImpDef.getValue(1));
8997 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
8998 }
8999 default:
9000 break;
9001 }
9002
9003 return Node;
9004}
9005
9006/// Assign the register class depending on the number of
9007/// bits set in the writemask
9008void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
9009 SDNode *Node) const {
9010 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
9011
9012 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
9013
9014 if (TII->isVOP3(MI.getOpcode())) {
9015 // Make sure constant bus requirements are respected.
9016 TII->legalizeOperandsVOP3(MRI, MI);
9017 return;
9018 }
9019
9020 // Replace unused atomics with the no return version.
9021 int NoRetAtomicOp = AMDGPU::getAtomicNoRetOp(MI.getOpcode());
9022 if (NoRetAtomicOp != -1) {
9023 if (!Node->hasAnyUseOfValue(0)) {
9024 MI.setDesc(TII->get(NoRetAtomicOp));
9025 MI.RemoveOperand(0);
9026 return;
9027 }
9028
9029 // For mubuf_atomic_cmpswap, we need to have tablegen use an extract_subreg
9030 // instruction, because the return type of these instructions is a vec2 of
9031 // the memory type, so it can be tied to the input operand.
9032 // This means these instructions always have a use, so we need to add a
9033 // special case to check if the atomic has only one extract_subreg use,
9034 // which itself has no uses.
9035 if ((Node->hasNUsesOfValue(1, 0) &&
9036 Node->use_begin()->isMachineOpcode() &&
9037 Node->use_begin()->getMachineOpcode() == AMDGPU::EXTRACT_SUBREG &&
9038 !Node->use_begin()->hasAnyUseOfValue(0))) {
9039 unsigned Def = MI.getOperand(0).getReg();
9040
9041 // Change this into a noret atomic.
9042 MI.setDesc(TII->get(NoRetAtomicOp));
9043 MI.RemoveOperand(0);
9044
9045 // If we only remove the def operand from the atomic instruction, the
9046 // extract_subreg will be left with a use of a vreg without a def.
9047 // So we need to insert an implicit_def to avoid machine verifier
9048 // errors.
9049 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
9050 TII->get(AMDGPU::IMPLICIT_DEF), Def);
9051 }
9052 return;
9053 }
9054}
9055
9056static SDValue buildSMovImm32(SelectionDAG &DAG, const SDLoc &DL,
9057 uint64_t Val) {
9058 SDValue K = DAG.getTargetConstant(Val, DL, MVT::i32);
9059 return SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, K), 0);
9060}
9061
9062MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,
9063 const SDLoc &DL,
9064 SDValue Ptr) const {
9065 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
9066
9067 // Build the half of the subregister with the constants before building the
9068 // full 128-bit register. If we are building multiple resource descriptors,
9069 // this will allow CSEing of the 2-component register.
9070 const SDValue Ops0[] = {
9071 DAG.getTargetConstant(AMDGPU::SGPR_64RegClassID, DL, MVT::i32),
9072 buildSMovImm32(DAG, DL, 0),
9073 DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
9074 buildSMovImm32(DAG, DL, TII->getDefaultRsrcDataFormat() >> 32),
9075 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
9076 };
9077
9078 SDValue SubRegHi = SDValue(DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL,
9079 MVT::v2i32, Ops0), 0);
9080
9081 // Combine the constants and the pointer.
9082 const SDValue Ops1[] = {
9083 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32),
9084 Ptr,
9085 DAG.getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32),
9086 SubRegHi,
9087 DAG.getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32)
9088 };
9089
9090 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1);
9091}
9092
9093/// Return a resource descriptor with the 'Add TID' bit enabled
9094/// The TID (Thread ID) is multiplied by the stride value (bits [61:48]
9095/// of the resource descriptor) to create an offset, which is added to
9096/// the resource pointer.
9097MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG, const SDLoc &DL,
9098 SDValue Ptr, uint32_t RsrcDword1,
9099 uint64_t RsrcDword2And3) const {
9100 SDValue PtrLo = DAG.getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr);
9101 SDValue PtrHi = DAG.getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr);
9102 if (RsrcDword1) {
9103 PtrHi = SDValue(DAG.getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi,
9104 DAG.getConstant(RsrcDword1, DL, MVT::i32)),
9105 0);
9106 }
9107
9108 SDValue DataLo = buildSMovImm32(DAG, DL,
9109 RsrcDword2And3 & UINT64_C(0xFFFFFFFF)0xFFFFFFFFUL);
9110 SDValue DataHi = buildSMovImm32(DAG, DL, RsrcDword2And3 >> 32);
9111
9112 const SDValue Ops[] = {
9113 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32),
9114 PtrLo,
9115 DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
9116 PtrHi,
9117 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32),
9118 DataLo,
9119 DAG.getTargetConstant(AMDGPU::sub2, DL, MVT::i32),
9120 DataHi,
9121 DAG.getTargetConstant(AMDGPU::sub3, DL, MVT::i32)
9122 };
9123
9124 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops);
9125}
9126
9127//===----------------------------------------------------------------------===//
9128// SI Inline Assembly Support
9129//===----------------------------------------------------------------------===//
9130
9131std::pair<unsigned, const TargetRegisterClass *>
9132SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
9133 StringRef Constraint,
9134 MVT VT) const {
9135 const TargetRegisterClass *RC = nullptr;
9136 if (Constraint.size() == 1) {
9137 switch (Constraint[0]) {
9138 default:
9139 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
9140 case 's':
9141 case 'r':
9142 switch (VT.getSizeInBits()) {
9143 default:
9144 return std::make_pair(0U, nullptr);
9145 case 32:
9146 case 16:
9147 RC = &AMDGPU::SReg_32_XM0RegClass;
9148 break;
9149 case 64:
9150 RC = &AMDGPU::SGPR_64RegClass;
9151 break;
9152 case 128:
9153 RC = &AMDGPU::SReg_128RegClass;
9154 break;
9155 case 256:
9156 RC = &AMDGPU::SReg_256RegClass;
9157 break;
9158 case 512:
9159 RC = &AMDGPU::SReg_512RegClass;
9160 break;
9161 }
9162 break;
9163 case 'v':
9164 switch (VT.getSizeInBits()) {
9165 default:
9166 return std::make_pair(0U, nullptr);
9167 case 32:
9168 case 16:
9169 RC = &AMDGPU::VGPR_32RegClass;
9170 break;
9171 case 64:
9172 RC = &AMDGPU::VReg_64RegClass;
9173 break;
9174 case 96:
9175 RC = &AMDGPU::VReg_96RegClass;
9176 break;
9177 case 128:
9178 RC = &AMDGPU::VReg_128RegClass;
9179 break;
9180 case 256:
9181 RC = &AMDGPU::VReg_256RegClass;
9182 break;
9183 case 512:
9184 RC = &AMDGPU::VReg_512RegClass;
9185 break;
9186 }
9187 break;
9188 }
9189 // We actually support i128, i16 and f16 as inline parameters
9190 // even if they are not reported as legal
9191 if (RC && (isTypeLegal(VT) || VT.SimpleTy == MVT::i128 ||
9192 VT.SimpleTy == MVT::i16 || VT.SimpleTy == MVT::f16))
9193 return std::make_pair(0U, RC);
9194 }
9195
9196 if (Constraint.size() > 1) {
9197 if (Constraint[1] == 'v') {
9198 RC = &AMDGPU::VGPR_32RegClass;
9199 } else if (Constraint[1] == 's') {
9200 RC = &AMDGPU::SGPR_32RegClass;
9201 }
9202
9203 if (RC) {
9204 uint32_t Idx;
9205 bool Failed = Constraint.substr(2).getAsInteger(10, Idx);
9206 if (!Failed && Idx < RC->getNumRegs())
9207 return std::make_pair(RC->getRegister(Idx), RC);
9208 }
9209 }
9210 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
9211}
9212
9213SITargetLowering::ConstraintType
9214SITargetLowering::getConstraintType(StringRef Constraint) const {
9215 if (Constraint.size() == 1) {
9216 switch (Constraint[0]) {
9217 default: break;
9218 case 's':
9219 case 'v':
9220 return C_RegisterClass;
9221 }
9222 }
9223 return TargetLowering::getConstraintType(Constraint);
9224}
9225
9226// Figure out which registers should be reserved for stack access. Only after
9227// the function is legalized do we know all of the non-spill stack objects or if
9228// calls are present.
9229void SITargetLowering::finalizeLowering(MachineFunction &MF) const {
9230 MachineRegisterInfo &MRI = MF.getRegInfo();
9231 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
9232 const MachineFrameInfo &MFI = MF.getFrameInfo();
9233 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
9234
9235 if (Info->isEntryFunction()) {
9236 // Callable functions have fixed registers used for stack access.
9237 reservePrivateMemoryRegs(getTargetMachine(), MF, *TRI, *Info);
9238 }
9239
9240 // We have to assume the SP is needed in case there are calls in the function
9241 // during lowering. Calls are only detected after the function is
9242 // lowered. We're about to reserve registers, so don't bother using it if we
9243 // aren't really going to use it.
9244 bool NeedSP = !Info->isEntryFunction() ||
9245 MFI.hasVarSizedObjects() ||
9246 MFI.hasCalls();
9247
9248 if (NeedSP) {
9249 unsigned ReservedStackPtrOffsetReg = TRI->reservedStackPtrOffsetReg(MF);
9250 Info->setStackPtrOffsetReg(ReservedStackPtrOffsetReg);
9251
9252 assert(Info->getStackPtrOffsetReg() != Info->getFrameOffsetReg())((Info->getStackPtrOffsetReg() != Info->getFrameOffsetReg
()) ? static_cast<void> (0) : __assert_fail ("Info->getStackPtrOffsetReg() != Info->getFrameOffsetReg()"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 9252, __PRETTY_FUNCTION__))
;
9253 assert(!TRI->isSubRegister(Info->getScratchRSrcReg(),((!TRI->isSubRegister(Info->getScratchRSrcReg(), Info->
getStackPtrOffsetReg())) ? static_cast<void> (0) : __assert_fail
("!TRI->isSubRegister(Info->getScratchRSrcReg(), Info->getStackPtrOffsetReg())"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 9254, __PRETTY_FUNCTION__))
9254 Info->getStackPtrOffsetReg()))((!TRI->isSubRegister(Info->getScratchRSrcReg(), Info->
getStackPtrOffsetReg())) ? static_cast<void> (0) : __assert_fail
("!TRI->isSubRegister(Info->getScratchRSrcReg(), Info->getStackPtrOffsetReg())"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 9254, __PRETTY_FUNCTION__))
;
9255 MRI.replaceRegWith(AMDGPU::SP_REG, Info->getStackPtrOffsetReg());
9256 }
9257
9258 MRI.replaceRegWith(AMDGPU::PRIVATE_RSRC_REG, Info->getScratchRSrcReg());
9259 MRI.replaceRegWith(AMDGPU::FP_REG, Info->getFrameOffsetReg());
9260 MRI.replaceRegWith(AMDGPU::SCRATCH_WAVE_OFFSET_REG,
9261 Info->getScratchWaveOffsetReg());
9262
9263 Info->limitOccupancy(MF);
9264
9265 TargetLoweringBase::finalizeLowering(MF);
9266}
9267
9268void SITargetLowering::computeKnownBitsForFrameIndex(const SDValue Op,
9269 KnownBits &Known,
9270 const APInt &DemandedElts,
9271 const SelectionDAG &DAG,
9272 unsigned Depth) const {
9273 TargetLowering::computeKnownBitsForFrameIndex(Op, Known, DemandedElts,
9274 DAG, Depth);
9275
9276 if (getSubtarget()->enableHugePrivateBuffer())
9277 return;
9278
9279 // Technically it may be possible to have a dispatch with a single workitem
9280 // that uses the full private memory size, but that's not really useful. We
9281 // can't use vaddr in MUBUF instructions if we don't know the address
9282 // calculation won't overflow, so assume the sign bit is never set.
9283 Known.Zero.setHighBits(AssumeFrameIndexHighZeroBits);
9284}
9285
9286LLVM_ATTRIBUTE_UNUSED__attribute__((__unused__))
9287static bool isCopyFromRegOfInlineAsm(const SDNode *N) {
9288 assert(N->getOpcode() == ISD::CopyFromReg)((N->getOpcode() == ISD::CopyFromReg) ? static_cast<void
> (0) : __assert_fail ("N->getOpcode() == ISD::CopyFromReg"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 9288, __PRETTY_FUNCTION__))
;
9289 do {
9290 // Follow the chain until we find an INLINEASM node.
9291 N = N->getOperand(0).getNode();
9292 if (N->getOpcode() == ISD::INLINEASM)
9293 return true;
9294 } while (N->getOpcode() == ISD::CopyFromReg);
9295 return false;
9296}
9297
9298bool SITargetLowering::isSDNodeSourceOfDivergence(const SDNode * N,
9299 FunctionLoweringInfo * FLI, LegacyDivergenceAnalysis * KDA) const
9300{
9301 switch (N->getOpcode()) {
9302 case ISD::CopyFromReg:
9303 {
9304 const RegisterSDNode *R = cast<RegisterSDNode>(N->getOperand(1));
9305 const MachineFunction * MF = FLI->MF;
9306 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
9307 const MachineRegisterInfo &MRI = MF->getRegInfo();
9308 const SIRegisterInfo &TRI = ST.getInstrInfo()->getRegisterInfo();
9309 unsigned Reg = R->getReg();
9310 if (TRI.isPhysicalRegister(Reg))
9311 return !TRI.isSGPRReg(MRI, Reg);
9312
9313 if (MRI.isLiveIn(Reg)) {
9314 // workitem.id.x workitem.id.y workitem.id.z
9315 // Any VGPR formal argument is also considered divergent
9316 if (!TRI.isSGPRReg(MRI, Reg))
9317 return true;
9318 // Formal arguments of non-entry functions
9319 // are conservatively considered divergent
9320 else if (!AMDGPU::isEntryFunctionCC(FLI->Fn->getCallingConv()))
9321 return true;
9322 return false;
9323 }
9324 const Value *V = FLI->getValueFromVirtualReg(Reg);
9325 if (V)
9326 return KDA->isDivergent(V);
9327 assert(Reg == FLI->DemoteRegister || isCopyFromRegOfInlineAsm(N))((Reg == FLI->DemoteRegister || isCopyFromRegOfInlineAsm(N
)) ? static_cast<void> (0) : __assert_fail ("Reg == FLI->DemoteRegister || isCopyFromRegOfInlineAsm(N)"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/AMDGPU/SIISelLowering.cpp"
, 9327, __PRETTY_FUNCTION__))
;
9328 return !TRI.isSGPRReg(MRI, Reg);
9329 }
9330 break;
9331 case ISD::LOAD: {
9332 const LoadSDNode *L = cast<LoadSDNode>(N);
9333 unsigned AS = L->getAddressSpace();
9334 // A flat load may access private memory.
9335 return AS == AMDGPUAS::PRIVATE_ADDRESS || AS == AMDGPUAS::FLAT_ADDRESS;
9336 } break;
9337 case ISD::CALLSEQ_END:
9338 return true;
9339 break;
9340 case ISD::INTRINSIC_WO_CHAIN:
9341 {
9342
9343 }
9344 return AMDGPU::isIntrinsicSourceOfDivergence(
9345 cast<ConstantSDNode>(N->getOperand(0))->getZExtValue());
9346 case ISD::INTRINSIC_W_CHAIN:
9347 return AMDGPU::isIntrinsicSourceOfDivergence(
9348 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
9349 // In some cases intrinsics that are a source of divergence have been
9350 // lowered to AMDGPUISD so we also need to check those too.
9351 case AMDGPUISD::INTERP_MOV:
9352 case AMDGPUISD::INTERP_P1:
9353 case AMDGPUISD::INTERP_P2:
9354 return true;
9355 }
9356 return false;
9357}
9358
9359bool SITargetLowering::denormalsEnabledForType(EVT VT) const {
9360 switch (VT.getScalarType().getSimpleVT().SimpleTy) {
9361 case MVT::f32:
9362 return Subtarget->hasFP32Denormals();
9363 case MVT::f64:
9364 return Subtarget->hasFP64Denormals();
9365 case MVT::f16:
9366 return Subtarget->hasFP16Denormals();
9367 default:
9368 return false;
9369 }
9370}
9371
9372bool SITargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
9373 const SelectionDAG &DAG,
9374 bool SNaN,
9375 unsigned Depth) const {
9376 if (Op.getOpcode() == AMDGPUISD::CLAMP) {
9377 if (Subtarget->enableDX10Clamp())
9378 return true; // Clamped to 0.
9379 return DAG.isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1);
9380 }
9381
9382 return AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(Op, DAG,
9383 SNaN, Depth);
9384}