.. ************************************************** * * * Automatically generated file, do not edit! * * * ************************************************** .. _amdgpu_synid_gfx950_addr_c8b8d4: addr ---- *Size:* 1 dword. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_addr_f2b449: addr ---- *Size:* 2 dwords. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_data_be4895: data ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_data_9ad749: data ---- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_data_cfb402: data ---- Instruction input. *Size:* 3 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_data_848ff7: data ---- Instruction input. *Size:* 4 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_data0_be4895: data0 ----- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_data0_9ad749: data0 ----- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_data0_cfb402: data0 ----- Instruction input. *Size:* 3 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_data0_848ff7: data0 ----- Instruction input. *Size:* 4 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_data1_be4895: data1 ----- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_data1_9ad749: data1 ----- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_literal_81e671: literal ------- *Size:* 1 dword. *Operands:* .. _amdgpu_synid_gfx950_literal_39b593: literal ------- *Size:* 1 dword. *Operands:* :ref:`imm16` .. _amdgpu_synid_gfx950_saddr_13d69a: saddr ----- *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_saddr_ce8216: saddr ----- *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sbase_010ce0: sbase ----- A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride. *Size:* 4 dwords. *Operands:* :ref:`s`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sbase_044055: sbase ----- A 64-bit base address for scalar memory operations. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sbase_0cd545: sbase ----- This operand is ignored by H/W and :ref:`flat_scratch` is supplied instead. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_scale_src0: scale_src0 ---------- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_scale_src1: scale_src1 ---------- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_sdata_aefe00: sdata ----- Input data for an atomic instruction. Optionally may serve as an output data: * If :ref:`glc` is specified, gets the memory value before the operation. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sdata_eb6f2a: sdata ----- Input data for an atomic instruction. Optionally may serve as an output data: * If :ref:`glc` is specified, gets the memory value before the operation. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sdata_c6aec1: sdata ----- Input data for an atomic instruction. Optionally may serve as an output data: * If :ref:`glc` is specified, gets the memory value before the operation. *Size:* 4 dwords. *Operands:* :ref:`s`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sdata_94342d: sdata ----- Instruction output. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sdata_d725ab: sdata ----- Instruction output. *Size:* 1 dword. *Operands:* :ref:`simm8` .. _amdgpu_synid_gfx950_sdata_3bc700: sdata ----- Instruction output. *Size:* 16 dwords. *Operands:* :ref:`s`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sdata_718cc4: sdata ----- Instruction output. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sdata_0804b1: sdata ----- Instruction output. *Size:* 4 dwords. *Operands:* :ref:`s`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sdata_362c37: sdata ----- Instruction output. *Size:* 8 dwords. *Operands:* :ref:`s`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sdst_02b357: sdst ---- *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec` .. _amdgpu_synid_gfx950_sdst_3bec61: sdst ---- Instruction output. *Size:* 1 dword if wavefront size is 32, otherwise 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sdst_1db612: sdst ---- Instruction output. *Size:* 1 dword if wavefront size is 32, otherwise 2 dwords. *Operands:* :ref:`vcc` .. _amdgpu_synid_gfx950_sdst_94342d: sdst ---- Instruction output. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sdst_06b266: sdst ---- Instruction output. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec` .. _amdgpu_synid_gfx950_sdst_718cc4: sdst ---- Instruction output. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_sdst_a319e6: sdst ---- Instruction output. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`exec` .. _amdgpu_synid_gfx950_simm16_7ed651: simm16 ------ *Size:* 1 dword. *Operands:* :ref:`hwreg` .. _amdgpu_synid_gfx950_simm16_39b593: simm16 ------ *Size:* 1 dword. *Operands:* :ref:`imm16` .. _amdgpu_synid_gfx950_simm16_3d2a4f: simm16 ------ *Size:* 1 dword. *Operands:* :ref:`label` .. _amdgpu_synid_gfx950_simm16_ee8b30: simm16 ------ *Size:* 1 dword. *Operands:* :ref:`sendmsg` .. _amdgpu_synid_gfx950_simm16_218bea: simm16 ------ *Size:* 1 dword. *Operands:* :ref:`waitcnt` .. _amdgpu_synid_gfx950_simm16_cc1716: simm16 ------ Instruction output. *Size:* 1 dword. *Operands:* :ref:`hwreg` .. _amdgpu_synid_gfx950_soffset_1189ef: soffset ------- An offset added to the base address to get memory address. * If offset is specified as a register, it supplies an unsigned byte offset. * If offset is specified as a 21-bit immediate, it supplies a signed byte offset. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0` .. _amdgpu_synid_gfx950_soffset_8aa27a: soffset ------- An unsigned 20-bit offset added to the base address to get memory address. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0` .. _amdgpu_synid_gfx950_soffset_d856a0: soffset ------- An unsigned byte offset. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_src0_1027ca: src0 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`a` .. _amdgpu_synid_gfx950_src0_6802ce: src0 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_src0_be4895: src0 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_src0_516946: src0 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`lds_direct` .. _amdgpu_synid_gfx950_src0_14b47a: src0 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_src0_0f0007: src0 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst`, :ref:`literal` .. _amdgpu_synid_gfx950_src0_168f33: src0 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`fconst` .. _amdgpu_synid_gfx950_src0_06ee74: src0 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`fconst`, :ref:`literal` .. _amdgpu_synid_gfx950_src0_9ad749: src0 ---- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_src0_e30a18: src0 ---- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_src0_62f8c2: src0 ---- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst`, :ref:`literal` .. _amdgpu_synid_gfx950_src0_848ff7: src0 ---- Instruction input. *Size:* 4 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_src0_ca334d: src0 ---- Instruction input. *Size:* 8 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_src0_1d4114: src0 ---- attr0.x through attr63.w, parameter attribute and channel to be interpolated .. _amdgpu_synid_gfx950_src1_43aa79: src1 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0` .. _amdgpu_synid_gfx950_src1_be4895: src1 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_src1_14b47a: src1 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_src1_d52854: src1 ---- Instruction input. *Size:* 16 dwords. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_src1_9ad749: src1 ---- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_src1_e30a18: src1 ---- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_src1_848ff7: src1 ---- Instruction input. *Size:* 4 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_src1_ca334d: src1 ---- Instruction input. *Size:* 8 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_src2_595c25: src2 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_src2_6802ce: src2 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_src2_14b47a: src2 ---- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_src2_14f1c8: src2 ---- Instruction input. *Size:* 16 dwords. *Operands:* :ref:`v`, :ref:`a`, :ref:`fconst` .. _amdgpu_synid_gfx950_src2_1ff383: src2 ---- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`a`, :ref:`fconst` .. _amdgpu_synid_gfx950_src2_e30a18: src2 ---- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_src2_a90bd6: src2 ---- Instruction input. *Size:* 32 dwords. *Operands:* :ref:`v`, :ref:`a`, :ref:`fconst` .. _amdgpu_synid_gfx950_src2_e016a1: src2 ---- Instruction input. *Size:* 4 dwords. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_src2_ca14ce: src2 ---- Instruction input. *Size:* 4 dwords. *Operands:* :ref:`v`, :ref:`a`, :ref:`fconst` .. _amdgpu_synid_gfx950_src2_f36021: src2 ---- Instruction input. *Size:* 8 dwords. *Operands:* :ref:`v`, :ref:`a`, :ref:`fconst` .. _amdgpu_synid_gfx950_srsrc: srsrc ----- Buffer resource constant which defines the address and characteristics of the buffer in memory. *Size:* 4 dwords. *Operands:* :ref:`s`, :ref:`ttmp` .. _amdgpu_synid_gfx950_ssrc0_595c25: ssrc0 ----- Instruction input. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_ssrc0_eecc17: ssrc0 ----- Instruction input. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst`, :ref:`literal` .. _amdgpu_synid_gfx950_ssrc0_e9f591: ssrc0 ----- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_ssrc0_1ce478: ssrc0 ----- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_ssrc0_83ef5a: ssrc0 ----- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst`, :ref:`literal` .. _amdgpu_synid_gfx950_ssrc1_5c7b50: ssrc1 ----- Instruction input. *Size:* 1 dword. *Operands:* .. _amdgpu_synid_gfx950_ssrc1_eecc17: ssrc1 ----- Instruction input. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst`, :ref:`literal` .. _amdgpu_synid_gfx950_ssrc1_1ce478: ssrc1 ----- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_ssrc1_83ef5a: ssrc1 ----- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst`, :ref:`literal` .. _amdgpu_synid_gfx950_vaddr: vaddr ----- This is an optional operand which may specify offset and/or index. *Size:* 0, 1 or 2 dwords. Size is controlled by modifiers :ref:`offen` and :ref:`idxen`: * If only :ref:`idxen` is specified, this operand supplies an index. Size is 1 dword. * If only :ref:`offen` is specified, this operand supplies an offset. Size is 1 dword. * If both modifiers are specified, index is in the first register and offset is in the second. Size is 2 dwords. * If none of these modifiers are specified, this operand must be set to :ref:`off`. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_vcc: vcc --- Vector condition code. *Size:* 1 dword. *Operands:* :ref:`vcc` .. _amdgpu_synid_gfx950_vdata_2a60db: vdata ----- Input data for an atomic instruction. Optionally may serve as an output data: * If :ref:`glc` is specified, gets the memory value before the operation. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdata_2d0375: vdata ----- Input data for an atomic instruction. Optionally may serve as an output data: * If :ref:`glc` is specified, gets the memory value before the operation. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdata_8e9b87: vdata ----- Input data for an atomic instruction. Optionally may serve as an output data: * If :ref:`glc` is specified, gets the memory value before the operation. *Size:* 4 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdata_fa7dbd: vdata ----- Instruction output. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdata_0f48d1: vdata ----- Instruction output. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdata_260aca: vdata ----- Instruction output. *Size:* 3 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdata_180bef: vdata ----- Instruction output. *Size:* 4 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdst_c8ee02: vdst ---- Data returned by a 32-bit atomic flat instruction. This is an optional operand. It must be used if and only if :ref:`glc` is specified. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdst_ef6c94: vdst ---- Data returned by a 64-bit atomic flat instruction. This is an optional operand. It must be used if and only if :ref:`glc` is specified. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdst_78dd0a: vdst ---- Instruction output. *Size:* 1 dword. *Operands:* :ref:`a` .. _amdgpu_synid_gfx950_vdst_59204c: vdst ---- Instruction output. *Size:* 1 dword. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`ttmp` .. _amdgpu_synid_gfx950_vdst_89680f: vdst ---- Instruction output. *Size:* 1 dword. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_vdst_fa7dbd: vdst ---- Instruction output. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdst_5f7812: vdst ---- Instruction output. *Size:* 16 dwords. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_vdst_d6f4bd: vdst ---- Instruction output. *Size:* 16 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdst_718cc4: vdst ---- Instruction output. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp` .. _amdgpu_synid_gfx950_vdst_a319e6: vdst ---- Instruction output. *Size:* 2 dwords. *Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`exec` .. _amdgpu_synid_gfx950_vdst_bdb32f: vdst ---- Instruction output. *Size:* 2 dwords. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_vdst_0f48d1: vdst ---- Instruction output. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdst_260aca: vdst ---- Instruction output. *Size:* 3 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdst_2eda77: vdst ---- Instruction output. *Size:* 32 dwords. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_vdst_8c77d4: vdst ---- Instruction output. *Size:* 32 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdst_69a144: vdst ---- Instruction output. *Size:* 4 dwords. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_vdst_180bef: vdst ---- Instruction output. *Size:* 4 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vdst_363335: vdst ---- Instruction output. *Size:* 6 dwords. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_vdst_c8d317: vdst ---- Instruction output. *Size:* 8 dwords. *Operands:* :ref:`v`, :ref:`a` .. _amdgpu_synid_gfx950_vsrc0_1027ca: vsrc0 ----- Instruction input. *Size:* 1 dword. *Operands:* :ref:`a` .. _amdgpu_synid_gfx950_vsrc0_6802ce: vsrc0 ----- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_vsrc0_14b47a: vsrc0 ----- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_vsrc0_0f0007: vsrc0 ----- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst`, :ref:`literal` .. _amdgpu_synid_gfx950_vsrc0_fd235e: vsrc0 ----- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_vsrc0_e30a18: vsrc0 ----- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_vsrc1_6802ce: vsrc1 ----- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v` .. _amdgpu_synid_gfx950_vsrc1_14b47a: vsrc1 ----- Instruction input. *Size:* 1 dword. *Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`fconst` .. _amdgpu_synid_gfx950_vsrc1_fd235e: vsrc1 ----- Instruction input. *Size:* 2 dwords. *Operands:* :ref:`v`