AMDGPUIGroupLP.h File Reference

#include "llvm/ADT/BitmaskEnum.h"
#include "llvm/CodeGen/ScheduleDAGMutation.h"
#include <memory>

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Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.
namespace	llvm::AMDGPU

Enumerations
enum class	llvm::AMDGPU::SchedulingPhase { llvm::AMDGPU::Initial , llvm::AMDGPU::PreRAReentry , llvm::AMDGPU::PostRA }
enum	llvm::AMDGPU::IGLPStrategyID : int { llvm::AMDGPU::MFMASmallGemmOptID = 0 , llvm::AMDGPU::MFMASmallGemmSingleWaveOptID = 1 , llvm::AMDGPU::MFMAExpInterleaveID = 2 , llvm::AMDGPU::MFMAExpSimpleInterleaveID = 3 }
	Operand 0 immediate for IGLP_OPT pseudo instructions. More...
enum class	llvm::AMDGPU::SchedGroupMask {   llvm::AMDGPU::NONE = 0u , llvm::AMDGPU::ALU = 1u << 0 , llvm::AMDGPU::VALU = 1u << 1 , llvm::AMDGPU::SALU = 1u << 2 ,   llvm::AMDGPU::MFMA = 1u << 3 , llvm::AMDGPU::VMEM = 1u << 4 , llvm::AMDGPU::VMEM_READ = 1u << 5 , llvm::AMDGPU::VMEM_WRITE = 1u << 6 ,   llvm::AMDGPU::DS = 1u << 7 , llvm::AMDGPU::DS_READ = 1u << 8 , llvm::AMDGPU::DS_WRITE = 1u << 9 , llvm::AMDGPU::TRANS = 1u << 10 ,   llvm::AMDGPU::LDSDMA = 1u << 11 , llvm::AMDGPU::ALL }

Functions
std::unique_ptr< ScheduleDAGMutation >	llvm::createIGroupLPDAGMutation (AMDGPU::SchedulingPhase Phase)
	Phase specifes whether or not this is a reentry into the IGroupLPDAGMutation.