LLVM 23.0.0git
AMDGPUTargetStreamer.cpp
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1//===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides AMDGPU specific target streamer methods.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AMDGPUTargetStreamer.h"
14#include "AMDGPUMCExpr.h"
15#include "AMDGPUMCKernelDescriptor.h"
16#include "AMDGPUMCTargetDesc.h"
17#include "AMDGPUPTNote.h"
18#include "Utils/AMDGPUBaseInfo.h"
19#include "Utils/AMDKernelCodeTUtils.h"
20#include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h"
21#include "llvm/BinaryFormat/ELF.h"
22#include "llvm/MC/MCAsmInfo.h"
23#include "llvm/MC/MCAssembler.h"
24#include "llvm/MC/MCContext.h"
25#include "llvm/MC/MCELFObjectWriter.h"
26#include "llvm/MC/MCELFStreamer.h"
27#include "llvm/MC/MCSubtargetInfo.h"
28#include "llvm/Support/AMDGPUMetadata.h"
29#include "llvm/Support/AMDHSAKernelDescriptor.h"
30#include "llvm/Support/CommandLine.h"
31#include "llvm/Support/FormattedStream.h"
32#include "llvm/TargetParser/TargetParser.h"
33
34using namespace llvm;
35using namespace llvm::AMDGPU;
36
37//===----------------------------------------------------------------------===//
38// AMDGPUTargetStreamer
39//===----------------------------------------------------------------------===//
40
41static cl::opt<unsigned>
42 ForceGenericVersion("amdgpu-force-generic-version",
43 cl::desc("Force a specific generic_v<N> flag to be "
44 "added. For testing purposes only."),
45 cl::ReallyHidden, cl::init(0));
46
47bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) {
48 msgpack::Document HSAMetadataDoc;
49 if (!HSAMetadataDoc.fromYAML(HSAMetadataString))
50 return false;
51 return EmitHSAMetadata(HSAMetadataDoc, false);
52}
53
54StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) {
55 AMDGPU::GPUKind AK;
56
57 // clang-format off
58 switch (ElfMach) {
59 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break;
60 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break;
61 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break;
62 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break;
63 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break;
64 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break;
65 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break;
66 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break;
67 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break;
68 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break;
69 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break;
70 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break;
71 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break;
72 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break;
73 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break;
74 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break;
75 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break;
76 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break;
77 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX602: AK = GK_GFX602; break;
78 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break;
79 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break;
80 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break;
81 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break;
82 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break;
83 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX705: AK = GK_GFX705; break;
84 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break;
85 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break;
86 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break;
87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX805: AK = GK_GFX805; break;
88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break;
89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break;
90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break;
91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break;
92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break;
93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: AK = GK_GFX908; break;
94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break;
95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A: AK = GK_GFX90A; break;
96 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C: AK = GK_GFX90C; break;
97 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX942: AK = GK_GFX942; break;
98 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX950: AK = GK_GFX950; break;
99 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break;
100 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break;
101 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break;
102 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013: AK = GK_GFX1013; break;
103 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: AK = GK_GFX1030; break;
104 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: AK = GK_GFX1031; break;
105 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032: AK = GK_GFX1032; break;
106 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033: AK = GK_GFX1033; break;
107 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034: AK = GK_GFX1034; break;
108 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035: AK = GK_GFX1035; break;
109 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036: AK = GK_GFX1036; break;
110 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100: AK = GK_GFX1100; break;
111 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1101: AK = GK_GFX1101; break;
112 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1102: AK = GK_GFX1102; break;
113 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1103: AK = GK_GFX1103; break;
114 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1150: AK = GK_GFX1150; break;
115 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1151: AK = GK_GFX1151; break;
116 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1152: AK = GK_GFX1152; break;
117 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1153: AK = GK_GFX1153; break;
118 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1170: AK = GK_GFX1170; break;
119 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1171: AK = GK_GFX1171; break;
120 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1172: AK = GK_GFX1172; break;
121 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1200: AK = GK_GFX1200; break;
122 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1201: AK = GK_GFX1201; break;
123 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1250: AK = GK_GFX1250; break;
124 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1251: AK = GK_GFX1251; break;
125 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1310: AK = GK_GFX1310; break;
126 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX9_GENERIC: AK = GK_GFX9_GENERIC; break;
127 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX9_4_GENERIC: AK = GK_GFX9_4_GENERIC; break;
128 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX10_1_GENERIC: AK = GK_GFX10_1_GENERIC; break;
129 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX10_3_GENERIC: AK = GK_GFX10_3_GENERIC; break;
130 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX11_GENERIC: AK = GK_GFX11_GENERIC; break;
131 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX12_GENERIC: AK = GK_GFX12_GENERIC; break;
132 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX12_5_GENERIC: AK = GK_GFX12_5_GENERIC; break;
133 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break;
134 default: AK = GK_NONE; break;
135 }
136 // clang-format on
137
138 StringRef GPUName = getArchNameAMDGCN(AK);
139 if (GPUName != "")
140 return GPUName;
141 return getArchNameR600(AK);
142}
143
144unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) {
145 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU);
146 if (AK == AMDGPU::GPUKind::GK_NONE)
147 AK = parseArchR600(GPU);
148
149 // clang-format off
150 switch (AK) {
151 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600;
152 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630;
153 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880;
154 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670;
155 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710;
156 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730;
157 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770;
158 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR;
159 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS;
160 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER;
161 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD;
162 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO;
163 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS;
164 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS;
165 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN;
166 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS;
167 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600;
168 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601;
169 case GK_GFX602: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX602;
170 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700;
171 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701;
172 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702;
173 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703;
174 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704;
175 case GK_GFX705: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX705;
176 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801;
177 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802;
178 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803;
179 case GK_GFX805: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX805;
180 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810;
181 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900;
182 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902;
183 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904;
184 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906;
185 case GK_GFX908: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX908;
186 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909;
187 case GK_GFX90A: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A;
188 case GK_GFX90C: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C;
189 case GK_GFX942: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX942;
190 case GK_GFX950: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX950;
191 case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010;
192 case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011;
193 case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012;
194 case GK_GFX1013: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013;
195 case GK_GFX1030: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030;
196 case GK_GFX1031: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031;
197 case GK_GFX1032: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032;
198 case GK_GFX1033: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033;
199 case GK_GFX1034: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034;
200 case GK_GFX1035: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035;
201 case GK_GFX1036: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036;
202 case GK_GFX1100: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100;
203 case GK_GFX1101: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1101;
204 case GK_GFX1102: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1102;
205 case GK_GFX1103: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1103;
206 case GK_GFX1150: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1150;
207 case GK_GFX1151: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1151;
208 case GK_GFX1152: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1152;
209 case GK_GFX1153: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1153;
210 case GK_GFX1170: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1170;
211 case GK_GFX1171: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1171;
212 case GK_GFX1172: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1172;
213 case GK_GFX1200: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1200;
214 case GK_GFX1201: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1201;
215 case GK_GFX1250: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1250;
216 case GK_GFX1251: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1251;
217 case GK_GFX1310: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1310;
218 case GK_GFX9_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX9_GENERIC;
219 case GK_GFX9_4_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX9_4_GENERIC;
220 case GK_GFX10_1_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX10_1_GENERIC;
221 case GK_GFX10_3_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX10_3_GENERIC;
222 case GK_GFX11_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX11_GENERIC;
223 case GK_GFX12_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX12_GENERIC;
224 case GK_GFX12_5_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX12_5_GENERIC;
225 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE;
226 }
227 // clang-format on
228
229 llvm_unreachable("unknown GPU");
230}
231
232//===----------------------------------------------------------------------===//
233// AMDGPUTargetAsmStreamer
234//===----------------------------------------------------------------------===//
235
239
240// A hook for emitting stuff at the end.
241// We use it for emitting the accumulated PAL metadata as directives.
242// The PAL metadata is reset after it is emitted.
243void AMDGPUTargetAsmStreamer::finish() {
244 std::string S;
245 getPALMetadata()->toString(S);
246 OS << S;
247
248 // Reset the pal metadata so its data will not affect a compilation that
249 // reuses this object.
250 getPALMetadata()->reset();
251}
252
253void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget() {
254 OS << "\t.amdgcn_target \"" << *getTargetID() << "\"\n";
255}
256
257void AMDGPUTargetAsmStreamer::EmitDirectiveAMDHSACodeObjectVersion(
258 unsigned COV) {
259 AMDGPUTargetStreamer::EmitDirectiveAMDHSACodeObjectVersion(COV);
260 OS << "\t.amdhsa_code_object_version " << COV << '\n';
261}
262
263void AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(AMDGPUMCKernelCodeT &Header) {
264 auto FoldAndPrint = [&](const MCExpr *Expr, raw_ostream &OS,
265 const MCAsmInfo *MAI) {
266 printAMDGPUMCExpr(foldAMDGPUMCExpr(Expr, getContext()), OS, MAI);
267 };
268
269 OS << "\t.amd_kernel_code_t\n";
270 Header.EmitKernelCodeT(OS, getContext(), FoldAndPrint);
271 OS << "\t.end_amd_kernel_code_t\n";
272}
273
274void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName,
275 unsigned Type) {
276 switch (Type) {
277 default: llvm_unreachable("Invalid AMDGPU symbol type");
278 case ELF::STT_AMDGPU_HSA_KERNEL:
279 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ;
280 break;
281 }
282}
283
284void AMDGPUTargetAsmStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size,
285 Align Alignment) {
286 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", "
287 << Alignment.value() << '\n';
288}
289
290void AMDGPUTargetAsmStreamer::EmitMCResourceInfo(
291 const MCSymbol *NumVGPR, const MCSymbol *NumAGPR,
292 const MCSymbol *NumExplicitSGPR, const MCSymbol *NumNamedBarrier,
293 const MCSymbol *PrivateSegmentSize, const MCSymbol *UsesVCC,
294 const MCSymbol *UsesFlatScratch, const MCSymbol *HasDynamicallySizedStack,
295 const MCSymbol *HasRecursion, const MCSymbol *HasIndirectCall) {
296#define PRINT_RES_INFO(ARG) \
297 OS << "\t.set "; \
298 ARG->print(OS, getContext().getAsmInfo()); \
299 OS << ", "; \
300 getContext().getAsmInfo()->printExpr(OS, *ARG->getVariableValue()); \
301 Streamer.addBlankLine();
302
303 PRINT_RES_INFO(NumVGPR);
304 PRINT_RES_INFO(NumAGPR);
305 PRINT_RES_INFO(NumExplicitSGPR);
306 PRINT_RES_INFO(NumNamedBarrier);
307 PRINT_RES_INFO(PrivateSegmentSize);
308 PRINT_RES_INFO(UsesVCC);
309 PRINT_RES_INFO(UsesFlatScratch);
310 PRINT_RES_INFO(HasDynamicallySizedStack);
311 PRINT_RES_INFO(HasRecursion);
312 PRINT_RES_INFO(HasIndirectCall);
313#undef PRINT_RES_INFO
314}
315
316void AMDGPUTargetAsmStreamer::EmitMCResourceMaximums(
317 const MCSymbol *MaxVGPR, const MCSymbol *MaxAGPR, const MCSymbol *MaxSGPR,
318 const MCSymbol *MaxNamedBarrier) {
319#define PRINT_RES_INFO(ARG) \
320 OS << "\t.set "; \
321 ARG->print(OS, getContext().getAsmInfo()); \
322 OS << ", "; \
323 getContext().getAsmInfo()->printExpr(OS, *ARG->getVariableValue()); \
324 Streamer.addBlankLine();
325
326 PRINT_RES_INFO(MaxVGPR);
327 PRINT_RES_INFO(MaxAGPR);
328 PRINT_RES_INFO(MaxSGPR);
329 PRINT_RES_INFO(MaxNamedBarrier);
330#undef PRINT_RES_INFO
331}
332
333bool AMDGPUTargetAsmStreamer::EmitISAVersion() {
334 OS << "\t.amd_amdgpu_isa \"" << getTargetID() << "\"\n";
335 return true;
336}
337
338bool AMDGPUTargetAsmStreamer::EmitHSAMetadata(
339 msgpack::Document &HSAMetadataDoc, bool Strict) {
340 HSAMD::V3::MetadataVerifier Verifier(Strict);
341 if (!Verifier.verify(HSAMetadataDoc.getRoot()))
342 return false;
343
344 std::string HSAMetadataString;
345 raw_string_ostream StrOS(HSAMetadataString);
346 HSAMetadataDoc.toYAML(StrOS);
347
348 OS << '\t' << HSAMD::V3::AssemblerDirectiveBegin << '\n';
349 OS << StrOS.str() << '\n';
350 OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n';
351 return true;
352}
353
354bool AMDGPUTargetAsmStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) {
355 const uint32_t Encoded_s_code_end = 0xbf9f0000;
356 const uint32_t Encoded_s_nop = 0xbf800000;
357 uint32_t Encoded_pad = Encoded_s_code_end;
358
359 // Instruction cache line size in bytes.
360 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
361 const unsigned CacheLineSize = 1u << Log2CacheLineSize;
362
363 // Extra padding amount in bytes to support prefetch mode 3.
364 unsigned FillSize = 3 * CacheLineSize;
365
366 if (AMDGPU::isGFX90A(STI)) {
367 Encoded_pad = Encoded_s_nop;
368 FillSize = 16 * CacheLineSize;
369 }
370
371 OS << "\t.p2alignl " << Log2CacheLineSize << ", " << Encoded_pad << '\n';
372 OS << "\t.fill " << (FillSize / 4) << ", 4, " << Encoded_pad << '\n';
373 return true;
374}
375
376void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
377 const MCSubtargetInfo &STI, StringRef KernelName,
378 const MCKernelDescriptor &KD, const MCExpr *NextVGPR,
379 const MCExpr *NextSGPR, const MCExpr *ReserveVCC,
380 const MCExpr *ReserveFlatScr) {
381 IsaVersion IVersion = getIsaVersion(STI.getCPU());
382 const MCAsmInfo *MAI = getContext().getAsmInfo();
383
384 OS << "\t.amdhsa_kernel " << KernelName << '\n';
385
386 auto PrintField = [&](const MCExpr *Expr, uint32_t Shift, uint32_t Mask,
387 StringRef Directive) {
388 OS << "\t\t" << Directive << ' ';
389 const MCExpr *ShiftedAndMaskedExpr =
390 MCKernelDescriptor::bits_get(Expr, Shift, Mask, getContext());
391 const MCExpr *New = foldAMDGPUMCExpr(ShiftedAndMaskedExpr, getContext());
392 printAMDGPUMCExpr(New, OS, MAI);
393 OS << '\n';
394 };
395
396 auto EmitMCExpr = [&](const MCExpr *Value) {
397 const MCExpr *NewExpr = foldAMDGPUMCExpr(Value, getContext());
398 printAMDGPUMCExpr(NewExpr, OS, MAI);
399 };
400
401 OS << "\t\t.amdhsa_group_segment_fixed_size ";
402 EmitMCExpr(KD.group_segment_fixed_size);
403 OS << '\n';
404
405 OS << "\t\t.amdhsa_private_segment_fixed_size ";
406 EmitMCExpr(KD.private_segment_fixed_size);
407 OS << '\n';
408
409 OS << "\t\t.amdhsa_kernarg_size ";
410 EmitMCExpr(KD.kernarg_size);
411 OS << '\n';
412
413 if (isGFX1250Plus(STI)) {
414 PrintField(KD.compute_pgm_rsrc2,
415 amdhsa::COMPUTE_PGM_RSRC2_GFX125_USER_SGPR_COUNT_SHIFT,
416 amdhsa::COMPUTE_PGM_RSRC2_GFX125_USER_SGPR_COUNT,
417 ".amdhsa_user_sgpr_count");
418 } else {
419 PrintField(KD.compute_pgm_rsrc2,
420 amdhsa::COMPUTE_PGM_RSRC2_GFX6_GFX120_USER_SGPR_COUNT_SHIFT,
421 amdhsa::COMPUTE_PGM_RSRC2_GFX6_GFX120_USER_SGPR_COUNT,
422 ".amdhsa_user_sgpr_count");
423 }
424
425 if (!hasArchitectedFlatScratch(STI))
426 PrintField(
427 KD.kernel_code_properties,
428 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_SHIFT,
429 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER,
430 ".amdhsa_user_sgpr_private_segment_buffer");
431 PrintField(KD.kernel_code_properties,
432 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR_SHIFT,
433 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR,
434 ".amdhsa_user_sgpr_dispatch_ptr");
435 PrintField(KD.kernel_code_properties,
436 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR_SHIFT,
437 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR,
438 ".amdhsa_user_sgpr_queue_ptr");
439 PrintField(KD.kernel_code_properties,
440 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR_SHIFT,
441 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR,
442 ".amdhsa_user_sgpr_kernarg_segment_ptr");
443 PrintField(KD.kernel_code_properties,
444 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID_SHIFT,
445 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID,
446 ".amdhsa_user_sgpr_dispatch_id");
447 if (!hasArchitectedFlatScratch(STI))
448 PrintField(KD.kernel_code_properties,
449 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT_SHIFT,
450 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT,
451 ".amdhsa_user_sgpr_flat_scratch_init");
452 if (hasKernargPreload(STI)) {
453 PrintField(KD.kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_LENGTH_SHIFT,
454 amdhsa::KERNARG_PRELOAD_SPEC_LENGTH,
455 ".amdhsa_user_sgpr_kernarg_preload_length");
456 PrintField(KD.kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_OFFSET_SHIFT,
457 amdhsa::KERNARG_PRELOAD_SPEC_OFFSET,
458 ".amdhsa_user_sgpr_kernarg_preload_offset");
459 }
460 PrintField(
461 KD.kernel_code_properties,
462 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_SHIFT,
463 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE,
464 ".amdhsa_user_sgpr_private_segment_size");
465 if (IVersion.Major >= 10)
466 PrintField(KD.kernel_code_properties,
467 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32_SHIFT,
468 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,
469 ".amdhsa_wavefront_size32");
470 if (CodeObjectVersion >= AMDGPU::AMDHSA_COV5)
471 PrintField(KD.kernel_code_properties,
472 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK_SHIFT,
473 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK,
474 ".amdhsa_uses_dynamic_stack");
475 PrintField(KD.compute_pgm_rsrc2,
476 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT_SHIFT,
477 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT,
478 (hasArchitectedFlatScratch(STI)
479 ? ".amdhsa_enable_private_segment"
480 : ".amdhsa_system_sgpr_private_segment_wavefront_offset"));
481 PrintField(KD.compute_pgm_rsrc2,
482 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X_SHIFT,
483 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X,
484 ".amdhsa_system_sgpr_workgroup_id_x");
485 PrintField(KD.compute_pgm_rsrc2,
486 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y_SHIFT,
487 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y,
488 ".amdhsa_system_sgpr_workgroup_id_y");
489 PrintField(KD.compute_pgm_rsrc2,
490 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z_SHIFT,
491 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z,
492 ".amdhsa_system_sgpr_workgroup_id_z");
493 PrintField(KD.compute_pgm_rsrc2,
494 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO_SHIFT,
495 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO,
496 ".amdhsa_system_sgpr_workgroup_info");
497 PrintField(KD.compute_pgm_rsrc2,
498 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID_SHIFT,
499 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID,
500 ".amdhsa_system_vgpr_workitem_id");
501
502 // These directives are required.
503 OS << "\t\t.amdhsa_next_free_vgpr ";
504 EmitMCExpr(NextVGPR);
505 OS << '\n';
506
507 OS << "\t\t.amdhsa_next_free_sgpr ";
508 EmitMCExpr(NextSGPR);
509 OS << '\n';
510
511 if (AMDGPU::isGFX90A(STI)) {
512 // MCExpr equivalent of taking the (accum_offset + 1) * 4.
513 const MCExpr *accum_bits = MCKernelDescriptor::bits_get(
514 KD.compute_pgm_rsrc3,
515 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET_SHIFT,
516 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET, getContext());
517 accum_bits = MCBinaryExpr::createAdd(
518 accum_bits, MCConstantExpr::create(1, getContext()), getContext());
519 accum_bits = MCBinaryExpr::createMul(
520 accum_bits, MCConstantExpr::create(4, getContext()), getContext());
521 OS << "\t\t.amdhsa_accum_offset ";
522 const MCExpr *New = foldAMDGPUMCExpr(accum_bits, getContext());
523 printAMDGPUMCExpr(New, OS, MAI);
524 OS << '\n';
525 }
526
527 if (isGFX1250Plus(STI))
528 PrintField(KD.compute_pgm_rsrc3,
529 amdhsa::COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT_SHIFT,
530 amdhsa::COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT,
531 ".amdhsa_named_barrier_count");
532
533 OS << "\t\t.amdhsa_reserve_vcc ";
534 EmitMCExpr(ReserveVCC);
535 OS << '\n';
536
537 if (IVersion.Major >= 7 && !hasArchitectedFlatScratch(STI)) {
538 OS << "\t\t.amdhsa_reserve_flat_scratch ";
539 EmitMCExpr(ReserveFlatScr);
540 OS << '\n';
541 }
542
543 switch (CodeObjectVersion) {
544 default:
545 break;
546 case AMDGPU::AMDHSA_COV4:
547 case AMDGPU::AMDHSA_COV5:
548 if (getTargetID()->isXnackSupported())
549 OS << "\t\t.amdhsa_reserve_xnack_mask " << getTargetID()->isXnackOnOrAny() << '\n';
550 break;
551 }
552
553 PrintField(KD.compute_pgm_rsrc1,
554 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32_SHIFT,
555 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32,
556 ".amdhsa_float_round_mode_32");
557 PrintField(KD.compute_pgm_rsrc1,
558 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64_SHIFT,
559 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64,
560 ".amdhsa_float_round_mode_16_64");
561 PrintField(KD.compute_pgm_rsrc1,
562 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32_SHIFT,
563 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32,
564 ".amdhsa_float_denorm_mode_32");
565 PrintField(KD.compute_pgm_rsrc1,
566 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64_SHIFT,
567 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64,
568 ".amdhsa_float_denorm_mode_16_64");
569 if (STI.hasFeature(AMDGPU::FeatureDX10ClampAndIEEEMode)) {
570 PrintField(KD.compute_pgm_rsrc1,
571 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP_SHIFT,
572 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP,
573 ".amdhsa_dx10_clamp");
574 PrintField(KD.compute_pgm_rsrc1,
575 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE_SHIFT,
576 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE,
577 ".amdhsa_ieee_mode");
578 }
579 if (IVersion.Major >= 9) {
580 PrintField(KD.compute_pgm_rsrc1,
581 amdhsa::COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL_SHIFT,
582 amdhsa::COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL,
583 ".amdhsa_fp16_overflow");
584 }
585 if (AMDGPU::isGFX90A(STI))
586 PrintField(KD.compute_pgm_rsrc3,
587 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT_SHIFT,
588 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT, ".amdhsa_tg_split");
589 if (AMDGPU::supportsWGP(STI))
590 PrintField(KD.compute_pgm_rsrc1,
591 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE_SHIFT,
592 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE,
593 ".amdhsa_workgroup_processor_mode");
594 if (IVersion.Major >= 10) {
595 PrintField(KD.compute_pgm_rsrc1,
596 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED_SHIFT,
597 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED,
598 ".amdhsa_memory_ordered");
599 PrintField(KD.compute_pgm_rsrc1,
600 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS_SHIFT,
601 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS,
602 ".amdhsa_forward_progress");
603 }
604 if (IVersion.Major >= 10 && IVersion.Major < 12) {
605 PrintField(KD.compute_pgm_rsrc3,
606 amdhsa::COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT_SHIFT,
607 amdhsa::COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT,
608 ".amdhsa_shared_vgpr_count");
609 }
610 if (IVersion.Major == 11) {
611 PrintField(KD.compute_pgm_rsrc3,
612 amdhsa::COMPUTE_PGM_RSRC3_GFX11_INST_PREF_SIZE_SHIFT,
613 amdhsa::COMPUTE_PGM_RSRC3_GFX11_INST_PREF_SIZE,
614 ".amdhsa_inst_pref_size");
615 }
616 if (IVersion.Major >= 12) {
617 PrintField(KD.compute_pgm_rsrc3,
618 amdhsa::COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE_SHIFT,
619 amdhsa::COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE,
620 ".amdhsa_inst_pref_size");
621 PrintField(KD.compute_pgm_rsrc1,
622 amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN_SHIFT,
623 amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN,
624 ".amdhsa_round_robin_scheduling");
625 }
626 PrintField(
627 KD.compute_pgm_rsrc2,
628 amdhsa::
629 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_SHIFT,
630 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION,
631 ".amdhsa_exception_fp_ieee_invalid_op");
632 PrintField(
633 KD.compute_pgm_rsrc2,
634 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_SHIFT,
635 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE,
636 ".amdhsa_exception_fp_denorm_src");
637 PrintField(
638 KD.compute_pgm_rsrc2,
639 amdhsa::
640 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_SHIFT,
641 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO,
642 ".amdhsa_exception_fp_ieee_div_zero");
643 PrintField(
644 KD.compute_pgm_rsrc2,
645 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_SHIFT,
646 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW,
647 ".amdhsa_exception_fp_ieee_overflow");
648 PrintField(
649 KD.compute_pgm_rsrc2,
650 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_SHIFT,
651 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW,
652 ".amdhsa_exception_fp_ieee_underflow");
653 PrintField(
654 KD.compute_pgm_rsrc2,
655 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_SHIFT,
656 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT,
657 ".amdhsa_exception_fp_ieee_inexact");
658 PrintField(
659 KD.compute_pgm_rsrc2,
660 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO_SHIFT,
661 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO,
662 ".amdhsa_exception_int_div_zero");
663
664 OS << "\t.end_amdhsa_kernel\n";
665}
666
667//===----------------------------------------------------------------------===//
668// AMDGPUTargetELFStreamer
669//===----------------------------------------------------------------------===//
670
674
675MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() {
676 return static_cast<MCELFStreamer &>(Streamer);
677}
678
679// A hook for emitting stuff at the end.
680// We use it for emitting the accumulated PAL metadata as a .note record.
681// The PAL metadata is reset after it is emitted.
682void AMDGPUTargetELFStreamer::finish() {
683 ELFObjectWriter &W = getStreamer().getWriter();
684 W.setELFHeaderEFlags(getEFlags());
685 W.setOverrideABIVersion(
686 getELFABIVersion(STI.getTargetTriple(), CodeObjectVersion));
687
688 std::string Blob;
689 const char *Vendor = getPALMetadata()->getVendor();
690 unsigned Type = getPALMetadata()->getType();
691 getPALMetadata()->toBlob(Type, Blob);
692 if (Blob.empty())
693 return;
694 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type,
695 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); });
696
697 // Reset the pal metadata so its data will not affect a compilation that
698 // reuses this object.
699 getPALMetadata()->reset();
700}
701
702void AMDGPUTargetELFStreamer::EmitNote(
703 StringRef Name, const MCExpr *DescSZ, unsigned NoteType,
704 function_ref<void(MCELFStreamer &)> EmitDesc) {
705 auto &S = getStreamer();
706 auto &Context = S.getContext();
707
708 auto NameSZ = Name.size() + 1;
709
710 unsigned NoteFlags = 0;
711 // TODO Apparently, this is currently needed for OpenCL as mentioned in
712 // https://reviews.llvm.org/D74995
713 if (isHsaAbi(STI))
714 NoteFlags = ELF::SHF_ALLOC;
715
716 S.pushSection();
717 S.switchSection(
718 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags));
719 S.emitInt32(NameSZ); // namesz
720 S.emitValue(DescSZ, 4); // descz
721 S.emitInt32(NoteType); // type
722 S.emitBytes(Name); // name
723 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
724 EmitDesc(S); // desc
725 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
726 S.popSection();
727}
728
729unsigned AMDGPUTargetELFStreamer::getEFlags() {
730 switch (STI.getTargetTriple().getArch()) {
731 default:
732 llvm_unreachable("Unsupported Arch");
733 case Triple::r600:
734 return getEFlagsR600();
735 case Triple::amdgcn:
736 return getEFlagsAMDGCN();
737 }
738}
739
740unsigned AMDGPUTargetELFStreamer::getEFlagsR600() {
741 assert(STI.getTargetTriple().getArch() == Triple::r600);
742
743 return getElfMach(STI.getCPU());
744}
745
746unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() {
747 assert(STI.getTargetTriple().isAMDGCN());
748
749 switch (STI.getTargetTriple().getOS()) {
750 default:
751 // TODO: Why are some tests have "mingw" listed as OS?
752 // llvm_unreachable("Unsupported OS");
753 case Triple::UnknownOS:
754 return getEFlagsUnknownOS();
755 case Triple::AMDHSA:
756 return getEFlagsAMDHSA();
757 case Triple::AMDPAL:
758 return getEFlagsAMDPAL();
759 case Triple::Mesa3D:
760 return getEFlagsMesa3D();
761 }
762}
763
764unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() {
765 // TODO: Why are some tests have "mingw" listed as OS?
766 // assert(STI.getTargetTriple().getOS() == Triple::UnknownOS);
767
768 return getEFlagsV3();
769}
770
771unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() {
772 assert(isHsaAbi(STI));
773
774 if (CodeObjectVersion >= 6)
775 return getEFlagsV6();
776 return getEFlagsV4();
777}
778
779unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() {
780 assert(STI.getTargetTriple().getOS() == Triple::AMDPAL);
781
782 return getEFlagsV3();
783}
784
785unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() {
786 assert(STI.getTargetTriple().getOS() == Triple::Mesa3D);
787
788 return getEFlagsV3();
789}
790
791unsigned AMDGPUTargetELFStreamer::getEFlagsV3() {
792 unsigned EFlagsV3 = 0;
793
794 // mach.
795 EFlagsV3 |= getElfMach(STI.getCPU());
796
797 // xnack.
798 if (getTargetID()->isXnackOnOrAny())
799 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_XNACK_V3;
800 // sramecc.
801 if (getTargetID()->isSramEccOnOrAny())
802 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_V3;
803
804 return EFlagsV3;
805}
806
807unsigned AMDGPUTargetELFStreamer::getEFlagsV4() {
808 unsigned EFlagsV4 = 0;
809
810 // mach.
811 EFlagsV4 |= getElfMach(STI.getCPU());
812
813 // xnack.
814 switch (getTargetID()->getXnackSetting()) {
815 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported:
816 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4;
817 break;
818 case AMDGPU::IsaInfo::TargetIDSetting::Any:
819 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ANY_V4;
820 break;
821 case AMDGPU::IsaInfo::TargetIDSetting::Off:
822 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_OFF_V4;
823 break;
824 case AMDGPU::IsaInfo::TargetIDSetting::On:
825 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ON_V4;
826 break;
827 }
828 // sramecc.
829 switch (getTargetID()->getSramEccSetting()) {
830 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported:
831 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4;
832 break;
833 case AMDGPU::IsaInfo::TargetIDSetting::Any:
834 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ANY_V4;
835 break;
836 case AMDGPU::IsaInfo::TargetIDSetting::Off:
837 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_OFF_V4;
838 break;
839 case AMDGPU::IsaInfo::TargetIDSetting::On:
840 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ON_V4;
841 break;
842 }
843
844 return EFlagsV4;
845}
846
847unsigned AMDGPUTargetELFStreamer::getEFlagsV6() {
848 unsigned Flags = getEFlagsV4();
849
850 unsigned Version = ForceGenericVersion;
851 if (!Version) {
852 switch (parseArchAMDGCN(STI.getCPU())) {
853 case AMDGPU::GK_GFX9_GENERIC:
854 Version = GenericVersion::GFX9;
855 break;
856 case AMDGPU::GK_GFX9_4_GENERIC:
857 Version = GenericVersion::GFX9_4;
858 break;
859 case AMDGPU::GK_GFX10_1_GENERIC:
860 Version = GenericVersion::GFX10_1;
861 break;
862 case AMDGPU::GK_GFX10_3_GENERIC:
863 Version = GenericVersion::GFX10_3;
864 break;
865 case AMDGPU::GK_GFX11_GENERIC:
866 Version = GenericVersion::GFX11;
867 break;
868 case AMDGPU::GK_GFX12_GENERIC:
869 Version = GenericVersion::GFX12;
870 break;
871 case AMDGPU::GK_GFX12_5_GENERIC:
872 Version = GenericVersion::GFX12_5;
873 break;
874 default:
875 break;
876 }
877 }
878
879 // Versions start at 1.
880 if (Version) {
881 if (Version > ELF::EF_AMDGPU_GENERIC_VERSION_MAX)
882 report_fatal_error("Cannot encode generic code object version " +
883 Twine(Version) +
884 " - no ELF flag can represent this version!");
885 Flags |= (Version << ELF::EF_AMDGPU_GENERIC_VERSION_OFFSET);
886 }
887
888 return Flags;
889}
890
891void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget() {}
892
893void AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(AMDGPUMCKernelCodeT &Header) {
894 MCStreamer &OS = getStreamer();
895 OS.pushSection();
896 Header.EmitKernelCodeT(OS, getContext());
897 OS.popSection();
898}
899
900void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName,
901 unsigned Type) {
902 auto *Symbol = static_cast<MCSymbolELF *>(
903 getStreamer().getContext().getOrCreateSymbol(SymbolName));
904 Symbol->setType(Type);
905}
906
907void AMDGPUTargetELFStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size,
908 Align Alignment) {
909 auto *SymbolELF = static_cast<MCSymbolELF *>(Symbol);
910 SymbolELF->setType(ELF::STT_OBJECT);
911
912 if (!SymbolELF->isBindingSet())
913 SymbolELF->setBinding(ELF::STB_GLOBAL);
914
915 if (SymbolELF->declareCommon(Size, Alignment)) {
916 report_fatal_error("Symbol: " + Symbol->getName() +
917 " redeclared as different type");
918 }
919
920 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS);
921 SymbolELF->setSize(MCConstantExpr::create(Size, getContext()));
922}
923
924bool AMDGPUTargetELFStreamer::EmitISAVersion() {
925 // Create two labels to mark the beginning and end of the desc field
926 // and a MCExpr to calculate the size of the desc field.
927 auto &Context = getContext();
928 auto *DescBegin = Context.createTempSymbol();
929 auto *DescEnd = Context.createTempSymbol();
930 auto *DescSZ = MCBinaryExpr::createSub(
931 MCSymbolRefExpr::create(DescEnd, Context),
932 MCSymbolRefExpr::create(DescBegin, Context), Context);
933
934 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_ISA_NAME,
935 [&](MCELFStreamer &OS) {
936 OS.emitLabel(DescBegin);
937
938 SmallString<32> Str;
939 raw_svector_ostream StrOS(Str);
940 StrOS << *getTargetID();
941
942 OS.emitBytes(StrOS.str());
943 OS.emitLabel(DescEnd);
944 });
945 return true;
946}
947
948bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc,
949 bool Strict) {
950 HSAMD::V3::MetadataVerifier Verifier(Strict);
951 if (!Verifier.verify(HSAMetadataDoc.getRoot()))
952 return false;
953
954 std::string HSAMetadataString;
955 HSAMetadataDoc.writeToBlob(HSAMetadataString);
956
957 // Create two labels to mark the beginning and end of the desc field
958 // and a MCExpr to calculate the size of the desc field.
959 auto &Context = getContext();
960 auto *DescBegin = Context.createTempSymbol();
961 auto *DescEnd = Context.createTempSymbol();
962 auto *DescSZ = MCBinaryExpr::createSub(
963 MCSymbolRefExpr::create(DescEnd, Context),
964 MCSymbolRefExpr::create(DescBegin, Context), Context);
965
966 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA,
967 [&](MCELFStreamer &OS) {
968 OS.emitLabel(DescBegin);
969 OS.emitBytes(HSAMetadataString);
970 OS.emitLabel(DescEnd);
971 });
972 return true;
973}
974
975bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) {
976 const uint32_t Encoded_s_code_end = 0xbf9f0000;
977 const uint32_t Encoded_s_nop = 0xbf800000;
978 uint32_t Encoded_pad = Encoded_s_code_end;
979
980 // Instruction cache line size in bytes.
981 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
982 const unsigned CacheLineSize = 1u << Log2CacheLineSize;
983
984 // Extra padding amount in bytes to support prefetch mode 3.
985 unsigned FillSize = 3 * CacheLineSize;
986
987 if (AMDGPU::isGFX90A(STI)) {
988 Encoded_pad = Encoded_s_nop;
989 FillSize = 16 * CacheLineSize;
990 }
991
992 MCStreamer &OS = getStreamer();
993 OS.pushSection();
994 OS.emitValueToAlignment(Align(CacheLineSize), Encoded_pad, 4);
995 for (unsigned I = 0; I < FillSize; I += 4)
996 OS.emitInt32(Encoded_pad);
997 OS.popSection();
998 return true;
999}
1000
1001void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor(
1002 const MCSubtargetInfo &STI, StringRef KernelName,
1003 const MCKernelDescriptor &KernelDescriptor, const MCExpr *NextVGPR,
1004 const MCExpr *NextSGPR, const MCExpr *ReserveVCC,
1005 const MCExpr *ReserveFlatScr) {
1006 auto &Streamer = getStreamer();
1007 auto &Context = Streamer.getContext();
1008
1009 auto *KernelCodeSymbol =
1010 static_cast<MCSymbolELF *>(Context.getOrCreateSymbol(Twine(KernelName)));
1011 auto *KernelDescriptorSymbol = static_cast<MCSymbolELF *>(
1012 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd")));
1013
1014 // Copy kernel descriptor symbol's binding, other and visibility from the
1015 // kernel code symbol.
1016 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding());
1017 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther());
1018 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility());
1019 // Kernel descriptor symbol's type and size are fixed.
1020 KernelDescriptorSymbol->setType(ELF::STT_OBJECT);
1021 KernelDescriptorSymbol->setSize(
1022 MCConstantExpr::create(sizeof(amdhsa::kernel_descriptor_t), Context));
1023
1024 // The visibility of the kernel code symbol must be protected or less to allow
1025 // static relocations from the kernel descriptor to be used.
1026 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT)
1027 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED);
1028
1029 Streamer.emitLabel(KernelDescriptorSymbol);
1030 Streamer.emitValue(
1031 KernelDescriptor.group_segment_fixed_size,
1032 sizeof(amdhsa::kernel_descriptor_t::group_segment_fixed_size));
1033 Streamer.emitValue(
1034 KernelDescriptor.private_segment_fixed_size,
1035 sizeof(amdhsa::kernel_descriptor_t::private_segment_fixed_size));
1036 Streamer.emitValue(KernelDescriptor.kernarg_size,
1037 sizeof(amdhsa::kernel_descriptor_t::kernarg_size));
1038
1039 for (uint32_t i = 0; i < sizeof(amdhsa::kernel_descriptor_t::reserved0); ++i)
1040 Streamer.emitInt8(0u);
1041
1042 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The
1043 // expression being created is:
1044 // (start of kernel code) - (start of kernel descriptor)
1045 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64.
1046 Streamer.emitValue(
1047 MCBinaryExpr::createSub(
1048 MCSymbolRefExpr::create(KernelCodeSymbol, AMDGPUMCExpr::S_REL64,
1049 Context),
1050 MCSymbolRefExpr::create(KernelDescriptorSymbol, Context), Context),
1051 sizeof(amdhsa::kernel_descriptor_t::kernel_code_entry_byte_offset));
1052 for (uint32_t i = 0; i < sizeof(amdhsa::kernel_descriptor_t::reserved1); ++i)
1053 Streamer.emitInt8(0u);
1054 Streamer.emitValue(KernelDescriptor.compute_pgm_rsrc3,
1055 sizeof(amdhsa::kernel_descriptor_t::compute_pgm_rsrc3));
1056 Streamer.emitValue(KernelDescriptor.compute_pgm_rsrc1,
1057 sizeof(amdhsa::kernel_descriptor_t::compute_pgm_rsrc1));
1058 Streamer.emitValue(KernelDescriptor.compute_pgm_rsrc2,
1059 sizeof(amdhsa::kernel_descriptor_t::compute_pgm_rsrc2));
1060 Streamer.emitValue(
1061 KernelDescriptor.kernel_code_properties,
1062 sizeof(amdhsa::kernel_descriptor_t::kernel_code_properties));
1063 Streamer.emitValue(KernelDescriptor.kernarg_preload,
1064 sizeof(amdhsa::kernel_descriptor_t::kernarg_preload));
1065 for (uint32_t i = 0; i < sizeof(amdhsa::kernel_descriptor_t::reserved3); ++i)
1066 Streamer.emitInt8(0u);
1067}
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
AMDGPUMCKernelDescriptor.h
AMDHSA kernel descriptor MCExpr struct for use in MC layer.
AMDGPUMCTargetDesc.h
Provides AMDGPU specific target descriptions.
AMDGPUMetadataVerifier.h
This is a verifier for AMDGPU HSA metadata, which can verify both well-typed metadata and untyped met...
AMDGPUMetadata.h
AMDGPU metadata definitions and in-memory representations.
AMDGPUPTNote.h
Enums and constants for AMDGPU PT_NOTE sections.
ForceGenericVersion
static cl::opt< unsigned > ForceGenericVersion("amdgpu-force-generic-version", cl::desc("Force a specific generic_v<N> flag to be " "added. For testing purposes only."), cl::ReallyHidden, cl::init(0))
PRINT_RES_INFO
#define PRINT_RES_INFO(ARG)
AMDHSAKernelDescriptor.h
AMDHSA kernel descriptor definitions.
AMDKernelCodeTUtils.h
MC layer struct for AMDGPUMCKernelCodeT, provides MCExpr functionality where required.
I
#define I(x, y, z)
Definition MD5.cpp:57
Verifier
verify safepoint Safepoint IR Verifier
Definition SafepointIRVerifier.cpp:246
CacheLineSize
static cl::opt< unsigned > CacheLineSize("cache-line-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target cache line size when " "specified by the user."))
llvm::AMDGPUPALMetadata::getVendor
const char * getVendor() const
Definition AMDGPUPALMetadata.cpp:1018
llvm::AMDGPUPALMetadata::toBlob
void toBlob(unsigned Type, std::string &S)
Definition AMDGPUPALMetadata.cpp:868
llvm::AMDGPUPALMetadata::toString
void toString(std::string &S)
Definition AMDGPUPALMetadata.cpp:815
llvm::AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer
AMDGPUTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
Definition AMDGPUTargetStreamer.cpp:236
llvm::AMDGPUTargetAsmStreamer::EmitHSAMetadata
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
Definition AMDGPUTargetStreamer.cpp:338
llvm::AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
Definition AMDGPUTargetStreamer.cpp:274
llvm::AMDGPUTargetAsmStreamer::EmitDirectiveAMDHSACodeObjectVersion
void EmitDirectiveAMDHSACodeObjectVersion(unsigned COV) override
Definition AMDGPUTargetStreamer.cpp:257
llvm::AMDGPUTargetAsmStreamer::EmitMCResourceMaximums
void EmitMCResourceMaximums(const MCSymbol *MaxVGPR, const MCSymbol *MaxAGPR, const MCSymbol *MaxSGPR, const MCSymbol *MaxNamedBarrier) override
Definition AMDGPUTargetStreamer.cpp:316
llvm::AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT
void EmitAMDKernelCodeT(AMDGPU::AMDGPUMCKernelCodeT &Header) override
Definition AMDGPUTargetStreamer.cpp:263
llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const AMDGPU::MCKernelDescriptor &KernelDescriptor, const MCExpr *NextVGPR, const MCExpr *NextSGPR, const MCExpr *ReserveVCC, const MCExpr *ReserveFlatScr) override
Definition AMDGPUTargetStreamer.cpp:376
llvm::AMDGPUTargetAsmStreamer::EmitMCResourceInfo
void EmitMCResourceInfo(const MCSymbol *NumVGPR, const MCSymbol *NumAGPR, const MCSymbol *NumExplicitSGPR, const MCSymbol *NumNamedBarrier, const MCSymbol *PrivateSegmentSize, const MCSymbol *UsesVCC, const MCSymbol *UsesFlatScratch, const MCSymbol *HasDynamicallySizedStack, const MCSymbol *HasRecursion, const MCSymbol *HasIndirectCall) override
Definition AMDGPUTargetStreamer.cpp:290
llvm::AMDGPUTargetAsmStreamer::EmitCodeEnd
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
Definition AMDGPUTargetStreamer.cpp:354
llvm::AMDGPUTargetAsmStreamer::emitAMDGPULDS
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
Definition AMDGPUTargetStreamer.cpp:284
llvm::AMDGPUTargetELFStreamer::EmitCodeEnd
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
Definition AMDGPUTargetStreamer.cpp:975
llvm::AMDGPUTargetELFStreamer::EmitAMDKernelCodeT
void EmitAMDKernelCodeT(AMDGPU::AMDGPUMCKernelCodeT &Header) override
Definition AMDGPUTargetStreamer.cpp:893
llvm::AMDGPUTargetELFStreamer::EmitHSAMetadata
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
Definition AMDGPUTargetStreamer.cpp:948
llvm::AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer
AMDGPUTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Definition AMDGPUTargetStreamer.cpp:671
llvm::AMDGPUTargetELFStreamer::emitAMDGPULDS
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
Definition AMDGPUTargetStreamer.cpp:907
llvm::AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const AMDGPU::MCKernelDescriptor &KernelDescriptor, const MCExpr *NextVGPR, const MCExpr *NextSGPR, const MCExpr *ReserveVCC, const MCExpr *ReserveFlatScr) override
Definition AMDGPUTargetStreamer.cpp:1001
llvm::AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
Definition AMDGPUTargetStreamer.cpp:900
llvm::AMDGPUTargetStreamer::EmitHSAMetadata
virtual bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict)
Emit HSA Metadata.
Definition AMDGPUTargetStreamer.h:88
llvm::AMDGPUTargetStreamer::getPALMetadata
AMDGPUPALMetadata * getPALMetadata()
Definition AMDGPUTargetStreamer.h:48
llvm::AMDGPUTargetStreamer::EmitDirectiveAMDHSACodeObjectVersion
virtual void EmitDirectiveAMDHSACodeObjectVersion(unsigned COV)
Definition AMDGPUTargetStreamer.h:52
llvm::AMDGPUTargetStreamer::EmitHSAMetadataV3
virtual bool EmitHSAMetadataV3(StringRef HSAMetadataString)
Definition AMDGPUTargetStreamer.cpp:47
llvm::AMDGPUTargetStreamer::getElfMach
static unsigned getElfMach(StringRef GPU)
Definition AMDGPUTargetStreamer.cpp:144
llvm::AMDGPUTargetStreamer::getArchNameFromElfMach
static StringRef getArchNameFromElfMach(unsigned ElfMach)
Definition AMDGPUTargetStreamer.cpp:54
llvm::AMDGPUTargetStreamer::getTargetID
const std::optional< AMDGPU::IsaInfo::AMDGPUTargetID > & getTargetID() const
Definition AMDGPUTargetStreamer.h:110
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition MCAsmInfo.h:64
llvm::MCBinaryExpr::createAdd
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx, SMLoc Loc=SMLoc())
Definition MCExpr.h:343
llvm::MCBinaryExpr::createMul
static const MCBinaryExpr * createMul(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition MCExpr.h:398
llvm::MCBinaryExpr::createSub
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition MCExpr.h:428
llvm::MCConstantExpr::create
static LLVM_ABI const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition MCExpr.cpp:212
llvm::MCContext::getAsmInfo
const MCAsmInfo * getAsmInfo() const
Definition MCContext.h:412
llvm::MCContext::getOrCreateSymbol
LLVM_ABI MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition MCContext.cpp:203
llvm::MCELFStreamer::getWriter
ELFObjectWriter & getWriter()
Definition MCELFStreamer.cpp:48
llvm::MCELFStreamer::emitLabel
void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc()) override
Emit a label for Symbol into the current section.
Definition MCELFStreamer.cpp:59
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition MCExpr.h:34
llvm::MCObjectStreamer::emitBytes
void emitBytes(StringRef Data) override
Emit the bytes in Data into the output.
Definition MCObjectStreamer.cpp:666
llvm::MCStreamer
Streaming machine code generation interface.
Definition MCStreamer.h:221
llvm::MCStreamer::popSection
virtual bool popSection()
Restore the current and previous section from the section stack.
Definition MCStreamer.cpp:1364
llvm::MCStreamer::getContext
MCContext & getContext() const
Definition MCStreamer.h:322
llvm::MCStreamer::emitValueToAlignment
virtual void emitValueToAlignment(Align Alignment, int64_t Fill=0, uint8_t FillLen=1, unsigned MaxBytesToEmit=0)
Emit some number of copies of Value until the byte alignment ByteAlignment is reached.
Definition MCStreamer.cpp:1356
llvm::MCStreamer::pushSection
void pushSection()
Save the current and previous section on the section stack.
Definition MCStreamer.h:449
llvm::MCStreamer::emitInt32
void emitInt32(uint64_t Value)
Definition MCStreamer.h:756
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition MCSubtargetInfo.h:77
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition MCSubtargetInfo.h:122
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition MCSubtargetInfo.h:111
llvm::MCSubtargetInfo::getCPU
StringRef getCPU() const
Definition MCSubtargetInfo.h:112
llvm::MCSymbolELF::setBinding
void setBinding(unsigned Binding) const
Definition MCSymbolELF.cpp:43
llvm::MCSymbolELF::setType
void setType(unsigned Type) const
Definition MCSymbolELF.cpp:92
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx, SMLoc Loc=SMLoc())
Definition MCExpr.h:214
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition MCSymbol.h:42
llvm::SmallString
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition SmallString.h:26
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
llvm::Triple::getArch
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition Triple.h:427
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition Twine.h:82
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition Type.h:46
llvm::Value
LLVM Value Representation.
Definition Value.h:75
llvm::formatted_raw_ostream
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
Definition FormattedStream.h:31
llvm::function_ref
An efficient, type-erasing, non-owning reference to a callable.
Definition STLFunctionalExtras.h:37
llvm::msgpack::Document
Simple in-memory representation of a document of msgpack objects with ability to find and create arra...
Definition MsgPackDocument.h:293
llvm::msgpack::Document::getRoot
DocNode & getRoot()
Get ref to the document's root element.
Definition MsgPackDocument.h:317
llvm::msgpack::Document::toYAML
LLVM_ABI void toYAML(raw_ostream &OS)
Convert MsgPack Document to YAML text.
Definition MsgPackDocumentYAML.cpp:247
llvm::msgpack::Document::writeToBlob
LLVM_ABI void writeToBlob(std::string &Blob)
Write a MsgPack document to a binary MsgPack blob.
Definition MsgPackDocument.cpp:355
llvm::msgpack::Document::fromYAML
LLVM_ABI bool fromYAML(StringRef S)
Read YAML text into the MsgPack document. Returns false on failure.
Definition MsgPackDocumentYAML.cpp:253
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition raw_ostream.h:662
llvm::raw_string_ostream::str
std::string & str()
Returns the string's reference.
Definition raw_ostream.h:680
llvm::raw_svector_ostream
A raw_ostream that writes to an SmallVector or SmallString.
Definition raw_ostream.h:692
llvm::raw_svector_ostream::str
StringRef str() const
Return a StringRef for the vector contents.
Definition raw_ostream.h:721
uint32_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm::AMDGPU::ElfNote::NoteNameV2
const char NoteNameV2[]
Definition AMDGPUPTNote.h:26
llvm::AMDGPU::ElfNote::SectionName
const char SectionName[]
Definition AMDGPUPTNote.h:24
llvm::AMDGPU::ElfNote::NoteNameV3
const char NoteNameV3[]
Definition AMDGPUPTNote.h:27
llvm::AMDGPU::GenericVersion::GFX12_5
static constexpr unsigned GFX12_5
Definition AMDGPUBaseInfo.h:61
llvm::AMDGPU::GenericVersion::GFX9_4
static constexpr unsigned GFX9_4
Definition AMDGPUBaseInfo.h:56
llvm::AMDGPU::GenericVersion::GFX10_1
static constexpr unsigned GFX10_1
Definition AMDGPUBaseInfo.h:57
llvm::AMDGPU::GenericVersion::GFX10_3
static constexpr unsigned GFX10_3
Definition AMDGPUBaseInfo.h:58
llvm::AMDGPU::GenericVersion::GFX11
static constexpr unsigned GFX11
Definition AMDGPUBaseInfo.h:59
llvm::AMDGPU::GenericVersion::GFX9
static constexpr unsigned GFX9
Definition AMDGPUBaseInfo.h:55
llvm::AMDGPU::GenericVersion::GFX12
static constexpr unsigned GFX12
Definition AMDGPUBaseInfo.h:60
llvm::AMDGPU::HSAMD::V3::AssemblerDirectiveBegin
constexpr char AssemblerDirectiveBegin[]
HSA metadata beginning assembler directive.
Definition AMDGPUMetadata.h:466
llvm::AMDGPU::HSAMD::V3::AssemblerDirectiveEnd
constexpr char AssemblerDirectiveEnd[]
HSA metadata ending assembler directive.
Definition AMDGPUMetadata.h:468
llvm::AMDGPU::getArchNameR600
LLVM_ABI StringRef getArchNameR600(GPUKind AK)
Definition TargetParser.cpp:92
llvm::AMDGPU::GPUKind
GPUKind
GPU kinds supported by the AMDGPU target.
Definition TargetParser.h:38
llvm::AMDGPU::printAMDGPUMCExpr
void printAMDGPUMCExpr(const MCExpr *Expr, raw_ostream &OS, const MCAsmInfo *MAI)
Definition AMDGPUMCExpr.cpp:695
llvm::AMDGPU::isHsaAbi
bool isHsaAbi(const MCSubtargetInfo &STI)
Definition AMDGPUBaseInfo.cpp:244
llvm::AMDGPU::getIsaVersion
LLVM_ABI IsaVersion getIsaVersion(StringRef GPU)
Definition TargetParser.cpp:158
llvm::AMDGPU::isGFX90A
bool isGFX90A(const MCSubtargetInfo &STI)
Definition AMDGPUBaseInfo.cpp:2744
llvm::AMDGPU::parseArchAMDGCN
LLVM_ABI GPUKind parseArchAMDGCN(StringRef CPU)
Definition TargetParser.cpp:103
llvm::AMDGPU::hasArchitectedFlatScratch
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
Definition AMDGPUBaseInfo.cpp:2752
llvm::AMDGPU::isGFX11Plus
bool isGFX11Plus(const MCSubtargetInfo &STI)
Definition AMDGPUBaseInfo.cpp:2680
llvm::AMDGPU::foldAMDGPUMCExpr
const MCExpr * foldAMDGPUMCExpr(const MCExpr *Expr, MCContext &Ctx)
Definition AMDGPUMCExpr.cpp:686
llvm::AMDGPU::getArchNameAMDGCN
LLVM_ABI StringRef getArchNameAMDGCN(GPUKind AK)
Definition TargetParser.cpp:81
llvm::AMDGPU::hasKernargPreload
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
Definition AMDGPUBaseInfo.cpp:2768
llvm::AMDGPU::supportsWGP
bool supportsWGP(const MCSubtargetInfo &STI)
Definition AMDGPUBaseInfo.cpp:2708
llvm::AMDGPU::isGFX1250Plus
bool isGFX1250Plus(const MCSubtargetInfo &STI)
Definition AMDGPUBaseInfo.cpp:2698
llvm::AMDGPU::getELFABIVersion
uint8_t getELFABIVersion(const Triple &T, unsigned CodeObjectVersion)
Definition AMDGPUBaseInfo.cpp:274
llvm::AMDGPU::parseArchR600
LLVM_ABI GPUKind parseArchR600(StringRef CPU)
Definition TargetParser.cpp:111
llvm::ELF::NT_AMDGPU_METADATA
@ NT_AMDGPU_METADATA
Definition ELF.h:1987
llvm::ELF::SHN_AMDGPU_LDS
@ SHN_AMDGPU_LDS
Definition ELF.h:1970
llvm::ELF::SHF_ALLOC
@ SHF_ALLOC
Definition ELF.h:1249
llvm::ELF::SHT_NOTE
@ SHT_NOTE
Definition ELF.h:1154
llvm::ELF::STB_GLOBAL
@ STB_GLOBAL
Definition ELF.h:1406
llvm::ELF::STT_AMDGPU_HSA_KERNEL
@ STT_AMDGPU_HSA_KERNEL
Definition ELF.h:1431
llvm::ELF::STT_OBJECT
@ STT_OBJECT
Definition ELF.h:1418
llvm::ELF::EF_AMDGPU_GENERIC_VERSION_MAX
@ EF_AMDGPU_GENERIC_VERSION_MAX
Definition ELF.h:925
llvm::ELF::EF_AMDGPU_FEATURE_XNACK_ANY_V4
@ EF_AMDGPU_FEATURE_XNACK_ANY_V4
Definition ELF.h:902
llvm::ELF::EF_AMDGPU_FEATURE_SRAMECC_V3
@ EF_AMDGPU_FEATURE_SRAMECC_V3
Definition ELF.h:893
llvm::ELF::EF_AMDGPU_GENERIC_VERSION_OFFSET
@ EF_AMDGPU_GENERIC_VERSION_OFFSET
Definition ELF.h:923
llvm::ELF::EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4
@ EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4
Definition ELF.h:913
llvm::ELF::EF_AMDGPU_FEATURE_SRAMECC_OFF_V4
@ EF_AMDGPU_FEATURE_SRAMECC_OFF_V4
Definition ELF.h:917
llvm::ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4
@ EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4
Definition ELF.h:900
llvm::ELF::EF_AMDGPU_FEATURE_XNACK_OFF_V4
@ EF_AMDGPU_FEATURE_XNACK_OFF_V4
Definition ELF.h:904
llvm::ELF::EF_AMDGPU_FEATURE_XNACK_V3
@ EF_AMDGPU_FEATURE_XNACK_V3
Definition ELF.h:888
llvm::ELF::EF_AMDGPU_FEATURE_XNACK_ON_V4
@ EF_AMDGPU_FEATURE_XNACK_ON_V4
Definition ELF.h:906
llvm::ELF::EF_AMDGPU_MACH_NONE
@ EF_AMDGPU_MACH_NONE
Definition ELF.h:849
llvm::ELF::EF_AMDGPU_FEATURE_SRAMECC_ANY_V4
@ EF_AMDGPU_FEATURE_SRAMECC_ANY_V4
Definition ELF.h:915
llvm::ELF::EF_AMDGPU_FEATURE_SRAMECC_ON_V4
@ EF_AMDGPU_FEATURE_SRAMECC_ON_V4
Definition ELF.h:919
llvm::ELF::NT_AMD_HSA_ISA_NAME
@ NT_AMD_HSA_ISA_NAME
Definition ELF.h:1980
llvm::ELF::STV_PROTECTED
@ STV_PROTECTED
Definition ELF.h:1438
llvm::ELF::STV_DEFAULT
@ STV_DEFAULT
Definition ELF.h:1435
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition CommandLine.h:444
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition FunctionInfo.h:25
llvm::Version
FunctionAddr VTableAddr uintptr_t uintptr_t Version
Definition InstrProf.h:334
llvm::report_fatal_error
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
Definition Error.cpp:163
llvm::AMDGPU::IsaVersion
Instruction set architecture version.
Definition TargetParser.h:51
llvm::AMDGPU::MCKernelDescriptor::bits_get
static const MCExpr * bits_get(const MCExpr *Src, uint32_t Shift, uint32_t Mask, MCContext &Ctx)
Definition AMDGPUMCKernelDescriptor.cpp:97
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition Alignment.h:39
llvm::Align::value
constexpr uint64_t value() const
This is a hole in the type system and should not be abused.
Definition Alignment.h:77
llvm::amdhsa::kernel_descriptor_t
Definition AMDHSAKernelDescriptor.h:267
llvm::amdhsa::kernel_descriptor_t::group_segment_fixed_size
uint32_t group_segment_fixed_size
Definition AMDHSAKernelDescriptor.h:268
llvm::amdhsa::kernel_descriptor_t::reserved3
uint8_t reserved3[4]
Definition AMDHSAKernelDescriptor.h:279
llvm::amdhsa::kernel_descriptor_t::reserved1
uint8_t reserved1[20]
Definition AMDHSAKernelDescriptor.h:273
llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc1
uint32_t compute_pgm_rsrc1
Definition AMDHSAKernelDescriptor.h:275
llvm::amdhsa::kernel_descriptor_t::private_segment_fixed_size
uint32_t private_segment_fixed_size
Definition AMDHSAKernelDescriptor.h:269
llvm::amdhsa::kernel_descriptor_t::kernarg_size
uint32_t kernarg_size
Definition AMDHSAKernelDescriptor.h:270
llvm::amdhsa::kernel_descriptor_t::kernarg_preload
uint16_t kernarg_preload
Definition AMDHSAKernelDescriptor.h:278
llvm::amdhsa::kernel_descriptor_t::reserved0
uint8_t reserved0[4]
Definition AMDHSAKernelDescriptor.h:271
llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc2
uint32_t compute_pgm_rsrc2
Definition AMDHSAKernelDescriptor.h:276
llvm::amdhsa::kernel_descriptor_t::kernel_code_properties
uint16_t kernel_code_properties
Definition AMDHSAKernelDescriptor.h:277
llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc3
uint32_t compute_pgm_rsrc3
Definition AMDHSAKernelDescriptor.h:274
llvm::amdhsa::kernel_descriptor_t::kernel_code_entry_byte_offset
int64_t kernel_code_entry_byte_offset
Definition AMDHSAKernelDescriptor.h:272
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