35#define DEBUG_TYPE "ppc-subtarget"
37#define GET_SUBTARGETINFO_TARGET_DESC
38#define GET_SUBTARGETINFO_CTOR
39#include "PPCGenSubtargetInfo.inc"
43 cl::desc(
"Enable Machine Pipeliner for PPC"),
49 initializeEnvironment();
50 initSubtargetFeatures(CPU, TuneCPU, FS);
61 TSInfo = std::make_unique<PPCSelectionDAGInfo>();
77void PPCSubtarget::initializeEnvironment() {
86 std::string CPUName = std::string(CPU);
87 if (CPUName.empty() || CPU ==
"generic") {
95 if (TuneCPU.
empty()) TuneCPU = CPUName;
105 if (IsPPC64 && has64BitSupport())
108 if (getTargetTriple().isPPC32SecurePlt())
111 if (HasSPE && IsPPC64)
113 if (HasSPE && (HasAltivec || HasVSX || HasFPU))
115 "SPE and traditional floating point cannot both be enabled.\n",
false);
126 if (HasAIXSmallLocalExecTLS || HasAIXSmallLocalDynamicTLS) {
127 if (!getTargetTriple().isOSAIX() || !IsPPC64)
129 "only supported on AIX in "
137 if (!
TM.getDataSections())
139 "only be specified with "
144 if (HasAIXShLibTLSModelOpt && (!getTargetTriple().isOSAIX() || !IsPPC64))
146 "is only supported on AIX in 64-bit mode.\n",
149 if (UsePointerGlueHelper && !getTargetTriple().isOSAIX())
166 return TargetSubtargetInfo::ANTIDEP_ALL;
170 CriticalPathRCs.clear();
171 CriticalPathRCs.push_back(isPPC64() ?
172 &PPC::G8RCRegClass : &PPC::GPRCRegClass);
198 return !GVar->hasAttribute(
"toc-data");
207 if (
TM.shouldAssumeDSOLocal(GV))
224 assert(GV &&
"Unexpected NULL GlobalValue");
241 std::optional<CodeModel::Model> MaybeCodeModel = GlobalVar->getCodeModel();
242 if (MaybeCodeModel) {
245 "invalid code model for AIX");
255 return isPPC64() && hasPCRelativeMemops() &&
isELFv2ABI() &&
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
static cl::opt< bool > EnableMachinePipeliner("aarch64-enable-pipeliner", cl::desc("Enable Machine Pipeliner for AArch64"), cl::init(false), cl::Hidden)
This file describes how to lower LLVM calls to machine code calls.
This file declares the targeting of the Machinelegalizer class for PowerPC.
This file declares the targeting of the RegisterBankInfo class for PowerPC.
static cl::opt< bool > EnableMachinePipeliner("ppc-enable-pipeliner", cl::desc("Enable Machine Pipeliner for PPC"), cl::init(false), cl::Hidden)
LLVM_ABI const GlobalObject * getAliaseeObject() const
This class provides the information for the PowerPC target legalizer for GlobalISel.
std::unique_ptr< InstructionSelector > InstSelector
bool enableMachinePipeliner() const override
Pipeliner customization.
bool useDFAforSMS() const override
Machine Pipeliner customization.
std::unique_ptr< LegalizerInfo > Legalizer
PPCSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, const PPCTargetMachine &TM)
This constructor initializes the data members to match that of the specified triple.
PPCFrameLowering FrameLowering
const CallLowering * getCallLowering() const override
const LegalizerInfo * getLegalizerInfo() const override
std::unique_ptr< RegisterBankInfo > RegBankInfo
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Align StackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override
bool isUsingPCRelativeCalls() const
bool enableSubRegLiveness() const override
const PPCTargetLowering * getTargetLowering() const override
InstructionSelector * getInstructionSelector() const override
unsigned CPUDirective
Which cpu directive was used.
AntiDepBreakMode getAntiDepBreakMode() const override
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
bool useAA() const override
PPCABI TargetABI
The selected ABI variant.
PPCSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef TuneCPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU, a TuneCPU, and feature string so that we c...
CodeModel::Model getCodeModel(const TargetMachine &TM, const GlobalValue *GV) const
Calculates the effective code model for argument GV.
Align getPlatformStackAlignment() const
const PPCTargetMachine & getTargetMachine() const
const PPCTargetMachine & TM
std::unique_ptr< const SelectionDAGTargetInfo > TSInfo
bool enableMachineScheduler() const override
Scheduling customization.
void overrideSchedPolicy(MachineSchedPolicy &Policy, const SchedRegion &Region) const override
const RegisterBankInfo * getRegBankInfo() const override
const PPCRegisterInfo * getRegisterInfo() const override
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
bool enablePostRAScheduler() const override
This overrides the PostRAScheduler bit in the SchedModel for each CPU.
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
Common code between 32-bit and 64-bit PowerPC targets.
Holds all the information related to register banks.
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
Represent a constant reference to a string, i.e.
constexpr bool empty() const
Check if the string is empty.
Primary interface to the complete machine description for the target machine.
CodeModel::Model getCodeModel() const
Returns the code model.
Triple - Helper class for working with autoconf configuration names.
LLVM_ABI StringRef getNormalizedPPCTargetCPU(const Triple &T, StringRef CPUName="")
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
InstructionSelector * createPPCInstructionSelector(const PPCTargetMachine &TM, const PPCSubtarget &Subtarget, const PPCRegisterBankInfo &RBI)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
A region of an MBB for scheduling.