LLVM 24.0.0git
PPCSubtarget.cpp
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1//===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the PPC specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPCSubtarget.h"
17#include "PPC.h"
18#include "PPCRegisterInfo.h"
19#include "PPCSelectionDAGInfo.h"
20#include "PPCTargetMachine.h"
25#include "llvm/IR/GlobalAlias.h"
26#include "llvm/IR/GlobalValue.h"
32
33using namespace llvm;
34
35#define DEBUG_TYPE "ppc-subtarget"
36
37#define GET_SUBTARGETINFO_TARGET_DESC
38#define GET_SUBTARGETINFO_CTOR
39#include "PPCGenSubtargetInfo.inc"
40
41static cl::opt<bool>
42 EnableMachinePipeliner("ppc-enable-pipeliner",
43 cl::desc("Enable Machine Pipeliner for PPC"),
44 cl::init(false), cl::Hidden);
45
47 StringRef TuneCPU,
48 StringRef FS) {
49 initializeEnvironment();
50 initSubtargetFeatures(CPU, TuneCPU, FS);
51 return *this;
52}
53
55 StringRef FS, StringRef ABIName,
56 const PPCTargetMachine &TM)
57 : PPCGenSubtargetInfo(TT, CPU, TuneCPU, FS),
58 TargetABI(PPCTargetMachine::computeABI(TT, ABIName)), TM(TM),
60 InstrInfo(*this), TLInfo(TM, *this) {
61 TSInfo = std::make_unique<PPCSelectionDAGInfo>();
62
64 Legalizer.reset(new PPCLegalizerInfo(*this));
65 auto *RBI = new PPCRegisterBankInfo(*getRegisterInfo());
66 RegBankInfo.reset(RBI);
67
68 InstSelector.reset(createPPCInstructionSelector(TM, *this, *RBI));
69}
70
72
76
77void PPCSubtarget::initializeEnvironment() {
81}
82
83void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU,
84 StringRef FS) {
85 // Determine default and user specified characteristics
86 std::string CPUName = std::string(CPU);
87 if (CPUName.empty() || CPU == "generic") {
88 if (getTargetTriple().getSubArch() == Triple::PPCSubArch_spe)
89 CPUName = "e500";
90 else
91 CPUName = std::string(PPC::getNormalizedPPCTargetCPU(getTargetTriple()));
92 }
93
94 // Determine the CPU to schedule for.
95 if (TuneCPU.empty()) TuneCPU = CPUName;
96
97 // Initialize scheduling itinerary for the specified CPU.
98 InstrItins = getInstrItineraryForCPU(CPUName);
99
100 // Parse features string.
101 ParseSubtargetFeatures(CPUName, TuneCPU, FS);
102
103 // If the user requested use of 64-bit regs, but the cpu selected doesn't
104 // support it, ignore.
105 if (IsPPC64 && has64BitSupport())
106 Use64BitRegs = true;
107
108 if (getTargetTriple().isPPC32SecurePlt())
109 IsSecurePlt = true;
110
111 if (HasSPE && IsPPC64)
112 report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
113 if (HasSPE && (HasAltivec || HasVSX || HasFPU))
115 "SPE and traditional floating point cannot both be enabled.\n", false);
116
117 // If not SPE, set standard FPU
118 if (!HasSPE)
119 HasFPU = true;
120
122
123 // Determine endianness.
124 IsLittleEndian = TM.isLittleEndian();
125
126 if (HasAIXSmallLocalExecTLS || HasAIXSmallLocalDynamicTLS) {
127 if (!getTargetTriple().isOSAIX() || !IsPPC64)
128 report_fatal_error("The aix-small-local-[exec|dynamic]-tls attribute is "
129 "only supported on AIX in "
130 "64-bit mode.\n",
131 false);
132 // The aix-small-local-[exec|dynamic]-tls attribute should only be used with
133 // -data-sections, as having data sections turned off with this option
134 // is not ideal for performance. Moreover, the
135 // small-local-[exec|dynamic]-tls region is a limited resource, and should
136 // not be used for variables that may be replaced.
137 if (!TM.getDataSections())
138 report_fatal_error("The aix-small-local-[exec|dynamic]-tls attribute can "
139 "only be specified with "
140 "-data-sections.\n",
141 false);
142 }
143
144 if (HasAIXShLibTLSModelOpt && (!getTargetTriple().isOSAIX() || !IsPPC64))
145 report_fatal_error("The aix-shared-lib-tls-model-opt attribute "
146 "is only supported on AIX in 64-bit mode.\n",
147 false);
148
149 if (UsePointerGlueHelper && !getTargetTriple().isOSAIX())
150 report_fatal_error("use-ptrgl-helper feature is only supported on AIX\n",
151 false);
152}
153
154bool PPCSubtarget::enableMachineScheduler() const { return true; }
155
157 return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner;
158}
159
160bool PPCSubtarget::useDFAforSMS() const { return false; }
161
162// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
163bool PPCSubtarget::enablePostRAScheduler() const { return true; }
164
165PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
166 return TargetSubtargetInfo::ANTIDEP_ALL;
167}
168
169void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
170 CriticalPathRCs.clear();
171 CriticalPathRCs.push_back(isPPC64() ?
172 &PPC::G8RCRegClass : &PPC::GPRCRegClass);
173}
174
176 const SchedRegion &Region) const {
177 // The GenericScheduler that we use defaults to scheduling bottom up only.
178 // We want to schedule from both the top and the bottom and so we set
179 // OnlyBottomUp to false.
180 // We want to do bi-directional scheduling since it provides a more balanced
181 // schedule leading to better performance.
182 Policy.OnlyBottomUp = false;
183 // Spilling is generally expensive on all PPC cores, so always enable
184 // register-pressure tracking.
185 Policy.ShouldTrackPressure = true;
186}
187
189 return true;
190}
191
192bool PPCSubtarget::enableSubRegLiveness() const { return true; }
193
195 if (isAIXABI()) {
196 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
197 // On AIX the only symbols that aren't indirect are toc-data.
198 return !GVar->hasAttribute("toc-data");
199
200 return true;
201 }
202
203 // Large code model always uses the TOC even for local symbols.
204 if (TM.getCodeModel() == CodeModel::Large)
205 return true;
206
207 if (TM.shouldAssumeDSOLocal(GV))
208 return false;
209 return true;
210}
211
213 const GlobalValue *GV) const {
214 // If there isn't an attribute to override the module code model
215 // this will be the effective code model.
216 CodeModel::Model ModuleModel = TM.getCodeModel();
217
218 // Initially support per global code model for AIX only.
219 if (!isAIXABI())
220 return ModuleModel;
221
222 // Only GlobalVariables carry an attribute which can override the module code
223 // model.
224 assert(GV && "Unexpected NULL GlobalValue");
225 const GlobalVariable *GlobalVar =
226 [](const GlobalValue *GV) -> const GlobalVariable * {
228 if (Var)
229 return Var;
230
231 const GlobalAlias *Alias = dyn_cast<GlobalAlias>(GV);
232 if (Alias)
234
235 return nullptr;
236 }(GV);
237
238 if (!GlobalVar)
239 return ModuleModel;
240
241 std::optional<CodeModel::Model> MaybeCodeModel = GlobalVar->getCodeModel();
242 if (MaybeCodeModel) {
243 CodeModel::Model CM = *MaybeCodeModel;
244 assert((CM == CodeModel::Small || CM == CodeModel::Large) &&
245 "invalid code model for AIX");
246 return CM;
247 }
248
249 return ModuleModel;
250}
251
253
255 return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() &&
257}
258
259// GlobalISEL
261 return CallLoweringInfo.get();
262}
263
265 return RegBankInfo.get();
266}
267
269 return Legalizer.get();
270}
271
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
static cl::opt< bool > EnableMachinePipeliner("aarch64-enable-pipeliner", cl::desc("Enable Machine Pipeliner for AArch64"), cl::init(false), cl::Hidden)
This file describes how to lower LLVM calls to machine code calls.
This file declares the targeting of the Machinelegalizer class for PowerPC.
This file declares the targeting of the RegisterBankInfo class for PowerPC.
static cl::opt< bool > EnableMachinePipeliner("ppc-enable-pipeliner", cl::desc("Enable Machine Pipeliner for PPC"), cl::init(false), cl::Hidden)
LLVM_ABI const GlobalObject * getAliaseeObject() const
Definition Globals.cpp:730
This class provides the information for the PowerPC target legalizer for GlobalISel.
std::unique_ptr< InstructionSelector > InstSelector
bool enableMachinePipeliner() const override
Pipeliner customization.
bool useDFAforSMS() const override
Machine Pipeliner customization.
std::unique_ptr< LegalizerInfo > Legalizer
PPCTargetLowering TLInfo
PPCSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, const PPCTargetMachine &TM)
This constructor initializes the data members to match that of the specified triple.
PPCFrameLowering FrameLowering
bool isAIXABI() const
const CallLowering * getCallLowering() const override
const LegalizerInfo * getLegalizerInfo() const override
std::unique_ptr< RegisterBankInfo > RegBankInfo
~PPCSubtarget() override
POPCNTDKind HasPOPCNTD
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Align StackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
PPCInstrInfo InstrInfo
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override
bool isUsingPCRelativeCalls() const
bool enableSubRegLiveness() const override
const PPCTargetLowering * getTargetLowering() const override
InstructionSelector * getInstructionSelector() const override
unsigned CPUDirective
Which cpu directive was used.
AntiDepBreakMode getAntiDepBreakMode() const override
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
bool useAA() const override
PPCABI TargetABI
The selected ABI variant.
PPCSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef TuneCPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU, a TuneCPU, and feature string so that we c...
CodeModel::Model getCodeModel(const TargetMachine &TM, const GlobalValue *GV) const
Calculates the effective code model for argument GV.
bool isELFv2ABI() const
Align getPlatformStackAlignment() const
const PPCTargetMachine & getTargetMachine() const
const PPCTargetMachine & TM
std::unique_ptr< const SelectionDAGTargetInfo > TSInfo
bool enableMachineScheduler() const override
Scheduling customization.
void overrideSchedPolicy(MachineSchedPolicy &Policy, const SchedRegion &Region) const override
const RegisterBankInfo * getRegBankInfo() const override
const PPCRegisterInfo * getRegisterInfo() const override
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
bool enablePostRAScheduler() const override
This overrides the PostRAScheduler bit in the SchedModel for each CPU.
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
Common code between 32-bit and 64-bit PowerPC targets.
Holds all the information related to register banks.
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
Represent a constant reference to a string, i.e.
Definition StringRef.h:56
constexpr bool empty() const
Check if the string is empty.
Definition StringRef.h:141
Primary interface to the complete machine description for the target machine.
CodeModel::Model getCodeModel() const
Returns the code model.
Triple - Helper class for working with autoconf configuration names.
Definition Triple.h:48
@ PPCSubArch_spe
Definition Triple.h:172
LLVM_ABI StringRef getNormalizedPPCTargetCPU(const Triple &T, StringRef CPUName="")
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:643
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
Definition Error.cpp:163
InstructionSelector * createPPCInstructionSelector(const PPCTargetMachine &TM, const PPCSubtarget &Subtarget, const PPCRegisterBankInfo &RBI)
@ PPC_ABI_ELFv2
Definition PPC.h:106
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition Alignment.h:39
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
A region of an MBB for scheduling.