llvm::AArch64InstrInfo Member List
This is the complete list of members for llvm::AArch64InstrInfo, including all inherited members.
| AArch64InstrInfo(const AArch64Subtarget &STI) | llvm::AArch64InstrInfo | explicit |
| analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override | llvm::AArch64InstrInfo | |
| analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify) const override | llvm::AArch64InstrInfo | |
| analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override | llvm::AArch64InstrInfo | |
| analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override | llvm::AArch64InstrInfo | |
| areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override | llvm::AArch64InstrInfo | |
| canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg, const MachineInstr &AddrI, ExtAddrMode &AM) const override | llvm::AArch64InstrInfo | |
| canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override | llvm::AArch64InstrInfo | |
| convertToFlagSettingOpc(unsigned Opc) | llvm::AArch64InstrInfo | static |
| copyGPRRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, unsigned Opcode, unsigned ZeroReg, llvm::ArrayRef< unsigned > Indices) const | llvm::AArch64InstrInfo | |
| copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override | llvm::AArch64InstrInfo | |
| copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const | llvm::AArch64InstrInfo | |
| emitLdStWithAddr(MachineInstr &MemI, const ExtAddrMode &AM) const override | llvm::AArch64InstrInfo | |
| foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override | llvm::AArch64InstrInfo | |
| foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const | llvm::AArch64InstrInfo | inline |
| getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override | llvm::AArch64InstrInfo | |
| getBranchDestBlock(const MachineInstr &MI) const override | llvm::AArch64InstrInfo | |
| getCombinerObjective(unsigned Pattern) const override | llvm::AArch64InstrInfo | |
| getInstSizeInBytes(const MachineInstr &MI) const override | llvm::AArch64InstrInfo | |
| getLdStAmountOp(const MachineInstr &MI) | llvm::AArch64InstrInfo | static |
| getLdStBaseOp(const MachineInstr &MI) | llvm::AArch64InstrInfo | static |
| getLdStOffsetOp(const MachineInstr &MI) | llvm::AArch64InstrInfo | static |
| getLoadStoreImmIdx(unsigned Opc) | llvm::AArch64InstrInfo | static |
| getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const | llvm::AArch64InstrInfo | |
| getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override | llvm::AArch64InstrInfo | |
| getMemOperandWithOffsetWidth(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, TypeSize &Width, const TargetRegisterInfo *TRI) const | llvm::AArch64InstrInfo | |
| getMemOpInfo(unsigned Opcode, TypeSize &Scale, TypeSize &Width, int64_t &MinOffset, int64_t &MaxOffset) | llvm::AArch64InstrInfo | static |
| getMemScale(unsigned Opc) | llvm::AArch64InstrInfo | static |
| getMemScale(const MachineInstr &MI) | llvm::AArch64InstrInfo | inlinestatic |
| getNop() const override | llvm::AArch64InstrInfo | |
| getRegisterInfo() const | llvm::AArch64InstrInfo | inline |
| getUnscaledLdSt(unsigned Opc) | llvm::AArch64InstrInfo | static |
| hasBTISemantics(const MachineInstr &MI) | llvm::AArch64InstrInfo | static |
| hasUnscaledLdStOffset(unsigned Opc) | llvm::AArch64InstrInfo | static |
| hasUnscaledLdStOffset(MachineInstr &MI) | llvm::AArch64InstrInfo | inlinestatic |
| insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override | llvm::AArch64InstrInfo | |
| insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override | llvm::AArch64InstrInfo | |
| insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override | llvm::AArch64InstrInfo | |
| insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override | llvm::AArch64InstrInfo | |
| isAsCheapAsAMove(const MachineInstr &MI) const override | llvm::AArch64InstrInfo | |
| isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override | llvm::AArch64InstrInfo | |
| isCandidateToMergeOrPair(const MachineInstr &MI) const | llvm::AArch64InstrInfo | |
| isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override | llvm::AArch64InstrInfo | |
| isCopyInstrImpl(const MachineInstr &MI) const override | llvm::AArch64InstrInfo | protected |
| isCopyLikeInstrImpl(const MachineInstr &MI) const override | llvm::AArch64InstrInfo | protected |
| isFpOrNEON(Register Reg) | llvm::AArch64InstrInfo | static |
| isFpOrNEON(const MachineInstr &MI) | llvm::AArch64InstrInfo | static |
| isFPRCopy(const MachineInstr &MI) | llvm::AArch64InstrInfo | static |
| isGPRCopy(const MachineInstr &MI) | llvm::AArch64InstrInfo | static |
| isGPRZero(const MachineInstr &MI) | llvm::AArch64InstrInfo | static |
| isHForm(const MachineInstr &MI) | llvm::AArch64InstrInfo | static |
| isLdStPairSuppressed(const MachineInstr &MI) | llvm::AArch64InstrInfo | static |
| isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override | llvm::AArch64InstrInfo | |
| isPairableLdStInst(const MachineInstr &MI) | llvm::AArch64InstrInfo | static |
| isPairedLdSt(const MachineInstr &MI) | llvm::AArch64InstrInfo | static |
| isPreLd(const MachineInstr &MI) | llvm::AArch64InstrInfo | static |
| isPreLdSt(const MachineInstr &MI) | llvm::AArch64InstrInfo | static |
| isPreSt(const MachineInstr &MI) | llvm::AArch64InstrInfo | static |
| isQForm(const MachineInstr &MI) | llvm::AArch64InstrInfo | static |
| isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override | llvm::AArch64InstrInfo | |
| isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override | llvm::AArch64InstrInfo | |
| isStridedAccess(const MachineInstr &MI) | llvm::AArch64InstrInfo | static |
| isSubregFoldable() const override | llvm::AArch64InstrInfo | inline |
| isTailCallReturnInst(const MachineInstr &MI) | llvm::AArch64InstrInfo | static |
| isThroughputPattern(unsigned Pattern) const override | llvm::AArch64InstrInfo | |
| loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override | llvm::AArch64InstrInfo | |
| optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override | llvm::AArch64InstrInfo | |
| optimizeCondBranch(MachineInstr &MI) const override | llvm::AArch64InstrInfo | |
| probedStackAlloc(MachineBasicBlock::iterator MBBI, Register TargetReg, bool FrameSetup) const | llvm::AArch64InstrInfo | |
| removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override | llvm::AArch64InstrInfo | |
| reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override | llvm::AArch64InstrInfo | |
| shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override | llvm::AArch64InstrInfo | |
| storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override | llvm::AArch64InstrInfo | |
| suppressLdStPair(MachineInstr &MI) | llvm::AArch64InstrInfo | static |
Generated on for LLVM by
1.14.0