LLVM  16.0.0git
InstructionSelectorImpl.h
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1 //===- llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file declares the API for the instruction selector.
10 /// This class is responsible for selecting machine instructions.
11 /// It's implemented by the target. It's used by the InstructionSelect pass.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
16 #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
17 
18 #include "llvm/ADT/SmallVector.h"
28 #include "llvm/IR/Constants.h"
29 #include "llvm/IR/DataLayout.h"
31 #include "llvm/Support/Debug.h"
34 #include <cassert>
35 #include <cstddef>
36 #include <cstdint>
37 
38 namespace llvm {
39 
40 /// GlobalISel PatFrag Predicates
41 enum {
46 };
47 
48 template <class TgtInstructionSelector, class PredicateBitset,
49  class ComplexMatcherMemFn, class CustomRendererFn>
51  TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State,
53  &ISelInfo,
54  const int64_t *MatchTable, const TargetInstrInfo &TII,
56  const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures,
57  CodeGenCoverage &CoverageInfo) const {
58 
59  uint64_t CurrentIdx = 0;
60  SmallVector<uint64_t, 4> OnFailResumeAt;
61 
62  // Bypass the flag check on the instruction, and only look at the MCInstrDesc.
63  bool NoFPException = !State.MIs[0]->getDesc().mayRaiseFPException();
64 
65  const uint16_t Flags = State.MIs[0]->getFlags();
66 
67  enum RejectAction { RejectAndGiveUp, RejectAndResume };
68  auto handleReject = [&]() -> RejectAction {
70  dbgs() << CurrentIdx << ": Rejected\n");
71  if (OnFailResumeAt.empty())
72  return RejectAndGiveUp;
73  CurrentIdx = OnFailResumeAt.pop_back_val();
75  dbgs() << CurrentIdx << ": Resume at " << CurrentIdx << " ("
76  << OnFailResumeAt.size() << " try-blocks remain)\n");
77  return RejectAndResume;
78  };
79 
80  auto propagateFlags = [=](NewMIVector &OutMIs) {
81  for (auto MIB : OutMIs) {
82  // Set the NoFPExcept flag when no original matched instruction could
83  // raise an FP exception, but the new instruction potentially might.
84  uint16_t MIBFlags = Flags;
85  if (NoFPException && MIB->mayRaiseFPException())
86  MIBFlags |= MachineInstr::NoFPExcept;
87  MIB.setMIFlags(MIBFlags);
88  }
89 
90  return true;
91  };
92 
93  while (true) {
94  assert(CurrentIdx != ~0u && "Invalid MatchTable index");
95  int64_t MatcherOpcode = MatchTable[CurrentIdx++];
96  switch (MatcherOpcode) {
97  case GIM_Try: {
99  dbgs() << CurrentIdx << ": Begin try-block\n");
100  OnFailResumeAt.push_back(MatchTable[CurrentIdx++]);
101  break;
102  }
103 
104  case GIM_RecordInsn: {
105  int64_t NewInsnID = MatchTable[CurrentIdx++];
106  int64_t InsnID = MatchTable[CurrentIdx++];
107  int64_t OpIdx = MatchTable[CurrentIdx++];
108 
109  // As an optimisation we require that MIs[0] is always the root. Refuse
110  // any attempt to modify it.
111  assert(NewInsnID != 0 && "Refusing to modify MIs[0]");
112 
113  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
114  if (!MO.isReg()) {
116  dbgs() << CurrentIdx << ": Not a register\n");
117  if (handleReject() == RejectAndGiveUp)
118  return false;
119  break;
120  }
123  dbgs() << CurrentIdx << ": Is a physical register\n");
124  if (handleReject() == RejectAndGiveUp)
125  return false;
126  break;
127  }
128 
129  MachineInstr *NewMI = MRI.getVRegDef(MO.getReg());
130  if ((size_t)NewInsnID < State.MIs.size())
131  State.MIs[NewInsnID] = NewMI;
132  else {
133  assert((size_t)NewInsnID == State.MIs.size() &&
134  "Expected to store MIs in order");
135  State.MIs.push_back(NewMI);
136  }
138  dbgs() << CurrentIdx << ": MIs[" << NewInsnID
139  << "] = GIM_RecordInsn(" << InsnID << ", " << OpIdx
140  << ")\n");
141  break;
142  }
143 
144  case GIM_CheckFeatures: {
145  int64_t ExpectedBitsetID = MatchTable[CurrentIdx++];
147  dbgs() << CurrentIdx
148  << ": GIM_CheckFeatures(ExpectedBitsetID="
149  << ExpectedBitsetID << ")\n");
150  if ((AvailableFeatures & ISelInfo.FeatureBitsets[ExpectedBitsetID]) !=
151  ISelInfo.FeatureBitsets[ExpectedBitsetID]) {
152  if (handleReject() == RejectAndGiveUp)
153  return false;
154  }
155  break;
156  }
157 
158  case GIM_CheckOpcode:
160  int64_t InsnID = MatchTable[CurrentIdx++];
161  int64_t Expected0 = MatchTable[CurrentIdx++];
162  int64_t Expected1 = -1;
163  if (MatcherOpcode == GIM_CheckOpcodeIsEither)
164  Expected1 = MatchTable[CurrentIdx++];
165 
166  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
167  unsigned Opcode = State.MIs[InsnID]->getOpcode();
168 
170  dbgs() << CurrentIdx << ": GIM_CheckOpcode(MIs[" << InsnID
171  << "], ExpectedOpcode=" << Expected0;
172  if (MatcherOpcode == GIM_CheckOpcodeIsEither)
173  dbgs() << " || " << Expected1;
174  dbgs() << ") // Got=" << Opcode << "\n";
175  );
176 
177  if (Opcode != Expected0 && Opcode != Expected1) {
178  if (handleReject() == RejectAndGiveUp)
179  return false;
180  }
181  break;
182  }
183  case GIM_SwitchOpcode: {
184  int64_t InsnID = MatchTable[CurrentIdx++];
185  int64_t LowerBound = MatchTable[CurrentIdx++];
186  int64_t UpperBound = MatchTable[CurrentIdx++];
187  int64_t Default = MatchTable[CurrentIdx++];
188 
189  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
190  const int64_t Opcode = State.MIs[InsnID]->getOpcode();
191 
193  dbgs() << CurrentIdx << ": GIM_SwitchOpcode(MIs[" << InsnID << "], ["
194  << LowerBound << ", " << UpperBound << "), Default=" << Default
195  << ", JumpTable...) // Got=" << Opcode << "\n";
196  });
197  if (Opcode < LowerBound || UpperBound <= Opcode) {
198  CurrentIdx = Default;
199  break;
200  }
201  CurrentIdx = MatchTable[CurrentIdx + (Opcode - LowerBound)];
202  if (!CurrentIdx) {
203  CurrentIdx = Default;
204  break;
205  }
206  OnFailResumeAt.push_back(Default);
207  break;
208  }
209 
210  case GIM_SwitchType: {
211  int64_t InsnID = MatchTable[CurrentIdx++];
212  int64_t OpIdx = MatchTable[CurrentIdx++];
213  int64_t LowerBound = MatchTable[CurrentIdx++];
214  int64_t UpperBound = MatchTable[CurrentIdx++];
215  int64_t Default = MatchTable[CurrentIdx++];
216 
217  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
218  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
219 
221  dbgs() << CurrentIdx << ": GIM_SwitchType(MIs[" << InsnID
222  << "]->getOperand(" << OpIdx << "), [" << LowerBound << ", "
223  << UpperBound << "), Default=" << Default
224  << ", JumpTable...) // Got=";
225  if (!MO.isReg())
226  dbgs() << "Not a VReg\n";
227  else
228  dbgs() << MRI.getType(MO.getReg()) << "\n";
229  });
230  if (!MO.isReg()) {
231  CurrentIdx = Default;
232  break;
233  }
234  const LLT Ty = MRI.getType(MO.getReg());
235  const auto TyI = ISelInfo.TypeIDMap.find(Ty);
236  if (TyI == ISelInfo.TypeIDMap.end()) {
237  CurrentIdx = Default;
238  break;
239  }
240  const int64_t TypeID = TyI->second;
241  if (TypeID < LowerBound || UpperBound <= TypeID) {
242  CurrentIdx = Default;
243  break;
244  }
245  CurrentIdx = MatchTable[CurrentIdx + (TypeID - LowerBound)];
246  if (!CurrentIdx) {
247  CurrentIdx = Default;
248  break;
249  }
250  OnFailResumeAt.push_back(Default);
251  break;
252  }
253 
254  case GIM_CheckNumOperands: {
255  int64_t InsnID = MatchTable[CurrentIdx++];
256  int64_t Expected = MatchTable[CurrentIdx++];
258  dbgs() << CurrentIdx << ": GIM_CheckNumOperands(MIs["
259  << InsnID << "], Expected=" << Expected << ")\n");
260  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
261  if (State.MIs[InsnID]->getNumOperands() != Expected) {
262  if (handleReject() == RejectAndGiveUp)
263  return false;
264  }
265  break;
266  }
269  int64_t InsnID = MatchTable[CurrentIdx++];
270  int64_t OpIdx = MatcherOpcode == GIM_CheckImmOperandPredicate
271  ? MatchTable[CurrentIdx++]
272  : 1;
273  int64_t Predicate = MatchTable[CurrentIdx++];
275  dbgs() << CurrentIdx << ": GIM_CheckImmPredicate(MIs["
276  << InsnID << "]->getOperand(" << OpIdx
277  << "), Predicate=" << Predicate << ")\n");
278  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
279  assert((State.MIs[InsnID]->getOperand(OpIdx).isImm() ||
280  State.MIs[InsnID]->getOperand(OpIdx).isCImm()) &&
281  "Expected immediate operand");
282  assert(Predicate > GIPFP_I64_Invalid && "Expected a valid predicate");
283  int64_t Value = 0;
284  if (State.MIs[InsnID]->getOperand(OpIdx).isCImm())
285  Value = State.MIs[InsnID]->getOperand(OpIdx).getCImm()->getSExtValue();
286  else if (State.MIs[InsnID]->getOperand(OpIdx).isImm())
287  Value = State.MIs[InsnID]->getOperand(OpIdx).getImm();
288  else
289  llvm_unreachable("Expected Imm or CImm operand");
290 
292  if (handleReject() == RejectAndGiveUp)
293  return false;
294  break;
295  }
297  int64_t InsnID = MatchTable[CurrentIdx++];
298  int64_t Predicate = MatchTable[CurrentIdx++];
300  dbgs()
301  << CurrentIdx << ": GIM_CheckAPIntImmPredicate(MIs["
302  << InsnID << "], Predicate=" << Predicate << ")\n");
303  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
304  assert(State.MIs[InsnID]->getOpcode() == TargetOpcode::G_CONSTANT &&
305  "Expected G_CONSTANT");
306  assert(Predicate > GIPFP_APInt_Invalid && "Expected a valid predicate");
307  APInt Value;
308  if (State.MIs[InsnID]->getOperand(1).isCImm())
309  Value = State.MIs[InsnID]->getOperand(1).getCImm()->getValue();
310  else
311  llvm_unreachable("Expected Imm or CImm operand");
312 
314  if (handleReject() == RejectAndGiveUp)
315  return false;
316  break;
317  }
319  int64_t InsnID = MatchTable[CurrentIdx++];
320  int64_t Predicate = MatchTable[CurrentIdx++];
322  dbgs()
323  << CurrentIdx << ": GIM_CheckAPFloatImmPredicate(MIs["
324  << InsnID << "], Predicate=" << Predicate << ")\n");
325  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
326  assert(State.MIs[InsnID]->getOpcode() == TargetOpcode::G_FCONSTANT &&
327  "Expected G_FCONSTANT");
328  assert(State.MIs[InsnID]->getOperand(1).isFPImm() && "Expected FPImm operand");
329  assert(Predicate > GIPFP_APFloat_Invalid && "Expected a valid predicate");
330  APFloat Value = State.MIs[InsnID]->getOperand(1).getFPImm()->getValueAPF();
331 
333  if (handleReject() == RejectAndGiveUp)
334  return false;
335  break;
336  }
339  int64_t InsnID = MatchTable[CurrentIdx++];
340 
342  dbgs() << CurrentIdx
343  << ": GIM_CheckBuildVectorAll{Zeros|Ones}(MIs["
344  << InsnID << "])\n");
345  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
346 
347  const MachineInstr *MI = State.MIs[InsnID];
348  assert((MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR ||
349  MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR_TRUNC) &&
350  "Expected G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC");
351 
352  if (MatcherOpcode == GIM_CheckIsBuildVectorAllOnes) {
353  if (!isBuildVectorAllOnes(*MI, MRI)) {
354  if (handleReject() == RejectAndGiveUp)
355  return false;
356  }
357  } else {
358  if (!isBuildVectorAllZeros(*MI, MRI)) {
359  if (handleReject() == RejectAndGiveUp)
360  return false;
361  }
362  }
363 
364  break;
365  }
367  int64_t InsnID = MatchTable[CurrentIdx++];
368  int64_t Predicate = MatchTable[CurrentIdx++];
370  dbgs()
371  << CurrentIdx << ": GIM_CheckCxxPredicate(MIs["
372  << InsnID << "], Predicate=" << Predicate << ")\n");
373  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
374  assert(Predicate > GIPFP_MI_Invalid && "Expected a valid predicate");
375 
376  if (!testMIPredicate_MI(Predicate, *State.MIs[InsnID],
377  State.RecordedOperands))
378  if (handleReject() == RejectAndGiveUp)
379  return false;
380  break;
381  }
382  case GIM_CheckHasNoUse: {
383  int64_t InsnID = MatchTable[CurrentIdx++];
384 
386  dbgs() << CurrentIdx << ": GIM_CheckHasNoUse(MIs["
387  << InsnID << "]\n");
388 
389  const MachineInstr *MI = State.MIs[InsnID];
390  assert(MI && "Used insn before defined");
391  assert(MI->getNumDefs() > 0 && "No defs");
392  const Register Res = MI->getOperand(0).getReg();
393 
394  if (!MRI.use_nodbg_empty(Res)) {
395  if (handleReject() == RejectAndGiveUp)
396  return false;
397  }
398 
399  break;
400  }
402  int64_t InsnID = MatchTable[CurrentIdx++];
403  AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
405  dbgs() << CurrentIdx << ": GIM_CheckAtomicOrdering(MIs["
406  << InsnID << "], " << (uint64_t)Ordering << ")\n");
407  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
408  if (!State.MIs[InsnID]->hasOneMemOperand())
409  if (handleReject() == RejectAndGiveUp)
410  return false;
411 
412  for (const auto &MMO : State.MIs[InsnID]->memoperands())
413  if (MMO->getMergedOrdering() != Ordering)
414  if (handleReject() == RejectAndGiveUp)
415  return false;
416  break;
417  }
419  int64_t InsnID = MatchTable[CurrentIdx++];
420  AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
422  dbgs() << CurrentIdx
423  << ": GIM_CheckAtomicOrderingOrStrongerThan(MIs["
424  << InsnID << "], " << (uint64_t)Ordering << ")\n");
425  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
426  if (!State.MIs[InsnID]->hasOneMemOperand())
427  if (handleReject() == RejectAndGiveUp)
428  return false;
429 
430  for (const auto &MMO : State.MIs[InsnID]->memoperands())
431  if (!isAtLeastOrStrongerThan(MMO->getMergedOrdering(), Ordering))
432  if (handleReject() == RejectAndGiveUp)
433  return false;
434  break;
435  }
437  int64_t InsnID = MatchTable[CurrentIdx++];
438  AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
440  dbgs() << CurrentIdx
441  << ": GIM_CheckAtomicOrderingWeakerThan(MIs["
442  << InsnID << "], " << (uint64_t)Ordering << ")\n");
443  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
444  if (!State.MIs[InsnID]->hasOneMemOperand())
445  if (handleReject() == RejectAndGiveUp)
446  return false;
447 
448  for (const auto &MMO : State.MIs[InsnID]->memoperands())
449  if (!isStrongerThan(Ordering, MMO->getMergedOrdering()))
450  if (handleReject() == RejectAndGiveUp)
451  return false;
452  break;
453  }
455  int64_t InsnID = MatchTable[CurrentIdx++];
456  int64_t MMOIdx = MatchTable[CurrentIdx++];
457  // This accepts a list of possible address spaces.
458  const int NumAddrSpace = MatchTable[CurrentIdx++];
459 
460  if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
461  if (handleReject() == RejectAndGiveUp)
462  return false;
463  break;
464  }
465 
466  // Need to still jump to the end of the list of address spaces if we find
467  // a match earlier.
468  const uint64_t LastIdx = CurrentIdx + NumAddrSpace;
469 
470  const MachineMemOperand *MMO
471  = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
472  const unsigned MMOAddrSpace = MMO->getAddrSpace();
473 
474  bool Success = false;
475  for (int I = 0; I != NumAddrSpace; ++I) {
476  unsigned AddrSpace = MatchTable[CurrentIdx++];
479  dbgs() << "addrspace(" << MMOAddrSpace << ") vs "
480  << AddrSpace << '\n');
481 
482  if (AddrSpace == MMOAddrSpace) {
483  Success = true;
484  break;
485  }
486  }
487 
488  CurrentIdx = LastIdx;
489  if (!Success && handleReject() == RejectAndGiveUp)
490  return false;
491  break;
492  }
494  int64_t InsnID = MatchTable[CurrentIdx++];
495  int64_t MMOIdx = MatchTable[CurrentIdx++];
496  unsigned MinAlign = MatchTable[CurrentIdx++];
497 
498  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
499 
500  if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
501  if (handleReject() == RejectAndGiveUp)
502  return false;
503  break;
504  }
505 
506  MachineMemOperand *MMO
507  = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
509  dbgs() << CurrentIdx << ": GIM_CheckMemoryAlignment"
510  << "(MIs[" << InsnID << "]->memoperands() + " << MMOIdx
511  << ")->getAlignment() >= " << MinAlign << ")\n");
512  if (MMO->getAlign() < MinAlign && handleReject() == RejectAndGiveUp)
513  return false;
514 
515  break;
516  }
518  int64_t InsnID = MatchTable[CurrentIdx++];
519  int64_t MMOIdx = MatchTable[CurrentIdx++];
520  uint64_t Size = MatchTable[CurrentIdx++];
521 
523  dbgs() << CurrentIdx
524  << ": GIM_CheckMemorySizeEqual(MIs[" << InsnID
525  << "]->memoperands() + " << MMOIdx
526  << ", Size=" << Size << ")\n");
527  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
528 
529  if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
530  if (handleReject() == RejectAndGiveUp)
531  return false;
532  break;
533  }
534 
535  MachineMemOperand *MMO = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
536 
538  dbgs() << MMO->getSize() << " bytes vs " << Size
539  << " bytes\n");
540  if (MMO->getSize() != Size)
541  if (handleReject() == RejectAndGiveUp)
542  return false;
543 
544  break;
545  }
549  int64_t InsnID = MatchTable[CurrentIdx++];
550  int64_t MMOIdx = MatchTable[CurrentIdx++];
551  int64_t OpIdx = MatchTable[CurrentIdx++];
552 
555  dbgs() << CurrentIdx << ": GIM_CheckMemorySize"
556  << (MatcherOpcode == GIM_CheckMemorySizeEqualToLLT
557  ? "EqualTo"
558  : MatcherOpcode == GIM_CheckMemorySizeGreaterThanLLT
559  ? "GreaterThan"
560  : "LessThan")
561  << "LLT(MIs[" << InsnID << "]->memoperands() + " << MMOIdx
562  << ", OpIdx=" << OpIdx << ")\n");
563  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
564 
565  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
566  if (!MO.isReg()) {
568  dbgs() << CurrentIdx << ": Not a register\n");
569  if (handleReject() == RejectAndGiveUp)
570  return false;
571  break;
572  }
573 
574  if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
575  if (handleReject() == RejectAndGiveUp)
576  return false;
577  break;
578  }
579 
580  MachineMemOperand *MMO = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
581 
582  unsigned Size = MRI.getType(MO.getReg()).getSizeInBits();
583  if (MatcherOpcode == GIM_CheckMemorySizeEqualToLLT &&
584  MMO->getSizeInBits() != Size) {
585  if (handleReject() == RejectAndGiveUp)
586  return false;
587  } else if (MatcherOpcode == GIM_CheckMemorySizeLessThanLLT &&
588  MMO->getSizeInBits() >= Size) {
589  if (handleReject() == RejectAndGiveUp)
590  return false;
591  } else if (MatcherOpcode == GIM_CheckMemorySizeGreaterThanLLT &&
592  MMO->getSizeInBits() <= Size)
593  if (handleReject() == RejectAndGiveUp)
594  return false;
595 
596  break;
597  }
598  case GIM_CheckType: {
599  int64_t InsnID = MatchTable[CurrentIdx++];
600  int64_t OpIdx = MatchTable[CurrentIdx++];
601  int64_t TypeID = MatchTable[CurrentIdx++];
603  dbgs() << CurrentIdx << ": GIM_CheckType(MIs[" << InsnID
604  << "]->getOperand(" << OpIdx
605  << "), TypeID=" << TypeID << ")\n");
606  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
607  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
608  if (!MO.isReg() ||
609  MRI.getType(MO.getReg()) != ISelInfo.TypeObjects[TypeID]) {
610  if (handleReject() == RejectAndGiveUp)
611  return false;
612  }
613  break;
614  }
615  case GIM_CheckPointerToAny: {
616  int64_t InsnID = MatchTable[CurrentIdx++];
617  int64_t OpIdx = MatchTable[CurrentIdx++];
618  uint64_t SizeInBits = MatchTable[CurrentIdx++];
619 
621  dbgs() << CurrentIdx << ": GIM_CheckPointerToAny(MIs["
622  << InsnID << "]->getOperand(" << OpIdx
623  << "), SizeInBits=" << SizeInBits << ")\n");
624  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
625  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
626  const LLT Ty = MRI.getType(MO.getReg());
627 
628  // iPTR must be looked up in the target.
629  if (SizeInBits == 0) {
630  MachineFunction *MF = State.MIs[InsnID]->getParent()->getParent();
631  const unsigned AddrSpace = Ty.getAddressSpace();
632  SizeInBits = MF->getDataLayout().getPointerSizeInBits(AddrSpace);
633  }
634 
635  assert(SizeInBits != 0 && "Pointer size must be known");
636 
637  if (MO.isReg()) {
638  if (!Ty.isPointer() || Ty.getSizeInBits() != SizeInBits)
639  if (handleReject() == RejectAndGiveUp)
640  return false;
641  } else if (handleReject() == RejectAndGiveUp)
642  return false;
643 
644  break;
645  }
646  case GIM_RecordNamedOperand: {
647  int64_t InsnID = MatchTable[CurrentIdx++];
648  int64_t OpIdx = MatchTable[CurrentIdx++];
649  uint64_t StoreIdx = MatchTable[CurrentIdx++];
650 
652  dbgs() << CurrentIdx << ": GIM_RecordNamedOperand(MIs["
653  << InsnID << "]->getOperand(" << OpIdx
654  << "), StoreIdx=" << StoreIdx << ")\n");
655  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
656  assert(StoreIdx < State.RecordedOperands.size() && "Index out of range");
657  State.RecordedOperands[StoreIdx] = &State.MIs[InsnID]->getOperand(OpIdx);
658  break;
659  }
661  int64_t InsnID = MatchTable[CurrentIdx++];
662  int64_t OpIdx = MatchTable[CurrentIdx++];
663  int64_t RCEnum = MatchTable[CurrentIdx++];
665  dbgs() << CurrentIdx << ": GIM_CheckRegBankForClass(MIs["
666  << InsnID << "]->getOperand(" << OpIdx
667  << "), RCEnum=" << RCEnum << ")\n");
668  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
669  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
670  if (!MO.isReg() ||
671  &RBI.getRegBankFromRegClass(*TRI.getRegClass(RCEnum),
672  MRI.getType(MO.getReg())) !=
673  RBI.getRegBank(MO.getReg(), MRI, TRI)) {
674  if (handleReject() == RejectAndGiveUp)
675  return false;
676  }
677  break;
678  }
679 
681  int64_t InsnID = MatchTable[CurrentIdx++];
682  int64_t OpIdx = MatchTable[CurrentIdx++];
683  int64_t RendererID = MatchTable[CurrentIdx++];
684  int64_t ComplexPredicateID = MatchTable[CurrentIdx++];
686  dbgs() << CurrentIdx << ": State.Renderers[" << RendererID
687  << "] = GIM_CheckComplexPattern(MIs[" << InsnID
688  << "]->getOperand(" << OpIdx
689  << "), ComplexPredicateID=" << ComplexPredicateID
690  << ")\n");
691  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
692  // FIXME: Use std::invoke() when it's available.
693  ComplexRendererFns Renderer =
694  (ISel.*ISelInfo.ComplexPredicates[ComplexPredicateID])(
695  State.MIs[InsnID]->getOperand(OpIdx));
696  if (Renderer)
697  State.Renderers[RendererID] = Renderer.value();
698  else
699  if (handleReject() == RejectAndGiveUp)
700  return false;
701  break;
702  }
703 
704  case GIM_CheckConstantInt: {
705  int64_t InsnID = MatchTable[CurrentIdx++];
706  int64_t OpIdx = MatchTable[CurrentIdx++];
707  int64_t Value = MatchTable[CurrentIdx++];
709  dbgs() << CurrentIdx << ": GIM_CheckConstantInt(MIs["
710  << InsnID << "]->getOperand(" << OpIdx
711  << "), Value=" << Value << ")\n");
712  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
713  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
714  if (MO.isReg()) {
715  // isOperandImmEqual() will sign-extend to 64-bits, so should we.
716  LLT Ty = MRI.getType(MO.getReg());
718 
719  if (!isOperandImmEqual(MO, Value, MRI)) {
720  if (handleReject() == RejectAndGiveUp)
721  return false;
722  }
723  } else if (handleReject() == RejectAndGiveUp)
724  return false;
725 
726  break;
727  }
728 
729  case GIM_CheckLiteralInt: {
730  int64_t InsnID = MatchTable[CurrentIdx++];
731  int64_t OpIdx = MatchTable[CurrentIdx++];
732  int64_t Value = MatchTable[CurrentIdx++];
734  dbgs() << CurrentIdx << ": GIM_CheckLiteralInt(MIs["
735  << InsnID << "]->getOperand(" << OpIdx
736  << "), Value=" << Value << ")\n");
737  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
738  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
739  if (MO.isImm() && MO.getImm() == Value)
740  break;
741 
742  if (MO.isCImm() && MO.getCImm()->equalsInt(Value))
743  break;
744 
745  if (handleReject() == RejectAndGiveUp)
746  return false;
747 
748  break;
749  }
750 
751  case GIM_CheckIntrinsicID: {
752  int64_t InsnID = MatchTable[CurrentIdx++];
753  int64_t OpIdx = MatchTable[CurrentIdx++];
754  int64_t Value = MatchTable[CurrentIdx++];
756  dbgs() << CurrentIdx << ": GIM_CheckIntrinsicID(MIs["
757  << InsnID << "]->getOperand(" << OpIdx
758  << "), Value=" << Value << ")\n");
759  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
760  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
761  if (!MO.isIntrinsicID() || MO.getIntrinsicID() != Value)
762  if (handleReject() == RejectAndGiveUp)
763  return false;
764  break;
765  }
766  case GIM_CheckCmpPredicate: {
767  int64_t InsnID = MatchTable[CurrentIdx++];
768  int64_t OpIdx = MatchTable[CurrentIdx++];
769  int64_t Value = MatchTable[CurrentIdx++];
771  dbgs() << CurrentIdx << ": GIM_CheckCmpPredicate(MIs["
772  << InsnID << "]->getOperand(" << OpIdx
773  << "), Value=" << Value << ")\n");
774  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
775  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
776  if (!MO.isPredicate() || MO.getPredicate() != Value)
777  if (handleReject() == RejectAndGiveUp)
778  return false;
779  break;
780  }
781  case GIM_CheckIsMBB: {
782  int64_t InsnID = MatchTable[CurrentIdx++];
783  int64_t OpIdx = MatchTable[CurrentIdx++];
785  dbgs() << CurrentIdx << ": GIM_CheckIsMBB(MIs[" << InsnID
786  << "]->getOperand(" << OpIdx << "))\n");
787  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
788  if (!State.MIs[InsnID]->getOperand(OpIdx).isMBB()) {
789  if (handleReject() == RejectAndGiveUp)
790  return false;
791  }
792  break;
793  }
794  case GIM_CheckIsImm: {
795  int64_t InsnID = MatchTable[CurrentIdx++];
796  int64_t OpIdx = MatchTable[CurrentIdx++];
798  dbgs() << CurrentIdx << ": GIM_CheckIsImm(MIs[" << InsnID
799  << "]->getOperand(" << OpIdx << "))\n");
800  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
801  if (!State.MIs[InsnID]->getOperand(OpIdx).isImm()) {
802  if (handleReject() == RejectAndGiveUp)
803  return false;
804  }
805  break;
806  }
807  case GIM_CheckIsSafeToFold: {
808  int64_t InsnID = MatchTable[CurrentIdx++];
810  dbgs() << CurrentIdx << ": GIM_CheckIsSafeToFold(MIs["
811  << InsnID << "])\n");
812  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
813  if (!isObviouslySafeToFold(*State.MIs[InsnID], *State.MIs[0])) {
814  if (handleReject() == RejectAndGiveUp)
815  return false;
816  }
817  break;
818  }
819  case GIM_CheckIsSameOperand: {
820  int64_t InsnID = MatchTable[CurrentIdx++];
821  int64_t OpIdx = MatchTable[CurrentIdx++];
822  int64_t OtherInsnID = MatchTable[CurrentIdx++];
823  int64_t OtherOpIdx = MatchTable[CurrentIdx++];
825  dbgs() << CurrentIdx << ": GIM_CheckIsSameOperand(MIs["
826  << InsnID << "][" << OpIdx << "], MIs["
827  << OtherInsnID << "][" << OtherOpIdx << "])\n");
828  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
829  assert(State.MIs[OtherInsnID] != nullptr && "Used insn before defined");
830  if (!State.MIs[InsnID]->getOperand(OpIdx).isIdenticalTo(
831  State.MIs[OtherInsnID]->getOperand(OtherOpIdx))) {
832  if (handleReject() == RejectAndGiveUp)
833  return false;
834  }
835  break;
836  }
837  case GIM_Reject:
839  dbgs() << CurrentIdx << ": GIM_Reject\n");
840  if (handleReject() == RejectAndGiveUp)
841  return false;
842  break;
843 
844  case GIR_MutateOpcode: {
845  int64_t OldInsnID = MatchTable[CurrentIdx++];
846  uint64_t NewInsnID = MatchTable[CurrentIdx++];
847  int64_t NewOpcode = MatchTable[CurrentIdx++];
848  if (NewInsnID >= OutMIs.size())
849  OutMIs.resize(NewInsnID + 1);
850 
851  OutMIs[NewInsnID] = MachineInstrBuilder(*State.MIs[OldInsnID]->getMF(),
852  State.MIs[OldInsnID]);
853  OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode));
855  dbgs() << CurrentIdx << ": GIR_MutateOpcode(OutMIs["
856  << NewInsnID << "], MIs[" << OldInsnID << "], "
857  << NewOpcode << ")\n");
858  break;
859  }
860 
861  case GIR_BuildMI: {
862  uint64_t NewInsnID = MatchTable[CurrentIdx++];
863  int64_t Opcode = MatchTable[CurrentIdx++];
864  if (NewInsnID >= OutMIs.size())
865  OutMIs.resize(NewInsnID + 1);
866 
867  OutMIs[NewInsnID] = BuildMI(*State.MIs[0]->getParent(), State.MIs[0],
868  MIMetadata(*State.MIs[0]), TII.get(Opcode));
870  dbgs() << CurrentIdx << ": GIR_BuildMI(OutMIs["
871  << NewInsnID << "], " << Opcode << ")\n");
872  break;
873  }
874 
875  case GIR_Copy: {
876  int64_t NewInsnID = MatchTable[CurrentIdx++];
877  int64_t OldInsnID = MatchTable[CurrentIdx++];
878  int64_t OpIdx = MatchTable[CurrentIdx++];
879  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
880  OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(OpIdx));
882  dbgs()
883  << CurrentIdx << ": GIR_Copy(OutMIs[" << NewInsnID
884  << "], MIs[" << OldInsnID << "], " << OpIdx << ")\n");
885  break;
886  }
887 
888  case GIR_CopyOrAddZeroReg: {
889  int64_t NewInsnID = MatchTable[CurrentIdx++];
890  int64_t OldInsnID = MatchTable[CurrentIdx++];
891  int64_t OpIdx = MatchTable[CurrentIdx++];
892  int64_t ZeroReg = MatchTable[CurrentIdx++];
893  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
894  MachineOperand &MO = State.MIs[OldInsnID]->getOperand(OpIdx);
895  if (isOperandImmEqual(MO, 0, MRI))
896  OutMIs[NewInsnID].addReg(ZeroReg);
897  else
898  OutMIs[NewInsnID].add(MO);
900  dbgs() << CurrentIdx << ": GIR_CopyOrAddZeroReg(OutMIs["
901  << NewInsnID << "], MIs[" << OldInsnID << "], "
902  << OpIdx << ", " << ZeroReg << ")\n");
903  break;
904  }
905 
906  case GIR_CopySubReg: {
907  int64_t NewInsnID = MatchTable[CurrentIdx++];
908  int64_t OldInsnID = MatchTable[CurrentIdx++];
909  int64_t OpIdx = MatchTable[CurrentIdx++];
910  int64_t SubRegIdx = MatchTable[CurrentIdx++];
911  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
912  OutMIs[NewInsnID].addReg(State.MIs[OldInsnID]->getOperand(OpIdx).getReg(),
913  0, SubRegIdx);
915  dbgs() << CurrentIdx << ": GIR_CopySubReg(OutMIs["
916  << NewInsnID << "], MIs[" << OldInsnID << "], "
917  << OpIdx << ", " << SubRegIdx << ")\n");
918  break;
919  }
920 
921  case GIR_AddImplicitDef: {
922  int64_t InsnID = MatchTable[CurrentIdx++];
923  int64_t RegNum = MatchTable[CurrentIdx++];
924  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
925  OutMIs[InsnID].addDef(RegNum, RegState::Implicit);
927  dbgs() << CurrentIdx << ": GIR_AddImplicitDef(OutMIs["
928  << InsnID << "], " << RegNum << ")\n");
929  break;
930  }
931 
932  case GIR_AddImplicitUse: {
933  int64_t InsnID = MatchTable[CurrentIdx++];
934  int64_t RegNum = MatchTable[CurrentIdx++];
935  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
936  OutMIs[InsnID].addUse(RegNum, RegState::Implicit);
938  dbgs() << CurrentIdx << ": GIR_AddImplicitUse(OutMIs["
939  << InsnID << "], " << RegNum << ")\n");
940  break;
941  }
942 
943  case GIR_AddRegister: {
944  int64_t InsnID = MatchTable[CurrentIdx++];
945  int64_t RegNum = MatchTable[CurrentIdx++];
946  uint64_t RegFlags = MatchTable[CurrentIdx++];
947  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
948  OutMIs[InsnID].addReg(RegNum, RegFlags);
951  dbgs() << CurrentIdx << ": GIR_AddRegister(OutMIs["
952  << InsnID << "], " << RegNum << ", " << RegFlags << ")\n");
953  break;
954  }
955 
956  case GIR_AddTempRegister:
957  case GIR_AddTempSubRegister: {
958  int64_t InsnID = MatchTable[CurrentIdx++];
959  int64_t TempRegID = MatchTable[CurrentIdx++];
960  uint64_t TempRegFlags = MatchTable[CurrentIdx++];
961  unsigned SubReg = 0;
962  if (MatcherOpcode == GIR_AddTempSubRegister)
963  SubReg = MatchTable[CurrentIdx++];
964 
965  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
966 
967  OutMIs[InsnID].addReg(State.TempRegisters[TempRegID], TempRegFlags, SubReg);
969  dbgs() << CurrentIdx << ": GIR_AddTempRegister(OutMIs["
970  << InsnID << "], TempRegisters[" << TempRegID
971  << "]";
972  if (SubReg)
973  dbgs() << '.' << TRI.getSubRegIndexName(SubReg);
974  dbgs() << ", " << TempRegFlags << ")\n");
975  break;
976  }
977 
978  case GIR_AddImm: {
979  int64_t InsnID = MatchTable[CurrentIdx++];
980  int64_t Imm = MatchTable[CurrentIdx++];
981  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
982  OutMIs[InsnID].addImm(Imm);
984  dbgs() << CurrentIdx << ": GIR_AddImm(OutMIs[" << InsnID
985  << "], " << Imm << ")\n");
986  break;
987  }
988 
989  case GIR_ComplexRenderer: {
990  int64_t InsnID = MatchTable[CurrentIdx++];
991  int64_t RendererID = MatchTable[CurrentIdx++];
992  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
993  for (const auto &RenderOpFn : State.Renderers[RendererID])
994  RenderOpFn(OutMIs[InsnID]);
996  dbgs() << CurrentIdx << ": GIR_ComplexRenderer(OutMIs["
997  << InsnID << "], " << RendererID << ")\n");
998  break;
999  }
1001  int64_t InsnID = MatchTable[CurrentIdx++];
1002  int64_t RendererID = MatchTable[CurrentIdx++];
1003  int64_t RenderOpID = MatchTable[CurrentIdx++];
1004  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1005  State.Renderers[RendererID][RenderOpID](OutMIs[InsnID]);
1007  dbgs() << CurrentIdx
1008  << ": GIR_ComplexSubOperandRenderer(OutMIs["
1009  << InsnID << "], " << RendererID << ", "
1010  << RenderOpID << ")\n");
1011  break;
1012  }
1013 
1014  case GIR_CopyConstantAsSImm: {
1015  int64_t NewInsnID = MatchTable[CurrentIdx++];
1016  int64_t OldInsnID = MatchTable[CurrentIdx++];
1017  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
1018  assert(State.MIs[OldInsnID]->getOpcode() == TargetOpcode::G_CONSTANT && "Expected G_CONSTANT");
1019  if (State.MIs[OldInsnID]->getOperand(1).isCImm()) {
1020  OutMIs[NewInsnID].addImm(
1021  State.MIs[OldInsnID]->getOperand(1).getCImm()->getSExtValue());
1022  } else if (State.MIs[OldInsnID]->getOperand(1).isImm())
1023  OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(1));
1024  else
1025  llvm_unreachable("Expected Imm or CImm operand");
1027  dbgs() << CurrentIdx << ": GIR_CopyConstantAsSImm(OutMIs["
1028  << NewInsnID << "], MIs[" << OldInsnID << "])\n");
1029  break;
1030  }
1031 
1032  // TODO: Needs a test case once we have a pattern that uses this.
1033  case GIR_CopyFConstantAsFPImm: {
1034  int64_t NewInsnID = MatchTable[CurrentIdx++];
1035  int64_t OldInsnID = MatchTable[CurrentIdx++];
1036  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
1037  assert(State.MIs[OldInsnID]->getOpcode() == TargetOpcode::G_FCONSTANT && "Expected G_FCONSTANT");
1038  if (State.MIs[OldInsnID]->getOperand(1).isFPImm())
1039  OutMIs[NewInsnID].addFPImm(
1040  State.MIs[OldInsnID]->getOperand(1).getFPImm());
1041  else
1042  llvm_unreachable("Expected FPImm operand");
1044  dbgs() << CurrentIdx << ": GIR_CopyFPConstantAsFPImm(OutMIs["
1045  << NewInsnID << "], MIs[" << OldInsnID << "])\n");
1046  break;
1047  }
1048 
1049  case GIR_CustomRenderer: {
1050  int64_t InsnID = MatchTable[CurrentIdx++];
1051  int64_t OldInsnID = MatchTable[CurrentIdx++];
1052  int64_t RendererFnID = MatchTable[CurrentIdx++];
1053  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1055  dbgs() << CurrentIdx << ": GIR_CustomRenderer(OutMIs["
1056  << InsnID << "], MIs[" << OldInsnID << "], "
1057  << RendererFnID << ")\n");
1058  (ISel.*ISelInfo.CustomRenderers[RendererFnID])(
1059  OutMIs[InsnID], *State.MIs[OldInsnID],
1060  -1); // Not a source operand of the old instruction.
1061  break;
1062  }
1064  int64_t InsnID = MatchTable[CurrentIdx++];
1065  int64_t OldInsnID = MatchTable[CurrentIdx++];
1066  int64_t OpIdx = MatchTable[CurrentIdx++];
1067  int64_t RendererFnID = MatchTable[CurrentIdx++];
1068  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1069 
1072  dbgs() << CurrentIdx << ": GIR_CustomOperandRenderer(OutMIs["
1073  << InsnID << "], MIs[" << OldInsnID << "]->getOperand("
1074  << OpIdx << "), "
1075  << RendererFnID << ")\n");
1076  (ISel.*ISelInfo.CustomRenderers[RendererFnID])(OutMIs[InsnID],
1077  *State.MIs[OldInsnID],
1078  OpIdx);
1079  break;
1080  }
1081  case GIR_ConstrainOperandRC: {
1082  int64_t InsnID = MatchTable[CurrentIdx++];
1083  int64_t OpIdx = MatchTable[CurrentIdx++];
1084  int64_t RCEnum = MatchTable[CurrentIdx++];
1085  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1086  MachineInstr &I = *OutMIs[InsnID].getInstr();
1087  MachineFunction &MF = *I.getParent()->getParent();
1089  const TargetRegisterClass &RC = *TRI.getRegClass(RCEnum);
1090  MachineOperand &MO = I.getOperand(OpIdx);
1091  constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC, MO);
1093  dbgs() << CurrentIdx << ": GIR_ConstrainOperandRC(OutMIs["
1094  << InsnID << "], " << OpIdx << ", " << RCEnum
1095  << ")\n");
1096  break;
1097  }
1098 
1100  int64_t InsnID = MatchTable[CurrentIdx++];
1101  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1102  constrainSelectedInstRegOperands(*OutMIs[InsnID].getInstr(), TII, TRI,
1103  RBI);
1105  dbgs() << CurrentIdx
1106  << ": GIR_ConstrainSelectedInstOperands(OutMIs["
1107  << InsnID << "])\n");
1108  break;
1109  }
1110 
1111  case GIR_MergeMemOperands: {
1112  int64_t InsnID = MatchTable[CurrentIdx++];
1113  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1114 
1116  dbgs() << CurrentIdx << ": GIR_MergeMemOperands(OutMIs["
1117  << InsnID << "]");
1118  int64_t MergeInsnID = GIU_MergeMemOperands_EndOfList;
1119  while ((MergeInsnID = MatchTable[CurrentIdx++]) !=
1122  dbgs() << ", MIs[" << MergeInsnID << "]");
1123  for (const auto &MMO : State.MIs[MergeInsnID]->memoperands())
1124  OutMIs[InsnID].addMemOperand(MMO);
1125  }
1127  break;
1128  }
1129 
1130  case GIR_EraseFromParent: {
1131  int64_t InsnID = MatchTable[CurrentIdx++];
1132  assert(State.MIs[InsnID] &&
1133  "Attempted to erase an undefined instruction");
1134  State.MIs[InsnID]->eraseFromParent();
1136  dbgs() << CurrentIdx << ": GIR_EraseFromParent(MIs["
1137  << InsnID << "])\n");
1138  break;
1139  }
1140 
1141  case GIR_MakeTempReg: {
1142  int64_t TempRegID = MatchTable[CurrentIdx++];
1143  int64_t TypeID = MatchTable[CurrentIdx++];
1144 
1145  State.TempRegisters[TempRegID] =
1146  MRI.createGenericVirtualRegister(ISelInfo.TypeObjects[TypeID]);
1148  dbgs() << CurrentIdx << ": TempRegs[" << TempRegID
1149  << "] = GIR_MakeTempReg(" << TypeID << ")\n");
1150  break;
1151  }
1152 
1153  case GIR_Coverage: {
1154  int64_t RuleID = MatchTable[CurrentIdx++];
1155  CoverageInfo.setCovered(RuleID);
1156 
1158  dbgs()
1159  << CurrentIdx << ": GIR_Coverage(" << RuleID << ")");
1160  break;
1161  }
1162 
1163  case GIR_Done:
1165  dbgs() << CurrentIdx << ": GIR_Done\n");
1166  propagateFlags(OutMIs);
1167  return true;
1168 
1169  default:
1170  llvm_unreachable("Unexpected command");
1171  }
1172  }
1173 }
1174 
1175 } // end namespace llvm
1176 
1177 #endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
llvm::InstructionSelector::MatcherState::Renderers
std::vector< ComplexRendererFns::value_type > Renderers
Definition: InstructionSelector.h:476
llvm::GIM_RecordInsn
@ GIM_RecordInsn
Record the specified instruction.
Definition: InstructionSelector.h:110
getName
static StringRef getName(Value *V)
Definition: ProvenanceAnalysisEvaluator.cpp:20
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::GIR_CopyOrAddZeroReg
@ GIR_CopyOrAddZeroReg
Copy an operand to the specified instruction or add a zero register if the operand is a zero immediat...
Definition: InstructionSelector.h:309
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::GIM_CheckIsSafeToFold
@ GIM_CheckIsSafeToFold
Check if the specified operand is safe to fold into the current instruction.
Definition: InstructionSelector.h:262
llvm::GIR_ComplexRenderer
@ GIR_ComplexRenderer
Render complex operands to the specified instruction.
Definition: InstructionSelector.h:350
llvm::GIM_CheckAtomicOrdering
@ GIM_CheckAtomicOrdering
Check a memory operation has the specified atomic ordering.
Definition: InstructionSelector.h:152
llvm::GIR_EraseFromParent
@ GIR_EraseFromParent
Erase from parent.
Definition: InstructionSelector.h:403
llvm::MachineMemOperand::getAlign
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
Definition: MachineOperand.cpp:1100
llvm::InstructionSelector::testMIPredicate_MI
virtual bool testMIPredicate_MI(unsigned, const MachineInstr &, const std::array< const MachineOperand *, 3 > &Operands) const
Definition: InstructionSelector.h:550
llvm::GIR_CustomRenderer
@ GIR_CustomRenderer
Render operands to the specified instruction using a custom function.
Definition: InstructionSelector.h:361
llvm::GIM_Try
@ GIM_Try
Begin a try-block to attempt a match and jump to OnFail if it is unsuccessful.
Definition: InstructionSelector.h:87
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::GIM_CheckIsSameOperand
@ GIM_CheckIsSameOperand
Check the specified operands are identical.
Definition: InstructionSelector.h:269
llvm::GIM_CheckLiteralInt
@ GIM_CheckLiteralInt
Check the operand is a specific literal integer (i.e.
Definition: InstructionSelector.h:236
llvm::MachineOperand::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition: MachineOperand.h:592
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::GIM_CheckI64ImmPredicate
@ GIM_CheckI64ImmPredicate
Check an immediate predicate on the specified instruction.
Definition: InstructionSelector.h:135
llvm::RegisterBankInfo::getRegBank
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
Definition: RegisterBankInfo.h:431
ErrorHandling.h
llvm::GIR_ConstrainOperandRC
@ GIR_ConstrainOperandRC
Constrain an instruction operand to a register class.
Definition: InstructionSelector.h:387
RegisterBankInfo.h
llvm::InstructionSelector::MatcherState
Definition: InstructionSelector.h:475
llvm::MachineMemOperand::getSizeInBits
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
Definition: MachineMemOperand.h:240
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::GIM_CheckPointerToAny
@ GIM_CheckPointerToAny
Check the type of a pointer to any address space.
Definition: InstructionSelector.h:212
TargetInstrInfo.h
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MachineOperand::isCImm
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
Definition: MachineOperand.h:324
llvm::InstructionSelector::MatcherState::MIs
RecordedMIVector MIs
Definition: InstructionSelector.h:477
llvm::Optional
Definition: APInt.h:33
llvm::GIM_CheckHasNoUse
@ GIM_CheckHasNoUse
Check if there's no use of the first result.
Definition: InstructionSelector.h:201
llvm::InstructionSelector::testImmPredicate_I64
virtual bool testImmPredicate_I64(unsigned, int64_t) const
Definition: InstructionSelector.h:538
llvm::GIM_CheckMemoryAlignment
@ GIM_CheckMemoryAlignment
Check the minimum alignment of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:175
llvm::GIM_CheckIntrinsicID
@ GIM_CheckIntrinsicID
Check the operand is a specific intrinsic ID.
Definition: InstructionSelector.h:241
llvm::Expected
Tagged union holding either a T or a Error.
Definition: APFloat.h:41
llvm::CodeGenCoverage::setCovered
void setCovered(uint64_t RuleID)
Definition: CodeGenCoverage.cpp:28
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::GIM_CheckType
@ GIM_CheckType
Check the type for the specified operand.
Definition: InstructionSelector.h:207
llvm::InstructionSelector::MatcherState::TempRegisters
DenseMap< unsigned, unsigned > TempRegisters
Definition: InstructionSelector.h:478
llvm::constrainSelectedInstRegOperands
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:153
MachineRegisterInfo.h
llvm::GIR_CopyConstantAsSImm
@ GIR_CopyConstantAsSImm
Render a G_CONSTANT operator as a sign-extended immediate.
Definition: InstructionSelector.h:375
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::isAtLeastOrStrongerThan
bool isAtLeastOrStrongerThan(AtomicOrdering AO, AtomicOrdering Other)
Definition: AtomicOrdering.h:105
llvm::GIR_AddTempSubRegister
@ GIR_AddTempSubRegister
Add a temporary register to the specified instruction.
Definition: InstructionSelector.h:341
llvm::GIM_CheckAtomicOrderingWeakerThan
@ GIM_CheckAtomicOrderingWeakerThan
Definition: InstructionSelector.h:154
llvm::MinAlign
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:600
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
DEBUG_WITH_TYPE
#define DEBUG_WITH_TYPE(TYPE, X)
DEBUG_WITH_TYPE macro - This macro should be used by passes to emit debug information.
Definition: Debug.h:64
llvm::InstructionSelector::ISelInfoTy::CustomRenderers
const CustomRendererFn * CustomRenderers
Definition: InstructionSelector.h:513
llvm::GIR_ComplexSubOperandRenderer
@ GIR_ComplexSubOperandRenderer
Render sub-operands of complex operands to the specified instruction.
Definition: InstructionSelector.h:356
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
Constants.h
llvm::MachineMemOperand::getAddrSpace
unsigned getAddrSpace() const
Definition: MachineMemOperand.h:228
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::GIM_CheckCmpPredicate
@ GIM_CheckCmpPredicate
Check the operand is a specific predicate.
Definition: InstructionSelector.h:247
llvm::GIM_Reject
@ GIM_Reject
Fail the current try-block, or completely fail to match if there is no current try-block.
Definition: InstructionSelector.h:282
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:152
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::InstructionSelector::CoverageInfo
CodeGenCoverage * CoverageInfo
Definition: InstructionSelector.h:444
Utils.h
llvm::GIR_AddRegister
@ GIR_AddRegister
Add an register to the specified instruction.
Definition: InstructionSelector.h:328
llvm::ConstantInt::equalsInt
bool equalsInt(uint64_t V) const
A helper method that can be used to determine if the constant contained within is equal to a constant...
Definition: Constants.h:168
TargetOpcodes.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::GIR_MutateOpcode
@ GIR_MutateOpcode
Mutate an instruction.
Definition: InstructionSelector.h:290
llvm::InstructionSelector::MatcherState::RecordedOperands
std::array< const MachineOperand *, 3 > RecordedOperands
Named operands that predicate with 'let PredicateCodeUsesOperands = 1' referenced in its argument lis...
Definition: InstructionSelector.h:483
llvm::SmallVectorImpl::resize
void resize(size_type N)
Definition: SmallVector.h:642
llvm::GIR_Copy
@ GIR_Copy
Copy an operand to the specified instruction.
Definition: InstructionSelector.h:301
llvm::GIM_CheckComplexPattern
@ GIM_CheckComplexPattern
Check the operand matches a complex predicate.
Definition: InstructionSelector.h:224
llvm::GIR_MakeTempReg
@ GIR_MakeTempReg
Create a new temporary register that's not constrained.
Definition: InstructionSelector.h:408
llvm::GIR_AddImplicitUse
@ GIR_AddImplicitUse
Add an implicit register use to the specified instruction.
Definition: InstructionSelector.h:324
llvm::GIR_Coverage
@ GIR_Coverage
Increment the rule coverage counter.
Definition: InstructionSelector.h:415
llvm::MachineInstr::NoFPExcept
@ NoFPExcept
Definition: MachineInstr.h:110
llvm::GIPFP_I64_Invalid
@ GIPFP_I64_Invalid
Definition: InstructionSelectorImpl.h:42
llvm::GIM_CheckMemorySizeEqualToLLT
@ GIM_CheckMemorySizeEqualToLLT
Check the size of the memory access for the given machine memory operand against the size of an opera...
Definition: InstructionSelector.h:182
llvm::GIM_CheckAPFloatImmPredicate
@ GIM_CheckAPFloatImmPredicate
Check a floating point immediate predicate on the specified instruction.
Definition: InstructionSelector.h:143
llvm::GIR_BuildMI
@ GIR_BuildMI
Build a new instruction.
Definition: InstructionSelector.h:295
llvm::MIMetadata
Set of metadata that should be preserved when using BuildMI().
Definition: MachineInstrBuilder.h:335
InstructionSelector.h
llvm::LLT::getAddressSpace
unsigned getAddressSpace() const
Definition: LowLevelTypeImpl.h:238
llvm::InstructionSelector::MF
MachineFunction * MF
Definition: InstructionSelector.h:446
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
TypeID
Type::TypeID TypeID
Definition: Mips16HardFloat.cpp:103
llvm::InstructionSelector::isOperandImmEqual
bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI) const
Definition: InstructionSelector.cpp:29
llvm::APFloat
Definition: APFloat.h:716
llvm::PPC::Predicate
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
llvm::InstructionSelector::ISelInfoTy::TypeIDMap
SmallDenseMap< LLT, unsigned, 64 > TypeIDMap
Definition: InstructionSelector.h:515
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::GIM_CheckCxxInsnPredicate
@ GIM_CheckCxxInsnPredicate
Check a generic C++ instruction predicate.
Definition: InstructionSelector.h:197
llvm::CodeGenCoverage
Definition: CodeGenCoverage.h:19
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineOperand::getCImm
const ConstantInt * getCImm() const
Definition: MachineOperand.h:551
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::GIPFP_APInt_Invalid
@ GIPFP_APInt_Invalid
Definition: InstructionSelectorImpl.h:43
llvm::GIM_CheckMemorySizeLessThanLLT
@ GIM_CheckMemorySizeLessThanLLT
Definition: InstructionSelector.h:183
llvm::GIM_CheckIsMBB
@ GIM_CheckIsMBB
Check the specified operand is an MBB.
Definition: InstructionSelector.h:252
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::GIM_CheckFeatures
@ GIM_CheckFeatures
Check the feature bits.
Definition: InstructionSelector.h:114
CodeGenCoverage.h
llvm::InstructionSelector::ISelInfoTy::TypeObjects
const LLT * TypeObjects
Definition: InstructionSelector.h:510
llvm::MachineOperand::getPredicate
unsigned getPredicate() const
Definition: MachineOperand.h:597
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::LLT::isPointer
bool isPointer() const
Definition: LowLevelTypeImpl.h:120
llvm::GIR_AddImm
@ GIR_AddImm
Add an immediate to the specified instruction.
Definition: InstructionSelector.h:346
llvm::GIM_CheckNumOperands
@ GIM_CheckNumOperands
Check the instruction has the right number of operands.
Definition: InstructionSelector.h:131
llvm::GIR_CopyFConstantAsFPImm
@ GIR_CopyFConstantAsFPImm
Render a G_FCONSTANT operator as a sign-extended immediate.
Definition: InstructionSelector.h:381
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::GIM_SwitchType
@ GIM_SwitchType
Switch over the LLT on the specified instruction operand.
Definition: InstructionSelector.h:104
llvm::GIM_CheckOpcode
@ GIM_CheckOpcode
Check the opcode on the specified instruction.
Definition: InstructionSelector.h:119
llvm::GIM_CheckMemorySizeEqualTo
@ GIM_CheckMemorySizeEqualTo
Check the size of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:159
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::GIR_ConstrainSelectedInstOperands
@ GIR_ConstrainSelectedInstOperands
Constrain an instructions operands according to the instruction description.
Definition: InstructionSelector.h:392
llvm::GIM_CheckAPIntImmPredicate
@ GIM_CheckAPIntImmPredicate
Check an immediate predicate on the specified instruction via an APInt.
Definition: InstructionSelector.h:139
llvm::InstructionSelector::testImmPredicate_APFloat
virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const
Definition: InstructionSelector.h:546
llvm::GIM_CheckIsImm
@ GIM_CheckIsImm
Check the specified operand is an Imm.
Definition: InstructionSelector.h:257
DataLayout.h
llvm::GIR_CopySubReg
@ GIR_CopySubReg
Copy an operand to the specified instruction.
Definition: InstructionSelector.h:315
llvm::MachineOperand::isIntrinsicID
bool isIntrinsicID() const
Definition: MachineOperand.h:351
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::GIR_AddImplicitDef
@ GIR_AddImplicitDef
Add an implicit register def to the specified instruction.
Definition: InstructionSelector.h:320
llvm::GIR_Done
@ GIR_Done
A successful emission.
Definition: InstructionSelector.h:411
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:718
llvm::InstructionSelector::ISelInfoTy::ComplexPredicates
const ComplexMatcherMemFn * ComplexPredicates
Definition: InstructionSelector.h:512
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::GIM_CheckRegBankForClass
@ GIM_CheckRegBankForClass
Check the register bank for the specified operand.
Definition: InstructionSelector.h:217
llvm::InstructionSelector::ISelInfoTy::FeatureBitsets
const PredicateBitset * FeatureBitsets
Definition: InstructionSelector.h:511
llvm::RegisterBankInfo::getRegBankFromRegClass
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const
Get a register bank that covers RC.
Definition: RegisterBankInfo.h:603
llvm::isBuildVectorAllOnes
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1129
llvm::GIM_SwitchOpcode
@ GIM_SwitchOpcode
Switch over the opcode on the specified instruction.
Definition: InstructionSelector.h:95
uint16_t
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:235
Success
#define Success
Definition: AArch64Disassembler.cpp:295
llvm::GIM_CheckConstantInt
@ GIM_CheckConstantInt
Check the operand is a specific integer.
Definition: InstructionSelector.h:230
llvm::GIR_CustomOperandRenderer
@ GIR_CustomOperandRenderer
Render operands to the specified instruction using a custom function, reading from a specific operand...
Definition: InstructionSelector.h:369
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::GIR_AddTempRegister
@ GIR_AddTempRegister
Add a temporary register to the specified instruction.
Definition: InstructionSelector.h:334
llvm::GIM_CheckAtomicOrderingOrStrongerThan
@ GIM_CheckAtomicOrderingOrStrongerThan
Definition: InstructionSelector.h:153
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
llvm::InstructionSelector::isObviouslySafeToFold
bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const
Return true if MI can obviously be folded into IntoMI.
Definition: InstructionSelector.cpp:55
llvm::GIM_CheckMemorySizeGreaterThanLLT
@ GIM_CheckMemorySizeGreaterThanLLT
Definition: InstructionSelector.h:184
llvm::GIM_CheckOpcodeIsEither
@ GIM_CheckOpcodeIsEither
Check the opcode on the specified instruction, checking 2 acceptable alternatives.
Definition: InstructionSelector.h:126
llvm::isStrongerThan
bool isStrongerThan(AtomicOrdering AO, AtomicOrdering Other)
Returns true if ao is stronger than other as defined by the AtomicOrdering lattice,...
Definition: AtomicOrdering.h:90
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::MachineOperand::isPredicate
bool isPredicate() const
Definition: MachineOperand.h:352
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
SmallVector.h
llvm::GIPFP_APFloat_Invalid
@ GIPFP_APFloat_Invalid
Definition: InstructionSelectorImpl.h:44
MachineInstrBuilder.h
llvm::GIU_MergeMemOperands_EndOfList
@ GIU_MergeMemOperands_EndOfList
Indicates the end of the variable-length MergeInsnID list in a GIR_MergeMemOperands opcode.
Definition: InstructionSelector.h:424
llvm::InstructionSelector::testImmPredicate_APInt
virtual bool testImmPredicate_APInt(unsigned, const APInt &) const
Definition: InstructionSelector.h:542
llvm::SmallVectorImpl::pop_back_val
T pop_back_val()
Definition: SmallVector.h:677
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:54
llvm::InstructionSelector::ISelInfoTy
Definition: InstructionSelector.h:497
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:285
llvm::Optional::value
constexpr const T & value() const &
Definition: Optional.h:281
llvm::GIPFP_MI_Invalid
@ GIPFP_MI_Invalid
Definition: InstructionSelectorImpl.h:45
MachineOperand.h
llvm::DataLayout::getPointerSizeInBits
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:412
llvm::GIM_CheckMemoryAddressSpace
@ GIM_CheckMemoryAddressSpace
Check the address space of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:168
llvm::InstructionSelector::executeMatchTable
bool executeMatchTable(TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State, const ISelInfoTy< PredicateBitset, ComplexMatcherMemFn, CustomRendererFn > &ISelInfo, const int64_t *MatchTable, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, CodeGenCoverage &CoverageInfo) const
Execute a given matcher table and return true if the match was successful and false otherwise.
Definition: InstructionSelectorImpl.h:50
raw_ostream.h
llvm::GIM_RecordNamedOperand
@ GIM_RecordNamedOperand
Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some named operands that will be ...
Definition: InstructionSelector.h:278
llvm::GIR_MergeMemOperands
@ GIR_MergeMemOperands
Merge all memory operands into instruction.
Definition: InstructionSelector.h:399
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
TargetRegisterInfo.h
Debug.h
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::isBuildVectorAllZeros
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1123
llvm::GIM_CheckIsBuildVectorAllZeros
@ GIM_CheckIsBuildVectorAllZeros
Definition: InstructionSelector.h:192
llvm::GIM_CheckImmOperandPredicate
@ GIM_CheckImmOperandPredicate
Check an immediate predicate on the specified instruction.
Definition: InstructionSelector.h:148
llvm::GIM_CheckIsBuildVectorAllOnes
@ GIM_CheckIsBuildVectorAllOnes
Check if this is a vector that can be treated as a vector splat constant.
Definition: InstructionSelector.h:191
llvm::LLT
Definition: LowLevelTypeImpl.h:39