15 #ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
16 #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
48 template <
class TgtInstructionSelector,
class PredicateBitset,
49 class ComplexMatcherMemFn,
class CustomRendererFn>
63 bool NoFPException = !State.
MIs[0]->getDesc().mayRaiseFPException();
67 enum RejectAction { RejectAndGiveUp, RejectAndResume };
68 auto handleReject = [&]() -> RejectAction {
70 dbgs() << CurrentIdx <<
": Rejected\n");
71 if (OnFailResumeAt.empty())
72 return RejectAndGiveUp;
75 dbgs() << CurrentIdx <<
": Resume at " << CurrentIdx <<
" ("
76 << OnFailResumeAt.size() <<
" try-blocks remain)\n");
77 return RejectAndResume;
81 for (
auto MIB : OutMIs) {
85 if (NoFPException && MIB->mayRaiseFPException())
87 MIB.setMIFlags(MIBFlags);
94 assert(CurrentIdx != ~0u &&
"Invalid MatchTable index");
95 int64_t MatcherOpcode = MatchTable[CurrentIdx++];
96 switch (MatcherOpcode) {
99 dbgs() << CurrentIdx <<
": Begin try-block\n");
100 OnFailResumeAt.push_back(MatchTable[CurrentIdx++]);
105 int64_t NewInsnID = MatchTable[CurrentIdx++];
106 int64_t InsnID = MatchTable[CurrentIdx++];
107 int64_t OpIdx = MatchTable[CurrentIdx++];
111 assert(NewInsnID != 0 &&
"Refusing to modify MIs[0]");
116 dbgs() << CurrentIdx <<
": Not a register\n");
117 if (handleReject() == RejectAndGiveUp)
123 dbgs() << CurrentIdx <<
": Is a physical register\n");
124 if (handleReject() == RejectAndGiveUp)
130 if ((
size_t)NewInsnID < State.
MIs.size())
131 State.
MIs[NewInsnID] = NewMI;
133 assert((
size_t)NewInsnID == State.
MIs.size() &&
134 "Expected to store MIs in order");
135 State.
MIs.push_back(NewMI);
138 dbgs() << CurrentIdx <<
": MIs[" << NewInsnID
139 <<
"] = GIM_RecordInsn(" << InsnID <<
", " << OpIdx
145 int64_t ExpectedBitsetID = MatchTable[CurrentIdx++];
148 <<
": GIM_CheckFeatures(ExpectedBitsetID="
149 << ExpectedBitsetID <<
")\n");
150 if ((AvailableFeatures & ISelInfo.
FeatureBitsets[ExpectedBitsetID]) !=
152 if (handleReject() == RejectAndGiveUp)
160 int64_t InsnID = MatchTable[CurrentIdx++];
161 int64_t Expected0 = MatchTable[CurrentIdx++];
162 int64_t Expected1 = -1;
164 Expected1 = MatchTable[CurrentIdx++];
166 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
167 unsigned Opcode = State.
MIs[InsnID]->getOpcode();
170 dbgs() << CurrentIdx <<
": GIM_CheckOpcode(MIs[" << InsnID
171 <<
"], ExpectedOpcode=" << Expected0;
173 dbgs() <<
" || " << Expected1;
174 dbgs() <<
") // Got=" << Opcode <<
"\n";
177 if (Opcode != Expected0 && Opcode != Expected1) {
178 if (handleReject() == RejectAndGiveUp)
184 int64_t InsnID = MatchTable[CurrentIdx++];
185 int64_t LowerBound = MatchTable[CurrentIdx++];
186 int64_t UpperBound = MatchTable[CurrentIdx++];
187 int64_t Default = MatchTable[CurrentIdx++];
189 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
190 const int64_t Opcode = State.
MIs[InsnID]->getOpcode();
193 dbgs() << CurrentIdx <<
": GIM_SwitchOpcode(MIs[" << InsnID <<
"], ["
194 << LowerBound <<
", " << UpperBound <<
"), Default=" << Default
195 <<
", JumpTable...) // Got=" << Opcode <<
"\n";
197 if (Opcode < LowerBound || UpperBound <= Opcode) {
198 CurrentIdx = Default;
201 CurrentIdx = MatchTable[CurrentIdx + (Opcode - LowerBound)];
203 CurrentIdx = Default;
206 OnFailResumeAt.push_back(Default);
211 int64_t InsnID = MatchTable[CurrentIdx++];
212 int64_t OpIdx = MatchTable[CurrentIdx++];
213 int64_t LowerBound = MatchTable[CurrentIdx++];
214 int64_t UpperBound = MatchTable[CurrentIdx++];
215 int64_t Default = MatchTable[CurrentIdx++];
217 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
221 dbgs() << CurrentIdx <<
": GIM_SwitchType(MIs[" << InsnID
222 <<
"]->getOperand(" << OpIdx <<
"), [" << LowerBound <<
", "
223 << UpperBound <<
"), Default=" << Default
224 <<
", JumpTable...) // Got=";
226 dbgs() <<
"Not a VReg\n";
231 CurrentIdx = Default;
235 const auto TyI = ISelInfo.
TypeIDMap.find(Ty);
237 CurrentIdx = Default;
240 const int64_t
TypeID = TyI->second;
242 CurrentIdx = Default;
245 CurrentIdx = MatchTable[CurrentIdx + (
TypeID - LowerBound)];
247 CurrentIdx = Default;
250 OnFailResumeAt.push_back(Default);
255 int64_t InsnID = MatchTable[CurrentIdx++];
256 int64_t
Expected = MatchTable[CurrentIdx++];
258 dbgs() << CurrentIdx <<
": GIM_CheckNumOperands(MIs["
259 << InsnID <<
"], Expected=" <<
Expected <<
")\n");
260 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
261 if (State.
MIs[InsnID]->getNumOperands() !=
Expected) {
262 if (handleReject() == RejectAndGiveUp)
269 int64_t InsnID = MatchTable[CurrentIdx++];
271 ? MatchTable[CurrentIdx++]
273 int64_t
Predicate = MatchTable[CurrentIdx++];
275 dbgs() << CurrentIdx <<
": GIM_CheckImmPredicate(MIs["
276 << InsnID <<
"]->getOperand(" << OpIdx
277 <<
"), Predicate=" <<
Predicate <<
")\n");
278 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
279 assert((State.
MIs[InsnID]->getOperand(OpIdx).isImm() ||
280 State.
MIs[InsnID]->getOperand(OpIdx).isCImm()) &&
281 "Expected immediate operand");
284 if (State.
MIs[InsnID]->getOperand(OpIdx).isCImm())
285 Value = State.
MIs[InsnID]->getOperand(OpIdx).getCImm()->getSExtValue();
286 else if (State.
MIs[InsnID]->getOperand(OpIdx).isImm())
287 Value = State.
MIs[InsnID]->getOperand(OpIdx).getImm();
292 if (handleReject() == RejectAndGiveUp)
297 int64_t InsnID = MatchTable[CurrentIdx++];
298 int64_t
Predicate = MatchTable[CurrentIdx++];
301 << CurrentIdx <<
": GIM_CheckAPIntImmPredicate(MIs["
302 << InsnID <<
"], Predicate=" <<
Predicate <<
")\n");
303 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
304 assert(State.
MIs[InsnID]->getOpcode() == TargetOpcode::G_CONSTANT &&
305 "Expected G_CONSTANT");
308 if (State.
MIs[InsnID]->getOperand(1).isCImm())
309 Value = State.
MIs[InsnID]->getOperand(1).getCImm()->getValue();
314 if (handleReject() == RejectAndGiveUp)
319 int64_t InsnID = MatchTable[CurrentIdx++];
320 int64_t
Predicate = MatchTable[CurrentIdx++];
323 << CurrentIdx <<
": GIM_CheckAPFloatImmPredicate(MIs["
324 << InsnID <<
"], Predicate=" <<
Predicate <<
")\n");
325 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
326 assert(State.
MIs[InsnID]->getOpcode() == TargetOpcode::G_FCONSTANT &&
327 "Expected G_FCONSTANT");
328 assert(State.
MIs[InsnID]->getOperand(1).isFPImm() &&
"Expected FPImm operand");
330 APFloat Value = State.
MIs[InsnID]->getOperand(1).getFPImm()->getValueAPF();
333 if (handleReject() == RejectAndGiveUp)
339 int64_t InsnID = MatchTable[CurrentIdx++];
343 <<
": GIM_CheckBuildVectorAll{Zeros|Ones}(MIs["
344 << InsnID <<
"])\n");
345 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
348 assert((
MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR ||
349 MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR_TRUNC) &&
350 "Expected G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC");
354 if (handleReject() == RejectAndGiveUp)
359 if (handleReject() == RejectAndGiveUp)
367 int64_t InsnID = MatchTable[CurrentIdx++];
368 int64_t
Predicate = MatchTable[CurrentIdx++];
371 << CurrentIdx <<
": GIM_CheckCxxPredicate(MIs["
372 << InsnID <<
"], Predicate=" <<
Predicate <<
")\n");
373 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
378 if (handleReject() == RejectAndGiveUp)
383 int64_t InsnID = MatchTable[CurrentIdx++];
386 dbgs() << CurrentIdx <<
": GIM_CheckAtomicOrdering(MIs["
387 << InsnID <<
"], " << (
uint64_t)Ordering <<
")\n");
388 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
389 if (!State.
MIs[InsnID]->hasOneMemOperand())
390 if (handleReject() == RejectAndGiveUp)
393 for (
const auto &MMO : State.
MIs[InsnID]->memoperands())
394 if (MMO->getMergedOrdering() != Ordering)
395 if (handleReject() == RejectAndGiveUp)
400 int64_t InsnID = MatchTable[CurrentIdx++];
404 <<
": GIM_CheckAtomicOrderingOrStrongerThan(MIs["
405 << InsnID <<
"], " << (
uint64_t)Ordering <<
")\n");
406 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
407 if (!State.
MIs[InsnID]->hasOneMemOperand())
408 if (handleReject() == RejectAndGiveUp)
411 for (
const auto &MMO : State.
MIs[InsnID]->memoperands())
413 if (handleReject() == RejectAndGiveUp)
418 int64_t InsnID = MatchTable[CurrentIdx++];
422 <<
": GIM_CheckAtomicOrderingWeakerThan(MIs["
423 << InsnID <<
"], " << (
uint64_t)Ordering <<
")\n");
424 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
425 if (!State.
MIs[InsnID]->hasOneMemOperand())
426 if (handleReject() == RejectAndGiveUp)
429 for (
const auto &MMO : State.
MIs[InsnID]->memoperands())
431 if (handleReject() == RejectAndGiveUp)
436 int64_t InsnID = MatchTable[CurrentIdx++];
437 int64_t MMOIdx = MatchTable[CurrentIdx++];
439 const int NumAddrSpace = MatchTable[CurrentIdx++];
441 if (State.
MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
442 if (handleReject() == RejectAndGiveUp)
449 const uint64_t LastIdx = CurrentIdx + NumAddrSpace;
452 = *(State.
MIs[InsnID]->memoperands_begin() + MMOIdx);
456 for (
int I = 0;
I != NumAddrSpace; ++
I) {
457 unsigned AddrSpace = MatchTable[CurrentIdx++];
460 dbgs() <<
"addrspace(" << MMOAddrSpace <<
") vs "
461 << AddrSpace <<
'\n');
463 if (AddrSpace == MMOAddrSpace) {
469 CurrentIdx = LastIdx;
470 if (!
Success && handleReject() == RejectAndGiveUp)
475 int64_t InsnID = MatchTable[CurrentIdx++];
476 int64_t MMOIdx = MatchTable[CurrentIdx++];
477 unsigned MinAlign = MatchTable[CurrentIdx++];
479 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
481 if (State.
MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
482 if (handleReject() == RejectAndGiveUp)
488 = *(State.
MIs[InsnID]->memoperands_begin() + MMOIdx);
490 dbgs() << CurrentIdx <<
": GIM_CheckMemoryAlignment"
491 <<
"(MIs[" << InsnID <<
"]->memoperands() + " << MMOIdx
492 <<
")->getAlignment() >= " <<
MinAlign <<
")\n");
499 int64_t InsnID = MatchTable[CurrentIdx++];
500 int64_t MMOIdx = MatchTable[CurrentIdx++];
501 uint64_t Size = MatchTable[CurrentIdx++];
505 <<
": GIM_CheckMemorySizeEqual(MIs[" << InsnID
506 <<
"]->memoperands() + " << MMOIdx
507 <<
", Size=" << Size <<
")\n");
508 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
510 if (State.
MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
511 if (handleReject() == RejectAndGiveUp)
522 if (handleReject() == RejectAndGiveUp)
530 int64_t InsnID = MatchTable[CurrentIdx++];
531 int64_t MMOIdx = MatchTable[CurrentIdx++];
532 int64_t OpIdx = MatchTable[CurrentIdx++];
536 dbgs() << CurrentIdx <<
": GIM_CheckMemorySize"
542 <<
"LLT(MIs[" << InsnID <<
"]->memoperands() + " << MMOIdx
543 <<
", OpIdx=" << OpIdx <<
")\n");
544 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
549 dbgs() << CurrentIdx <<
": Not a register\n");
550 if (handleReject() == RejectAndGiveUp)
555 if (State.
MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
556 if (handleReject() == RejectAndGiveUp)
563 unsigned Size =
MRI.getType(MO.
getReg()).getSizeInBits();
566 if (handleReject() == RejectAndGiveUp)
570 if (handleReject() == RejectAndGiveUp)
574 if (handleReject() == RejectAndGiveUp)
580 int64_t InsnID = MatchTable[CurrentIdx++];
581 int64_t OpIdx = MatchTable[CurrentIdx++];
582 int64_t
TypeID = MatchTable[CurrentIdx++];
584 dbgs() << CurrentIdx <<
": GIM_CheckType(MIs[" << InsnID
585 <<
"]->getOperand(" << OpIdx
586 <<
"), TypeID=" <<
TypeID <<
")\n");
587 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
591 if (handleReject() == RejectAndGiveUp)
597 int64_t InsnID = MatchTable[CurrentIdx++];
598 int64_t OpIdx = MatchTable[CurrentIdx++];
599 uint64_t SizeInBits = MatchTable[CurrentIdx++];
602 dbgs() << CurrentIdx <<
": GIM_CheckPointerToAny(MIs["
603 << InsnID <<
"]->getOperand(" << OpIdx
604 <<
"), SizeInBits=" << SizeInBits <<
")\n");
605 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
610 if (SizeInBits == 0) {
616 assert(SizeInBits != 0 &&
"Pointer size must be known");
620 if (handleReject() == RejectAndGiveUp)
622 }
else if (handleReject() == RejectAndGiveUp)
628 int64_t InsnID = MatchTable[CurrentIdx++];
629 int64_t OpIdx = MatchTable[CurrentIdx++];
630 uint64_t StoreIdx = MatchTable[CurrentIdx++];
633 dbgs() << CurrentIdx <<
": GIM_RecordNamedOperand(MIs["
634 << InsnID <<
"]->getOperand(" << OpIdx
635 <<
"), StoreIdx=" << StoreIdx <<
")\n");
636 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
642 int64_t InsnID = MatchTable[CurrentIdx++];
643 int64_t OpIdx = MatchTable[CurrentIdx++];
644 int64_t RCEnum = MatchTable[CurrentIdx++];
646 dbgs() << CurrentIdx <<
": GIM_CheckRegBankForClass(MIs["
647 << InsnID <<
"]->getOperand(" << OpIdx
648 <<
"), RCEnum=" << RCEnum <<
")\n");
649 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
655 if (handleReject() == RejectAndGiveUp)
662 int64_t InsnID = MatchTable[CurrentIdx++];
663 int64_t OpIdx = MatchTable[CurrentIdx++];
664 int64_t RendererID = MatchTable[CurrentIdx++];
665 int64_t ComplexPredicateID = MatchTable[CurrentIdx++];
667 dbgs() << CurrentIdx <<
": State.Renderers[" << RendererID
668 <<
"] = GIM_CheckComplexPattern(MIs[" << InsnID
669 <<
"]->getOperand(" << OpIdx
670 <<
"), ComplexPredicateID=" << ComplexPredicateID
672 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
676 State.
MIs[InsnID]->getOperand(OpIdx));
680 if (handleReject() == RejectAndGiveUp)
686 int64_t InsnID = MatchTable[CurrentIdx++];
687 int64_t OpIdx = MatchTable[CurrentIdx++];
688 int64_t
Value = MatchTable[CurrentIdx++];
690 dbgs() << CurrentIdx <<
": GIM_CheckConstantInt(MIs["
691 << InsnID <<
"]->getOperand(" << OpIdx
692 <<
"), Value=" <<
Value <<
")\n");
693 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
701 if (handleReject() == RejectAndGiveUp)
704 }
else if (handleReject() == RejectAndGiveUp)
711 int64_t InsnID = MatchTable[CurrentIdx++];
712 int64_t OpIdx = MatchTable[CurrentIdx++];
713 int64_t
Value = MatchTable[CurrentIdx++];
715 dbgs() << CurrentIdx <<
": GIM_CheckLiteralInt(MIs["
716 << InsnID <<
"]->getOperand(" << OpIdx
717 <<
"), Value=" <<
Value <<
")\n");
718 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
726 if (handleReject() == RejectAndGiveUp)
733 int64_t InsnID = MatchTable[CurrentIdx++];
734 int64_t OpIdx = MatchTable[CurrentIdx++];
735 int64_t
Value = MatchTable[CurrentIdx++];
737 dbgs() << CurrentIdx <<
": GIM_CheckIntrinsicID(MIs["
738 << InsnID <<
"]->getOperand(" << OpIdx
739 <<
"), Value=" <<
Value <<
")\n");
740 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
743 if (handleReject() == RejectAndGiveUp)
748 int64_t InsnID = MatchTable[CurrentIdx++];
749 int64_t OpIdx = MatchTable[CurrentIdx++];
750 int64_t
Value = MatchTable[CurrentIdx++];
752 dbgs() << CurrentIdx <<
": GIM_CheckCmpPredicate(MIs["
753 << InsnID <<
"]->getOperand(" << OpIdx
754 <<
"), Value=" <<
Value <<
")\n");
755 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
758 if (handleReject() == RejectAndGiveUp)
763 int64_t InsnID = MatchTable[CurrentIdx++];
764 int64_t OpIdx = MatchTable[CurrentIdx++];
766 dbgs() << CurrentIdx <<
": GIM_CheckIsMBB(MIs[" << InsnID
767 <<
"]->getOperand(" << OpIdx <<
"))\n");
768 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
769 if (!State.
MIs[InsnID]->getOperand(OpIdx).isMBB()) {
770 if (handleReject() == RejectAndGiveUp)
776 int64_t InsnID = MatchTable[CurrentIdx++];
777 int64_t OpIdx = MatchTable[CurrentIdx++];
779 dbgs() << CurrentIdx <<
": GIM_CheckIsImm(MIs[" << InsnID
780 <<
"]->getOperand(" << OpIdx <<
"))\n");
781 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
782 if (!State.
MIs[InsnID]->getOperand(OpIdx).isImm()) {
783 if (handleReject() == RejectAndGiveUp)
789 int64_t InsnID = MatchTable[CurrentIdx++];
791 dbgs() << CurrentIdx <<
": GIM_CheckIsSafeToFold(MIs["
792 << InsnID <<
"])\n");
793 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
795 if (handleReject() == RejectAndGiveUp)
801 int64_t InsnID = MatchTable[CurrentIdx++];
802 int64_t OpIdx = MatchTable[CurrentIdx++];
803 int64_t OtherInsnID = MatchTable[CurrentIdx++];
804 int64_t OtherOpIdx = MatchTable[CurrentIdx++];
806 dbgs() << CurrentIdx <<
": GIM_CheckIsSameOperand(MIs["
807 << InsnID <<
"][" << OpIdx <<
"], MIs["
808 << OtherInsnID <<
"][" << OtherOpIdx <<
"])\n");
809 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
810 assert(State.
MIs[OtherInsnID] !=
nullptr &&
"Used insn before defined");
811 if (!State.
MIs[InsnID]->getOperand(OpIdx).isIdenticalTo(
812 State.
MIs[OtherInsnID]->getOperand(OtherOpIdx))) {
813 if (handleReject() == RejectAndGiveUp)
820 dbgs() << CurrentIdx <<
": GIM_Reject\n");
821 if (handleReject() == RejectAndGiveUp)
826 int64_t OldInsnID = MatchTable[CurrentIdx++];
827 uint64_t NewInsnID = MatchTable[CurrentIdx++];
828 int64_t NewOpcode = MatchTable[CurrentIdx++];
829 if (NewInsnID >= OutMIs.size())
830 OutMIs.
resize(NewInsnID + 1);
833 State.
MIs[OldInsnID]);
834 OutMIs[NewInsnID]->setDesc(
TII.get(NewOpcode));
836 dbgs() << CurrentIdx <<
": GIR_MutateOpcode(OutMIs["
837 << NewInsnID <<
"], MIs[" << OldInsnID <<
"], "
838 << NewOpcode <<
")\n");
843 uint64_t NewInsnID = MatchTable[CurrentIdx++];
844 int64_t Opcode = MatchTable[CurrentIdx++];
845 if (NewInsnID >= OutMIs.size())
846 OutMIs.
resize(NewInsnID + 1);
848 OutMIs[NewInsnID] =
BuildMI(*State.
MIs[0]->getParent(), State.
MIs[0],
849 State.
MIs[0]->getDebugLoc(),
TII.get(Opcode));
851 dbgs() << CurrentIdx <<
": GIR_BuildMI(OutMIs["
852 << NewInsnID <<
"], " << Opcode <<
")\n");
857 int64_t NewInsnID = MatchTable[CurrentIdx++];
858 int64_t OldInsnID = MatchTable[CurrentIdx++];
859 int64_t OpIdx = MatchTable[CurrentIdx++];
860 assert(OutMIs[NewInsnID] &&
"Attempted to add to undefined instruction");
861 OutMIs[NewInsnID].add(State.
MIs[OldInsnID]->getOperand(OpIdx));
864 << CurrentIdx <<
": GIR_Copy(OutMIs[" << NewInsnID
865 <<
"], MIs[" << OldInsnID <<
"], " << OpIdx <<
")\n");
870 int64_t NewInsnID = MatchTable[CurrentIdx++];
871 int64_t OldInsnID = MatchTable[CurrentIdx++];
872 int64_t OpIdx = MatchTable[CurrentIdx++];
873 int64_t ZeroReg = MatchTable[CurrentIdx++];
874 assert(OutMIs[NewInsnID] &&
"Attempted to add to undefined instruction");
877 OutMIs[NewInsnID].addReg(ZeroReg);
879 OutMIs[NewInsnID].add(MO);
881 dbgs() << CurrentIdx <<
": GIR_CopyOrAddZeroReg(OutMIs["
882 << NewInsnID <<
"], MIs[" << OldInsnID <<
"], "
883 << OpIdx <<
", " << ZeroReg <<
")\n");
888 int64_t NewInsnID = MatchTable[CurrentIdx++];
889 int64_t OldInsnID = MatchTable[CurrentIdx++];
890 int64_t OpIdx = MatchTable[CurrentIdx++];
891 int64_t SubRegIdx = MatchTable[CurrentIdx++];
892 assert(OutMIs[NewInsnID] &&
"Attempted to add to undefined instruction");
893 OutMIs[NewInsnID].addReg(State.
MIs[OldInsnID]->getOperand(OpIdx).getReg(),
896 dbgs() << CurrentIdx <<
": GIR_CopySubReg(OutMIs["
897 << NewInsnID <<
"], MIs[" << OldInsnID <<
"], "
898 << OpIdx <<
", " << SubRegIdx <<
")\n");
903 int64_t InsnID = MatchTable[CurrentIdx++];
904 int64_t RegNum = MatchTable[CurrentIdx++];
905 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
908 dbgs() << CurrentIdx <<
": GIR_AddImplicitDef(OutMIs["
909 << InsnID <<
"], " << RegNum <<
")\n");
914 int64_t InsnID = MatchTable[CurrentIdx++];
915 int64_t RegNum = MatchTable[CurrentIdx++];
916 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
919 dbgs() << CurrentIdx <<
": GIR_AddImplicitUse(OutMIs["
920 << InsnID <<
"], " << RegNum <<
")\n");
925 int64_t InsnID = MatchTable[CurrentIdx++];
926 int64_t RegNum = MatchTable[CurrentIdx++];
927 uint64_t RegFlags = MatchTable[CurrentIdx++];
928 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
929 OutMIs[InsnID].addReg(RegNum, RegFlags);
932 dbgs() << CurrentIdx <<
": GIR_AddRegister(OutMIs["
933 << InsnID <<
"], " << RegNum <<
", " << RegFlags <<
")\n");
939 int64_t InsnID = MatchTable[CurrentIdx++];
940 int64_t TempRegID = MatchTable[CurrentIdx++];
941 uint64_t TempRegFlags = MatchTable[CurrentIdx++];
944 SubReg = MatchTable[CurrentIdx++];
946 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
950 dbgs() << CurrentIdx <<
": GIR_AddTempRegister(OutMIs["
951 << InsnID <<
"], TempRegisters[" << TempRegID
955 dbgs() <<
", " << TempRegFlags <<
")\n");
960 int64_t InsnID = MatchTable[CurrentIdx++];
961 int64_t Imm = MatchTable[CurrentIdx++];
962 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
963 OutMIs[InsnID].addImm(Imm);
965 dbgs() << CurrentIdx <<
": GIR_AddImm(OutMIs[" << InsnID
966 <<
"], " << Imm <<
")\n");
971 int64_t InsnID = MatchTable[CurrentIdx++];
972 int64_t RendererID = MatchTable[CurrentIdx++];
973 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
974 for (
const auto &RenderOpFn : State.
Renderers[RendererID])
975 RenderOpFn(OutMIs[InsnID]);
977 dbgs() << CurrentIdx <<
": GIR_ComplexRenderer(OutMIs["
978 << InsnID <<
"], " << RendererID <<
")\n");
982 int64_t InsnID = MatchTable[CurrentIdx++];
983 int64_t RendererID = MatchTable[CurrentIdx++];
984 int64_t RenderOpID = MatchTable[CurrentIdx++];
985 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
986 State.
Renderers[RendererID][RenderOpID](OutMIs[InsnID]);
989 <<
": GIR_ComplexSubOperandRenderer(OutMIs["
990 << InsnID <<
"], " << RendererID <<
", "
991 << RenderOpID <<
")\n");
996 int64_t NewInsnID = MatchTable[CurrentIdx++];
997 int64_t OldInsnID = MatchTable[CurrentIdx++];
998 assert(OutMIs[NewInsnID] &&
"Attempted to add to undefined instruction");
999 assert(State.
MIs[OldInsnID]->getOpcode() == TargetOpcode::G_CONSTANT &&
"Expected G_CONSTANT");
1000 if (State.
MIs[OldInsnID]->getOperand(1).isCImm()) {
1001 OutMIs[NewInsnID].addImm(
1002 State.
MIs[OldInsnID]->getOperand(1).getCImm()->getSExtValue());
1003 }
else if (State.
MIs[OldInsnID]->getOperand(1).isImm())
1004 OutMIs[NewInsnID].add(State.
MIs[OldInsnID]->getOperand(1));
1008 dbgs() << CurrentIdx <<
": GIR_CopyConstantAsSImm(OutMIs["
1009 << NewInsnID <<
"], MIs[" << OldInsnID <<
"])\n");
1015 int64_t NewInsnID = MatchTable[CurrentIdx++];
1016 int64_t OldInsnID = MatchTable[CurrentIdx++];
1017 assert(OutMIs[NewInsnID] &&
"Attempted to add to undefined instruction");
1018 assert(State.
MIs[OldInsnID]->getOpcode() == TargetOpcode::G_FCONSTANT &&
"Expected G_FCONSTANT");
1019 if (State.
MIs[OldInsnID]->getOperand(1).isFPImm())
1020 OutMIs[NewInsnID].addFPImm(
1021 State.
MIs[OldInsnID]->getOperand(1).getFPImm());
1025 dbgs() << CurrentIdx <<
": GIR_CopyFPConstantAsFPImm(OutMIs["
1026 << NewInsnID <<
"], MIs[" << OldInsnID <<
"])\n");
1031 int64_t InsnID = MatchTable[CurrentIdx++];
1032 int64_t OldInsnID = MatchTable[CurrentIdx++];
1033 int64_t RendererFnID = MatchTable[CurrentIdx++];
1034 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1036 dbgs() << CurrentIdx <<
": GIR_CustomRenderer(OutMIs["
1037 << InsnID <<
"], MIs[" << OldInsnID <<
"], "
1038 << RendererFnID <<
")\n");
1040 OutMIs[InsnID], *State.
MIs[OldInsnID],
1045 int64_t InsnID = MatchTable[CurrentIdx++];
1046 int64_t OldInsnID = MatchTable[CurrentIdx++];
1047 int64_t OpIdx = MatchTable[CurrentIdx++];
1048 int64_t RendererFnID = MatchTable[CurrentIdx++];
1049 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1053 dbgs() << CurrentIdx <<
": GIR_CustomOperandRenderer(OutMIs["
1054 << InsnID <<
"], MIs[" << OldInsnID <<
"]->getOperand("
1056 << RendererFnID <<
")\n");
1058 *State.
MIs[OldInsnID],
1063 int64_t InsnID = MatchTable[CurrentIdx++];
1064 int64_t OpIdx = MatchTable[CurrentIdx++];
1065 int64_t RCEnum = MatchTable[CurrentIdx++];
1066 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1074 dbgs() << CurrentIdx <<
": GIR_ConstrainOperandRC(OutMIs["
1075 << InsnID <<
"], " << OpIdx <<
", " << RCEnum
1081 int64_t InsnID = MatchTable[CurrentIdx++];
1082 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1086 dbgs() << CurrentIdx
1087 <<
": GIR_ConstrainSelectedInstOperands(OutMIs["
1088 << InsnID <<
"])\n");
1093 int64_t InsnID = MatchTable[CurrentIdx++];
1094 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1097 dbgs() << CurrentIdx <<
": GIR_MergeMemOperands(OutMIs["
1100 while ((MergeInsnID = MatchTable[CurrentIdx++]) !=
1103 dbgs() <<
", MIs[" << MergeInsnID <<
"]");
1104 for (
const auto &MMO : State.
MIs[MergeInsnID]->memoperands())
1105 OutMIs[InsnID].addMemOperand(MMO);
1112 int64_t InsnID = MatchTable[CurrentIdx++];
1114 "Attempted to erase an undefined instruction");
1115 State.
MIs[InsnID]->eraseFromParent();
1117 dbgs() << CurrentIdx <<
": GIR_EraseFromParent(MIs["
1118 << InsnID <<
"])\n");
1123 int64_t TempRegID = MatchTable[CurrentIdx++];
1124 int64_t
TypeID = MatchTable[CurrentIdx++];
1129 dbgs() << CurrentIdx <<
": TempRegs[" << TempRegID
1130 <<
"] = GIR_MakeTempReg(" <<
TypeID <<
")\n");
1135 int64_t RuleID = MatchTable[CurrentIdx++];
1140 << CurrentIdx <<
": GIR_Coverage(" << RuleID <<
")");
1146 dbgs() << CurrentIdx <<
": GIR_Done\n");
1147 propagateFlags(OutMIs);
1158 #endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H