LLVM  13.0.0git
InstructionSelectorImpl.h
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1 //===- llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file declares the API for the instruction selector.
10 /// This class is responsible for selecting machine instructions.
11 /// It's implemented by the target. It's used by the InstructionSelect pass.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
16 #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
17 
18 #include "llvm/ADT/SmallVector.h"
28 #include "llvm/IR/Constants.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/Support/Debug.h"
33 #include <cassert>
34 #include <cstddef>
35 #include <cstdint>
36 
37 namespace llvm {
38 
39 /// GlobalISel PatFrag Predicates
40 enum {
45 };
46 
47 template <class TgtInstructionSelector, class PredicateBitset,
48  class ComplexMatcherMemFn, class CustomRendererFn>
50  TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State,
52  &ISelInfo,
53  const int64_t *MatchTable, const TargetInstrInfo &TII,
55  const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures,
56  CodeGenCoverage &CoverageInfo) const {
57 
58  uint64_t CurrentIdx = 0;
59  SmallVector<uint64_t, 4> OnFailResumeAt;
60 
61  // Bypass the flag check on the instruction, and only look at the MCInstrDesc.
62  bool NoFPException = !State.MIs[0]->getDesc().mayRaiseFPException();
63 
64  const uint16_t Flags = State.MIs[0]->getFlags();
65 
66  enum RejectAction { RejectAndGiveUp, RejectAndResume };
67  auto handleReject = [&]() -> RejectAction {
69  dbgs() << CurrentIdx << ": Rejected\n");
70  if (OnFailResumeAt.empty())
71  return RejectAndGiveUp;
72  CurrentIdx = OnFailResumeAt.pop_back_val();
74  dbgs() << CurrentIdx << ": Resume at " << CurrentIdx << " ("
75  << OnFailResumeAt.size() << " try-blocks remain)\n");
76  return RejectAndResume;
77  };
78 
79  auto propagateFlags = [=](NewMIVector &OutMIs) {
80  for (auto MIB : OutMIs) {
81  // Set the NoFPExcept flag when no original matched instruction could
82  // raise an FP exception, but the new instruction potentially might.
83  uint16_t MIBFlags = Flags;
84  if (NoFPException && MIB->mayRaiseFPException())
85  MIBFlags |= MachineInstr::NoFPExcept;
86  MIB.setMIFlags(MIBFlags);
87  }
88 
89  return true;
90  };
91 
92  while (true) {
93  assert(CurrentIdx != ~0u && "Invalid MatchTable index");
94  int64_t MatcherOpcode = MatchTable[CurrentIdx++];
95  switch (MatcherOpcode) {
96  case GIM_Try: {
98  dbgs() << CurrentIdx << ": Begin try-block\n");
99  OnFailResumeAt.push_back(MatchTable[CurrentIdx++]);
100  break;
101  }
102 
103  case GIM_RecordInsn: {
104  int64_t NewInsnID = MatchTable[CurrentIdx++];
105  int64_t InsnID = MatchTable[CurrentIdx++];
106  int64_t OpIdx = MatchTable[CurrentIdx++];
107 
108  // As an optimisation we require that MIs[0] is always the root. Refuse
109  // any attempt to modify it.
110  assert(NewInsnID != 0 && "Refusing to modify MIs[0]");
111 
112  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
113  if (!MO.isReg()) {
115  dbgs() << CurrentIdx << ": Not a register\n");
116  if (handleReject() == RejectAndGiveUp)
117  return false;
118  break;
119  }
122  dbgs() << CurrentIdx << ": Is a physical register\n");
123  if (handleReject() == RejectAndGiveUp)
124  return false;
125  break;
126  }
127 
128  MachineInstr *NewMI = MRI.getVRegDef(MO.getReg());
129  if ((size_t)NewInsnID < State.MIs.size())
130  State.MIs[NewInsnID] = NewMI;
131  else {
132  assert((size_t)NewInsnID == State.MIs.size() &&
133  "Expected to store MIs in order");
134  State.MIs.push_back(NewMI);
135  }
137  dbgs() << CurrentIdx << ": MIs[" << NewInsnID
138  << "] = GIM_RecordInsn(" << InsnID << ", " << OpIdx
139  << ")\n");
140  break;
141  }
142 
143  case GIM_CheckFeatures: {
144  int64_t ExpectedBitsetID = MatchTable[CurrentIdx++];
146  dbgs() << CurrentIdx
147  << ": GIM_CheckFeatures(ExpectedBitsetID="
148  << ExpectedBitsetID << ")\n");
149  if ((AvailableFeatures & ISelInfo.FeatureBitsets[ExpectedBitsetID]) !=
150  ISelInfo.FeatureBitsets[ExpectedBitsetID]) {
151  if (handleReject() == RejectAndGiveUp)
152  return false;
153  }
154  break;
155  }
156 
157  case GIM_CheckOpcode:
159  int64_t InsnID = MatchTable[CurrentIdx++];
160  int64_t Expected0 = MatchTable[CurrentIdx++];
161  int64_t Expected1 = -1;
162  if (MatcherOpcode == GIM_CheckOpcodeIsEither)
163  Expected1 = MatchTable[CurrentIdx++];
164 
165  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
166  unsigned Opcode = State.MIs[InsnID]->getOpcode();
167 
169  dbgs() << CurrentIdx << ": GIM_CheckOpcode(MIs[" << InsnID
170  << "], ExpectedOpcode=" << Expected0;
171  if (MatcherOpcode == GIM_CheckOpcodeIsEither)
172  dbgs() << " || " << Expected1;
173  dbgs() << ") // Got=" << Opcode << "\n";
174  );
175 
176  if (Opcode != Expected0 && Opcode != Expected1) {
177  if (handleReject() == RejectAndGiveUp)
178  return false;
179  }
180  break;
181  }
182  case GIM_SwitchOpcode: {
183  int64_t InsnID = MatchTable[CurrentIdx++];
184  int64_t LowerBound = MatchTable[CurrentIdx++];
185  int64_t UpperBound = MatchTable[CurrentIdx++];
186  int64_t Default = MatchTable[CurrentIdx++];
187 
188  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
189  const int64_t Opcode = State.MIs[InsnID]->getOpcode();
190 
192  dbgs() << CurrentIdx << ": GIM_SwitchOpcode(MIs[" << InsnID << "], ["
193  << LowerBound << ", " << UpperBound << "), Default=" << Default
194  << ", JumpTable...) // Got=" << Opcode << "\n";
195  });
196  if (Opcode < LowerBound || UpperBound <= Opcode) {
197  CurrentIdx = Default;
198  break;
199  }
200  CurrentIdx = MatchTable[CurrentIdx + (Opcode - LowerBound)];
201  if (!CurrentIdx) {
202  CurrentIdx = Default;
203  break;
204  }
205  OnFailResumeAt.push_back(Default);
206  break;
207  }
208 
209  case GIM_SwitchType: {
210  int64_t InsnID = MatchTable[CurrentIdx++];
211  int64_t OpIdx = MatchTable[CurrentIdx++];
212  int64_t LowerBound = MatchTable[CurrentIdx++];
213  int64_t UpperBound = MatchTable[CurrentIdx++];
214  int64_t Default = MatchTable[CurrentIdx++];
215 
216  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
217  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
218 
220  dbgs() << CurrentIdx << ": GIM_SwitchType(MIs[" << InsnID
221  << "]->getOperand(" << OpIdx << "), [" << LowerBound << ", "
222  << UpperBound << "), Default=" << Default
223  << ", JumpTable...) // Got=";
224  if (!MO.isReg())
225  dbgs() << "Not a VReg\n";
226  else
227  dbgs() << MRI.getType(MO.getReg()) << "\n";
228  });
229  if (!MO.isReg()) {
230  CurrentIdx = Default;
231  break;
232  }
233  const LLT Ty = MRI.getType(MO.getReg());
234  const auto TyI = ISelInfo.TypeIDMap.find(Ty);
235  if (TyI == ISelInfo.TypeIDMap.end()) {
236  CurrentIdx = Default;
237  break;
238  }
239  const int64_t TypeID = TyI->second;
240  if (TypeID < LowerBound || UpperBound <= TypeID) {
241  CurrentIdx = Default;
242  break;
243  }
244  CurrentIdx = MatchTable[CurrentIdx + (TypeID - LowerBound)];
245  if (!CurrentIdx) {
246  CurrentIdx = Default;
247  break;
248  }
249  OnFailResumeAt.push_back(Default);
250  break;
251  }
252 
253  case GIM_CheckNumOperands: {
254  int64_t InsnID = MatchTable[CurrentIdx++];
255  int64_t Expected = MatchTable[CurrentIdx++];
257  dbgs() << CurrentIdx << ": GIM_CheckNumOperands(MIs["
258  << InsnID << "], Expected=" << Expected << ")\n");
259  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
260  if (State.MIs[InsnID]->getNumOperands() != Expected) {
261  if (handleReject() == RejectAndGiveUp)
262  return false;
263  }
264  break;
265  }
267  int64_t InsnID = MatchTable[CurrentIdx++];
268  int64_t Predicate = MatchTable[CurrentIdx++];
270  dbgs()
271  << CurrentIdx << ": GIM_CheckI64ImmPredicate(MIs["
272  << InsnID << "], Predicate=" << Predicate << ")\n");
273  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
274  assert(State.MIs[InsnID]->getOpcode() == TargetOpcode::G_CONSTANT &&
275  "Expected G_CONSTANT");
276  assert(Predicate > GIPFP_I64_Invalid && "Expected a valid predicate");
277  int64_t Value = 0;
278  if (State.MIs[InsnID]->getOperand(1).isCImm())
279  Value = State.MIs[InsnID]->getOperand(1).getCImm()->getSExtValue();
280  else if (State.MIs[InsnID]->getOperand(1).isImm())
281  Value = State.MIs[InsnID]->getOperand(1).getImm();
282  else
283  llvm_unreachable("Expected Imm or CImm operand");
284 
286  if (handleReject() == RejectAndGiveUp)
287  return false;
288  break;
289  }
291  int64_t InsnID = MatchTable[CurrentIdx++];
292  int64_t Predicate = MatchTable[CurrentIdx++];
294  dbgs()
295  << CurrentIdx << ": GIM_CheckAPIntImmPredicate(MIs["
296  << InsnID << "], Predicate=" << Predicate << ")\n");
297  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
298  assert(State.MIs[InsnID]->getOpcode() == TargetOpcode::G_CONSTANT &&
299  "Expected G_CONSTANT");
300  assert(Predicate > GIPFP_APInt_Invalid && "Expected a valid predicate");
301  APInt Value;
302  if (State.MIs[InsnID]->getOperand(1).isCImm())
303  Value = State.MIs[InsnID]->getOperand(1).getCImm()->getValue();
304  else
305  llvm_unreachable("Expected Imm or CImm operand");
306 
308  if (handleReject() == RejectAndGiveUp)
309  return false;
310  break;
311  }
313  int64_t InsnID = MatchTable[CurrentIdx++];
314  int64_t Predicate = MatchTable[CurrentIdx++];
316  dbgs()
317  << CurrentIdx << ": GIM_CheckAPFloatImmPredicate(MIs["
318  << InsnID << "], Predicate=" << Predicate << ")\n");
319  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
320  assert(State.MIs[InsnID]->getOpcode() == TargetOpcode::G_FCONSTANT &&
321  "Expected G_FCONSTANT");
322  assert(State.MIs[InsnID]->getOperand(1).isFPImm() && "Expected FPImm operand");
323  assert(Predicate > GIPFP_APFloat_Invalid && "Expected a valid predicate");
324  APFloat Value = State.MIs[InsnID]->getOperand(1).getFPImm()->getValueAPF();
325 
327  if (handleReject() == RejectAndGiveUp)
328  return false;
329  break;
330  }
333  int64_t InsnID = MatchTable[CurrentIdx++];
334 
336  dbgs() << CurrentIdx
337  << ": GIM_CheckBuildVectorAll{Zeros|Ones}(MIs["
338  << InsnID << "])\n");
339  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
340 
341  const MachineInstr *MI = State.MIs[InsnID];
342  assert((MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR ||
343  MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR_TRUNC) &&
344  "Expected G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC");
345 
346  if (MatcherOpcode == GIM_CheckIsBuildVectorAllOnes) {
347  if (!isBuildVectorAllOnes(*MI, MRI)) {
348  if (handleReject() == RejectAndGiveUp)
349  return false;
350  }
351  } else {
352  if (!isBuildVectorAllZeros(*MI, MRI)) {
353  if (handleReject() == RejectAndGiveUp)
354  return false;
355  }
356  }
357 
358  break;
359  }
361  int64_t InsnID = MatchTable[CurrentIdx++];
362  int64_t Predicate = MatchTable[CurrentIdx++];
364  dbgs()
365  << CurrentIdx << ": GIM_CheckCxxPredicate(MIs["
366  << InsnID << "], Predicate=" << Predicate << ")\n");
367  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
368  assert(Predicate > GIPFP_MI_Invalid && "Expected a valid predicate");
369 
370  if (!testMIPredicate_MI(Predicate, *State.MIs[InsnID],
371  State.RecordedOperands))
372  if (handleReject() == RejectAndGiveUp)
373  return false;
374  break;
375  }
377  int64_t InsnID = MatchTable[CurrentIdx++];
378  AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
380  dbgs() << CurrentIdx << ": GIM_CheckAtomicOrdering(MIs["
381  << InsnID << "], " << (uint64_t)Ordering << ")\n");
382  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
383  if (!State.MIs[InsnID]->hasOneMemOperand())
384  if (handleReject() == RejectAndGiveUp)
385  return false;
386 
387  for (const auto &MMO : State.MIs[InsnID]->memoperands())
388  if (MMO->getOrdering() != Ordering)
389  if (handleReject() == RejectAndGiveUp)
390  return false;
391  break;
392  }
394  int64_t InsnID = MatchTable[CurrentIdx++];
395  AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
397  dbgs() << CurrentIdx
398  << ": GIM_CheckAtomicOrderingOrStrongerThan(MIs["
399  << InsnID << "], " << (uint64_t)Ordering << ")\n");
400  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
401  if (!State.MIs[InsnID]->hasOneMemOperand())
402  if (handleReject() == RejectAndGiveUp)
403  return false;
404 
405  for (const auto &MMO : State.MIs[InsnID]->memoperands())
406  if (!isAtLeastOrStrongerThan(MMO->getOrdering(), Ordering))
407  if (handleReject() == RejectAndGiveUp)
408  return false;
409  break;
410  }
412  int64_t InsnID = MatchTable[CurrentIdx++];
413  AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
415  dbgs() << CurrentIdx
416  << ": GIM_CheckAtomicOrderingWeakerThan(MIs["
417  << InsnID << "], " << (uint64_t)Ordering << ")\n");
418  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
419  if (!State.MIs[InsnID]->hasOneMemOperand())
420  if (handleReject() == RejectAndGiveUp)
421  return false;
422 
423  for (const auto &MMO : State.MIs[InsnID]->memoperands())
424  if (!isStrongerThan(Ordering, MMO->getOrdering()))
425  if (handleReject() == RejectAndGiveUp)
426  return false;
427  break;
428  }
430  int64_t InsnID = MatchTable[CurrentIdx++];
431  int64_t MMOIdx = MatchTable[CurrentIdx++];
432  // This accepts a list of possible address spaces.
433  const int NumAddrSpace = MatchTable[CurrentIdx++];
434 
435  if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
436  if (handleReject() == RejectAndGiveUp)
437  return false;
438  break;
439  }
440 
441  // Need to still jump to the end of the list of address spaces if we find
442  // a match earlier.
443  const uint64_t LastIdx = CurrentIdx + NumAddrSpace;
444 
445  const MachineMemOperand *MMO
446  = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
447  const unsigned MMOAddrSpace = MMO->getAddrSpace();
448 
449  bool Success = false;
450  for (int I = 0; I != NumAddrSpace; ++I) {
451  unsigned AddrSpace = MatchTable[CurrentIdx++];
454  dbgs() << "addrspace(" << MMOAddrSpace << ") vs "
455  << AddrSpace << '\n');
456 
457  if (AddrSpace == MMOAddrSpace) {
458  Success = true;
459  break;
460  }
461  }
462 
463  CurrentIdx = LastIdx;
464  if (!Success && handleReject() == RejectAndGiveUp)
465  return false;
466  break;
467  }
469  int64_t InsnID = MatchTable[CurrentIdx++];
470  int64_t MMOIdx = MatchTable[CurrentIdx++];
471  unsigned MinAlign = MatchTable[CurrentIdx++];
472 
473  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
474 
475  if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
476  if (handleReject() == RejectAndGiveUp)
477  return false;
478  break;
479  }
480 
481  MachineMemOperand *MMO
482  = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
484  dbgs() << CurrentIdx << ": GIM_CheckMemoryAlignment"
485  << "(MIs[" << InsnID << "]->memoperands() + " << MMOIdx
486  << ")->getAlignment() >= " << MinAlign << ")\n");
487  if (MMO->getAlign() < MinAlign && handleReject() == RejectAndGiveUp)
488  return false;
489 
490  break;
491  }
493  int64_t InsnID = MatchTable[CurrentIdx++];
494  int64_t MMOIdx = MatchTable[CurrentIdx++];
495  uint64_t Size = MatchTable[CurrentIdx++];
496 
498  dbgs() << CurrentIdx
499  << ": GIM_CheckMemorySizeEqual(MIs[" << InsnID
500  << "]->memoperands() + " << MMOIdx
501  << ", Size=" << Size << ")\n");
502  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
503 
504  if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
505  if (handleReject() == RejectAndGiveUp)
506  return false;
507  break;
508  }
509 
510  MachineMemOperand *MMO = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
511 
513  dbgs() << MMO->getSize() << " bytes vs " << Size
514  << " bytes\n");
515  if (MMO->getSize() != Size)
516  if (handleReject() == RejectAndGiveUp)
517  return false;
518 
519  break;
520  }
524  int64_t InsnID = MatchTable[CurrentIdx++];
525  int64_t MMOIdx = MatchTable[CurrentIdx++];
526  int64_t OpIdx = MatchTable[CurrentIdx++];
527 
530  dbgs() << CurrentIdx << ": GIM_CheckMemorySize"
531  << (MatcherOpcode == GIM_CheckMemorySizeEqualToLLT
532  ? "EqualTo"
533  : MatcherOpcode == GIM_CheckMemorySizeGreaterThanLLT
534  ? "GreaterThan"
535  : "LessThan")
536  << "LLT(MIs[" << InsnID << "]->memoperands() + " << MMOIdx
537  << ", OpIdx=" << OpIdx << ")\n");
538  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
539 
540  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
541  if (!MO.isReg()) {
543  dbgs() << CurrentIdx << ": Not a register\n");
544  if (handleReject() == RejectAndGiveUp)
545  return false;
546  break;
547  }
548 
549  if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
550  if (handleReject() == RejectAndGiveUp)
551  return false;
552  break;
553  }
554 
555  MachineMemOperand *MMO = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
556 
557  unsigned Size = MRI.getType(MO.getReg()).getSizeInBits();
558  if (MatcherOpcode == GIM_CheckMemorySizeEqualToLLT &&
559  MMO->getSizeInBits() != Size) {
560  if (handleReject() == RejectAndGiveUp)
561  return false;
562  } else if (MatcherOpcode == GIM_CheckMemorySizeLessThanLLT &&
563  MMO->getSizeInBits() >= Size) {
564  if (handleReject() == RejectAndGiveUp)
565  return false;
566  } else if (MatcherOpcode == GIM_CheckMemorySizeGreaterThanLLT &&
567  MMO->getSizeInBits() <= Size)
568  if (handleReject() == RejectAndGiveUp)
569  return false;
570 
571  break;
572  }
573  case GIM_CheckType: {
574  int64_t InsnID = MatchTable[CurrentIdx++];
575  int64_t OpIdx = MatchTable[CurrentIdx++];
576  int64_t TypeID = MatchTable[CurrentIdx++];
578  dbgs() << CurrentIdx << ": GIM_CheckType(MIs[" << InsnID
579  << "]->getOperand(" << OpIdx
580  << "), TypeID=" << TypeID << ")\n");
581  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
582  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
583  if (!MO.isReg() ||
584  MRI.getType(MO.getReg()) != ISelInfo.TypeObjects[TypeID]) {
585  if (handleReject() == RejectAndGiveUp)
586  return false;
587  }
588  break;
589  }
590  case GIM_CheckPointerToAny: {
591  int64_t InsnID = MatchTable[CurrentIdx++];
592  int64_t OpIdx = MatchTable[CurrentIdx++];
593  int64_t SizeInBits = MatchTable[CurrentIdx++];
594 
596  dbgs() << CurrentIdx << ": GIM_CheckPointerToAny(MIs["
597  << InsnID << "]->getOperand(" << OpIdx
598  << "), SizeInBits=" << SizeInBits << ")\n");
599  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
600  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
601  const LLT Ty = MRI.getType(MO.getReg());
602 
603  // iPTR must be looked up in the target.
604  if (SizeInBits == 0) {
605  MachineFunction *MF = State.MIs[InsnID]->getParent()->getParent();
606  const unsigned AddrSpace = Ty.getAddressSpace();
607  SizeInBits = MF->getDataLayout().getPointerSizeInBits(AddrSpace);
608  }
609 
610  assert(SizeInBits != 0 && "Pointer size must be known");
611 
612  if (MO.isReg()) {
613  if (!Ty.isPointer() || Ty.getSizeInBits() != SizeInBits)
614  if (handleReject() == RejectAndGiveUp)
615  return false;
616  } else if (handleReject() == RejectAndGiveUp)
617  return false;
618 
619  break;
620  }
621  case GIM_RecordNamedOperand: {
622  int64_t InsnID = MatchTable[CurrentIdx++];
623  int64_t OpIdx = MatchTable[CurrentIdx++];
624  uint64_t StoreIdx = MatchTable[CurrentIdx++];
625 
627  dbgs() << CurrentIdx << ": GIM_RecordNamedOperand(MIs["
628  << InsnID << "]->getOperand(" << OpIdx
629  << "), StoreIdx=" << StoreIdx << ")\n");
630  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
631  assert(StoreIdx < State.RecordedOperands.size() && "Index out of range");
632  State.RecordedOperands[StoreIdx] = &State.MIs[InsnID]->getOperand(OpIdx);
633  break;
634  }
636  int64_t InsnID = MatchTable[CurrentIdx++];
637  int64_t OpIdx = MatchTable[CurrentIdx++];
638  int64_t RCEnum = MatchTable[CurrentIdx++];
640  dbgs() << CurrentIdx << ": GIM_CheckRegBankForClass(MIs["
641  << InsnID << "]->getOperand(" << OpIdx
642  << "), RCEnum=" << RCEnum << ")\n");
643  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
644  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
645  if (!MO.isReg() ||
646  &RBI.getRegBankFromRegClass(*TRI.getRegClass(RCEnum),
647  MRI.getType(MO.getReg())) !=
648  RBI.getRegBank(MO.getReg(), MRI, TRI)) {
649  if (handleReject() == RejectAndGiveUp)
650  return false;
651  }
652  break;
653  }
654 
656  int64_t InsnID = MatchTable[CurrentIdx++];
657  int64_t OpIdx = MatchTable[CurrentIdx++];
658  int64_t RendererID = MatchTable[CurrentIdx++];
659  int64_t ComplexPredicateID = MatchTable[CurrentIdx++];
661  dbgs() << CurrentIdx << ": State.Renderers[" << RendererID
662  << "] = GIM_CheckComplexPattern(MIs[" << InsnID
663  << "]->getOperand(" << OpIdx
664  << "), ComplexPredicateID=" << ComplexPredicateID
665  << ")\n");
666  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
667  // FIXME: Use std::invoke() when it's available.
668  ComplexRendererFns Renderer =
669  (ISel.*ISelInfo.ComplexPredicates[ComplexPredicateID])(
670  State.MIs[InsnID]->getOperand(OpIdx));
671  if (Renderer.hasValue())
672  State.Renderers[RendererID] = Renderer.getValue();
673  else
674  if (handleReject() == RejectAndGiveUp)
675  return false;
676  break;
677  }
678 
679  case GIM_CheckConstantInt: {
680  int64_t InsnID = MatchTable[CurrentIdx++];
681  int64_t OpIdx = MatchTable[CurrentIdx++];
682  int64_t Value = MatchTable[CurrentIdx++];
684  dbgs() << CurrentIdx << ": GIM_CheckConstantInt(MIs["
685  << InsnID << "]->getOperand(" << OpIdx
686  << "), Value=" << Value << ")\n");
687  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
688  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
689  if (MO.isReg()) {
690  // isOperandImmEqual() will sign-extend to 64-bits, so should we.
691  LLT Ty = MRI.getType(MO.getReg());
693 
694  if (!isOperandImmEqual(MO, Value, MRI)) {
695  if (handleReject() == RejectAndGiveUp)
696  return false;
697  }
698  } else if (handleReject() == RejectAndGiveUp)
699  return false;
700 
701  break;
702  }
703 
704  case GIM_CheckLiteralInt: {
705  int64_t InsnID = MatchTable[CurrentIdx++];
706  int64_t OpIdx = MatchTable[CurrentIdx++];
707  int64_t Value = MatchTable[CurrentIdx++];
709  dbgs() << CurrentIdx << ": GIM_CheckLiteralInt(MIs["
710  << InsnID << "]->getOperand(" << OpIdx
711  << "), Value=" << Value << ")\n");
712  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
713  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
714  if (MO.isImm() && MO.getImm() == Value)
715  break;
716 
717  if (MO.isCImm() && MO.getCImm()->equalsInt(Value))
718  break;
719 
720  if (handleReject() == RejectAndGiveUp)
721  return false;
722 
723  break;
724  }
725 
726  case GIM_CheckIntrinsicID: {
727  int64_t InsnID = MatchTable[CurrentIdx++];
728  int64_t OpIdx = MatchTable[CurrentIdx++];
729  int64_t Value = MatchTable[CurrentIdx++];
731  dbgs() << CurrentIdx << ": GIM_CheckIntrinsicID(MIs["
732  << InsnID << "]->getOperand(" << OpIdx
733  << "), Value=" << Value << ")\n");
734  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
735  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
736  if (!MO.isIntrinsicID() || MO.getIntrinsicID() != Value)
737  if (handleReject() == RejectAndGiveUp)
738  return false;
739  break;
740  }
741  case GIM_CheckCmpPredicate: {
742  int64_t InsnID = MatchTable[CurrentIdx++];
743  int64_t OpIdx = MatchTable[CurrentIdx++];
744  int64_t Value = MatchTable[CurrentIdx++];
746  dbgs() << CurrentIdx << ": GIM_CheckCmpPredicate(MIs["
747  << InsnID << "]->getOperand(" << OpIdx
748  << "), Value=" << Value << ")\n");
749  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
750  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
751  if (!MO.isPredicate() || MO.getPredicate() != Value)
752  if (handleReject() == RejectAndGiveUp)
753  return false;
754  break;
755  }
756  case GIM_CheckIsMBB: {
757  int64_t InsnID = MatchTable[CurrentIdx++];
758  int64_t OpIdx = MatchTable[CurrentIdx++];
760  dbgs() << CurrentIdx << ": GIM_CheckIsMBB(MIs[" << InsnID
761  << "]->getOperand(" << OpIdx << "))\n");
762  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
763  if (!State.MIs[InsnID]->getOperand(OpIdx).isMBB()) {
764  if (handleReject() == RejectAndGiveUp)
765  return false;
766  }
767  break;
768  }
769  case GIM_CheckIsImm: {
770  int64_t InsnID = MatchTable[CurrentIdx++];
771  int64_t OpIdx = MatchTable[CurrentIdx++];
773  dbgs() << CurrentIdx << ": GIM_CheckIsImm(MIs[" << InsnID
774  << "]->getOperand(" << OpIdx << "))\n");
775  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
776  if (!State.MIs[InsnID]->getOperand(OpIdx).isImm()) {
777  if (handleReject() == RejectAndGiveUp)
778  return false;
779  }
780  break;
781  }
782  case GIM_CheckIsSafeToFold: {
783  int64_t InsnID = MatchTable[CurrentIdx++];
785  dbgs() << CurrentIdx << ": GIM_CheckIsSafeToFold(MIs["
786  << InsnID << "])\n");
787  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
788  if (!isObviouslySafeToFold(*State.MIs[InsnID], *State.MIs[0])) {
789  if (handleReject() == RejectAndGiveUp)
790  return false;
791  }
792  break;
793  }
794  case GIM_CheckIsSameOperand: {
795  int64_t InsnID = MatchTable[CurrentIdx++];
796  int64_t OpIdx = MatchTable[CurrentIdx++];
797  int64_t OtherInsnID = MatchTable[CurrentIdx++];
798  int64_t OtherOpIdx = MatchTable[CurrentIdx++];
800  dbgs() << CurrentIdx << ": GIM_CheckIsSameOperand(MIs["
801  << InsnID << "][" << OpIdx << "], MIs["
802  << OtherInsnID << "][" << OtherOpIdx << "])\n");
803  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
804  assert(State.MIs[OtherInsnID] != nullptr && "Used insn before defined");
805  if (!State.MIs[InsnID]->getOperand(OpIdx).isIdenticalTo(
806  State.MIs[OtherInsnID]->getOperand(OtherOpIdx))) {
807  if (handleReject() == RejectAndGiveUp)
808  return false;
809  }
810  break;
811  }
812  case GIM_Reject:
814  dbgs() << CurrentIdx << ": GIM_Reject\n");
815  if (handleReject() == RejectAndGiveUp)
816  return false;
817  break;
818 
819  case GIR_MutateOpcode: {
820  int64_t OldInsnID = MatchTable[CurrentIdx++];
821  uint64_t NewInsnID = MatchTable[CurrentIdx++];
822  int64_t NewOpcode = MatchTable[CurrentIdx++];
823  if (NewInsnID >= OutMIs.size())
824  OutMIs.resize(NewInsnID + 1);
825 
826  OutMIs[NewInsnID] = MachineInstrBuilder(*State.MIs[OldInsnID]->getMF(),
827  State.MIs[OldInsnID]);
828  OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode));
830  dbgs() << CurrentIdx << ": GIR_MutateOpcode(OutMIs["
831  << NewInsnID << "], MIs[" << OldInsnID << "], "
832  << NewOpcode << ")\n");
833  break;
834  }
835 
836  case GIR_BuildMI: {
837  uint64_t NewInsnID = MatchTable[CurrentIdx++];
838  int64_t Opcode = MatchTable[CurrentIdx++];
839  if (NewInsnID >= OutMIs.size())
840  OutMIs.resize(NewInsnID + 1);
841 
842  OutMIs[NewInsnID] = BuildMI(*State.MIs[0]->getParent(), State.MIs[0],
843  State.MIs[0]->getDebugLoc(), TII.get(Opcode));
845  dbgs() << CurrentIdx << ": GIR_BuildMI(OutMIs["
846  << NewInsnID << "], " << Opcode << ")\n");
847  break;
848  }
849 
850  case GIR_Copy: {
851  int64_t NewInsnID = MatchTable[CurrentIdx++];
852  int64_t OldInsnID = MatchTable[CurrentIdx++];
853  int64_t OpIdx = MatchTable[CurrentIdx++];
854  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
855  OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(OpIdx));
857  dbgs()
858  << CurrentIdx << ": GIR_Copy(OutMIs[" << NewInsnID
859  << "], MIs[" << OldInsnID << "], " << OpIdx << ")\n");
860  break;
861  }
862 
863  case GIR_CopyOrAddZeroReg: {
864  int64_t NewInsnID = MatchTable[CurrentIdx++];
865  int64_t OldInsnID = MatchTable[CurrentIdx++];
866  int64_t OpIdx = MatchTable[CurrentIdx++];
867  int64_t ZeroReg = MatchTable[CurrentIdx++];
868  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
869  MachineOperand &MO = State.MIs[OldInsnID]->getOperand(OpIdx);
870  if (isOperandImmEqual(MO, 0, MRI))
871  OutMIs[NewInsnID].addReg(ZeroReg);
872  else
873  OutMIs[NewInsnID].add(MO);
875  dbgs() << CurrentIdx << ": GIR_CopyOrAddZeroReg(OutMIs["
876  << NewInsnID << "], MIs[" << OldInsnID << "], "
877  << OpIdx << ", " << ZeroReg << ")\n");
878  break;
879  }
880 
881  case GIR_CopySubReg: {
882  int64_t NewInsnID = MatchTable[CurrentIdx++];
883  int64_t OldInsnID = MatchTable[CurrentIdx++];
884  int64_t OpIdx = MatchTable[CurrentIdx++];
885  int64_t SubRegIdx = MatchTable[CurrentIdx++];
886  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
887  OutMIs[NewInsnID].addReg(State.MIs[OldInsnID]->getOperand(OpIdx).getReg(),
888  0, SubRegIdx);
890  dbgs() << CurrentIdx << ": GIR_CopySubReg(OutMIs["
891  << NewInsnID << "], MIs[" << OldInsnID << "], "
892  << OpIdx << ", " << SubRegIdx << ")\n");
893  break;
894  }
895 
896  case GIR_AddImplicitDef: {
897  int64_t InsnID = MatchTable[CurrentIdx++];
898  int64_t RegNum = MatchTable[CurrentIdx++];
899  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
900  OutMIs[InsnID].addDef(RegNum, RegState::Implicit);
902  dbgs() << CurrentIdx << ": GIR_AddImplicitDef(OutMIs["
903  << InsnID << "], " << RegNum << ")\n");
904  break;
905  }
906 
907  case GIR_AddImplicitUse: {
908  int64_t InsnID = MatchTable[CurrentIdx++];
909  int64_t RegNum = MatchTable[CurrentIdx++];
910  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
911  OutMIs[InsnID].addUse(RegNum, RegState::Implicit);
913  dbgs() << CurrentIdx << ": GIR_AddImplicitUse(OutMIs["
914  << InsnID << "], " << RegNum << ")\n");
915  break;
916  }
917 
918  case GIR_AddRegister: {
919  int64_t InsnID = MatchTable[CurrentIdx++];
920  int64_t RegNum = MatchTable[CurrentIdx++];
921  uint64_t RegFlags = MatchTable[CurrentIdx++];
922  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
923  OutMIs[InsnID].addReg(RegNum, RegFlags);
926  dbgs() << CurrentIdx << ": GIR_AddRegister(OutMIs["
927  << InsnID << "], " << RegNum << ", " << RegFlags << ")\n");
928  break;
929  }
930 
931  case GIR_AddTempRegister:
932  case GIR_AddTempSubRegister: {
933  int64_t InsnID = MatchTable[CurrentIdx++];
934  int64_t TempRegID = MatchTable[CurrentIdx++];
935  uint64_t TempRegFlags = MatchTable[CurrentIdx++];
936  unsigned SubReg = 0;
937  if (MatcherOpcode == GIR_AddTempSubRegister)
938  SubReg = MatchTable[CurrentIdx++];
939 
940  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
941 
942  OutMIs[InsnID].addReg(State.TempRegisters[TempRegID], TempRegFlags, SubReg);
944  dbgs() << CurrentIdx << ": GIR_AddTempRegister(OutMIs["
945  << InsnID << "], TempRegisters[" << TempRegID
946  << "]";
947  if (SubReg)
948  dbgs() << '.' << TRI.getSubRegIndexName(SubReg);
949  dbgs() << ", " << TempRegFlags << ")\n");
950  break;
951  }
952 
953  case GIR_AddImm: {
954  int64_t InsnID = MatchTable[CurrentIdx++];
955  int64_t Imm = MatchTable[CurrentIdx++];
956  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
957  OutMIs[InsnID].addImm(Imm);
959  dbgs() << CurrentIdx << ": GIR_AddImm(OutMIs[" << InsnID
960  << "], " << Imm << ")\n");
961  break;
962  }
963 
964  case GIR_ComplexRenderer: {
965  int64_t InsnID = MatchTable[CurrentIdx++];
966  int64_t RendererID = MatchTable[CurrentIdx++];
967  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
968  for (const auto &RenderOpFn : State.Renderers[RendererID])
969  RenderOpFn(OutMIs[InsnID]);
971  dbgs() << CurrentIdx << ": GIR_ComplexRenderer(OutMIs["
972  << InsnID << "], " << RendererID << ")\n");
973  break;
974  }
976  int64_t InsnID = MatchTable[CurrentIdx++];
977  int64_t RendererID = MatchTable[CurrentIdx++];
978  int64_t RenderOpID = MatchTable[CurrentIdx++];
979  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
980  State.Renderers[RendererID][RenderOpID](OutMIs[InsnID]);
982  dbgs() << CurrentIdx
983  << ": GIR_ComplexSubOperandRenderer(OutMIs["
984  << InsnID << "], " << RendererID << ", "
985  << RenderOpID << ")\n");
986  break;
987  }
988 
989  case GIR_CopyConstantAsSImm: {
990  int64_t NewInsnID = MatchTable[CurrentIdx++];
991  int64_t OldInsnID = MatchTable[CurrentIdx++];
992  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
993  assert(State.MIs[OldInsnID]->getOpcode() == TargetOpcode::G_CONSTANT && "Expected G_CONSTANT");
994  if (State.MIs[OldInsnID]->getOperand(1).isCImm()) {
995  OutMIs[NewInsnID].addImm(
996  State.MIs[OldInsnID]->getOperand(1).getCImm()->getSExtValue());
997  } else if (State.MIs[OldInsnID]->getOperand(1).isImm())
998  OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(1));
999  else
1000  llvm_unreachable("Expected Imm or CImm operand");
1002  dbgs() << CurrentIdx << ": GIR_CopyConstantAsSImm(OutMIs["
1003  << NewInsnID << "], MIs[" << OldInsnID << "])\n");
1004  break;
1005  }
1006 
1007  // TODO: Needs a test case once we have a pattern that uses this.
1008  case GIR_CopyFConstantAsFPImm: {
1009  int64_t NewInsnID = MatchTable[CurrentIdx++];
1010  int64_t OldInsnID = MatchTable[CurrentIdx++];
1011  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
1012  assert(State.MIs[OldInsnID]->getOpcode() == TargetOpcode::G_FCONSTANT && "Expected G_FCONSTANT");
1013  if (State.MIs[OldInsnID]->getOperand(1).isFPImm())
1014  OutMIs[NewInsnID].addFPImm(
1015  State.MIs[OldInsnID]->getOperand(1).getFPImm());
1016  else
1017  llvm_unreachable("Expected FPImm operand");
1019  dbgs() << CurrentIdx << ": GIR_CopyFPConstantAsFPImm(OutMIs["
1020  << NewInsnID << "], MIs[" << OldInsnID << "])\n");
1021  break;
1022  }
1023 
1024  case GIR_CustomRenderer: {
1025  int64_t InsnID = MatchTable[CurrentIdx++];
1026  int64_t OldInsnID = MatchTable[CurrentIdx++];
1027  int64_t RendererFnID = MatchTable[CurrentIdx++];
1028  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1030  dbgs() << CurrentIdx << ": GIR_CustomRenderer(OutMIs["
1031  << InsnID << "], MIs[" << OldInsnID << "], "
1032  << RendererFnID << ")\n");
1033  (ISel.*ISelInfo.CustomRenderers[RendererFnID])(
1034  OutMIs[InsnID], *State.MIs[OldInsnID],
1035  -1); // Not a source operand of the old instruction.
1036  break;
1037  }
1039  int64_t InsnID = MatchTable[CurrentIdx++];
1040  int64_t OldInsnID = MatchTable[CurrentIdx++];
1041  int64_t OpIdx = MatchTable[CurrentIdx++];
1042  int64_t RendererFnID = MatchTable[CurrentIdx++];
1043  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1044 
1047  dbgs() << CurrentIdx << ": GIR_CustomOperandRenderer(OutMIs["
1048  << InsnID << "], MIs[" << OldInsnID << "]->getOperand("
1049  << OpIdx << "), "
1050  << RendererFnID << ")\n");
1051  (ISel.*ISelInfo.CustomRenderers[RendererFnID])(OutMIs[InsnID],
1052  *State.MIs[OldInsnID],
1053  OpIdx);
1054  break;
1055  }
1056  case GIR_ConstrainOperandRC: {
1057  int64_t InsnID = MatchTable[CurrentIdx++];
1058  int64_t OpIdx = MatchTable[CurrentIdx++];
1059  int64_t RCEnum = MatchTable[CurrentIdx++];
1060  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1061  MachineInstr &I = *OutMIs[InsnID].getInstr();
1062  MachineFunction &MF = *I.getParent()->getParent();
1064  const TargetRegisterClass &RC = *TRI.getRegClass(RCEnum);
1065  MachineOperand &MO = I.getOperand(OpIdx);
1066  constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC, MO);
1068  dbgs() << CurrentIdx << ": GIR_ConstrainOperandRC(OutMIs["
1069  << InsnID << "], " << OpIdx << ", " << RCEnum
1070  << ")\n");
1071  break;
1072  }
1073 
1075  int64_t InsnID = MatchTable[CurrentIdx++];
1076  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1077  constrainSelectedInstRegOperands(*OutMIs[InsnID].getInstr(), TII, TRI,
1078  RBI);
1080  dbgs() << CurrentIdx
1081  << ": GIR_ConstrainSelectedInstOperands(OutMIs["
1082  << InsnID << "])\n");
1083  break;
1084  }
1085 
1086  case GIR_MergeMemOperands: {
1087  int64_t InsnID = MatchTable[CurrentIdx++];
1088  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1089 
1091  dbgs() << CurrentIdx << ": GIR_MergeMemOperands(OutMIs["
1092  << InsnID << "]");
1093  int64_t MergeInsnID = GIU_MergeMemOperands_EndOfList;
1094  while ((MergeInsnID = MatchTable[CurrentIdx++]) !=
1097  dbgs() << ", MIs[" << MergeInsnID << "]");
1098  for (const auto &MMO : State.MIs[MergeInsnID]->memoperands())
1099  OutMIs[InsnID].addMemOperand(MMO);
1100  }
1102  break;
1103  }
1104 
1105  case GIR_EraseFromParent: {
1106  int64_t InsnID = MatchTable[CurrentIdx++];
1107  assert(State.MIs[InsnID] &&
1108  "Attempted to erase an undefined instruction");
1109  State.MIs[InsnID]->eraseFromParent();
1111  dbgs() << CurrentIdx << ": GIR_EraseFromParent(MIs["
1112  << InsnID << "])\n");
1113  break;
1114  }
1115 
1116  case GIR_MakeTempReg: {
1117  int64_t TempRegID = MatchTable[CurrentIdx++];
1118  int64_t TypeID = MatchTable[CurrentIdx++];
1119 
1120  State.TempRegisters[TempRegID] =
1121  MRI.createGenericVirtualRegister(ISelInfo.TypeObjects[TypeID]);
1123  dbgs() << CurrentIdx << ": TempRegs[" << TempRegID
1124  << "] = GIR_MakeTempReg(" << TypeID << ")\n");
1125  break;
1126  }
1127 
1128  case GIR_Coverage: {
1129  int64_t RuleID = MatchTable[CurrentIdx++];
1130  CoverageInfo.setCovered(RuleID);
1131 
1133  dbgs()
1134  << CurrentIdx << ": GIR_Coverage(" << RuleID << ")");
1135  break;
1136  }
1137 
1138  case GIR_Done:
1140  dbgs() << CurrentIdx << ": GIR_Done\n");
1141  propagateFlags(OutMIs);
1142  return true;
1143 
1144  default:
1145  llvm_unreachable("Unexpected command");
1146  }
1147  }
1148 }
1149 
1150 } // end namespace llvm
1151 
1152 #endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::InstructionSelector::MatcherState::Renderers
std::vector< ComplexRendererFns::value_type > Renderers
Definition: InstructionSelector.h:466
llvm::GIM_CheckNumOperands
@ GIM_CheckNumOperands
Check the instruction has the right number of operands.
Definition: InstructionSelector.h:130
llvm::GIM_CheckLiteralInt
@ GIM_CheckLiteralInt
Check the operand is a specific literal integer (i.e.
Definition: InstructionSelector.h:226
getName
static StringRef getName(Value *V)
Definition: ProvenanceAnalysisEvaluator.cpp:42
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm
Definition: AllocatorList.h:23
llvm::GIM_CheckAPFloatImmPredicate
@ GIM_CheckAPFloatImmPredicate
Check a floating point immediate predicate on the specified instruction.
Definition: InstructionSelector.h:142
llvm::GIM_CheckPointerToAny
@ GIM_CheckPointerToAny
Check the type of a pointer to any address space.
Definition: InstructionSelector.h:202
llvm::isBuildVectorAllOnes
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:910
llvm::GIR_AddRegister
@ GIR_AddRegister
Add an register to the specified instruction.
Definition: InstructionSelector.h:318
llvm::GIM_CheckMemorySizeGreaterThanLLT
@ GIM_CheckMemorySizeGreaterThanLLT
Definition: InstructionSelector.h:178
llvm::GIM_CheckAtomicOrdering
@ GIM_CheckAtomicOrdering
Check a memory operation has the specified atomic ordering.
Definition: InstructionSelector.h:146
llvm::MachineMemOperand::getAlign
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
Definition: MachineOperand.cpp:1069
llvm::InstructionSelector::testMIPredicate_MI
virtual bool testMIPredicate_MI(unsigned, const MachineInstr &, const std::array< const MachineOperand *, 3 > &Operands) const
Definition: InstructionSelector.h:540
llvm::GIM_CheckMemoryAlignment
@ GIM_CheckMemoryAlignment
Check the minimum alignment of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:169
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::GIM_CheckI64ImmPredicate
@ GIM_CheckI64ImmPredicate
Check an immediate predicate on the specified instruction.
Definition: InstructionSelector.h:134
llvm::GIM_CheckIsBuildVectorAllOnes
@ GIM_CheckIsBuildVectorAllOnes
Check if this is a vector that can be treated as a vector splat constant.
Definition: InstructionSelector.h:185
llvm::GIR_ComplexRenderer
@ GIR_ComplexRenderer
Render complex operands to the specified instruction.
Definition: InstructionSelector.h:340
llvm::MachineOperand::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition: MachineOperand.h:580
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::GIM_RecordInsn
@ GIM_RecordInsn
Record the specified instruction.
Definition: InstructionSelector.h:109
llvm::RegisterBankInfo::getRegBank
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
Definition: RegisterBankInfo.h:432
ErrorHandling.h
RegisterBankInfo.h
llvm::InstructionSelector::MatcherState
Definition: InstructionSelector.h:465
llvm::GIR_ConstrainSelectedInstOperands
@ GIR_ConstrainSelectedInstOperands
Constrain an instructions operands according to the instruction description.
Definition: InstructionSelector.h:382
llvm::MachineMemOperand::getSizeInBits
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
Definition: MachineMemOperand.h:224
llvm::GIM_CheckFeatures
@ GIM_CheckFeatures
Check the feature bits.
Definition: InstructionSelector.h:113
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
TargetInstrInfo.h
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MachineOperand::isCImm
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
Definition: MachineOperand.h:322
llvm::InstructionSelector::MatcherState::MIs
RecordedMIVector MIs
Definition: InstructionSelector.h:467
llvm::GIM_CheckOpcodeIsEither
@ GIM_CheckOpcodeIsEither
Check the opcode on the specified instruction, checking 2 acceptable alternatives.
Definition: InstructionSelector.h:125
llvm::Optional
Definition: APInt.h:34
llvm::InstructionSelector::testImmPredicate_I64
virtual bool testImmPredicate_I64(unsigned, int64_t) const
Definition: InstructionSelector.h:528
llvm::GIM_Try
@ GIM_Try
Begin a try-block to attempt a match and jump to OnFail if it is unsuccessful.
Definition: InstructionSelector.h:86
llvm::GIM_CheckComplexPattern
@ GIM_CheckComplexPattern
Check the operand matches a complex predicate.
Definition: InstructionSelector.h:214
llvm::GIM_RecordNamedOperand
@ GIM_RecordNamedOperand
Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some named operands that will be ...
Definition: InstructionSelector.h:268
llvm::Expected
Tagged union holding either a T or a Error.
Definition: APFloat.h:42
llvm::SmallVectorImpl::pop_back_val
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:635
llvm::CodeGenCoverage::setCovered
void setCovered(uint64_t RuleID)
Definition: CodeGenCoverage.cpp:28
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::GIU_MergeMemOperands_EndOfList
@ GIU_MergeMemOperands_EndOfList
Indicates the end of the variable-length MergeInsnID list in a GIR_MergeMemOperands opcode.
Definition: InstructionSelector.h:414
llvm::InstructionSelector::MatcherState::TempRegisters
DenseMap< unsigned, unsigned > TempRegisters
Definition: InstructionSelector.h:468
llvm::constrainSelectedInstRegOperands
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:134
MachineRegisterInfo.h
llvm::GIR_AddTempSubRegister
@ GIR_AddTempSubRegister
Add a temporary register to the specified instruction.
Definition: InstructionSelector.h:331
llvm::Optional::hasValue
constexpr bool hasValue() const
Definition: Optional.h:286
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
llvm::isAtLeastOrStrongerThan
bool isAtLeastOrStrongerThan(AtomicOrdering AO, AtomicOrdering Other)
Definition: AtomicOrdering.h:105
llvm::GIR_AddTempRegister
@ GIR_AddTempRegister
Add a temporary register to the specified instruction.
Definition: InstructionSelector.h:324
llvm::GIM_CheckIsBuildVectorAllZeros
@ GIM_CheckIsBuildVectorAllZeros
Definition: InstructionSelector.h:186
llvm::MinAlign
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:672
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
DEBUG_WITH_TYPE
#define DEBUG_WITH_TYPE(TYPE, X)
DEBUG_WITH_TYPE macro - This macro should be used by passes to emit debug information.
Definition: Debug.h:64
llvm::InstructionSelector::ISelInfoTy::CustomRenderers
const CustomRendererFn * CustomRenderers
Definition: InstructionSelector.h:503
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
Constants.h
llvm::MachineMemOperand::getAddrSpace
unsigned getAddrSpace() const
Definition: MachineMemOperand.h:218
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:534
llvm::LLT::getSizeInBits
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:109
llvm::GIR_MutateOpcode
@ GIR_MutateOpcode
Mutate an instruction.
Definition: InstructionSelector.h:280
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::GIR_CopySubReg
@ GIR_CopySubReg
Copy an operand to the specified instruction.
Definition: InstructionSelector.h:305
llvm::InstructionSelector::CoverageInfo
CodeGenCoverage * CoverageInfo
Definition: InstructionSelector.h:434
Utils.h
llvm::ConstantInt::equalsInt
bool equalsInt(uint64_t V) const
A helper method that can be used to determine if the constant contained within is equal to a constant...
Definition: Constants.h:166
TargetOpcodes.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::GIR_CopyFConstantAsFPImm
@ GIR_CopyFConstantAsFPImm
Render a G_FCONSTANT operator as a sign-extended immediate.
Definition: InstructionSelector.h:371
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::GIPFP_I64_Invalid
@ GIPFP_I64_Invalid
Definition: InstructionSelectorImpl.h:41
llvm::InstructionSelector::MatcherState::RecordedOperands
std::array< const MachineOperand *, 3 > RecordedOperands
Named operands that predicate with 'let PredicateCodeUsesOperands = 1' referenced in its argument lis...
Definition: InstructionSelector.h:473
llvm::GIM_CheckAPIntImmPredicate
@ GIM_CheckAPIntImmPredicate
Check an immediate predicate on the specified instruction via an APInt.
Definition: InstructionSelector.h:138
llvm::SmallVectorImpl::resize
void resize(size_type N)
Definition: SmallVector.h:606
llvm::GIR_CustomRenderer
@ GIR_CustomRenderer
Render operands to the specified instruction using a custom function.
Definition: InstructionSelector.h:351
llvm::GIR_Done
@ GIR_Done
A successful emission.
Definition: InstructionSelector.h:401
llvm::GIR_Copy
@ GIR_Copy
Copy an operand to the specified instruction.
Definition: InstructionSelector.h:291
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:47
llvm::GIM_CheckRegBankForClass
@ GIM_CheckRegBankForClass
Check the register bank for the specified operand.
Definition: InstructionSelector.h:207
llvm::GIM_CheckIsMBB
@ GIM_CheckIsMBB
Check the specified operand is an MBB.
Definition: InstructionSelector.h:242
llvm::GIR_ConstrainOperandRC
@ GIR_ConstrainOperandRC
Constrain an instruction operand to a register class.
Definition: InstructionSelector.h:377
llvm::MachineInstr::NoFPExcept
@ NoFPExcept
Definition: MachineInstr.h:108
llvm::GIM_CheckMemorySizeLessThanLLT
@ GIM_CheckMemorySizeLessThanLLT
Definition: InstructionSelector.h:177
llvm::GIM_SwitchType
@ GIM_SwitchType
Switch over the LLT on the specified instruction operand.
Definition: InstructionSelector.h:103
llvm::GIR_AddImplicitUse
@ GIR_AddImplicitUse
Add an implicit register use to the specified instruction.
Definition: InstructionSelector.h:314
InstructionSelector.h
llvm::LLT::getAddressSpace
unsigned getAddressSpace() const
Definition: LowLevelTypeImpl.h:178
llvm::InstructionSelector::MF
MachineFunction * MF
Definition: InstructionSelector.h:436
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
TypeID
Type::TypeID TypeID
Definition: Mips16HardFloat.cpp:102
llvm::InstructionSelector::isOperandImmEqual
bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI) const
Definition: InstructionSelector.cpp:36
llvm::APFloat
Definition: APFloat.h:701
llvm::PPC::Predicate
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
llvm::InstructionSelector::ISelInfoTy::TypeIDMap
SmallDenseMap< LLT, unsigned, 64 > TypeIDMap
Definition: InstructionSelector.h:505
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::GIM_CheckAtomicOrderingOrStrongerThan
@ GIM_CheckAtomicOrderingOrStrongerThan
Definition: InstructionSelector.h:147
llvm::CodeGenCoverage
Definition: CodeGenCoverage.h:20
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:318
llvm::MachineOperand::getCImm
const ConstantInt * getCImm() const
Definition: MachineOperand.h:539
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::GIM_CheckOpcode
@ GIM_CheckOpcode
Check the opcode on the specified instruction.
Definition: InstructionSelector.h:118
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:70
llvm::GIR_CopyOrAddZeroReg
@ GIR_CopyOrAddZeroReg
Copy an operand to the specified instruction or add a zero register if the operand is a zero immediat...
Definition: InstructionSelector.h:299
llvm::GIR_MakeTempReg
@ GIR_MakeTempReg
Create a new temporary register that's not constrained.
Definition: InstructionSelector.h:398
llvm::GIR_Coverage
@ GIR_Coverage
Increment the rule coverage counter.
Definition: InstructionSelector.h:405
llvm::GIM_CheckMemorySizeEqualToLLT
@ GIM_CheckMemorySizeEqualToLLT
Check the size of the memory access for the given machine memory operand against the size of an opera...
Definition: InstructionSelector.h:176
llvm::GIM_CheckIntrinsicID
@ GIM_CheckIntrinsicID
Check the operand is a specific intrinsic ID.
Definition: InstructionSelector.h:231
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::isBuildVectorAllZeros
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:905
llvm::GIM_CheckMemoryAddressSpace
@ GIM_CheckMemoryAddressSpace
Check the address space of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:162
llvm::InstructionSelector::ISelInfoTy::TypeObjects
const LLT * TypeObjects
Definition: InstructionSelector.h:500
llvm::MachineOperand::getPredicate
unsigned getPredicate() const
Definition: MachineOperand.h:585
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::LLT::isPointer
bool isPointer() const
Definition: LowLevelTypeImpl.h:94
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:357
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:71
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::InstructionSelector::testImmPredicate_APFloat
virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const
Definition: InstructionSelector.h:536
llvm::GIM_Reject
@ GIM_Reject
Fail the current try-block, or completely fail to match if there is no current try-block.
Definition: InstructionSelector.h:272
llvm::GIPFP_APInt_Invalid
@ GIPFP_APInt_Invalid
Definition: InstructionSelectorImpl.h:42
DataLayout.h
llvm::GIPFP_MI_Invalid
@ GIPFP_MI_Invalid
Definition: InstructionSelectorImpl.h:44
llvm::GIM_CheckIsImm
@ GIM_CheckIsImm
Check the specified operand is an Imm.
Definition: InstructionSelector.h:247
llvm::MachineOperand::isIntrinsicID
bool isIntrinsicID() const
Definition: MachineOperand.h:349
llvm::GIM_CheckMemorySizeEqualTo
@ GIM_CheckMemorySizeEqualTo
Check the size of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:153
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::GIM_CheckCmpPredicate
@ GIM_CheckCmpPredicate
Check the operand is a specific predicate.
Definition: InstructionSelector.h:237
llvm::GIM_CheckConstantInt
@ GIM_CheckConstantInt
Check the operand is a specific integer.
Definition: InstructionSelector.h:220
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:777
llvm::InstructionSelector::ISelInfoTy::ComplexPredicates
const ComplexMatcherMemFn * ComplexPredicates
Definition: InstructionSelector.h:502
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::InstructionSelector::ISelInfoTy::FeatureBitsets
const PredicateBitset * FeatureBitsets
Definition: InstructionSelector.h:501
llvm::RegisterBankInfo::getRegBankFromRegClass
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const
Get a register bank that covers RC.
Definition: RegisterBankInfo.h:604
llvm::GIR_BuildMI
@ GIR_BuildMI
Build a new instruction.
Definition: InstructionSelector.h:285
llvm::GIR_MergeMemOperands
@ GIR_MergeMemOperands
Merge all memory operands into instruction.
Definition: InstructionSelector.h:389
uint16_t
llvm::GIM_CheckIsSameOperand
@ GIM_CheckIsSameOperand
Check the specified operands are identical.
Definition: InstructionSelector.h:259
llvm::GIM_CheckAtomicOrderingWeakerThan
@ GIM_CheckAtomicOrderingWeakerThan
Definition: InstructionSelector.h:148
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:221
Success
#define Success
Definition: AArch64Disassembler.cpp:248
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:320
llvm::InstructionSelector::isObviouslySafeToFold
bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const
Return true if MI can obviously be folded into IntoMI.
Definition: InstructionSelector.cpp:62
llvm::isStrongerThan
bool isStrongerThan(AtomicOrdering AO, AtomicOrdering Other)
Returns true if ao is stronger than other as defined by the AtomicOrdering lattice,...
Definition: AtomicOrdering.h:90
llvm::GIR_AddImplicitDef
@ GIR_AddImplicitDef
Add an implicit register def to the specified instruction.
Definition: InstructionSelector.h:310
llvm::GIR_EraseFromParent
@ GIR_EraseFromParent
Erase from parent.
Definition: InstructionSelector.h:393
llvm::GIM_CheckIsSafeToFold
@ GIM_CheckIsSafeToFold
Check if the specified operand is safe to fold into the current instruction.
Definition: InstructionSelector.h:252
llvm::MachineOperand::isPredicate
bool isPredicate() const
Definition: MachineOperand.h:350
llvm::GIM_SwitchOpcode
@ GIM_SwitchOpcode
Switch over the opcode on the specified instruction.
Definition: InstructionSelector.h:94
SmallVector.h
llvm::GIR_CopyConstantAsSImm
@ GIR_CopyConstantAsSImm
Render a G_CONSTANT operator as a sign-extended immediate.
Definition: InstructionSelector.h:365
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:329
llvm::InstructionSelector::testImmPredicate_APInt
virtual bool testImmPredicate_APInt(unsigned, const APInt &) const
Definition: InstructionSelector.h:532
llvm::GIR_AddImm
@ GIR_AddImm
Add an immediate to the specified instruction.
Definition: InstructionSelector.h:336
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:48
llvm::InstructionSelector::ISelInfoTy
Definition: InstructionSelector.h:487
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:260
MachineOperand.h
llvm::GIR_CustomOperandRenderer
@ GIR_CustomOperandRenderer
Render operands to the specified instruction using a custom function, reading from a specific operand...
Definition: InstructionSelector.h:359
llvm::DataLayout::getPointerSizeInBits
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:404
llvm::GIR_ComplexSubOperandRenderer
@ GIR_ComplexSubOperandRenderer
Render sub-operands of complex operands to the specified instruction.
Definition: InstructionSelector.h:346
llvm::GIPFP_APFloat_Invalid
@ GIPFP_APFloat_Invalid
Definition: InstructionSelectorImpl.h:43
llvm::InstructionSelector::executeMatchTable
bool executeMatchTable(TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State, const ISelInfoTy< PredicateBitset, ComplexMatcherMemFn, CustomRendererFn > &ISelInfo, const int64_t *MatchTable, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, CodeGenCoverage &CoverageInfo) const
Execute a given matcher table and return true if the match was successful and false otherwise.
Definition: InstructionSelectorImpl.h:49
llvm::GIM_CheckType
@ GIM_CheckType
Check the type for the specified operand.
Definition: InstructionSelector.h:197
raw_ostream.h
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
TargetRegisterInfo.h
Debug.h
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::Optional::getValue
constexpr const T & getValue() const LLVM_LVALUE_FUNCTION
Definition: Optional.h:280
llvm::GIM_CheckCxxInsnPredicate
@ GIM_CheckCxxInsnPredicate
Check a generic C++ instruction predicate.
Definition: InstructionSelector.h:191
llvm::LLT
Definition: LowLevelTypeImpl.h:40