Functions
Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause	different (semantically equivalent) instructions to be used in place of the requested instruction

Variables
Code Generation Notes for	MSA

Code Generation Notes for reduce the size of the ISel	matcher

Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of	cases

Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place	Instructions

Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place two instructions might be equally valid for some given IR and one is chosen in preference to the other bclri	b

Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place two instructions might be equally valid for some given IR and one is chosen in preference to the other bclri splat[bhwd] instructions will be selected instead of vshf[bhwd] Unlike the ilv and pck *	instructions

Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place two instructions might be equally valid for some given IR and one is chosen in preference to the other bclri splat[bhwd] instructions will be selected instead of vshf[bhwd] Unlike the ilv and pck this is matched from MipsISD::VSHF instead of a special case MipsISD node ilvl	d

Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place two instructions might be equally valid for some given IR and one is chosen in preference to the other bclri splat[bhwd] instructions will be selected instead of vshf[bhwd] Unlike the ilv and pck this is matched from MipsISD::VSHF instead of a special case MipsISD node ilvl pckev or pckev d since ilvev d covers the same shuffle ilvev d will be emitted instead ilvr ilvod pckod or pckod d since ilvod d covers the same shuffle ilvod d will be emitted instead splat[bhwd] The intrinsic will work as expected	However

Function Documentation

◆ different()

Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause different ( semantically equivalent )

Variable Documentation

◆ b

Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place two instructions might be equally valid for some given IR and one is chosen in preference to the other bclri b

Definition at line 30 of file MSA.txt.

◆ cases

Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of cases

Definition at line 6 of file MSA.txt.

Referenced by llvm::SwitchInst::findCaseDest(), and llvm::SwitchInst::findCaseValue().

◆ d

Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place two instructions might be equally valid for some given IR and one is chosen in preference to the other bclri splat [bhwd] instructions will be selected instead of vshf [bhwd] Unlike the ilv and pck this is matched from MipsISD::VSHF instead of a special case MipsISD node ilvl pckev or pckev d since ilvev d covers the same shuffle ilvev d will be emitted instead ilvr ilvod pckod d

Definition at line 35 of file MSA.txt.

◆ However

Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place two instructions might be equally valid for some given IR and one is chosen in preference to the other bclri splat [bhwd] instructions will be selected instead of vshf [bhwd] Unlike the ilv and pck this is matched from MipsISD::VSHF instead of a special case MipsISD node ilvl pckev or pckev d since ilvev d covers the same shuffle ilvev d will be emitted instead ilvr ilvod pckod or pckod d since ilvod d covers the same shuffle ilvod d will be emitted instead splat [bhwd] The intrinsic will work as expected However

Definition at line 44 of file MSA.txt.

◆ Instructions

Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place Instructions

Initial value:

============
 
This section describes any quirks of instruction selection for MSA. For
example

Definition at line 11 of file MSA.txt.

Referenced by findCommonDominator(), llvm::StackLifetime::getFullLiveRange(), llvm::StackLifetime::getMarkers(), rescheduleCanonically(), simplifyARM64Opcodes(), and tryEmitAutoInitRemark().

◆ instructions

Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place two instructions might be equally valid for some given IR and one is chosen in preference to the other bclri splat [bhwd] instructions will be selected instead of vshf [bhwd] Unlike the ilv and pck* instructions

Definition at line 31 of file MSA.txt.

◆ matcher

Code Generation Notes for reduce the size of the ISel matcher

Definition at line 5 of file MSA.txt.

◆ MSA

Code Generation Notes for MSA