LLVM  13.0.0git
Functions | Variables
lib/Target/Mips/MSA.txt File Reference

Functions

Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause different (semantically equivalent) instructions to be used in place of the requested instruction
 

Variables

Code Generation Notes for MSA
 
Code Generation Notes for reduce the size of the ISel matcher
 
Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of cases
 
Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place Instructions
 
Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place two instructions might be equally valid for some given IR and one is chosen in preference to the other bclri b
 
Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place two instructions might be equally valid for some given IR and one is chosen in preference to the other bclri splat[bhwd] instructions will be selected instead of vshf[bhwd] Unlike the ilv and pck * instructions
 
Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place two instructions might be equally valid for some given IR and one is chosen in preference to the other bclri splat[bhwd] instructions will be selected instead of vshf[bhwd] Unlike the ilv and pck this is matched from MipsISD::VSHF instead of a special case MipsISD node ilvl d
 
Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place two instructions might be equally valid for some given IR and one is chosen in preference to the other bclri splat[bhwd] instructions will be selected instead of vshf[bhwd] Unlike the ilv and pck this is matched from MipsISD::VSHF instead of a special case MipsISD node ilvl pckev or pckev d since ilvev d covers the same shuffle ilvev d will be emitted instead ilvr ilvod pckod or pckod d since ilvod d covers the same shuffle ilvod d will be emitted instead splat[bhwd] The intrinsic will work as expected However
 

Function Documentation

◆ different()

Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause different ( semantically  equivalent)

Variable Documentation

◆ b

Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place two instructions might be equally valid for some given IR and one is chosen in preference to the other bclri b

Definition at line 30 of file MSA.txt.

◆ cases

Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of cases

Definition at line 6 of file MSA.txt.

Referenced by llvm::SwitchInst::findCaseDest(), and llvm::SwitchInst::findCaseValue().

◆ d

Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place two instructions might be equally valid for some given IR and one is chosen in preference to the other bclri splat [bhwd] instructions will be selected instead of vshf [bhwd] Unlike the ilv and pck this is matched from MipsISD::VSHF instead of a special case MipsISD node ilvl pckev or pckev d since ilvev d covers the same shuffle ilvev d will be emitted instead ilvr ilvod pckod d

Definition at line 35 of file MSA.txt.

◆ However

Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place two instructions might be equally valid for some given IR and one is chosen in preference to the other bclri splat [bhwd] instructions will be selected instead of vshf [bhwd] Unlike the ilv and pck this is matched from MipsISD::VSHF instead of a special case MipsISD node ilvl pckev or pckev d since ilvev d covers the same shuffle ilvev d will be emitted instead ilvr ilvod pckod or pckod d since ilvod d covers the same shuffle ilvod d will be emitted instead splat [bhwd] The intrinsic will work as expected However

Definition at line 44 of file MSA.txt.

◆ Instructions

Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place Instructions
Initial value:
============
This section describes any quirks of instruction selection for MSA. For

Definition at line 11 of file MSA.txt.

Referenced by findCommonDominator(), llvm::StackLifetime::getFullLiveRange(), llvm::StackLifetime::getMarkers(), rescheduleCanonically(), simplifyOpcodes(), and tryEmitAutoInitRemark().

◆ instructions

Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place two instructions might be equally valid for some given IR and one is chosen in preference to the other bclri splat [bhwd] instructions will be selected instead of vshf [bhwd] Unlike the ilv and pck* instructions

Definition at line 31 of file MSA.txt.

◆ matcher

Code Generation Notes for reduce the size of the ISel matcher

Definition at line 5 of file MSA.txt.

◆ MSA

Code Generation Notes for MSA
Initial value:
=============================
Intrinsics are lowered to SelectionDAG nodes where possible in order to enable
optimisation

Definition at line 2 of file MSA.txt.

Referenced by llvm::yaml::ScalarBitSetTraits< ELFYAML::MIPS_AFL_ASE >::bitset().

to
Should compile to
Definition: README.txt:449
llvm::LegalityPredicates::any
Predicate any(Predicate P0, Predicate P1)
True iff P0 or P1 are true.
Definition: LegalizerInfo.h:209
in
The object format emitted by the WebAssembly backed is documented in
Definition: README.txt:11
nodes
Unify divergent function exit nodes
Definition: AMDGPUUnifyDivergentExitNodes.cpp:87
MSA
Code Generation Notes for MSA
Definition: MSA.txt:2
example
llvm lib Support Unix the directory structure underneath this directory could look like only those directories actually needing to be created should be created further subdirectories could be created to reflect versions of the various standards For example
Definition: README.txt:15
instruction
Since we know that Vector is byte aligned and we know the element offset of we should change the load into a lve *x instruction
Definition: README_ALTIVEC.txt:37
lowered
into xmm2 addss xmm2 xmm1 xmm3 addss xmm3 movaps xmm0 unpcklps xmm0 ret seems silly when it could just be one addps Expand libm rounding functions main should enable SSE DAZ mode and other fast SSE modes Think about doing i64 math in SSE regs on x86 This testcase should have no SSE instructions in and only one load from a constant double ret double C the select is being lowered
Definition: README-SSE.txt:89
possible
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements possible
Definition: README.txt:410
This
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical This
Definition: README.txt:418
of
Add support for conditional and other related patterns Instead of
Definition: README.txt:134