LLVM
17.0.0git
|
Functions | |
Decimal Convert From to National Zoned Signed int_ppc_altivec_bcdcfno int_ppc_altivec_bcdcfzo int_ppc_altivec_bcdctno int_ppc_altivec_bcdctzo int_ppc_altivec_bcdcfsqo int_ppc_altivec_bcdctsqo int_ppc_altivec_bcdcpsgno int_ppc_altivec_bcdsetsgno int_ppc_altivec_bcdso int_ppc_altivec_bcduso int_ppc_altivec_bcdsro i e VA byte[7] Decimal(Unsigned) Truncate Define DAG Node in PPCInstrInfo def def def def DAG patterns of each | instruction (PPCInstrVSX.td) |
Round to Odd of | QP (Negative) Multiply- |
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← | bfp_ROUND_TO_BFP128 (RO, FPSCR.RN, v) result ← bfp_CONVERT_TO_BFP128(rnd) xsmsubqp(o) v ← bfp_MULTIPLY_ADD(src1 |
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← | bfp_NEGATE (src2)) rnd ← bfp_ROUND_TO_BFP128(RO |
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← FPSCR v result ← | bfp_CONVERT_TO_BFP128 (rnd) xsnmaddqp(o) v ← bfp_MULTIPLY_ADD(src1 |
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← FPSCR v result ← src2 rnd ← | bfp_NEGATE (bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v)) result ← bfp_CONVERT_TO_BFP128(rnd) xsnmsubqp(o) v ← bfp_MULTIPLY_ADD(src1 |
Variables | |
TODO | __pad4__ |
TODO use VCMP VCMPo form(support intrinsic) - Vector Extract Unsigned | vpermr |
TODO use VCMP VCMPo form(support intrinsic) - Vector Extract Unsigned | int_ppc_altivec_vpermr |
TODO use VCMP VCMPo form(support intrinsic) - Vector Extract Unsigned | v16i8 |
Vector Rotate Left Mask Mask | Insert |
Vector Rotate Left Mask Mask | vrlwnm |
Vector Rotate Left Mask Mask | int_ppc_altivec_vrlwnm |
Vector Rotate Left Mask Mask | v4i32 |
VX1_Int_Ty< 133, "vrlwmi", int_ppc_altivec_vrlwmi, v4i32 > | |
VX1_Int_Ty< 453, "vrldnm", int_ppc_altivec_vrldnm, v2i64 > | |
VX1_Int_Ty< 197, "vrldmi", int_ppc_altivec_vrldmi, v2i64 > | |
Vector Shift Left | Right |
Vector Shift Left don t map to llvm shl and | lshr |
Vector Shift Left don t map to llvm shl and because they have different | semantics |
Vector Shift Left don t map to llvm shl and because they have different e g | vslv |
Vector Shift Left don t map to llvm shl and because they have different e g | int_ppc_altivec_vslv |
VX1_Int_Ty< 1796, "vsrv", int_ppc_altivec_vsrv, v16i8 > | |
Vector Multiply by Write Unsigned | Quadword |
Vector Multiply by Write Unsigned | vmul10uq |
Vector Multiply by Write Unsigned | int_ppc_altivec_vmul10uq |
Vector Multiply by Write Unsigned | v1i128 |
VX1_Int_Ty< 1, "vmul10cuq", int_ppc_altivec_vmul10cuq, v1i128 > | |
Vector Multiply by Extended Write Unsigned | vmul10euq |
Vector Multiply by Extended Write Unsigned | int_ppc_altivec_vmul10euq |
VX1_Int_Ty< 65, "vmul10ecuq", int_ppc_altivec_vmul10ecuq, v1i128 > | |
Decimal Convert From to National Zoned Signed | QWord |
Decimal Convert From to National Zoned Signed int_ppc_altivec_bcdcfno | i1 |
Decimal Convert From to National Zoned Signed int_ppc_altivec_bcdcfno int_ppc_altivec_bcdcfzo int_ppc_altivec_bcdctno int_ppc_altivec_bcdctzo int_ppc_altivec_bcdcfsqo int_ppc_altivec_bcdctsqo int_ppc_altivec_bcdcpsgno int_ppc_altivec_bcdsetsgno int_ppc_altivec_bcdso int_ppc_altivec_bcduso int_ppc_altivec_bcdsro i e VA byte[7] Decimal(Unsigned) Truncate Define DAG Node in PPCInstrInfo | td |
Decimal Convert From to National Zoned Signed int_ppc_altivec_bcdcfno int_ppc_altivec_bcdcfzo int_ppc_altivec_bcdctno int_ppc_altivec_bcdctzo int_ppc_altivec_bcdcfsqo int_ppc_altivec_bcdctsqo int_ppc_altivec_bcdcpsgno int_ppc_altivec_bcdsetsgno int_ppc_altivec_bcdso int_ppc_altivec_bcduso int_ppc_altivec_bcdsro i e VA byte[7] Decimal(Unsigned) Truncate Define DAG Node in PPCInstrInfo | SDTFPBinOp |
Decimal Convert From to National Zoned Signed int_ppc_altivec_bcdcfno int_ppc_altivec_bcdcfzo int_ppc_altivec_bcdctno int_ppc_altivec_bcdctzo int_ppc_altivec_bcdcfsqo int_ppc_altivec_bcdctsqo int_ppc_altivec_bcdcpsgno int_ppc_altivec_bcdsetsgno int_ppc_altivec_bcdso int_ppc_altivec_bcduso int_ppc_altivec_bcdsro i e VA byte[7] Decimal(Unsigned) Truncate Define DAG Node in PPCInstrInfo def | PPCfdivrto |
Decimal Convert From to National Zoned Signed int_ppc_altivec_bcdcfno int_ppc_altivec_bcdcfzo int_ppc_altivec_bcdctno int_ppc_altivec_bcdctzo int_ppc_altivec_bcdcfsqo int_ppc_altivec_bcdctsqo int_ppc_altivec_bcdcpsgno int_ppc_altivec_bcdsetsgno int_ppc_altivec_bcdso int_ppc_altivec_bcduso int_ppc_altivec_bcdsro i e VA byte[7] Decimal(Unsigned) Truncate Define DAG Node in PPCInstrInfo def def | PPCfmulrto |
Decimal Convert From to National Zoned Signed int_ppc_altivec_bcdcfno int_ppc_altivec_bcdcfzo int_ppc_altivec_bcdctno int_ppc_altivec_bcdctzo int_ppc_altivec_bcdcfsqo int_ppc_altivec_bcdctsqo int_ppc_altivec_bcdcpsgno int_ppc_altivec_bcdsetsgno int_ppc_altivec_bcdso int_ppc_altivec_bcduso int_ppc_altivec_bcdsro i e VA byte[7] Decimal(Unsigned) Truncate Define DAG Node in PPCInstrInfo def def def | PPCfsubrto |
Decimal Convert From to National Zoned Signed int_ppc_altivec_bcdcfno int_ppc_altivec_bcdcfzo int_ppc_altivec_bcdctno int_ppc_altivec_bcdctzo int_ppc_altivec_bcdcfsqo int_ppc_altivec_bcdctsqo int_ppc_altivec_bcdcpsgno int_ppc_altivec_bcdsetsgno int_ppc_altivec_bcdso int_ppc_altivec_bcduso int_ppc_altivec_bcdsro i e VA byte[7] Decimal(Unsigned) Truncate Define DAG Node in PPCInstrInfo def def def def | PPCfsqrtrto |
Decimal Convert From to National Zoned Signed int_ppc_altivec_bcdcfno int_ppc_altivec_bcdcfzo int_ppc_altivec_bcdctno int_ppc_altivec_bcdctzo int_ppc_altivec_bcdcfsqo int_ppc_altivec_bcdctsqo int_ppc_altivec_bcdcpsgno int_ppc_altivec_bcdsetsgno int_ppc_altivec_bcdso int_ppc_altivec_bcduso int_ppc_altivec_bcdsro i e VA byte[7] Decimal(Unsigned) Truncate Define DAG Node in PPCInstrInfo def def def def | SDTFPUnaryOp |
__pad5__ | |
fma | f128 |
fma | RegConstraint<"$vTi = $vT"> |
fma | NoEncode<"$vTi"> |
fma | AltVSXFMARel |
__pad6__ | |
SDTFPTernaryOp | |
It looks like we only need to define PPCfmarto for these | instructions |
It looks like we only need to define PPCfmarto for these because according to | PowerISA_V3 |
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s | result |
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s | src3 |
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← FPSCR | RN |
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← FPSCR v result ← src2 rnd ← FPSCR v result ← | bfp_CONVERT_TO_BFP128 (rnd) DAG patterns of each instruction(PPCInstrVSX.td)[(set f128:$vT,(PPCfmarto f128:$vA, f128:$vB,(fneg f128:$vTi)))] |
QP Compare Ordered | Unordered |
QP Compare Ordered outs | crrc |
QP Compare Ordered outs ins | vsfrc |
QP Compare Ordered outs ins xscmpudp | $crD |
QP Compare Ordered outs ins xscmpudp | $XA |
QP Compare Ordered outs ins xscmpudp | $XB |
QP Compare Ordered outs ins xscmpudp | IIC_FPCompare |
QP Compare Ordered outs ins xscmpudp No | SDAG |
QP Compare Ordered outs ins xscmpudp No | intrinsic |
QP Compare Ordered outs ins xscmpudp No builtin are required Or llvm fcmp order unorder compare DP QP Compare | Exponents |
QP Compare Ordered outs ins xscmpudp No builtin are required Or llvm fcmp order unorder compare DP QP Compare builtin are required DP | Compare == |
QP Compare Ordered outs ins xscmpudp No builtin are required Or llvm fcmp order unorder compare DP QP Compare builtin are required DP xscmp *dp write to VSX register Use int_ppc_vsx_xscmpeqdp | f64 |
QP Compare Ordered outs ins xscmpudp No builtin are required Or llvm fcmp order unorder compare DP QP Compare builtin are required DP xscmp *dp write to VSX register Use int_ppc_vsx_xscmpeqdp int_ppc_vsx_xscmpgedp int_ppc_vsx_xscmpgtdp int_ppc_vsx_xscmpnedp | xvcmpeqdp |
QP Compare Ordered outs ins xscmpudp No builtin are required Or llvm fcmp order unorder compare DP QP Compare builtin are required DP xscmp *dp write to VSX register Use int_ppc_vsx_xscmpeqdp int_ppc_vsx_xscmpgedp int_ppc_vsx_xscmpgtdp int_ppc_vsx_xscmpnedp | $XT |
QP Compare Ordered outs ins xscmpudp No builtin are required Or llvm fcmp order unorder compare DP QP Compare builtin are required DP xscmp *dp write to VSX register Use int_ppc_vsx_xscmpeqdp int_ppc_vsx_xscmpgedp int_ppc_vsx_xscmpgtdp int_ppc_vsx_xscmpnedp | IIC_VecFPCompare |
QP Compare Ordered outs ins xscmpudp No builtin are required Or llvm fcmp order unorder compare DP QP Compare builtin are required DP xscmp *dp write to VSX register Use int_ppc_vsx_xscmpeqdp int_ppc_vsx_xscmpgedp int_ppc_vsx_xscmpgtdp int_ppc_vsx_xscmpnedp | int_ppc_vsx_xvcmpeqdp |
QP Compare Ordered outs ins xscmpudp No builtin are required Or llvm fcmp order unorder compare DP QP Compare builtin are required DP xscmp *dp write to VSX register Use int_ppc_vsx_xscmpeqdp int_ppc_vsx_xscmpgedp int_ppc_vsx_xscmpgtdp int_ppc_vsx_xscmpnedp | v2i64 |
QP Compare Ordered outs ins xscmpudp No builtin are required Or llvm fcmp order unorder compare DP QP Compare builtin are required DP xscmp *dp write to VSX register Use int_ppc_vsx_xscmpeqdp int_ppc_vsx_xscmpgedp int_ppc_vsx_xscmpgtdp int_ppc_vsx_xscmpnedp | v2f64 |
So we should use XX3Form_Rcr to implement intrinsic Convert DP | QP |
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp | IIC_VecFP |
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp | So |
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision | Integer |
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision | XSRDPIC |
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision | XSRDPIM |
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store | Vector |
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store load | ix16addr |
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector | Indexed |
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load | xoaddr |
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins | memrr |
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx | $src |
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx | IIC_LdStLFD |
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load | iaddrX4 |
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to | DP |
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to outs | vssrc |
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to outs ins lxsspx set | f32 |
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to outs ins lxsspx set load store outs ins lxsiwzx set PPClfiwzx | outs |
This returns a reference to a raw_fd_ostream for standard output. More... | |
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to outs ins lxsspx set load store outs ins lxsiwzx set PPClfiwzx ins stxsiwx | $dst |
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to outs ins lxsspx set load store outs ins lxsiwzx set PPClfiwzx ins stxsiwx | IIC_LdStSTFD |
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to outs ins lxsspx set load store outs ins lxsiwzx set PPClfiwzx ins stxsiwx PPCstfiwx outs | vsrc |
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to outs ins lxsspx set load store outs ins lxsiwzx set PPClfiwzx ins stxsiwx PPCstfiwx outs ins lxvd2x set | v8i16 |
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to outs ins lxsspx set load store outs ins lxsiwzx set PPClfiwzx ins stxsiwx PPCstfiwx outs ins lxvd2x set int_ppc_vsx_lxvh8x int_ppc_vsx_lxvb16x ins stxvd2x store int_ppc_vsx_lxvl int_ppc_vsx_lxvll int_ppc_vsx_lxvwsx st[dw] | at |
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← FPSCR v result ← bfp_CONVERT_TO_BFP128 | ( | rnd | ) |
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← FPSCR v result ← src2 rnd ← bfp_NEGATE | ( | bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v) | ) |
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← FPSCR v result ← src2 rnd ← bfp_NEGATE | ( | src2 | ) |
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← bfp_ROUND_TO_BFP128 | ( | RO | , |
FPSCR. | RN, | ||
v | |||
) |
Decimal Convert From to National Zoned Signed int_ppc_altivec_bcdcfno int_ppc_altivec_bcdcfzo int_ppc_altivec_bcdctno int_ppc_altivec_bcdctzo int_ppc_altivec_bcdcfsqo int_ppc_altivec_bcdctsqo int_ppc_altivec_bcdcpsgno int_ppc_altivec_bcdsetsgno int_ppc_altivec_bcdso int_ppc_altivec_bcduso int_ppc_altivec_bcdsro i e VA byte [7] Decimal (Unsigned) Truncate Define DAG Node in PPCInstrInfo def def def def DAG patterns of each instruction | ( | PPCInstrVSX. | td | ) |
Definition at line 211 of file README_P9.txt.
References llvm::MCID::Add.
Definition at line 245 of file README_P9.txt.
References llvm::MCID::Add.
Definition at line 301 of file README_P9.txt.
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round& Convert QP DP (dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin (set f128:$vT, (int_ppc_vsx_xsrqpi f128:$vB)) (set f128 yields<n x <ty> ><result> yields<ty><result> No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to outs ins lxsspx set load store outs ins lxsiwzx set PPClfiwzx ins stxsiwx PPCstfiwx outs ins lxvd2x set int_ppc_vsx_lxvh8x int_ppc_vsx_lxvb16x ins stxvd2x $dst |
Definition at line 538 of file README_P9.txt.
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round& Convert QP DP (dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin (set f128:$vT, (int_ppc_vsx_xsrqpi f128:$vB)) (set f128 yields<n x <ty> ><result> yields<ty><result> No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to outs ins lxsspx set load store outs ins lxsiwzx set PPClfiwzx ins stxsiwx PPCstfiwx outs ins lxvd2x $src |
Definition at line 512 of file README_P9.txt.
QP Compare Ordered outs ins xscmpudp No builtin are required Or llvm fcmp order unorder compare DP QP Compare builtin are required DP xscmp *dp write to VSX register Use int_ppc_vsx_xscmpeqdp int_ppc_vsx_xscmpgedp int_ppc_vsx_xscmpgtdp int_ppc_vsx_xscmpnedp $XA |
Definition at line 301 of file README_P9.txt.
Definition at line 301 of file README_P9.txt.
Definition at line 322 of file README_P9.txt.
TODO __pad4__ |
Definition at line 9 of file README_P9.txt.
__pad5__ |
Definition at line 226 of file README_P9.txt.
__pad6__ |
Definition at line 250 of file README_P9.txt.
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← FPSCR v result ← src2 rnd ← FPSCR v result ← AltVSXFMARel |
Definition at line 228 of file README_P9.txt.
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round& Convert QP DP (dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin (set f128:$vT, (int_ppc_vsx_xsrqpi f128:$vB)) (set f128 yields<n x <ty> ><result> yields<ty><result> No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to outs ins lxsspx set load store outs ins lxsiwzx set PPClfiwzx ins stxsiwx PPCstfiwx outs ins lxvd2x set int_ppc_vsx_lxvh8x int_ppc_vsx_lxvb16x ins stxvd2x store int_ppc_vsx_lxvl int_ppc_vsx_lxvll int_ppc_vsx_lxvwsx st [dw] at |
Definition at line 578 of file README_P9.txt.
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← FPSCR v result ← src2 rnd ← FPSCR v result ← bfp_CONVERT_TO_BFP128(rnd) DAG patterns of each instruction(PPCInstrVSX.td)[(set f128:$vT,(PPCfmarto f128:$vA, f128:$vB,(fneg f128:$vTi)))] |
Definition at line 273 of file README_P9.txt.
QP Compare Ordered outs ins xscmpudp No builtin are required Or llvm fcmp order unorder compare DP QP Compare builtin are required DP Compare == |
Definition at line 309 of file README_P9.txt.
Referenced by llvm::OpenMPIRBuilder::createAtomicCompare(), findLoopComponents(), getCompareSourceReg(), isCompareZero(), llvm::coverage::CoverageMapping::load(), llvm::ConstantRange::multiply(), llvm::ConstantRange::smul_fast(), llvm::ConstantRange::smul_sat(), and llvm::sortPtrAccesses().
Definition at line 299 of file README_P9.txt.
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP |
Definition at line 520 of file README_P9.txt.
Referenced by combineVPDPBUSDPattern(), llvm::LLVMContext::diagnose(), llvm::LTOCodeGenerator::DiagnosticHandler(), llvm::XCoreRegisterInfo::getReservedRegs(), LLVMGetDiagInfoDescription(), llvm::LinkDiagnosticInfo::print(), llvm::DiagnosticInfoInlineAsm::print(), llvm::DiagnosticInfoDebugMetadataVersion::print(), llvm::DiagnosticInfoIgnoringInvalidDebugMetadata::print(), llvm::DiagnosticInfoSampleProfile::print(), llvm::DiagnosticInfoPGOProfile::print(), llvm::DiagnosticInfoResourceLimit::print(), llvm::DiagnosticInfoOptimizationBase::print(), llvm::DiagnosticInfoMIRParser::print(), llvm::DiagnosticInfoISelFallback::print(), llvm::DiagnosticInfoUnsupported::print(), llvm::DiagnosticInfoMisExpect::print(), llvm::DiagnosticInfoSrcMgr::print(), llvm::DiagnosticInfoDontCall::print(), and llvm::LegacyDivergenceAnalysisImpl::run().
QP Compare Ordered outs ins xscmpudp No builtin are required Or llvm fcmp order unorder compare DP QP Compare Exponents |
Definition at line 307 of file README_P9.txt.
fma f128 |
Definition at line 226 of file README_P9.txt.
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round& Convert QP DP (dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin (set f128:$vT, (int_ppc_vsx_xsrqpi f128:$vB)) (set f128 yields<n x <ty> ><result> yields<ty><result> No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to outs ins lxsspx set f32 |
Definition at line 522 of file README_P9.txt.
QP Compare Ordered outs ins xscmpudp No builtin are required Or llvm fcmp order unorder compare DP QP Compare builtin are required DP xscmp *dp write to VSX register Use int_ppc_vsx_xscmpeqdp int_ppc_vsx_xscmpgedp int_ppc_vsx_xscmpgtdp int_ppc_vsx_xscmpnedp f64 |
Definition at line 314 of file README_P9.txt.
Decimal Convert From to National Zoned Signed int_ppc_altivec_bcdcfno int_ppc_altivec_bcdcfzo int_ppc_altivec_bcdctno int_ppc_altivec_bcdctzo int_ppc_altivec_bcdcfsqo int_ppc_altivec_bcdctsqo int_ppc_altivec_bcdcpsgno int_ppc_altivec_bcdsetsgno int_ppc_altivec_bcdso int_ppc_altivec_bcduso int_ppc_altivec_bcdsro i1 |
Definition at line 147 of file README_P9.txt.
Referenced by abort_gzip(), foo(), and ValuesOverlap().
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round& Convert QP DP (dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin (set f128:$vT, (int_ppc_vsx_xsrqpi f128:$vB)) (set f128 yields<n x <ty> ><result> yields<ty><result> No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to outs ins lxsspx set load store iaddrX4 |
Definition at line 516 of file README_P9.txt.
Definition at line 301 of file README_P9.txt.
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round& Convert QP DP (dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin (set f128:$vT, (int_ppc_vsx_xsrqpi f128:$vB)) (set f128 yields<n x <ty> ><result> yields<ty><result> No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to outs ins lxsspx set load store outs ins lxsiwzx set PPClfiwzx ins stxsiwx PPCstfiwx outs ins lxvd2x IIC_LdStLFD |
Definition at line 512 of file README_P9.txt.
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round& Convert QP DP (dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin (set f128:$vT, (int_ppc_vsx_xsrqpi f128:$vB)) (set f128 yields<n x <ty> ><result> yields<ty><result> No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to outs ins lxsspx set load store outs ins lxsiwzx set PPClfiwzx ins stxsiwx PPCstfiwx outs ins lxvd2x set int_ppc_vsx_lxvh8x int_ppc_vsx_lxvb16x ins stxvd2x IIC_LdStSTFD |
Definition at line 538 of file README_P9.txt.
Definition at line 331 of file README_P9.txt.
QP Compare Ordered outs ins xscmpudp No builtin are required Or llvm fcmp order unorder compare DP QP Compare builtin are required DP xscmp* dp write to VSX register Use int_ppc_vsx_xscmpeqdp int_ppc_vsx_xscmpgedp int_ppc_vsx_xscmpgtdp int_ppc_vsx_xscmpnedp IIC_VecFPCompare |
Definition at line 322 of file README_P9.txt.
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round& Convert QP DP (dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin (set f128:$vT, (int_ppc_vsx_xsrqpi f128:$vB)) (set f128 yields<n x <ty> ><result> yields<ty><result> No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector Indexed |
Definition at line 505 of file README_P9.txt.
Referenced by llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getLoadVP(), llvm::SelectionDAG::getMaskedLoad(), llvm::SelectionDAG::getMaskedStore(), llvm::SelectionDAG::getStoreVP(), llvm::SelectionDAG::getStridedLoadVP(), llvm::SelectionDAG::getStridedStoreVP(), and validInsertValueIndex().
Vector Rotate Left Mask Mask Insert |
Definition at line 112 of file README_P9.txt.
Referenced by llvm::BlockFrequencyInfoImplBase::analyzeIrreducible(), llvm::DomTreeBuilder::SemiNCAInfo< DomTreeT >::ApplyNextUpdate(), llvm::DomTreeBuilder::SemiNCAInfo< DomTreeT >::ApplyUpdates(), llvm::WebAssemblyDebugValueManager::clone(), combineTargetShuffle(), createIrreducibleLoop(), createUnreachableSwitchDefault(), llvm::EpilogueVectorizerEpilogueLoop::emitMinimumVectorEpilogueIterCountCheck(), FoldCondBranchOnValueKnownInPredecessorImpl(), FoldTwoEntryPHINode(), llvm::X86MachineFunctionInfo::getPreallocatedIdForCallSite(), llvm::HexagonTTIImpl::getScalarizationOverhead(), llvm::X86TTIImpl::getScalarizationOverhead(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getScalarizationOverhead(), llvm::TargetTransformInfo::getScalarizationOverhead(), getVRegDef(), instCombineSVEDup(), isSafeToMove(), llvm::SIInstrInfo::legalizeOperands(), LLVMBuildArrayMalloc(), LLVMBuildFree(), LLVMBuildMalloc(), matchShuffleAsINSERTQ(), llvm::WebAssemblyDebugValueManager::move(), moveAndTeeForMultiUse(), moveForSingleUse(), llvm::sys::unicode::nearestMatchesForCodepointName(), performBranchToCommonDestFolding(), performDupLane128Combine(), reduceMaskedLoadToScalarLoad(), rematerializeCheapDef(), removeEmptyCleanup(), removeSwitchAfterSelectFold(), removeUndefIntroducingPredecessor(), llvm::RegBankSelect::RepairingPlacement::RepairingPlacement(), llvm::AArch64TargetLowering::shouldSinkOperands(), SimplifyCondBranchToCondBranch(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), splitBlock(), llvm::RegBankSelect::RepairingPlacement::switchTo(), SwitchToLookupTable(), TryToMergeLandingPad(), tryWidenCondBranchToCondBranch(), and llvm::InstCombinerImpl::visitInsertElementInst().
Definition at line 250 of file README_P9.txt.
Definition at line 140 of file README_P9.txt.
Definition at line 134 of file README_P9.txt.
Definition at line 108 of file README_P9.txt.
Vector Rotate Left Mask Mask int_ppc_altivec_vrlwnm |
Definition at line 112 of file README_P9.txt.
Definition at line 128 of file README_P9.txt.
QP Compare Ordered outs ins xscmpudp No builtin are required Or llvm fcmp order unorder compare DP QP Compare builtin are required DP xscmp* dp write to VSX register Use int_ppc_vsx_xscmpeqdp int_ppc_vsx_xscmpgedp int_ppc_vsx_xscmpgtdp int_ppc_vsx_xscmpnedp int_ppc_vsx_xvcmpeqdp |
Definition at line 323 of file README_P9.txt.
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round& Convert QP DP (dword[1] is set to zero) No builtin are required Round to Quad Precision Integer |
Definition at line 366 of file README_P9.txt.
Referenced by llvm::DwarfUnit::addSectionOffset(), llvm::DwarfUnit::addSInt(), llvm::DwarfUnit::addUInt(), llvm::DIEInteger::DIEInteger(), EnumLiteral::EnumLiteral(), llvm::MipsRegisterBankInfo::getInstrMapping(), llvm::DIEInteger::getValue(), EnumLiteral::match(), parseHexOcta(), EnumLiteral::printLeft(), llvm::DIEInteger::setValue(), writeInteger(), and writeVariableSizedInteger().
Definition at line 303 of file README_P9.txt.
Referenced by llvm::pdb::DIARawSymbol::dump().
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round& Convert QP DP (dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin (set f128:$vT, (int_ppc_vsx_xsrqpi f128:$vB)) (set f128 yields<n x <ty> ><result> yields<ty><result> No builtin are required Load Store load store ix16addr |
Definition at line 498 of file README_P9.txt.
Definition at line 118 of file README_P9.txt.
Referenced by llvm::InstCombinerImpl::foldICmpShlConstant(), llvm::APSInt::operator>>(), llvm::APInt::relativeLShr(), simplifyAndInst(), and llvm::APFixedPoint::toString().
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round& Convert QP DP (dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin (set f128:$vT, (int_ppc_vsx_xsrqpi f128:$vB)) (set f128 yields<n x <ty> ><result> yields<ty><result> No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to outs ins lxsspx set load store outs ins lxsiwzx set PPClfiwzx ins stxsiwx PPCstfiwx outs ins lxvd2x set int_ppc_vsx_lxvh8x int_ppc_vsx_lxvb16x ins memrr |
Definition at line 511 of file README_P9.txt.
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← FPSCR v result ← src2 rnd ← FPSCR v result ← NoEncode<"$vTi"> |
Definition at line 227 of file README_P9.txt.
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round& Convert QP DP (dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin (set f128:$vT, (int_ppc_vsx_xsrqpi f128:$vB)) (set f128 yields<n x <ty> ><result> yields<ty><result> No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to outs ins lxsspx set load store outs ins lxsiwzx set PPClfiwzx ins stxsiwx PPCstfiwx outs ins lxvd2x set int_ppc_vsx_lxvh8x int_ppc_vsx_lxvb16x outs |
This returns a reference to a raw_fd_ostream for standard output.
Use it like: outs() << "foo" << "bar";
Definition at line 537 of file README_P9.txt.
References assert(), llvm::sys::fs::OF_None, and S.
Referenced by llvm::AMDGPUDisassembler::decodeKernelDescriptor(), llvm::dlltoolDriverMain(), llvm::pdb::PDBSymbol::dumpChildStats(), llvm::AADepGraph::dumpGraph(), llvm::pdb::PDBSymbol::dumpProperties(), llvm::fouts(), llvm::logicalview::LVCompare::getInstance(), llvm::logicalview::LVReader::getInstance(), llvm::libDriverMain(), llvm::DWARFLinker::link(), lle_X_printf(), llvm::AADepGraph::print(), llvm::AttributorCallGraph::print(), llvm::cl::Option::printEnumValHelpStr(), llvm::cl::generic_parser_base::printGenericOptionDiff(), llvm::cl::Option::printHelpStr(), llvm::cl::generic_parser_base::printOptionInfo(), llvm::cl::basic_parser_impl::printOptionInfo(), llvm::cl::basic_parser_impl::printOptionName(), llvm::cl::basic_parser_impl::printOptionNoValue(), llvm::ToolOutputFile::ToolOutputFile(), and llvm::writeToOutput().
Definition at line 253 of file README_P9.txt.
Decimal Convert From to National Zoned Signed int_ppc_altivec_bcdcfno int_ppc_altivec_bcdcfzo int_ppc_altivec_bcdctno int_ppc_altivec_bcdctzo int_ppc_altivec_bcdcfsqo int_ppc_altivec_bcdctsqo int_ppc_altivec_bcdcpsgno int_ppc_altivec_bcdsetsgno int_ppc_altivec_bcdso int_ppc_altivec_bcduso int_ppc_altivec_bcdsro i e VA byte [7] Decimal (Unsigned) Truncate Define DAG Node in PPCInstrInfo def PPCfdivrto |
Definition at line 205 of file README_P9.txt.
Decimal Convert From to National Zoned Signed int_ppc_altivec_bcdcfno int_ppc_altivec_bcdcfzo int_ppc_altivec_bcdctno int_ppc_altivec_bcdctzo int_ppc_altivec_bcdcfsqo int_ppc_altivec_bcdctsqo int_ppc_altivec_bcdcpsgno int_ppc_altivec_bcdsetsgno int_ppc_altivec_bcdso int_ppc_altivec_bcduso int_ppc_altivec_bcdsro i e VA byte [7] Decimal (Unsigned) Truncate Define DAG Node in PPCInstrInfo def def PPCfmulrto |
Definition at line 206 of file README_P9.txt.
Decimal Convert From to National Zoned Signed int_ppc_altivec_bcdcfno int_ppc_altivec_bcdcfzo int_ppc_altivec_bcdctno int_ppc_altivec_bcdctzo int_ppc_altivec_bcdcfsqo int_ppc_altivec_bcdctsqo int_ppc_altivec_bcdcpsgno int_ppc_altivec_bcdsetsgno int_ppc_altivec_bcdso int_ppc_altivec_bcduso int_ppc_altivec_bcdsro i e VA byte [7] Decimal (Unsigned) Truncate Define DAG Node in PPCInstrInfo def def def def PPCfsqrtrto |
Definition at line 208 of file README_P9.txt.
Decimal Convert From to National Zoned Signed int_ppc_altivec_bcdcfno int_ppc_altivec_bcdcfzo int_ppc_altivec_bcdctno int_ppc_altivec_bcdctzo int_ppc_altivec_bcdcfsqo int_ppc_altivec_bcdctsqo int_ppc_altivec_bcdcpsgno int_ppc_altivec_bcdsetsgno int_ppc_altivec_bcdso int_ppc_altivec_bcduso int_ppc_altivec_bcdsro i e VA byte [7] Decimal (Unsigned) Truncate Define DAG Node in PPCInstrInfo def def def PPCfsubrto |
Definition at line 207 of file README_P9.txt.
Definition at line 329 of file README_P9.txt.
Definition at line 131 of file README_P9.txt.
Definition at line 146 of file README_P9.txt.
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← FPSCR v result ← src2 rnd ← FPSCR v result ← RegConstraint<"$vTi = $vT"> |
Definition at line 227 of file README_P9.txt.
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s result |
Definition at line 256 of file README_P9.txt.
Referenced by addAndInterleaveWithUnsupported(), llvm::MachO::InterfaceFile::addSymbol(), llvm::DIExpression::append(), BURRSort(), llvm::detail::IEEEFloat::compare(), llvm::sys::CompareAndSwap(), llvm::APFloat::convertToInteger(), llvm::ConvertUTF16toUTF32(), llvm::ConvertUTF16toUTF8(), llvm::ConvertUTF32toUTF16(), llvm::ConvertUTF32toUTF8(), llvm::ConvertUTF8toUTF16(), llvm::ConvertUTF8toUTF32Impl(), llvm::ConvertUTF8toWide(), llvm::LegacyLegalizerInfo::decreaseToSmallerTypesAndIncreaseToSmallest(), llvm::sys::fs::equivalent(), llvm::hashing::detail::fetch32(), llvm::hashing::detail::fetch64(), findBasePointers(), getBranchCondString(), getClearedMemory(), llvm::SDVTListNode::getSDVTList(), getSingleExitNode(), llvm::sampleprof::SampleProfileReaderText::hasFormat(), llvm::LegacyLegalizerInfo::increaseToLargerTypesAndDecreaseToLargest(), llvm::SetVector< llvm::MCSection *, SmallVector< llvm::MCSection *, N >, SmallDenseSet< llvm::MCSection *, N > >::insert(), llvm::sys::fs::is_directory(), llvm::sys::fs::is_regular_file(), llvm::sys::fs::is_symlink_file(), llvm::dwarf::isCPlusPlus(), llvm::dwarf::isFortran(), llvm::detail::ValueMatchesMono< T >::MatchAndExplain(), llvm::sys::path::native(), llvm::detail::IEEEFloat::next(), llvm::MachO::ArchitectureSet::operator std::string(), llvm::partAsHex(), llvm::powerOf5(), llvm::detail::IEEEFloat::remainder(), widen_1(), and widen_8_16().
Definition at line 118 of file README_P9.txt.
Referenced by llvm::createMinMaxOp(), llvm::createSelectCmpOp(), llvm::createSelectCmpTargetReduction(), llvm::fmt_pad(), llvm::detail::PadAdapter< T >::format(), llvm::ImutAVLTree< ImutInfo >::getMaxElement(), getTryAncestor(), llvm::IntervalTree< LVAddress, LVScope * >::insert(), llvm::IntervalData< PointT, ValueT >::IntervalData(), llvm::PatternMatch::match_combine_and< LTy, RTy >::match_combine_and(), llvm::PatternMatch::match_combine_or< LTy, RTy >::match_combine_or(), matchINS(), llvm::iplist_impl< simple_ilist< llvm::AliasSet, Options... >, ilist_traits< llvm::AliasSet > >::merge(), llvm::object::MachOChainedFixupEntry::moveNext(), llvm::detail::PadAdapter< T >::PadAdapter(), llvm::IntervalData< PointT, ValueT >::right(), llvm::logicalview::sortByKind(), llvm::logicalview::sortByLine(), llvm::logicalview::sortByName(), llvm::formatv_object_base::splitLiteralAndReplacement(), and std::swap().
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← FPSCR v result ← src2 rnd ← FPSCR RN |
Definition at line 262 of file README_P9.txt.
Referenced by AVRDAGToDAGISel::select< ISD::STORE >(), llvm::DDGBuilder::createRootNode(), GetCodeName(), llvm::DominatorTreeBase< BasicBlock, false >::getDescendants(), llvm::MachineRegionNode::operator==(), llvm::MachineRegion::operator==(), llvm::RegionNode::operator==(), and llvm::Region::operator==().
Definition at line 301 of file README_P9.txt.
Referenced by llvm::SelectionDAG::FlagInserter::FlagInserter().
Decimal Convert From to National Zoned Signed int_ppc_altivec_bcdcfno int_ppc_altivec_bcdcfzo int_ppc_altivec_bcdctno int_ppc_altivec_bcdctzo int_ppc_altivec_bcdcfsqo int_ppc_altivec_bcdctsqo int_ppc_altivec_bcdcpsgno int_ppc_altivec_bcdsetsgno int_ppc_altivec_bcdso int_ppc_altivec_bcduso int_ppc_altivec_bcdsro i e VA byte [7] Decimal (Unsigned) Truncate Define DAG Node in PPCInstrInfo def def def SDTFPBinOp |
Definition at line 205 of file README_P9.txt.
SDTFPTernaryOp |
Definition at line 250 of file README_P9.txt.
Decimal Convert From to National Zoned Signed int_ppc_altivec_bcdcfno int_ppc_altivec_bcdcfzo int_ppc_altivec_bcdctno int_ppc_altivec_bcdctzo int_ppc_altivec_bcdcfsqo int_ppc_altivec_bcdctsqo int_ppc_altivec_bcdcpsgno int_ppc_altivec_bcdsetsgno int_ppc_altivec_bcdso int_ppc_altivec_bcduso int_ppc_altivec_bcdsro i e VA byte [7] Decimal (Unsigned) Truncate Define DAG Node in PPCInstrInfo def def def def SDTFPUnaryOp |
Definition at line 209 of file README_P9.txt.
Definition at line 119 of file README_P9.txt.
Referenced by llvm::APFloatBase::semanticsMaxExponent(), llvm::APFloatBase::semanticsMinExponent(), llvm::APFloatBase::semanticsPrecision(), and llvm::APFloatBase::semanticsSizeInBits().
Definition at line 331 of file README_P9.txt.
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← FPSCR v result ← src2 rnd ← src3 |
Definition at line 256 of file README_P9.txt.
Decimal Convert From to National Zoned Signed int_ppc_altivec_bcdcfno int_ppc_altivec_bcdcfzo int_ppc_altivec_bcdctno int_ppc_altivec_bcdctzo int_ppc_altivec_bcdcfsqo int_ppc_altivec_bcdctsqo int_ppc_altivec_bcdcpsgno int_ppc_altivec_bcdsetsgno int_ppc_altivec_bcdso int_ppc_altivec_bcduso int_ppc_altivec_bcdsro i e VA byte [7] Decimal (Unsigned) Truncate Define DAG Node in PPCInstrInfo td |
Definition at line 166 of file README_P9.txt.
Definition at line 299 of file README_P9.txt.
Referenced by addAcquireOrdering(), addReleaseOrdering(), getDecodedOrdering(), llvm::AANoSync::isNonRelaxedAtomic(), and llvm::promoteLoopAccessesToScalars().
Definition at line 108 of file README_P9.txt.
Decimal Convert From to National Zoned Signed int_ppc_altivec_bcdcfno int_ppc_altivec_bcdcfzo int_ppc_altivec_bcdctno int_ppc_altivec_bcdctzo int_ppc_altivec_bcdcfsqo int_ppc_altivec_bcdctsqo int_ppc_altivec_bcdcpsgno int_ppc_altivec_bcdsetsgno int_ppc_altivec_bcdso int_ppc_altivec_bcduso int_ppc_altivec_bcdsro v1i128 |
Definition at line 134 of file README_P9.txt.
QP Compare Ordered outs ins xscmpudp No builtin are required Or llvm fcmp order unorder compare DP QP Compare builtin are required DP xscmp* dp write to VSX register Use int_ppc_vsx_xscmpeqdp int_ppc_vsx_xscmpgedp int_ppc_vsx_xscmpgtdp int_ppc_vsx_xscmpnedp v2f64 |
Definition at line 323 of file README_P9.txt.
QP Compare Ordered outs ins xscmpudp No builtin are required Or llvm fcmp order unorder compare DP QP Compare builtin are required DP xscmp* dp write to VSX register Use int_ppc_vsx_xscmpeqdp int_ppc_vsx_xscmpgedp int_ppc_vsx_xscmpgtdp int_ppc_vsx_xscmpnedp v2i64 |
Definition at line 323 of file README_P9.txt.
Vector Rotate Left Mask Mask v4i32 |
Definition at line 112 of file README_P9.txt.
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round& Convert QP DP (dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin (set f128:$vT, (int_ppc_vsx_xsrqpi f128:$vB)) (set f128 yields<n x <ty> ><result> yields<ty><result> No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to outs ins lxsspx set load store outs ins lxsiwzx set PPClfiwzx ins stxsiwx PPCstfiwx outs ins lxvd2x set int_ppc_vsx_lxvh8x int_ppc_vsx_lxvb16x ins stxvd2x store v8i16 |
Definition at line 548 of file README_P9.txt.
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round& Convert QP DP (dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin (set f128:$vT, (int_ppc_vsx_xsrqpi f128:$vB)) (set f128 yields<n x <ty> ><result> yields<ty><result> No builtin are required Load Store Vector |
Definition at line 497 of file README_P9.txt.
Referenced by llvm::PBQP::applyR1(), llvm::PBQP::applyR2(), llvm::MapVector< AssertingVH< Instruction >, AssertingVH< Value > >::back(), llvm::BlotMapVector< KeyT, ValueT >::begin(), llvm::MapVector< AssertingVH< Instruction >, AssertingVH< Value > >::begin(), llvm::UniqueVector< DebugVariable >::begin(), llvm::SmallSet< unsigned, 16 >::begin(), llvm::FoldingSetVector< T, VectorT >::begin(), llvm::BlotMapVector< KeyT, ValueT >::blot(), llvm::MapVector< AssertingVH< Instruction >, AssertingVH< Value > >::clear(), llvm::BlotMapVector< KeyT, ValueT >::clear(), llvm::SmallSet< unsigned, 16 >::clear(), llvm::FoldingSetVector< T, VectorT >::clear(), llvm::SmallSet< unsigned, 16 >::contains(), llvm::SmallSet< unsigned, 16 >::count(), llvm::MapVector< AssertingVH< Instruction >, AssertingVH< Value > >::empty(), llvm::UniqueVector< DebugVariable >::empty(), llvm::BlotMapVector< KeyT, ValueT >::empty(), llvm::SmallSet< unsigned, 16 >::empty(), llvm::BlotMapVector< KeyT, ValueT >::end(), llvm::MapVector< AssertingVH< Instruction >, AssertingVH< Value > >::end(), llvm::UniqueVector< DebugVariable >::end(), llvm::SmallSet< unsigned, 16 >::end(), llvm::FoldingSetVector< T, VectorT >::end(), llvm::MapVector< AssertingVH< Instruction >, AssertingVH< Value > >::erase(), llvm::SmallSet< unsigned, 16 >::erase(), llvm::BlotMapVector< KeyT, ValueT >::find(), llvm::MapVector< AssertingVH< Instruction >, AssertingVH< Value > >::find(), llvm::MapVector< AssertingVH< Instruction >, AssertingVH< Value > >::front(), llvm::XCoreTTIImpl::getNumberOfRegisters(), llvm::WebAssemblyTTIImpl::getNumberOfRegisters(), llvm::SystemZTTIImpl::getNumberOfRegisters(), llvm::HexagonTTIImpl::getNumberOfRegisters(), llvm::AArch64TTIImpl::getNumberOfRegisters(), llvm::X86TTIImpl::getNumberOfRegisters(), llvm::ARMTTIImpl::getNumberOfRegisters(), llvm::FoldingSetVector< T, VectorT >::GetOrInsertNode(), llvm::PPCTTIImpl::getRegisterClassForType(), llvm::RISCVTTIImpl::getRegisterClassForType(), llvm::TargetTransformInfoImplBase::getRegisterClassForType(), llvm::TargetTransformInfo::getRegisterClassForType(), llvm::GetElementPtrInst::getTypeAtIndex(), llvm::BlotMapVector< KeyT, ValueT >::insert(), llvm::MapVector< AssertingVH< Instruction >, AssertingVH< Value > >::insert(), llvm::SmallSet< unsigned, 16 >::insert(), llvm::FoldingSetVector< T, VectorT >::InsertNode(), instrumentMaskedLoadOrStore(), llvm::R600InstrInfo::isLegalUpTo(), llvm::MapVector< AssertingVH< Instruction >, AssertingVH< Value > >::lookup(), llvm::BlotMapVector< KeyT, ValueT >::operator[](), llvm::UniqueVector< DebugVariable >::operator[](), llvm::MapVector< AssertingVH< Instruction >, AssertingVH< Value > >::operator[](), performPostLD1Combine(), llvm::MapVector< AssertingVH< Instruction >, AssertingVH< Value > >::pop_back(), llvm::MapVector< AssertingVH< Instruction >, AssertingVH< Value > >::rbegin(), llvm::MapVector< AssertingVH< Instruction >, AssertingVH< Value > >::remove_if(), llvm::MapVector< AssertingVH< Instruction >, AssertingVH< Value > >::rend(), llvm::MapVector< AssertingVH< Instruction >, AssertingVH< Value > >::reserve(), llvm::UniqueVector< DebugVariable >::reset(), llvm::MapVector< AssertingVH< Instruction >, AssertingVH< Value > >::size(), llvm::UniqueVector< DebugVariable >::size(), llvm::SmallSet< unsigned, 16 >::size(), llvm::MapVector< AssertingVH< Instruction >, AssertingVH< Value > >::swap(), llvm::MapVector< AssertingVH< Instruction >, AssertingVH< Value > >::takeVector(), and llvm::SetVector< llvm::MCSection *, SmallVector< llvm::MCSection *, N >, SmallDenseSet< llvm::MCSection *, N > >::takeVector().
Definition at line 140 of file README_P9.txt.
Definition at line 134 of file README_P9.txt.
Definition at line 9 of file README_P9.txt.
Vector Rotate Left Mask Mask vrlwnm |
Definition at line 112 of file README_P9.txt.
Definition at line 300 of file README_P9.txt.
Definition at line 128 of file README_P9.txt.
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round& Convert QP DP (dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin (set f128:$vT, (int_ppc_vsx_xsrqpi f128:$vB)) (set f128 yields<n x <ty> ><result> yields<ty><result> No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to outs ins lxsspx set load store outs ins lxsiwzx set PPClfiwzx ins stxsiwx PPCstfiwx outs ins lxvd2x set int_ppc_vsx_lxvh8x int_ppc_vsx_lxvb16x ins vsrc |
Definition at line 545 of file README_P9.txt.
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round& Convert QP DP (dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin (set f128:$vT, (int_ppc_vsx_xsrqpi f128:$vB)) (set f128 yields<n x <ty> ><result> yields<ty><result> No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to outs vssrc |
Definition at line 520 of file README_P9.txt.
VX1_Int_Ty< 1, "vmul10cuq", int_ppc_altivec_vmul10cuq, v1i128 > |
Definition at line 135 of file README_P9.txt.
VX1_Int_Ty< 133, "vrlwmi", int_ppc_altivec_vrlwmi, v4i32 > |
Definition at line 113 of file README_P9.txt.
VX1_Int_Ty< 1796, "vsrv", int_ppc_altivec_vsrv, v16i8 > |
Definition at line 129 of file README_P9.txt.
VX1_Int_Ty< 197, "vrldmi", int_ppc_altivec_vrldmi, v2i64 > |
Definition at line 115 of file README_P9.txt.
VX1_Int_Ty< 453, "vrldnm", int_ppc_altivec_vrldnm, v2i64 > |
Definition at line 114 of file README_P9.txt.
VX1_Int_Ty< 65, "vmul10ecuq", int_ppc_altivec_vmul10ecuq, v1i128 > |
Definition at line 141 of file README_P9.txt.
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round& Convert QP DP (dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin (set f128:$vT, (int_ppc_vsx_xsrqpi f128:$vB)) (set f128 yields<n x <ty> ><result> yields<ty><result> No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to outs ins lxsspx set load store outs ins lxsiwzx set PPClfiwzx ins stxsiwx PPCstfiwx outs ins lxvd2x set int_ppc_vsx_lxvh8x int_ppc_vsx_lxvb16x ins stxvd2x store int_ppc_vsx_lxvl int_ppc_vsx_lxvll int_ppc_vsx_lxvwsx xoaddr |
Definition at line 506 of file README_P9.txt.
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round& Convert QP DP (dword[1] is set to zero) No builtin are required Round to Quad Precision XSRDPIC |
Definition at line 366 of file README_P9.txt.
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round& Convert QP DP (dword[1] is set to zero) No builtin are required Round to Quad Precision XSRDPIM |
Definition at line 366 of file README_P9.txt.
QP Compare Ordered outs ins xscmpudp No builtin are required Or llvm fcmp order unorder compare DP QP Compare builtin are required DP xscmp* dp write to VSX register Use int_ppc_vsx_xscmpeqdp int_ppc_vsx_xscmpgedp int_ppc_vsx_xscmpgtdp int_ppc_vsx_xscmpnedp xvcmpeqdp |
Definition at line 321 of file README_P9.txt.