LLVM  13.0.0git
RISCVMCInstLower.cpp
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1 //===-- RISCVMCInstLower.cpp - Convert RISCV MachineInstr to an MCInst ------=//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains code to lower RISCV MachineInstrs to their corresponding
10 // MCInst records.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "RISCV.h"
15 #include "RISCVSubtarget.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
26 
27 using namespace llvm;
28 
30  const AsmPrinter &AP) {
31  MCContext &Ctx = AP.OutContext;
33 
34  switch (MO.getTargetFlags()) {
35  default:
36  llvm_unreachable("Unknown target flag on GV operand");
37  case RISCVII::MO_None:
39  break;
40  case RISCVII::MO_CALL:
42  break;
43  case RISCVII::MO_PLT:
45  break;
46  case RISCVII::MO_LO:
48  break;
49  case RISCVII::MO_HI:
51  break;
54  break;
57  break;
58  case RISCVII::MO_GOT_HI:
60  break;
63  break;
66  break;
69  break;
72  break;
75  break;
76  }
77 
78  const MCExpr *ME =
80 
81  if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
83  ME, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
84 
86  ME = RISCVMCExpr::create(ME, Kind, Ctx);
87  return MCOperand::createExpr(ME);
88 }
89 
91  MCOperand &MCOp,
92  const AsmPrinter &AP) {
93  switch (MO.getType()) {
94  default:
95  report_fatal_error("LowerRISCVMachineInstrToMCInst: unknown operand type");
97  // Ignore all implicit register operands.
98  if (MO.isImplicit())
99  return false;
100  MCOp = MCOperand::createReg(MO.getReg());
101  break;
103  // Regmasks are like implicit defs.
104  return false;
106  MCOp = MCOperand::createImm(MO.getImm());
107  break;
109  MCOp = lowerSymbolOperand(MO, MO.getMBB()->getSymbol(), AP);
110  break;
112  MCOp = lowerSymbolOperand(MO, AP.getSymbol(MO.getGlobal()), AP);
113  break;
115  MCOp = lowerSymbolOperand(
116  MO, AP.GetBlockAddressSymbol(MO.getBlockAddress()), AP);
117  break;
119  MCOp = lowerSymbolOperand(
120  MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()), AP);
121  break;
123  MCOp = lowerSymbolOperand(MO, AP.GetCPISymbol(MO.getIndex()), AP);
124  break;
126  MCOp = lowerSymbolOperand(MO, AP.GetJTISymbol(MO.getIndex()), AP);
127  break;
128  }
129  return true;
130 }
131 
133  MCInst &OutMI) {
134  const RISCVVPseudosTable::PseudoInfo *RVV =
135  RISCVVPseudosTable::getPseudoInfo(MI->getOpcode());
136  if (!RVV)
137  return false;
138 
139  OutMI.setOpcode(RVV->BaseInstr);
140 
141  const MachineBasicBlock *MBB = MI->getParent();
142  assert(MBB && "MI expected to be in a basic block");
143  const MachineFunction *MF = MBB->getParent();
144  assert(MF && "MBB expected to be in a machine function");
145 
146  const TargetRegisterInfo *TRI =
147  MF->getSubtarget<RISCVSubtarget>().getRegisterInfo();
148  assert(TRI && "TargetRegisterInfo expected");
149 
150  uint64_t TSFlags = MI->getDesc().TSFlags;
151  int NumOps = MI->getNumExplicitOperands();
152 
153  for (const MachineOperand &MO : MI->explicit_operands()) {
154  int OpNo = (int)MI->getOperandNo(&MO);
155  assert(OpNo >= 0 && "Operand number doesn't fit in an 'int' type");
156 
157  // Skip VL and SEW operands which are the last two operands if present.
158  if ((TSFlags & RISCVII::HasVLOpMask) && OpNo == (NumOps - 2))
159  continue;
160  if ((TSFlags & RISCVII::HasSEWOpMask) && OpNo == (NumOps - 1))
161  continue;
162 
163  // Skip merge op. It should be the first operand after the result.
164  if ((TSFlags & RISCVII::HasMergeOpMask) && OpNo == 1) {
165  assert(MI->getNumExplicitDefs() == 1);
166  continue;
167  }
168 
169  MCOperand MCOp;
170  switch (MO.getType()) {
171  default:
172  llvm_unreachable("Unknown operand type");
174  unsigned Reg = MO.getReg();
175 
176  if (RISCV::VRM2RegClass.contains(Reg) ||
177  RISCV::VRM4RegClass.contains(Reg) ||
178  RISCV::VRM8RegClass.contains(Reg)) {
179  Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
180  assert(Reg && "Subregister does not exist");
181  } else if (RISCV::FPR16RegClass.contains(Reg)) {
182  Reg = TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass);
183  assert(Reg && "Subregister does not exist");
184  } else if (RISCV::FPR64RegClass.contains(Reg)) {
185  Reg = TRI->getSubReg(Reg, RISCV::sub_32);
186  assert(Reg && "Superregister does not exist");
187  }
188 
189  MCOp = MCOperand::createReg(Reg);
190  break;
191  }
193  MCOp = MCOperand::createImm(MO.getImm());
194  break;
195  }
196  OutMI.addOperand(MCOp);
197  }
198 
199  // Unmasked pseudo instructions need to append dummy mask operand to
200  // V instructions. All V instructions are modeled as the masked version.
201  if (TSFlags & RISCVII::HasDummyMaskOpMask)
202  OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister));
203 
204  return true;
205 }
206 
208  AsmPrinter &AP) {
210  return false;
211 
212  OutMI.setOpcode(MI->getOpcode());
213 
214  for (const MachineOperand &MO : MI->operands()) {
215  MCOperand MCOp;
216  if (LowerRISCVMachineOperandToMCOperand(MO, MCOp, AP))
217  OutMI.addOperand(MCOp);
218  }
219 
220  switch (OutMI.getOpcode()) {
221  case TargetOpcode::PATCHABLE_FUNCTION_ENTER: {
222  const Function &F = MI->getParent()->getParent()->getFunction();
223  if (F.hasFnAttribute("patchable-function-entry")) {
224  unsigned Num;
225  if (F.getFnAttribute("patchable-function-entry")
226  .getValueAsString()
227  .getAsInteger(10, Num))
228  return false;
229  AP.emitNops(Num);
230  return true;
231  }
232  break;
233  }
234  case RISCV::PseudoReadVLENB:
235  OutMI.setOpcode(RISCV::CSRRS);
237  RISCVSysReg::lookupSysRegByName("VLENB")->Encoding));
238  OutMI.addOperand(MCOperand::createReg(RISCV::X0));
239  break;
240  case RISCV::PseudoReadVL:
241  OutMI.setOpcode(RISCV::CSRRS);
242  OutMI.addOperand(
244  OutMI.addOperand(MCOperand::createReg(RISCV::X0));
245  break;
246  }
247  return false;
248 }
llvm::EngineKind::Kind
Kind
Definition: ExecutionEngine.h:524
AsmPrinter.h
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition: MachineOperand.h:63
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
MachineInstr.h
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:53
llvm
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::RISCVII::MO_PLT
@ MO_PLT
Definition: RISCVBaseInfo.h:92
llvm::RISCVII::HasVLOpMask
@ HasVLOpMask
Definition: RISCVBaseInfo.h:77
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:161
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:560
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:140
llvm::RISCVMCExpr::VK_RISCV_TLS_GD_HI
@ VK_RISCV_TLS_GD_HI
Definition: RISCVMCExpr.h:36
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:71
llvm::Function
Definition: Function.h:61
llvm::RISCVMCExpr::VK_RISCV_TPREL_ADD
@ VK_RISCV_TPREL_ADD
Definition: RISCVMCExpr.h:34
llvm::AArch64SysReg::lookupSysRegByName
const SysReg * lookupSysRegByName(StringRef)
llvm::MCConstantExpr::create
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::MachineOperand::getBlockAddress
const BlockAddress * getBlockAddress() const
Definition: MachineOperand.h:565
ErrorHandling.h
MachineBasicBlock.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::MachineOperand::isJTI
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
Definition: MachineOperand.h:334
RISCVMCExpr.h
llvm::RISCVMCExpr::VK_RISCV_TPREL_LO
@ VK_RISCV_TPREL_LO
Definition: RISCVMCExpr.h:32
llvm::RISCVVPseudosTable::PseudoInfo
Definition: RISCVInstrInfo.h:159
llvm::RISCVII::MO_GOT_HI
@ MO_GOT_HI
Definition: RISCVBaseInfo.h:97
llvm::RISCVMCExpr::VK_RISCV_HI
@ VK_RISCV_HI
Definition: RISCVMCExpr.h:28
llvm::RISCVII::MO_PCREL_HI
@ MO_PCREL_HI
Definition: RISCVBaseInfo.h:96
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:183
llvm::RISCVII::MO_TLS_GD_HI
@ MO_TLS_GD_HI
Definition: RISCVBaseInfo.h:102
llvm::RISCVMCExpr::VK_RISCV_TPREL_HI
@ VK_RISCV_TPREL_HI
Definition: RISCVMCExpr.h:33
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:597
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::MachineOperand::MO_Register
@ MO_Register
Register operand.
Definition: MachineOperand.h:52
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::RISCVMCExpr::VK_RISCV_TLS_GOT_HI
@ VK_RISCV_TLS_GOT_HI
Definition: RISCVMCExpr.h:35
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:196
llvm::RISCVMCExpr::VariantKind
VariantKind
Definition: RISCVMCExpr.h:25
llvm::RISCVVPseudosTable::PseudoInfo::BaseInstr
uint16_t BaseInstr
Definition: RISCVInstrInfo.h:161
llvm::RISCVII::MO_TPREL_HI
@ MO_TPREL_HI
Definition: RISCVBaseInfo.h:99
llvm::MachineBasicBlock::getSymbol
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
Definition: MachineBasicBlock.cpp:59
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:377
llvm::RISCVMCExpr::VK_RISCV_LO
@ VK_RISCV_LO
Definition: RISCVMCExpr.h:27
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:62
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:534
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
MCContext.h
llvm::lowerRISCVMachineInstrToMCInst
bool lowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP)
Definition: RISCVMCInstLower.cpp:207
MCInst.h
llvm::MachineOperand::isMBB
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Definition: MachineOperand.h:326
llvm::LowerRISCVMachineOperandToMCOperand
bool LowerRISCVMachineOperandToMCOperand(const MachineOperand &MO, MCOperand &MCOp, const AsmPrinter &AP)
Definition: RISCVMCInstLower.cpp:90
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:209
llvm::RISCVMCExpr::VK_RISCV_None
@ VK_RISCV_None
Definition: RISCVMCExpr.h:26
llvm::RISCVII::MO_CALL
@ MO_CALL
Definition: RISCVBaseInfo.h:91
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:555
llvm::RISCVMCExpr::create
static const RISCVMCExpr * create(const MCExpr *Expr, VariantKind Kind, MCContext &Ctx)
Definition: RISCVMCExpr.cpp:30
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:218
llvm::AsmPrinter::GetCPISymbol
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
Definition: AsmPrinter.cpp:3039
llvm::RISCVMCExpr::VK_RISCV_PCREL_HI
@ VK_RISCV_PCREL_HI
Definition: RISCVMCExpr.h:30
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::AsmPrinter::GetBlockAddressSymbol
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
Definition: AsmPrinter.cpp:3030
llvm::TargetRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: TargetRegisterInfo.h:561
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:216
llvm::RISCVMCExpr::VK_RISCV_PCREL_LO
@ VK_RISCV_PCREL_LO
Definition: RISCVMCExpr.h:29
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AsmPrinter::getSymbol
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:472
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::RISCVMCExpr::VK_RISCV_GOT_HI
@ VK_RISCV_GOT_HI
Definition: RISCVMCExpr.h:31
llvm::AsmPrinter::OutContext
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:92
llvm::RISCVII::MO_TPREL_LO
@ MO_TPREL_LO
Definition: RISCVBaseInfo.h:98
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:357
RISCV.h
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::RISCVII::MO_None
@ MO_None
Definition: RISCVBaseInfo.h:90
llvm::RISCVII::HasDummyMaskOpMask
@ HasDummyMaskOpMask
Definition: RISCVBaseInfo.h:57
llvm::MachineOperand::MO_JumpTableIndex
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
Definition: MachineOperand.h:60
llvm::MCBinaryExpr::createAdd
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:521
llvm::AsmPrinter::GetExternalSymbolSymbol
MCSymbol * GetExternalSymbolSymbol(StringRef Sym) const
Return the MCSymbol for the specified ExternalSymbol.
Definition: AsmPrinter.cpp:3086
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:549
MCAsmInfo.h
llvm::AsmPrinter::GetJTISymbol
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
Definition: AsmPrinter.cpp:3067
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:133
llvm::RISCVII::MO_PCREL_LO
@ MO_PCREL_LO
Definition: RISCVBaseInfo.h:95
llvm::MachineOperand::MO_MachineBasicBlock
@ MO_MachineBasicBlock
MachineBasicBlock reference.
Definition: MachineOperand.h:56
lowerSymbolOperand
static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym, const AsmPrinter &AP)
Definition: RISCVMCInstLower.cpp:29
llvm::RISCVII::HasSEWOpMask
@ HasSEWOpMask
Definition: RISCVBaseInfo.h:72
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::RISCVII::MO_HI
@ MO_HI
Definition: RISCVBaseInfo.h:94
llvm::AsmPrinter::emitNops
void emitNops(unsigned N)
Emit N NOP instructions.
Definition: AsmPrinter.cpp:3016
llvm::MachineOperand::MO_ExternalSymbol
@ MO_ExternalSymbol
Name of external global symbol.
Definition: MachineOperand.h:61
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:554
llvm::RISCVII::MO_LO
@ MO_LO
Definition: RISCVBaseInfo.h:93
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:197
llvm::AsmPrinter
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:82
llvm::RISCVII::MO_TLS_GOT_HI
@ MO_TLS_GOT_HI
Definition: RISCVBaseInfo.h:101
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:382
lowerRISCVVMachineInstrToMCInst
static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI)
Definition: RISCVMCInstLower.cpp:132
RISCVSubtarget.h
llvm::RISCVMCExpr::VK_RISCV_CALL
@ VK_RISCV_CALL
Definition: RISCVMCExpr.h:37
llvm::MachineOperand::getSymbolName
const char * getSymbolName() const
Definition: MachineOperand.h:605
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1078
llvm::RISCVII::HasMergeOpMask
@ HasMergeOpMask
Definition: RISCVBaseInfo.h:67
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
llvm::MCSymbolRefExpr::VK_None
@ VK_None
Definition: MCExpr.h:195
llvm::MachineOperand::MO_RegisterMask
@ MO_RegisterMask
Mask of preserved registers.
Definition: MachineOperand.h:64
llvm::RISCVMCExpr::VK_RISCV_CALL_PLT
@ VK_RISCV_CALL_PLT
Definition: RISCVMCExpr.h:38
raw_ostream.h
MCExpr.h
llvm::RISCVII::MO_TPREL_ADD
@ MO_TPREL_ADD
Definition: RISCVBaseInfo.h:100
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::MachineOperand::MO_ConstantPoolIndex
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
Definition: MachineOperand.h:58