LLVM  16.0.0git
RISCVSExtWRemoval.cpp
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1 //===-------------- RISCVSExtWRemoval.cpp - MI sext.w Removal -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===---------------------------------------------------------------------===//
8 //
9 // This pass removes unneeded sext.w instructions at the MI level.
10 //
11 //===---------------------------------------------------------------------===//
12 
13 #include "RISCV.h"
15 #include "RISCVSubtarget.h"
16 #include "llvm/ADT/Statistic.h"
19 
20 using namespace llvm;
21 
22 #define DEBUG_TYPE "riscv-sextw-removal"
23 
24 STATISTIC(NumRemovedSExtW, "Number of removed sign-extensions");
25 STATISTIC(NumTransformedToWInstrs,
26  "Number of instructions transformed to W-ops");
27 
28 static cl::opt<bool> DisableSExtWRemoval("riscv-disable-sextw-removal",
29  cl::desc("Disable removal of sext.w"),
30  cl::init(false), cl::Hidden);
31 namespace {
32 
33 class RISCVSExtWRemoval : public MachineFunctionPass {
34 public:
35  static char ID;
36 
37  RISCVSExtWRemoval() : MachineFunctionPass(ID) {
39  }
40 
41  bool runOnMachineFunction(MachineFunction &MF) override;
42 
43  void getAnalysisUsage(AnalysisUsage &AU) const override {
44  AU.setPreservesCFG();
46  }
47 
48  StringRef getPassName() const override { return "RISCV sext.w Removal"; }
49 };
50 
51 } // end anonymous namespace
52 
53 char RISCVSExtWRemoval::ID = 0;
54 INITIALIZE_PASS(RISCVSExtWRemoval, DEBUG_TYPE, "RISCV sext.w Removal", false,
55  false)
56 
58  return new RISCVSExtWRemoval();
59 }
60 
61 // returns true if all uses of OrigMI only depend on the lower word of its
62 // output, so we can transform OrigMI to the corresponding W-version.
63 // TODO: handle multiple interdependent transformations
64 static bool hasAllWUsers(const MachineInstr &OrigMI, MachineRegisterInfo &MRI) {
65 
68 
69  Worklist.push_back(&OrigMI);
70 
71  while (!Worklist.empty()) {
72  const MachineInstr *MI = Worklist.pop_back_val();
73 
74  if (!Visited.insert(MI).second)
75  continue;
76 
77  // Only handle instructions with one def.
78  if (MI->getNumExplicitDefs() != 1)
79  return false;
80 
81  for (auto &UserOp : MRI.use_operands(MI->getOperand(0).getReg())) {
82  const MachineInstr *UserMI = UserOp.getParent();
83  unsigned OpIdx = UserMI->getOperandNo(&UserOp);
84 
85  switch (UserMI->getOpcode()) {
86  default:
87  return false;
88 
89  case RISCV::ADDIW:
90  case RISCV::ADDW:
91  case RISCV::DIVUW:
92  case RISCV::DIVW:
93  case RISCV::MULW:
94  case RISCV::REMUW:
95  case RISCV::REMW:
96  case RISCV::SLLIW:
97  case RISCV::SLLW:
98  case RISCV::SRAIW:
99  case RISCV::SRAW:
100  case RISCV::SRLIW:
101  case RISCV::SRLW:
102  case RISCV::SUBW:
103  case RISCV::ROLW:
104  case RISCV::RORW:
105  case RISCV::RORIW:
106  case RISCV::CLZW:
107  case RISCV::CTZW:
108  case RISCV::CPOPW:
109  case RISCV::SLLI_UW:
110  case RISCV::FMV_H_X:
111  case RISCV::FMV_W_X:
112  case RISCV::FCVT_H_W:
113  case RISCV::FCVT_H_WU:
114  case RISCV::FCVT_S_W:
115  case RISCV::FCVT_S_WU:
116  case RISCV::FCVT_D_W:
117  case RISCV::FCVT_D_WU:
118  case RISCV::SEXT_B:
119  case RISCV::SEXT_H:
120  case RISCV::ZEXT_H_RV64:
121  case RISCV::PACK:
122  case RISCV::PACKH:
123  case RISCV::PACKW:
124  break;
125 
126  // these overwrite higher input bits, otherwise the lower word of output
127  // depends only on the lower word of input. So check their uses read W.
128  case RISCV::SLLI:
129  if (UserMI->getOperand(2).getImm() >= 32)
130  break;
131  Worklist.push_back(UserMI);
132  break;
133  case RISCV::ANDI:
134  if (isUInt<11>(UserMI->getOperand(2).getImm()))
135  break;
136  Worklist.push_back(UserMI);
137  break;
138  case RISCV::ORI:
139  if (!isUInt<11>(UserMI->getOperand(2).getImm()))
140  break;
141  Worklist.push_back(UserMI);
142  break;
143 
144  case RISCV::SLL:
145  case RISCV::BSET:
146  case RISCV::BCLR:
147  case RISCV::BINV:
148  // Operand 2 is the shift amount which uses 6 bits.
149  if (OpIdx == 2)
150  break;
151  Worklist.push_back(UserMI);
152  break;
153 
154  case RISCV::SRA:
155  case RISCV::SRL:
156  case RISCV::ROL:
157  case RISCV::ROR:
158  // Operand 2 is the shift amount which uses 6 bits.
159  if (OpIdx == 2)
160  break;
161  return false;
162 
163  case RISCV::ADD_UW:
164  case RISCV::SH1ADD_UW:
165  case RISCV::SH2ADD_UW:
166  case RISCV::SH3ADD_UW:
167  // Operand 1 is implicitly zero extended.
168  if (OpIdx == 1)
169  break;
170  Worklist.push_back(UserMI);
171  break;
172 
173  case RISCV::BEXTI:
174  if (UserMI->getOperand(2).getImm() >= 32)
175  return false;
176  break;
177 
178  case RISCV::SB:
179  case RISCV::SH:
180  case RISCV::SW:
181  // The first argument is the value to store.
182  if (OpIdx != 0)
183  return false;
184  break;
185 
186  // For these, lower word of output in these operations, depends only on
187  // the lower word of input. So, we check all uses only read lower word.
188  case RISCV::COPY:
189  case RISCV::PHI:
190 
191  case RISCV::ADD:
192  case RISCV::ADDI:
193  case RISCV::AND:
194  case RISCV::MUL:
195  case RISCV::OR:
196  case RISCV::SUB:
197  case RISCV::XOR:
198  case RISCV::XORI:
199 
200  case RISCV::ANDN:
201  case RISCV::BREV8:
202  case RISCV::CLMUL:
203  case RISCV::ORC_B:
204  case RISCV::ORN:
205  case RISCV::SH1ADD:
206  case RISCV::SH2ADD:
207  case RISCV::SH3ADD:
208  case RISCV::XNOR:
209  case RISCV::BSETI:
210  case RISCV::BCLRI:
211  case RISCV::BINVI:
212  Worklist.push_back(UserMI);
213  break;
214 
215  case RISCV::PseudoCCMOVGPR:
216  // Either operand 4 or operand 5 is returned by this instruction. If
217  // only the lower word of the result is used, then only the lower word
218  // of operand 4 and 5 is used.
219  if (OpIdx != 4 && OpIdx != 5)
220  return false;
221  Worklist.push_back(UserMI);
222  break;
223  }
224  }
225  }
226 
227  return true;
228 }
229 
230 // This function returns true if the machine instruction always outputs a value
231 // where bits 63:32 match bit 31.
232 // TODO: Allocate a bit in TSFlags for the W instructions?
233 // TODO: Add other W instructions.
235  switch (MI.getOpcode()) {
236  case RISCV::LUI:
237  case RISCV::LW:
238  case RISCV::ADDW:
239  case RISCV::ADDIW:
240  case RISCV::SUBW:
241  case RISCV::MULW:
242  case RISCV::SLLW:
243  case RISCV::SLLIW:
244  case RISCV::SRAW:
245  case RISCV::SRAIW:
246  case RISCV::SRLW:
247  case RISCV::SRLIW:
248  case RISCV::DIVW:
249  case RISCV::DIVUW:
250  case RISCV::REMW:
251  case RISCV::REMUW:
252  case RISCV::ROLW:
253  case RISCV::RORW:
254  case RISCV::RORIW:
255  case RISCV::CLZW:
256  case RISCV::CTZW:
257  case RISCV::CPOPW:
258  case RISCV::PACKW:
259  case RISCV::FCVT_W_H:
260  case RISCV::FCVT_WU_H:
261  case RISCV::FCVT_W_S:
262  case RISCV::FCVT_WU_S:
263  case RISCV::FCVT_W_D:
264  case RISCV::FCVT_WU_D:
265  case RISCV::FMV_X_W:
266  // The following aren't W instructions, but are either sign extended from a
267  // smaller size, always outputs a small integer, or put zeros in bits 63:31.
268  case RISCV::LBU:
269  case RISCV::LHU:
270  case RISCV::LB:
271  case RISCV::LH:
272  case RISCV::SLT:
273  case RISCV::SLTI:
274  case RISCV::SLTU:
275  case RISCV::SLTIU:
276  case RISCV::FEQ_H:
277  case RISCV::FEQ_S:
278  case RISCV::FEQ_D:
279  case RISCV::FLT_H:
280  case RISCV::FLT_S:
281  case RISCV::FLT_D:
282  case RISCV::FLE_H:
283  case RISCV::FLE_S:
284  case RISCV::FLE_D:
285  case RISCV::SEXT_B:
286  case RISCV::SEXT_H:
287  case RISCV::ZEXT_H_RV64:
288  case RISCV::FMV_X_H:
289  case RISCV::BEXT:
290  case RISCV::BEXTI:
291  case RISCV::CLZ:
292  case RISCV::CPOP:
293  case RISCV::CTZ:
294  case RISCV::PACKH:
295  return true;
296  // shifting right sufficiently makes the value 32-bit sign-extended
297  case RISCV::SRAI:
298  return MI.getOperand(2).getImm() >= 32;
299  case RISCV::SRLI:
300  return MI.getOperand(2).getImm() > 32;
301  // The LI pattern ADDI rd, X0, imm is sign extended.
302  case RISCV::ADDI:
303  return MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0;
304  // An ANDI with an 11 bit immediate will zero bits 63:11.
305  case RISCV::ANDI:
306  return isUInt<11>(MI.getOperand(2).getImm());
307  // An ORI with an >11 bit immediate (negative 12-bit) will set bits 63:11.
308  case RISCV::ORI:
309  return !isUInt<11>(MI.getOperand(2).getImm());
310  // Copying from X0 produces zero.
311  case RISCV::COPY:
312  return MI.getOperand(1).getReg() == RISCV::X0;
313 
314  }
315 
316  return false;
317 }
318 
320  SmallPtrSetImpl<MachineInstr *> &FixableDef) {
321 
324 
325  Worklist.push_back(&OrigMI);
326 
327  while (!Worklist.empty()) {
328  MachineInstr *MI = Worklist.pop_back_val();
329 
330  // If we already visited this instruction, we don't need to check it again.
331  if (!Visited.insert(MI).second)
332  continue;
333 
334  // If this is a sign extending operation we don't need to look any further.
335  if (isSignExtendingOpW(*MI, MRI))
336  continue;
337 
338  // Is this an instruction that propagates sign extend?
339  switch (MI->getOpcode()) {
340  default:
341  // Unknown opcode, give up.
342  return false;
343  case RISCV::COPY: {
344  const MachineFunction *MF = MI->getMF();
345  const RISCVMachineFunctionInfo *RVFI =
347 
348  // If this is the entry block and the register is livein, see if we know
349  // it is sign extended.
350  if (MI->getParent() == &MF->front()) {
351  Register VReg = MI->getOperand(0).getReg();
352  if (MF->getRegInfo().isLiveIn(VReg) && RVFI->isSExt32Register(VReg))
353  continue;
354  }
355 
356  // TODO: Handle returns from calls?
357 
358  Register SrcReg = MI->getOperand(1).getReg();
359 
360  // If this is a copy from another register, check its source instruction.
361  if (!SrcReg.isVirtual())
362  return false;
363  MachineInstr *SrcMI = MRI.getVRegDef(SrcReg);
364  if (!SrcMI)
365  return false;
366 
367  // Add SrcMI to the worklist.
368  Worklist.push_back(SrcMI);
369  break;
370  }
371 
372  // For these, we just need to check if the 1st operand is sign extended.
373  case RISCV::BCLRI:
374  case RISCV::BINVI:
375  case RISCV::BSETI:
376  if (MI->getOperand(2).getImm() >= 31)
377  return false;
378  [[fallthrough]];
379  case RISCV::REM:
380  case RISCV::ANDI:
381  case RISCV::ORI:
382  case RISCV::XORI: {
383  // |Remainder| is always <= |Dividend|. If D is 32-bit, then so is R.
384  // DIV doesn't work because of the edge case 0xf..f 8000 0000 / (long)-1
385  // Logical operations use a sign extended 12-bit immediate.
386  Register SrcReg = MI->getOperand(1).getReg();
387  if (!SrcReg.isVirtual())
388  return false;
389  MachineInstr *SrcMI = MRI.getVRegDef(SrcReg);
390  if (!SrcMI)
391  return false;
392 
393  // Add SrcMI to the worklist.
394  Worklist.push_back(SrcMI);
395  break;
396  }
397  case RISCV::REMU:
398  case RISCV::AND:
399  case RISCV::OR:
400  case RISCV::XOR:
401  case RISCV::ANDN:
402  case RISCV::ORN:
403  case RISCV::XNOR:
404  case RISCV::MAX:
405  case RISCV::MAXU:
406  case RISCV::MIN:
407  case RISCV::MINU:
408  case RISCV::PseudoCCMOVGPR:
409  case RISCV::PHI: {
410  // If all incoming values are sign-extended, the output of AND, OR, XOR,
411  // MIN, MAX, or PHI is also sign-extended.
412 
413  // The input registers for PHI are operand 1, 3, ...
414  // The input registers for PseudoCCMOVGPR are 4 and 5.
415  // The input registers for others are operand 1 and 2.
416  unsigned B = 1, E = 3, D = 1;
417  if (MI->getOpcode() == RISCV::PHI) {
418  E = MI->getNumOperands();
419  D = 2;
420  } else if (MI->getOpcode() == RISCV::PseudoCCMOVGPR) {
421  B = 4;
422  E = 6;
423  }
424 
425  for (unsigned I = B; I != E; I += D) {
426  if (!MI->getOperand(I).isReg())
427  return false;
428 
429  Register SrcReg = MI->getOperand(I).getReg();
430  if (!SrcReg.isVirtual())
431  return false;
432  MachineInstr *SrcMI = MRI.getVRegDef(SrcReg);
433  if (!SrcMI)
434  return false;
435 
436  // Add SrcMI to the worklist.
437  Worklist.push_back(SrcMI);
438  }
439 
440  break;
441  }
442 
443  // With these opcode, we can "fix" them with the W-version
444  // if we know all users of the result only rely on bits 31:0
445  case RISCV::SLLI:
446  // SLLIW reads the lowest 5 bits, while SLLI reads lowest 6 bits
447  if (MI->getOperand(2).getImm() >= 32)
448  return false;
449  [[fallthrough]];
450  case RISCV::ADDI:
451  case RISCV::ADD:
452  case RISCV::LD:
453  case RISCV::LWU:
454  case RISCV::MUL:
455  case RISCV::SUB:
456  if (hasAllWUsers(*MI, MRI)) {
457  FixableDef.insert(MI);
458  break;
459  }
460  return false;
461  }
462  }
463 
464  // If we get here, then every node we visited produces a sign extended value
465  // or propagated sign extended values. So the result must be sign extended.
466  return true;
467 }
468 
469 static unsigned getWOp(unsigned Opcode) {
470  switch (Opcode) {
471  case RISCV::ADDI:
472  return RISCV::ADDIW;
473  case RISCV::ADD:
474  return RISCV::ADDW;
475  case RISCV::LD:
476  case RISCV::LWU:
477  return RISCV::LW;
478  case RISCV::MUL:
479  return RISCV::MULW;
480  case RISCV::SLLI:
481  return RISCV::SLLIW;
482  case RISCV::SUB:
483  return RISCV::SUBW;
484  default:
485  llvm_unreachable("Unexpected opcode for replacement with W variant");
486  }
487 }
488 
489 bool RISCVSExtWRemoval::runOnMachineFunction(MachineFunction &MF) {
490  if (skipFunction(MF.getFunction()) || DisableSExtWRemoval)
491  return false;
492 
495  const RISCVInstrInfo &TII = *ST.getInstrInfo();
496 
497  if (!ST.is64Bit())
498  return false;
499 
500  bool MadeChange = false;
501 
502  for (MachineBasicBlock &MBB : MF) {
503  for (auto I = MBB.begin(), IE = MBB.end(); I != IE;) {
504  MachineInstr *MI = &*I++;
505 
506  // We're looking for the sext.w pattern ADDIW rd, rs1, 0.
507  if (!RISCV::isSEXT_W(*MI))
508  continue;
509 
510  // Input should be a virtual register.
511  Register SrcReg = MI->getOperand(1).getReg();
512  if (!SrcReg.isVirtual())
513  continue;
514 
516  MachineInstr &SrcMI = *MRI.getVRegDef(SrcReg);
517 
518  // If all definitions reaching MI sign-extend their output,
519  // then sext.w is redundant
520  if (!isSignExtendedW(SrcMI, MRI, FixableDef))
521  continue;
522 
523  Register DstReg = MI->getOperand(0).getReg();
524  if (!MRI.constrainRegClass(SrcReg, MRI.getRegClass(DstReg)))
525  continue;
526 
527  // Convert Fixable instructions to their W versions.
528  for (MachineInstr *Fixable : FixableDef) {
529  LLVM_DEBUG(dbgs() << "Replacing " << *Fixable);
530  Fixable->setDesc(TII.get(getWOp(Fixable->getOpcode())));
531  Fixable->clearFlag(MachineInstr::MIFlag::NoSWrap);
532  Fixable->clearFlag(MachineInstr::MIFlag::NoUWrap);
533  Fixable->clearFlag(MachineInstr::MIFlag::IsExact);
534  LLVM_DEBUG(dbgs() << " with " << *Fixable);
535  ++NumTransformedToWInstrs;
536  }
537 
538  LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
539  MRI.replaceRegWith(DstReg, SrcReg);
540  MRI.clearKillFlags(SrcReg);
541  MI->eraseFromParent();
542  ++NumRemovedSExtW;
543  MadeChange = true;
544  }
545  }
546 
547  return MadeChange;
548 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::MachineInstr::getOperandNo
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:706
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::RISCVISD::SLLW
@ SLLW
Definition: RISCVISelLowering.h:65
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
llvm::AArch64PACKey::ID
ID
Definition: AArch64BaseInfo.h:818
PHI
Rewrite undef for PHI
Definition: AMDGPURewriteUndefForPHI.cpp:101
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::RISCVISD::FMV_H_X
@ FMV_H_X
Definition: RISCVISelLowering.h:97
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::RISCVISD::DIVUW
@ DIVUW
Definition: RISCVISelLowering.h:72
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
Statistic.h
DisableSExtWRemoval
static cl::opt< bool > DisableSExtWRemoval("riscv-disable-sextw-removal", cl::desc("Disable removal of sext.w"), cl::init(false), cl::Hidden)
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
TargetInstrInfo.h
llvm::MachineRegisterInfo::use_operands
iterator_range< use_iterator > use_operands(Register Reg) const
Definition: MachineRegisterInfo.h:477
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:450
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:167
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
INITIALIZE_PASS
INITIALIZE_PASS(RISCVSExtWRemoval, DEBUG_TYPE, "RISCV sext.w Removal", false, false) FunctionPass *llvm
Definition: RISCVSExtWRemoval.cpp:54
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:866
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:755
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:692
llvm::initializeRISCVSExtWRemovalPass
void initializeRISCVSExtWRemovalPass(PassRegistry &)
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
isSignExtendingOpW
static bool isSignExtendingOpW(MachineInstr &MI, MachineRegisterInfo &MRI)
Definition: RISCVSExtWRemoval.cpp:234
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:396
llvm::AArch64_AM::ROR
@ ROR
Definition: AArch64AddressingModes.h:38
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::RISCVISD::DIVW
@ DIVW
Definition: RISCVISelLowering.h:71
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::RISCVISD::CLZW
@ CLZW
Definition: RISCVISelLowering.h:80
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:647
llvm::ARM_PROC::IE
@ IE
Definition: ARMBaseInfo.h:27
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::MachineRegisterInfo::clearKillFlags
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
Definition: MachineRegisterInfo.cpp:433
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::cl::opt< bool >
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:447
CLZ
This should be recognized as CLZ
Definition: README.txt:238
llvm::RISCVISD::ROLW
@ ROLW
Definition: RISCVISelLowering.h:76
llvm::RISCVMachineFunctionInfo
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
Definition: RISCVMachineFunctionInfo.h:47
MachineFunctionPass.h
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
DEBUG_TYPE
#define DEBUG_TYPE
Definition: RISCVSExtWRemoval.cpp:22
llvm::AVRISD::ROL
@ ROL
Bit rotate left.
Definition: AVRISelLowering.h:51
llvm::RISCVISD::BREV8
@ BREV8
Definition: RISCVISelLowering.h:127
llvm::RISCVISD::SRAW
@ SRAW
Definition: RISCVISelLowering.h:66
llvm::RISCVISD::ORC_B
@ ORC_B
Definition: RISCVISelLowering.h:128
RISCV.h
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::RISCVISD::REMUW
@ REMUW
Definition: RISCVISelLowering.h:73
hasAllWUsers
static bool hasAllWUsers(const MachineInstr &OrigMI, MachineRegisterInfo &MRI)
Definition: RISCVSExtWRemoval.cpp:64
llvm::RISCVInstrInfo
Definition: RISCVInstrInfo.h:44
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::AnalysisUsage::setPreservesCFG
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:265
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:516
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:313
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:668
llvm::RISCVISD::RORW
@ RORW
Definition: RISCVISelLowering.h:77
llvm::MachineRegisterInfo::replaceRegWith
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
Definition: MachineRegisterInfo.cpp:378
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
isSignExtendedW
static bool isSignExtendedW(MachineInstr &OrigMI, MachineRegisterInfo &MRI, SmallPtrSetImpl< MachineInstr * > &FixableDef)
Definition: RISCVSExtWRemoval.cpp:319
llvm::createRISCVSExtWRemovalPass
FunctionPass * createRISCVSExtWRemovalPass()
llvm::MachineRegisterInfo::isLiveIn
bool isLiveIn(Register Reg) const
Definition: MachineRegisterInfo.cpp:438
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
llvm::RISCVISD::SRLW
@ SRLW
Definition: RISCVISelLowering.h:67
getWOp
static unsigned getWOp(unsigned Opcode)
Definition: RISCVSExtWRemoval.cpp:469
llvm::SystemZISD::PACK
@ PACK
Definition: SystemZISelLowering.h:205
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::RISCVMachineFunctionInfo::isSExt32Register
bool isSExt32Register(Register Reg) const
Definition: RISCVMachineFunctionInfo.cpp:43
RISCVSubtarget.h
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:305
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:241
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:693
llvm::SmallVectorImpl::pop_back_val
T pop_back_val()
Definition: SmallVector.h:677
RISCVMachineFunctionInfo.h
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:82
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:344
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::cl::desc
Definition: CommandLine.h:413
llvm::RISCV::isSEXT_W
bool isSEXT_W(const MachineInstr &MI)
Definition: RISCVInstrInfo.cpp:2331
llvm::RISCVISD::CTZW
@ CTZW
Definition: RISCVISelLowering.h:81
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:307
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:365