LLVM  15.0.0git
RISCVSExtWRemoval.cpp
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1 //===-------------- RISCVSExtWRemoval.cpp - MI sext.w Removal -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===---------------------------------------------------------------------===//
8 //
9 // This pass removes unneeded sext.w instructions at the MI level.
10 //
11 //===---------------------------------------------------------------------===//
12 
13 #include "RISCV.h"
14 #include "RISCVSubtarget.h"
15 #include "llvm/ADT/Statistic.h"
18 
19 using namespace llvm;
20 
21 #define DEBUG_TYPE "riscv-sextw-removal"
22 
23 STATISTIC(NumRemovedSExtW, "Number of removed sign-extensions");
24 STATISTIC(NumTransformedToWInstrs,
25  "Number of instructions transformed to W-ops");
26 
27 static cl::opt<bool> DisableSExtWRemoval("riscv-disable-sextw-removal",
28  cl::desc("Disable removal of sext.w"),
29  cl::init(false), cl::Hidden);
30 namespace {
31 
32 class RISCVSExtWRemoval : public MachineFunctionPass {
33 public:
34  static char ID;
35 
36  RISCVSExtWRemoval() : MachineFunctionPass(ID) {
38  }
39 
40  bool runOnMachineFunction(MachineFunction &MF) override;
41 
42  void getAnalysisUsage(AnalysisUsage &AU) const override {
43  AU.setPreservesCFG();
45  }
46 
47  StringRef getPassName() const override { return "RISCV sext.w Removal"; }
48 };
49 
50 } // end anonymous namespace
51 
52 char RISCVSExtWRemoval::ID = 0;
53 INITIALIZE_PASS(RISCVSExtWRemoval, DEBUG_TYPE, "RISCV sext.w Removal", false,
54  false)
55 
57  return new RISCVSExtWRemoval();
58 }
59 
60 // add uses of MI to the Worklist
61 static void addUses(const MachineInstr &MI,
64  for (auto &UserOp : MRI.reg_operands(MI.getOperand(0).getReg())) {
65  const auto *User = UserOp.getParent();
66  if (User == &MI) // ignore the def, current MI
67  continue;
68  Worklist.push_back(User);
69  }
70 }
71 
72 // returns true if all uses of OrigMI only depend on the lower word of its
73 // output, so we can transform OrigMI to the corresponding W-version.
74 // TODO: handle multiple interdependent transformations
75 static bool isAllUsesReadW(const MachineInstr &OrigMI,
77 
80 
81  Visited.insert(&OrigMI);
82  addUses(OrigMI, Worklist, MRI);
83 
84  while (!Worklist.empty()) {
85  const MachineInstr *MI = Worklist.pop_back_val();
86 
87  if (!Visited.insert(MI).second) {
88  // If we've looped back to OrigMI through a PHI cycle, we can't transform
89  // LD or LWU, because these operations use all 64 bits of input.
90  if (MI == &OrigMI) {
91  unsigned opcode = MI->getOpcode();
92  if (opcode == RISCV::LD || opcode == RISCV::LWU)
93  return false;
94  }
95  continue;
96  }
97 
98  switch (MI->getOpcode()) {
99  case RISCV::ADDIW:
100  case RISCV::ADDW:
101  case RISCV::DIVUW:
102  case RISCV::DIVW:
103  case RISCV::MULW:
104  case RISCV::REMUW:
105  case RISCV::REMW:
106  case RISCV::SLLIW:
107  case RISCV::SLLW:
108  case RISCV::SRAIW:
109  case RISCV::SRAW:
110  case RISCV::SRLIW:
111  case RISCV::SRLW:
112  case RISCV::SUBW:
113  case RISCV::ROLW:
114  case RISCV::RORW:
115  case RISCV::RORIW:
116  case RISCV::CLZW:
117  case RISCV::CTZW:
118  case RISCV::CPOPW:
119  case RISCV::SLLI_UW:
120  case RISCV::FCVT_S_W:
121  case RISCV::FCVT_S_WU:
122  case RISCV::FCVT_D_W:
123  case RISCV::FCVT_D_WU:
124  continue;
125 
126  // these overwrite higher input bits, otherwise the lower word of output
127  // depends only on the lower word of input. So check their uses read W.
128  case RISCV::SLLI:
129  if (MI->getOperand(2).getImm() >= 32)
130  continue;
131  addUses(*MI, Worklist, MRI);
132  continue;
133  case RISCV::ANDI:
134  if (isUInt<11>(MI->getOperand(2).getImm()))
135  continue;
136  addUses(*MI, Worklist, MRI);
137  continue;
138  case RISCV::ORI:
139  if (!isUInt<11>(MI->getOperand(2).getImm()))
140  continue;
141  addUses(*MI, Worklist, MRI);
142  continue;
143 
144  case RISCV::BEXTI:
145  if (MI->getOperand(2).getImm() >= 32)
146  return false;
147  continue;
148 
149  // For these, lower word of output in these operations, depends only on
150  // the lower word of input. So, we check all uses only read lower word.
151  case RISCV::COPY:
152  case RISCV::PHI:
153 
154  case RISCV::ADD:
155  case RISCV::ADDI:
156  case RISCV::AND:
157  case RISCV::MUL:
158  case RISCV::OR:
159  case RISCV::SLL:
160  case RISCV::SUB:
161  case RISCV::XOR:
162  case RISCV::XORI:
163 
164  case RISCV::ADD_UW:
165  case RISCV::ANDN:
166  case RISCV::CLMUL:
167  case RISCV::ORC_B:
168  case RISCV::ORN:
169  case RISCV::SEXT_B:
170  case RISCV::SEXT_H:
171  case RISCV::SH1ADD:
172  case RISCV::SH1ADD_UW:
173  case RISCV::SH2ADD:
174  case RISCV::SH2ADD_UW:
175  case RISCV::SH3ADD:
176  case RISCV::SH3ADD_UW:
177  case RISCV::XNOR:
178  case RISCV::ZEXT_H_RV64:
179  addUses(*MI, Worklist, MRI);
180  continue;
181  default:
182  return false;
183  }
184  }
185  return true;
186 }
187 
188 // This function returns true if the machine instruction always outputs a value
189 // where bits 63:32 match bit 31.
190 // Alternatively, if the instruction can be converted to W variant
191 // (e.g. ADD->ADDW) and all of its uses only use the lower word of its output,
192 // then return true and add the instr to FixableDef to be convereted later
193 // TODO: Allocate a bit in TSFlags for the W instructions?
194 // TODO: Add other W instructions.
196  SmallPtrSetImpl<MachineInstr *> &FixableDef) {
197  switch (MI.getOpcode()) {
198  case RISCV::LUI:
199  case RISCV::LW:
200  case RISCV::ADDW:
201  case RISCV::ADDIW:
202  case RISCV::SUBW:
203  case RISCV::MULW:
204  case RISCV::SLLW:
205  case RISCV::SLLIW:
206  case RISCV::SRAW:
207  case RISCV::SRAIW:
208  case RISCV::SRLW:
209  case RISCV::SRLIW:
210  case RISCV::DIVW:
211  case RISCV::DIVUW:
212  case RISCV::REMW:
213  case RISCV::REMUW:
214  case RISCV::ROLW:
215  case RISCV::RORW:
216  case RISCV::RORIW:
217  case RISCV::CLZW:
218  case RISCV::CTZW:
219  case RISCV::CPOPW:
220  case RISCV::FCVT_W_H:
221  case RISCV::FCVT_WU_H:
222  case RISCV::FCVT_W_S:
223  case RISCV::FCVT_WU_S:
224  case RISCV::FCVT_W_D:
225  case RISCV::FCVT_WU_D:
226  case RISCV::FMV_X_W:
227  // The following aren't W instructions, but are either sign extended from a
228  // smaller size, always outputs a small integer, or put zeros in bits 63:31.
229  case RISCV::LBU:
230  case RISCV::LHU:
231  case RISCV::LB:
232  case RISCV::LH:
233  case RISCV::SLT:
234  case RISCV::SLTI:
235  case RISCV::SLTU:
236  case RISCV::SLTIU:
237  case RISCV::SEXT_B:
238  case RISCV::SEXT_H:
239  case RISCV::ZEXT_H_RV64:
240  case RISCV::FMV_X_H:
241  case RISCV::BEXT:
242  case RISCV::BEXTI:
243  case RISCV::CLZ:
244  case RISCV::CPOP:
245  case RISCV::CTZ:
246  return true;
247  // shifting right sufficiently makes the value 32-bit sign-extended
248  case RISCV::SRAI:
249  return MI.getOperand(2).getImm() >= 32;
250  case RISCV::SRLI:
251  return MI.getOperand(2).getImm() > 32;
252  // The LI pattern ADDI rd, X0, imm is sign extended.
253  case RISCV::ADDI:
254  if (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0)
255  return true;
256  if (isAllUsesReadW(MI, MRI)) {
257  // transform to ADDIW
258  FixableDef.insert(&MI);
259  return true;
260  }
261  return false;
262  // An ANDI with an 11 bit immediate will zero bits 63:11.
263  case RISCV::ANDI:
264  return isUInt<11>(MI.getOperand(2).getImm());
265  // An ORI with an >11 bit immediate (negative 12-bit) will set bits 63:11.
266  case RISCV::ORI:
267  return !isUInt<11>(MI.getOperand(2).getImm());
268  // Copying from X0 produces zero.
269  case RISCV::COPY:
270  return MI.getOperand(1).getReg() == RISCV::X0;
271 
272  // With these opcode, we can "fix" them with the W-version
273  // if we know all users of the result only rely on bits 31:0
274  case RISCV::SLLI:
275  // SLLIW reads the lowest 5 bits, while SLLI reads lowest 6 bits
276  if (MI.getOperand(2).getImm() >= 32)
277  return false;
279  case RISCV::ADD:
280  case RISCV::LD:
281  case RISCV::LWU:
282  case RISCV::MUL:
283  case RISCV::SUB:
284  if (isAllUsesReadW(MI, MRI)) {
285  FixableDef.insert(&MI);
286  return true;
287  }
288  }
289 
290  return false;
291 }
292 
294  SmallPtrSetImpl<MachineInstr *> &FixableDef) {
295 
298 
299  Worklist.push_back(&OrigMI);
300 
301  while (!Worklist.empty()) {
302  MachineInstr *MI = Worklist.pop_back_val();
303 
304  // If we already visited this instruction, we don't need to check it again.
305  if (!Visited.insert(MI).second)
306  continue;
307 
308  // If this is a sign extending operation we don't need to look any further.
309  if (isSignExtendingOpW(*MI, MRI, FixableDef))
310  continue;
311 
312  // Is this an instruction that propagates sign extend.
313  switch (MI->getOpcode()) {
314  default:
315  // Unknown opcode, give up.
316  return false;
317  case RISCV::COPY: {
318  Register SrcReg = MI->getOperand(1).getReg();
319 
320  // TODO: Handle arguments and returns from calls?
321 
322  // If this is a copy from another register, check its source instruction.
323  if (!SrcReg.isVirtual())
324  return false;
325  MachineInstr *SrcMI = MRI.getVRegDef(SrcReg);
326  if (!SrcMI)
327  return false;
328 
329  // Add SrcMI to the worklist.
330  Worklist.push_back(SrcMI);
331  break;
332  }
333 
334  // For these, we just need to check if the 1st operand is sign extended.
335  case RISCV::BCLRI:
336  case RISCV::BINVI:
337  case RISCV::BSETI:
338  if (MI->getOperand(2).getImm() >= 31)
339  return false;
341  case RISCV::REM:
342  case RISCV::ANDI:
343  case RISCV::ORI:
344  case RISCV::XORI: {
345  // |Remainder| is always <= |Dividend|. If D is 32-bit, then so is R.
346  // DIV doesn't work because of the edge case 0xf..f 8000 0000 / (long)-1
347  // Logical operations use a sign extended 12-bit immediate.
348  Register SrcReg = MI->getOperand(1).getReg();
349  if (!SrcReg.isVirtual())
350  return false;
351  MachineInstr *SrcMI = MRI.getVRegDef(SrcReg);
352  if (!SrcMI)
353  return false;
354 
355  // Add SrcMI to the worklist.
356  Worklist.push_back(SrcMI);
357  break;
358  }
359  case RISCV::REMU:
360  case RISCV::AND:
361  case RISCV::OR:
362  case RISCV::XOR:
363  case RISCV::ANDN:
364  case RISCV::ORN:
365  case RISCV::XNOR:
366  case RISCV::MAX:
367  case RISCV::MAXU:
368  case RISCV::MIN:
369  case RISCV::MINU:
370  case RISCV::PHI: {
371  // If all incoming values are sign-extended, the output of AND, OR, XOR,
372  // MIN, MAX, or PHI is also sign-extended.
373 
374  // The input registers for PHI are operand 1, 3, ...
375  // The input registers for others are operand 1 and 2.
376  unsigned E = 3, D = 1;
377  if (MI->getOpcode() == RISCV::PHI) {
378  E = MI->getNumOperands();
379  D = 2;
380  }
381 
382  for (unsigned I = 1; I != E; I += D) {
383  if (!MI->getOperand(I).isReg())
384  return false;
385 
386  Register SrcReg = MI->getOperand(I).getReg();
387  if (!SrcReg.isVirtual())
388  return false;
389  MachineInstr *SrcMI = MRI.getVRegDef(SrcReg);
390  if (!SrcMI)
391  return false;
392 
393  // Add SrcMI to the worklist.
394  Worklist.push_back(SrcMI);
395  }
396 
397  break;
398  }
399  }
400  }
401 
402  // If we get here, then every node we visited produces a sign extended value
403  // or propagated sign extended values. So the result must be sign extended.
404  return true;
405 }
406 
407 static unsigned getWOp(unsigned Opcode) {
408  switch (Opcode) {
409  case RISCV::ADDI:
410  return RISCV::ADDIW;
411  case RISCV::ADD:
412  return RISCV::ADDW;
413  case RISCV::LD:
414  case RISCV::LWU:
415  return RISCV::LW;
416  case RISCV::MUL:
417  return RISCV::MULW;
418  case RISCV::SLLI:
419  return RISCV::SLLIW;
420  case RISCV::SUB:
421  return RISCV::SUBW;
422  default:
423  llvm_unreachable("Unexpected opcode for replacement with W variant");
424  }
425 }
426 
427 bool RISCVSExtWRemoval::runOnMachineFunction(MachineFunction &MF) {
428  if (skipFunction(MF.getFunction()) || DisableSExtWRemoval)
429  return false;
430 
433 
434  if (!ST.is64Bit())
435  return false;
436 
437  SmallPtrSet<MachineInstr *, 4> SExtWRemovalCands;
438 
439  // Replacing instructions invalidates the MI iterator
440  // we collect the candidates, then iterate over them separately.
441  for (MachineBasicBlock &MBB : MF) {
442  for (auto I = MBB.begin(), IE = MBB.end(); I != IE;) {
443  MachineInstr *MI = &*I++;
444 
445  // We're looking for the sext.w pattern ADDIW rd, rs1, 0.
446  if (MI->getOpcode() != RISCV::ADDIW || !MI->getOperand(2).isImm() ||
447  MI->getOperand(2).getImm() != 0 || !MI->getOperand(1).isReg())
448  continue;
449 
450  // Input should be a virtual register.
451  Register SrcReg = MI->getOperand(1).getReg();
452  if (!SrcReg.isVirtual())
453  continue;
454 
455  SExtWRemovalCands.insert(MI);
456  }
457  }
458 
459  bool MadeChange = false;
460  for (auto MI : SExtWRemovalCands) {
462  Register SrcReg = MI->getOperand(1).getReg();
463  MachineInstr &SrcMI = *MRI.getVRegDef(SrcReg);
464 
465  // If all definitions reaching MI sign-extend their output,
466  // then sext.w is redundant
467  if (!isSignExtendedW(SrcMI, MRI, FixableDef))
468  continue;
469 
470  Register DstReg = MI->getOperand(0).getReg();
471  if (!MRI.constrainRegClass(SrcReg, MRI.getRegClass(DstReg)))
472  continue;
473  // Replace Fixable instructions with their W versions.
474  for (MachineInstr *Fixable : FixableDef) {
475  MachineBasicBlock &MBB = *Fixable->getParent();
476  const DebugLoc &DL = Fixable->getDebugLoc();
477  unsigned Code = getWOp(Fixable->getOpcode());
478  MachineInstrBuilder Replacement =
479  BuildMI(MBB, Fixable, DL, ST.getInstrInfo()->get(Code));
480  for (auto Op : Fixable->operands())
481  Replacement.add(Op);
482  for (auto Op : Fixable->memoperands())
483  Replacement.addMemOperand(Op);
484 
485  LLVM_DEBUG(dbgs() << "Replacing " << *Fixable);
486  LLVM_DEBUG(dbgs() << " with " << *Replacement);
487 
488  Fixable->eraseFromParent();
489  ++NumTransformedToWInstrs;
490  }
491 
492  LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
493  MRI.replaceRegWith(DstReg, SrcReg);
494  MRI.clearKillFlags(SrcReg);
495  MI->eraseFromParent();
496  ++NumRemovedSExtW;
497  MadeChange = true;
498  }
499 
500  return MadeChange;
501 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
isSignExtendingOpW
static bool isSignExtendingOpW(MachineInstr &MI, MachineRegisterInfo &MRI, SmallPtrSetImpl< MachineInstr * > &FixableDef)
Definition: RISCVSExtWRemoval.cpp:195
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::RISCVISD::SLLW
@ SLLW
Definition: RISCVISelLowering.h:48
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::RISCVISD::DIVUW
@ DIVUW
Definition: RISCVISelLowering.h:55
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
Statistic.h
llvm::tgtok::Code
@ Code
Definition: TGLexer.h:50
DisableSExtWRemoval
static cl::opt< bool > DisableSExtWRemoval("riscv-disable-sextw-removal", cl::desc("Disable removal of sext.w"), cl::init(false), cl::Hidden)
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
TargetInstrInfo.h
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:450
llvm::SmallVectorImpl::pop_back_val
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:654
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:103
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
INITIALIZE_PASS
INITIALIZE_PASS(RISCVSExtWRemoval, DEBUG_TYPE, "RISCV sext.w Removal", false, false) FunctionPass *llvm
Definition: RISCVSExtWRemoval.cpp:53
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:650
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::User
Definition: User.h:44
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::initializeRISCVSExtWRemovalPass
void initializeRISCVSExtWRemovalPass(PassRegistry &)
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:396
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::RISCVISD::DIVW
@ DIVW
Definition: RISCVISelLowering.h:54
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::RISCVISD::CLZW
@ CLZW
Definition: RISCVISelLowering.h:63
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:642
llvm::ARM_PROC::IE
@ IE
Definition: ARMBaseInfo.h:27
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::MachineRegisterInfo::clearKillFlags
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
Definition: MachineRegisterInfo.cpp:427
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:640
llvm::cl::opt< bool >
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
isAllUsesReadW
static bool isAllUsesReadW(const MachineInstr &OrigMI, MachineRegisterInfo &MRI)
Definition: RISCVSExtWRemoval.cpp:75
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
CLZ
This should be recognized as CLZ
Definition: README.txt:238
llvm::RISCVISD::ROLW
@ ROLW
Definition: RISCVISelLowering.h:59
MachineFunctionPass.h
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::MachineRegisterInfo::reg_operands
iterator_range< reg_iterator > reg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:294
DEBUG_TYPE
#define DEBUG_TYPE
Definition: RISCVSExtWRemoval.cpp:21
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::RISCVISD::SRAW
@ SRAW
Definition: RISCVISelLowering.h:49
RISCV.h
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::RISCVISD::REMUW
@ REMUW
Definition: RISCVISelLowering.h:56
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::AnalysisUsage::setPreservesCFG
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:263
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:280
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:668
llvm::RISCVISD::RORW
@ RORW
Definition: RISCVISelLowering.h:60
llvm::MachineRegisterInfo::replaceRegWith
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
Definition: MachineRegisterInfo.cpp:378
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
isSignExtendedW
static bool isSignExtendedW(MachineInstr &OrigMI, MachineRegisterInfo &MRI, SmallPtrSetImpl< MachineInstr * > &FixableDef)
Definition: RISCVSExtWRemoval.cpp:293
llvm::createRISCVSExtWRemovalPass
FunctionPass * createRISCVSExtWRemovalPass()
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:606
llvm::RISCVISD::SRLW
@ SRLW
Definition: RISCVISelLowering.h:50
getWOp
static unsigned getWOp(unsigned Opcode)
Definition: RISCVSExtWRemoval.cpp:407
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:341
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
RISCVSubtarget.h
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:277
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:241
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:83
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
addUses
static void addUses(const MachineInstr &MI, SmallVectorImpl< const MachineInstr * > &Worklist, MachineRegisterInfo &MRI)
Definition: RISCVSExtWRemoval.cpp:61
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:344
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::cl::desc
Definition: CommandLine.h:405
llvm::RISCVISD::CTZW
@ CTZW
Definition: RISCVISelLowering.h:64
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:279
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:365
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37