LLVM  14.0.0git
SIMCCodeEmitter.cpp
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1 //===-- SIMCCodeEmitter.cpp - SI Code Emitter -----------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The SI code emitter produces machine code that can be executed
11 /// directly on the GPU device.
12 //
13 //===----------------------------------------------------------------------===//
14 
18 #include "SIDefines.h"
19 #include "Utils/AMDGPUBaseInfo.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 
25 using namespace llvm;
26 
27 namespace {
28 
29 class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
30  const MCRegisterInfo &MRI;
31 
32  /// Encode an fp or int literal
33  uint32_t getLitEncoding(const MCOperand &MO, const MCOperandInfo &OpInfo,
34  const MCSubtargetInfo &STI) const;
35 
36 public:
37  SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
38  MCContext &ctx)
39  : AMDGPUMCCodeEmitter(mcii), MRI(mri) {}
40  SIMCCodeEmitter(const SIMCCodeEmitter &) = delete;
41  SIMCCodeEmitter &operator=(const SIMCCodeEmitter &) = delete;
42 
43  /// Encode the instruction and write it to the OS.
44  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
46  const MCSubtargetInfo &STI) const override;
47 
48  /// \returns the encoding for an MCOperand.
49  uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
51  const MCSubtargetInfo &STI) const override;
52 
53  /// Use a fixup to encode the simm16 field for SOPP branch
54  /// instructions.
55  unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
57  const MCSubtargetInfo &STI) const override;
58 
59  unsigned getSMEMOffsetEncoding(const MCInst &MI, unsigned OpNo,
61  const MCSubtargetInfo &STI) const override;
62 
63  unsigned getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
65  const MCSubtargetInfo &STI) const override;
66 
67  unsigned getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
69  const MCSubtargetInfo &STI) const override;
70 
71  unsigned getAVOperandEncoding(const MCInst &MI, unsigned OpNo,
73  const MCSubtargetInfo &STI) const override;
74 
75 private:
76  uint64_t getImplicitOpSelHiEncoding(int Opcode) const;
77 };
78 
79 } // end anonymous namespace
80 
82  const MCRegisterInfo &MRI,
83  MCContext &Ctx) {
84  return new SIMCCodeEmitter(MCII, MRI, Ctx);
85 }
86 
87 // Returns the encoding value to use if the given integer is an integer inline
88 // immediate value, or 0 if it is not.
89 template <typename IntTy>
90 static uint32_t getIntInlineImmEncoding(IntTy Imm) {
91  if (Imm >= 0 && Imm <= 64)
92  return 128 + Imm;
93 
94  if (Imm >= -16 && Imm <= -1)
95  return 192 + std::abs(Imm);
96 
97  return 0;
98 }
99 
101  uint16_t IntImm = getIntInlineImmEncoding(static_cast<int16_t>(Val));
102  return IntImm == 0 ? 255 : IntImm;
103 }
104 
106  uint16_t IntImm = getIntInlineImmEncoding(static_cast<int16_t>(Val));
107  if (IntImm != 0)
108  return IntImm;
109 
110  if (Val == 0x3800) // 0.5
111  return 240;
112 
113  if (Val == 0xB800) // -0.5
114  return 241;
115 
116  if (Val == 0x3C00) // 1.0
117  return 242;
118 
119  if (Val == 0xBC00) // -1.0
120  return 243;
121 
122  if (Val == 0x4000) // 2.0
123  return 244;
124 
125  if (Val == 0xC000) // -2.0
126  return 245;
127 
128  if (Val == 0x4400) // 4.0
129  return 246;
130 
131  if (Val == 0xC400) // -4.0
132  return 247;
133 
134  if (Val == 0x3118 && // 1.0 / (2.0 * pi)
135  STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
136  return 248;
137 
138  return 255;
139 }
140 
142  uint32_t IntImm = getIntInlineImmEncoding(static_cast<int32_t>(Val));
143  if (IntImm != 0)
144  return IntImm;
145 
146  if (Val == FloatToBits(0.5f))
147  return 240;
148 
149  if (Val == FloatToBits(-0.5f))
150  return 241;
151 
152  if (Val == FloatToBits(1.0f))
153  return 242;
154 
155  if (Val == FloatToBits(-1.0f))
156  return 243;
157 
158  if (Val == FloatToBits(2.0f))
159  return 244;
160 
161  if (Val == FloatToBits(-2.0f))
162  return 245;
163 
164  if (Val == FloatToBits(4.0f))
165  return 246;
166 
167  if (Val == FloatToBits(-4.0f))
168  return 247;
169 
170  if (Val == 0x3e22f983 && // 1.0 / (2.0 * pi)
171  STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
172  return 248;
173 
174  return 255;
175 }
176 
178  uint32_t IntImm = getIntInlineImmEncoding(static_cast<int64_t>(Val));
179  if (IntImm != 0)
180  return IntImm;
181 
182  if (Val == DoubleToBits(0.5))
183  return 240;
184 
185  if (Val == DoubleToBits(-0.5))
186  return 241;
187 
188  if (Val == DoubleToBits(1.0))
189  return 242;
190 
191  if (Val == DoubleToBits(-1.0))
192  return 243;
193 
194  if (Val == DoubleToBits(2.0))
195  return 244;
196 
197  if (Val == DoubleToBits(-2.0))
198  return 245;
199 
200  if (Val == DoubleToBits(4.0))
201  return 246;
202 
203  if (Val == DoubleToBits(-4.0))
204  return 247;
205 
206  if (Val == 0x3fc45f306dc9c882 && // 1.0 / (2.0 * pi)
207  STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
208  return 248;
209 
210  return 255;
211 }
212 
213 uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
214  const MCOperandInfo &OpInfo,
215  const MCSubtargetInfo &STI) const {
216  int64_t Imm;
217  if (MO.isExpr()) {
218  const auto *C = dyn_cast<MCConstantExpr>(MO.getExpr());
219  if (!C)
220  return 255;
221 
222  Imm = C->getValue();
223  } else {
224 
225  assert(!MO.isDFPImm());
226 
227  if (!MO.isImm())
228  return ~0;
229 
230  Imm = MO.getImm();
231  }
232 
233  switch (OpInfo.OperandType) {
244  return getLit32Encoding(static_cast<uint32_t>(Imm), STI);
245 
251  return getLit64Encoding(static_cast<uint64_t>(Imm), STI);
252 
256  return getLit16IntEncoding(static_cast<uint16_t>(Imm), STI);
260  // FIXME Is this correct? What do inline immediates do on SI for f16 src
261  // which does not have f16 support?
262  return getLit16Encoding(static_cast<uint16_t>(Imm), STI);
265  if (!isUInt<16>(Imm) && STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal])
266  return getLit32Encoding(static_cast<uint32_t>(Imm), STI);
268  return getLit16Encoding(static_cast<uint16_t>(Imm), STI);
270  }
273  return getLit16IntEncoding(static_cast<uint16_t>(Imm), STI);
276  uint16_t Lo16 = static_cast<uint16_t>(Imm);
277  uint32_t Encoding = getLit16Encoding(Lo16, STI);
278  return Encoding;
279  }
280  default:
281  llvm_unreachable("invalid operand size");
282  }
283 }
284 
285 uint64_t SIMCCodeEmitter::getImplicitOpSelHiEncoding(int Opcode) const {
286  using namespace AMDGPU::VOP3PEncoding;
287  using namespace AMDGPU::OpName;
288 
289  if (AMDGPU::getNamedOperandIdx(Opcode, op_sel_hi) != -1) {
290  if (AMDGPU::getNamedOperandIdx(Opcode, src2) != -1)
291  return 0;
292  if (AMDGPU::getNamedOperandIdx(Opcode, src1) != -1)
293  return OP_SEL_HI_2;
294  if (AMDGPU::getNamedOperandIdx(Opcode, src0) != -1)
295  return OP_SEL_HI_1 | OP_SEL_HI_2;
296  }
298 }
299 
300 void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
302  const MCSubtargetInfo &STI) const {
303  verifyInstructionPredicates(MI,
304  computeAvailableFeatures(STI.getFeatureBits()));
305 
306  int Opcode = MI.getOpcode();
307  uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
308  const MCInstrDesc &Desc = MCII.get(Opcode);
309  unsigned bytes = Desc.getSize();
310 
311  // Set unused op_sel_hi bits to 1 for VOP3P and MAI instructions.
312  // Note that accvgpr_read/write are MAI, have src0, but do not use op_sel.
313  if ((Desc.TSFlags & SIInstrFlags::VOP3P) ||
314  Opcode == AMDGPU::V_ACCVGPR_READ_B32_vi ||
315  Opcode == AMDGPU::V_ACCVGPR_WRITE_B32_vi) {
316  Encoding |= getImplicitOpSelHiEncoding(Opcode);
317  }
318 
319  for (unsigned i = 0; i < bytes; i++) {
320  OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
321  }
322 
323  // NSA encoding.
324  if (AMDGPU::isGFX10Plus(STI) && Desc.TSFlags & SIInstrFlags::MIMG) {
325  int vaddr0 = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
326  AMDGPU::OpName::vaddr0);
327  int srsrc = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
328  AMDGPU::OpName::srsrc);
329  assert(vaddr0 >= 0 && srsrc > vaddr0);
330  unsigned NumExtraAddrs = srsrc - vaddr0 - 1;
331  unsigned NumPadding = (-NumExtraAddrs) & 3;
332 
333  for (unsigned i = 0; i < NumExtraAddrs; ++i)
334  OS.write((uint8_t)getMachineOpValue(MI, MI.getOperand(vaddr0 + 1 + i),
335  Fixups, STI));
336  for (unsigned i = 0; i < NumPadding; ++i)
337  OS.write(0);
338  }
339 
340  if ((bytes > 8 && STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) ||
341  (bytes > 4 && !STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]))
342  return;
343 
344  // Check for additional literals in SRC0/1/2 (Op 1/2/3)
345  for (unsigned i = 0, e = Desc.getNumOperands(); i < e; ++i) {
346 
347  // Check if this operand should be encoded as [SV]Src
348  if (!AMDGPU::isSISrcOperand(Desc, i))
349  continue;
350 
351  // Is this operand a literal immediate?
352  const MCOperand &Op = MI.getOperand(i);
353  if (getLitEncoding(Op, Desc.OpInfo[i], STI) != 255)
354  continue;
355 
356  // Yes! Encode it
357  int64_t Imm = 0;
358 
359  if (Op.isImm())
360  Imm = Op.getImm();
361  else if (Op.isExpr()) {
362  if (const auto *C = dyn_cast<MCConstantExpr>(Op.getExpr()))
363  Imm = C->getValue();
364 
365  } else if (!Op.isExpr()) // Exprs will be replaced with a fixup value.
366  llvm_unreachable("Must be immediate or expr");
367 
368  for (unsigned j = 0; j < 4; j++) {
369  OS.write((uint8_t) ((Imm >> (8 * j)) & 0xff));
370  }
371 
372  // Only one literal value allowed
373  break;
374  }
375 }
376 
377 unsigned SIMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
379  const MCSubtargetInfo &STI) const {
380  const MCOperand &MO = MI.getOperand(OpNo);
381 
382  if (MO.isExpr()) {
383  const MCExpr *Expr = MO.getExpr();
385  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
386  return 0;
387  }
388 
389  return getMachineOpValue(MI, MO, Fixups, STI);
390 }
391 
392 unsigned SIMCCodeEmitter::getSMEMOffsetEncoding(const MCInst &MI, unsigned OpNo,
394  const MCSubtargetInfo &STI) const {
395  auto Offset = MI.getOperand(OpNo).getImm();
396  // VI only supports 20-bit unsigned offsets.
397  assert(!AMDGPU::isVI(STI) || isUInt<20>(Offset));
398  return Offset;
399 }
400 
401 unsigned
402 SIMCCodeEmitter::getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
404  const MCSubtargetInfo &STI) const {
405  using namespace AMDGPU::SDWA;
406 
407  uint64_t RegEnc = 0;
408 
409  const MCOperand &MO = MI.getOperand(OpNo);
410 
411  if (MO.isReg()) {
412  unsigned Reg = MO.getReg();
413  RegEnc |= MRI.getEncodingValue(Reg);
417  }
418  return RegEnc;
419  } else {
420  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
421  uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI);
422  if (Enc != ~0U && Enc != 255) {
423  return Enc | SDWA9EncValues::SRC_SGPR_MASK;
424  }
425  }
426 
427  llvm_unreachable("Unsupported operand kind");
428  return 0;
429 }
430 
431 unsigned
432 SIMCCodeEmitter::getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
434  const MCSubtargetInfo &STI) const {
435  using namespace AMDGPU::SDWA;
436 
437  uint64_t RegEnc = 0;
438 
439  const MCOperand &MO = MI.getOperand(OpNo);
440 
441  unsigned Reg = MO.getReg();
442  if (Reg != AMDGPU::VCC && Reg != AMDGPU::VCC_LO) {
443  RegEnc |= MRI.getEncodingValue(Reg);
446  }
447  return RegEnc;
448 }
449 
450 unsigned
451 SIMCCodeEmitter::getAVOperandEncoding(const MCInst &MI, unsigned OpNo,
453  const MCSubtargetInfo &STI) const {
454  unsigned Reg = MI.getOperand(OpNo).getReg();
455  uint64_t Enc = MRI.getEncodingValue(Reg);
456 
457  // VGPR and AGPR have the same encoding, but SrcA and SrcB operands of mfma
458  // instructions use acc[0:1] modifier bits to distinguish. These bits are
459  // encoded as a virtual 9th bit of the register for these operands.
460  if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) ||
461  MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg) ||
462  MRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) ||
463  MRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) ||
464  MRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) ||
465  MRI.getRegClass(AMDGPU::AReg_192RegClassID).contains(Reg) ||
466  MRI.getRegClass(AMDGPU::AReg_224RegClassID).contains(Reg) ||
467  MRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg) ||
468  MRI.getRegClass(AMDGPU::AGPR_LO16RegClassID).contains(Reg))
469  Enc |= 512;
470 
471  return Enc;
472 }
473 
474 static bool needsPCRel(const MCExpr *Expr) {
475  switch (Expr->getKind()) {
476  case MCExpr::SymbolRef: {
477  auto *SE = cast<MCSymbolRefExpr>(Expr);
478  MCSymbolRefExpr::VariantKind Kind = SE->getKind();
481  }
482  case MCExpr::Binary: {
483  auto *BE = cast<MCBinaryExpr>(Expr);
484  if (BE->getOpcode() == MCBinaryExpr::Sub)
485  return false;
486  return needsPCRel(BE->getLHS()) || needsPCRel(BE->getRHS());
487  }
488  case MCExpr::Unary:
489  return needsPCRel(cast<MCUnaryExpr>(Expr)->getSubExpr());
490  case MCExpr::Target:
491  case MCExpr::Constant:
492  return false;
493  }
494  llvm_unreachable("invalid kind");
495 }
496 
497 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
498  const MCOperand &MO,
500  const MCSubtargetInfo &STI) const {
501  if (MO.isReg())
502  return MRI.getEncodingValue(MO.getReg());
503 
504  if (MO.isExpr() && MO.getExpr()->getKind() != MCExpr::Constant) {
505  // FIXME: If this is expression is PCRel or not should not depend on what
506  // the expression looks like. Given that this is just a general expression,
507  // it should probably be FK_Data_4 and whatever is producing
508  //
509  // s_add_u32 s2, s2, (extern_const_addrspace+16
510  //
511  // And expecting a PCRel should instead produce
512  //
513  // .Ltmp1:
514  // s_add_u32 s2, s2, (extern_const_addrspace+16)-.Ltmp1
516  if (needsPCRel(MO.getExpr()))
517  Kind = FK_PCRel_4;
518  else
519  Kind = FK_Data_4;
520 
521  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
522  uint32_t Offset = Desc.getSize();
523  assert(Offset == 4 || Offset == 8);
524 
525  Fixups.push_back(
526  MCFixup::create(Offset, MO.getExpr(), Kind, MI.getLoc()));
527  }
528 
529  // Figure out the operand number, needed for isSrcOperand check
530  unsigned OpNo = 0;
531  for (unsigned e = MI.getNumOperands(); OpNo < e; ++OpNo) {
532  if (&MO == &MI.getOperand(OpNo))
533  break;
534  }
535 
536  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
537  if (AMDGPU::isSISrcOperand(Desc, OpNo)) {
538  uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI);
539  if (Enc != ~0U &&
540  (Enc != 255 || Desc.getSize() == 4 || Desc.getSize() == 8))
541  return Enc;
542 
543  } else if (MO.isImm())
544  return MO.getImm();
545 
546  llvm_unreachable("Encoding of this operand type is not supported yet.");
547  return 0;
548 }
549 
550 #define ENABLE_INSTR_PREDICATE_VERIFIER
551 #include "AMDGPUGenMCCodeEmitter.inc"
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:161
i
i
Definition: README.txt:29
llvm::AMDGPU::mc2PseudoReg
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
Definition: AMDGPUBaseInfo.cpp:1555
needsPCRel
static bool needsPCRel(const MCExpr *Expr)
Definition: SIMCCodeEmitter.cpp:474
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
AMDGPUFixupKinds.h
llvm::AMDGPU::VOP3PEncoding::OP_SEL_HI_0
@ OP_SEL_HI_0
Definition: SIDefines.h:767
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
Definition: SIDefines.h:156
getLit64Encoding
static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI)
Definition: SIMCCodeEmitter.cpp:177
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::AMDGPU::fixup_si_sopp_br
@ fixup_si_sopp_br
16-bit PC relative fixup for SOPP branch instructions.
Definition: AMDGPUFixupKinds.h:18
llvm::SIInstrFlags::VOP3P
@ VOP3P
Definition: SIDefines.h:45
llvm::AMDGPU::OPERAND_REG_IMM_V2FP16
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:150
llvm::MCFixup::create
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
llvm::createSIMCCodeEmitter
MCCodeEmitter * createSIMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Definition: SIMCCodeEmitter.cpp:81
llvm::AMDGPU::OPERAND_REG_IMM_V2INT32
@ OPERAND_REG_IMM_V2INT32
Definition: SIDefines.h:152
llvm::FloatToBits
uint32_t FloatToBits(float Float)
This function takes a float and returns the bit equivalent 32-bit integer.
Definition: MathExtras.h:663
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
getLit32Encoding
static uint32_t getLit32Encoding(uint32_t Val, const MCSubtargetInfo &STI)
Definition: SIMCCodeEmitter.cpp:141
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::AMDGPU::SDWA::VOPC_DST_SGPR_MASK
@ VOPC_DST_SGPR_MASK
Definition: SIDefines.h:666
llvm::AMDGPU::getNamedOperandIdx
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
llvm::MCOperandInfo
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:83
llvm::AMDGPU::OPERAND_REG_IMM_FP32
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:147
llvm::TargetRegisterClass::contains
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
Definition: TargetRegisterInfo.h:93
llvm::FK_Data_4
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:203
llvm::MCInstrDesc::getSize
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:616
llvm::SIInstrFlags::MIMG
@ MIMG
Definition: SIDefines.h:56
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32
@ OPERAND_REG_INLINE_C_INT32
Definition: SIDefines.h:157
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::MCExpr::Target
@ Target
Target specific expression.
Definition: MCExpr.h:42
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:170
MCContext.h
AMDGPUMCCodeEmitter.h
llvm::AMDGPU::isSGPR
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
Definition: AMDGPUBaseInfo.cpp:1481
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::DoubleToBits
uint64_t DoubleToBits(double Double)
This function takes a double and returns the bit equivalent 64-bit integer.
Definition: MathExtras.h:653
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::AArch64::Fixups
Fixups
Definition: AArch64FixupKinds.h:17
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::AMDGPU::OPERAND_REG_IMM_FP64
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:148
llvm::raw_ostream::write
raw_ostream & write(unsigned char C)
Definition: raw_ostream.cpp:220
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::AMDGPU::OPERAND_REG_IMM_V2FP32
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:153
llvm::MCExpr::getKind
ExprKind getKind() const
Definition: MCExpr.h:81
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT32
@ OPERAND_REG_INLINE_C_V2INT32
Definition: SIDefines.h:164
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::AMDGPU::isGFX10Plus
bool isGFX10Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1455
llvm::MCExpr::Binary
@ Binary
Binary expressions.
Definition: MCExpr.h:38
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
getLit16IntEncoding
static uint32_t getLit16IntEncoding(uint16_t Val, const MCSubtargetInfo &STI)
Definition: SIMCCodeEmitter.cpp:100
llvm::AMDGPU::VOP3PEncoding::OP_SEL_HI_2
@ OP_SEL_HI_2
Definition: SIDefines.h:769
llvm::AMDGPU::isVI
bool isVI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1439
llvm::AMDGPU::SDWA::SRC_VGPR_MASK
@ SRC_VGPR_MASK
Definition: SIDefines.h:664
llvm::MCSymbolRefExpr::VK_AMDGPU_ABS32_HI
@ VK_AMDGPU_ABS32_HI
Definition: MCExpr.h:339
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
AMDGPUMCTargetDesc.h
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_C_INT64
Definition: SIDefines.h:158
llvm::MCSymbolRefExpr::VariantKind
VariantKind
Definition: MCExpr.h:194
llvm::isUInt< 16 >
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:408
uint64_t
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:160
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:95
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
MCRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
getIntInlineImmEncoding
static uint32_t getIntInlineImmEncoding(IntTy Imm)
Definition: SIMCCodeEmitter.cpp:90
llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT16
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
Definition: SIDefines.h:168
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:206
llvm::AMDGPU::VOP3PEncoding::OP_SEL_HI_1
@ OP_SEL_HI_1
Definition: SIDefines.h:768
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:162
llvm::FK_PCRel_4
@ FK_PCRel_4
A four-byte pc relative fixup.
Definition: MCFixup.h:30
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:171
llvm::AMDGPU::OPERAND_REG_IMM_INT16
@ OPERAND_REG_IMM_INT16
Definition: SIDefines.h:146
llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32
@ OPERAND_REG_INLINE_AC_INT32
Definition: SIDefines.h:169
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
uint32_t
llvm::AMDGPU::isSISrcOperand
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
Definition: AMDGPUBaseInfo.cpp:1563
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:273
llvm::AMDGPUMCCodeEmitter
Definition: AMDGPUMCCodeEmitter.h:28
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:172
j
return j(j<< 16)
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
llvm::AMDGPU::SDWA::SRC_SGPR_MASK
@ SRC_SGPR_MASK
Definition: SIDefines.h:663
llvm::AMDGPU::OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:151
uint16_t
SDWA
@ SDWA
Definition: SIInstrInfo.cpp:7680
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:321
SIDefines.h
llvm::MCBinaryExpr::Sub
@ Sub
Subtraction.
Definition: MCExpr.h:505
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:163
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:114
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:165
llvm::MCOperand::isExpr
bool isExpr() const
Definition: MCInst.h:65
llvm::MCFixupKind
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
llvm::AMDGPU::SDWA::VOPC_DST_VCC_MASK
@ VOPC_DST_VCC_MASK
Definition: SIDefines.h:665
llvm::MCExpr::SymbolRef
@ SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:40
llvm::MCExpr::Unary
@ Unary
Unary expressions.
Definition: MCExpr.h:41
llvm::MCExpr::Constant
@ Constant
Constant expressions.
Definition: MCExpr.h:39
llvm::AMDGPU::OPERAND_REG_IMM_INT32
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:144
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:159
getLit16Encoding
static uint32_t getLit16Encoding(uint16_t Val, const MCSubtargetInfo &STI)
Definition: SIMCCodeEmitter.cpp:105
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::AMDGPU::OPERAND_REG_IMM_FP16
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:149
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:173
llvm::abs
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1284
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:228
llvm::MCOperand::isDFPImm
bool isDFPImm() const
Definition: MCInst.h:64
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::AMDGPU::OPERAND_REG_IMM_INT64
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:145
llvm::MCSymbolRefExpr::VK_AMDGPU_ABS32_LO
@ VK_AMDGPU_ABS32_LO
Definition: MCExpr.h:338
llvm::AMDGPU::Fixups
Fixups
Definition: AMDGPUFixupKinds.h:16
AMDGPUBaseInfo.h
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:174