A64FX enum value | llvm::AArch64Subtarget | |
AArch64Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, const TargetMachine &TM, bool LittleEndian, unsigned MinSVEVectorSizeInBitsOverride=0, unsigned MaxSVEVectorSizeInBitsOverride=0, bool StreamingSVEModeDisabled=true) | llvm::AArch64Subtarget | |
addrSinkUsingGEPs() const override | llvm::AArch64Subtarget | inline |
Ampere1 enum value | llvm::AArch64Subtarget | |
Ampere1A enum value | llvm::AArch64Subtarget | |
AppleA10 enum value | llvm::AArch64Subtarget | |
AppleA11 enum value | llvm::AArch64Subtarget | |
AppleA12 enum value | llvm::AArch64Subtarget | |
AppleA13 enum value | llvm::AArch64Subtarget | |
AppleA14 enum value | llvm::AArch64Subtarget | |
AppleA15 enum value | llvm::AArch64Subtarget | |
AppleA16 enum value | llvm::AArch64Subtarget | |
AppleA7 enum value | llvm::AArch64Subtarget | |
ARMProcFamily | llvm::AArch64Subtarget | protected |
ARMProcFamilyEnum enum name | llvm::AArch64Subtarget | |
CacheLineSize | llvm::AArch64Subtarget | protected |
CallLoweringInfo | llvm::AArch64Subtarget | protected |
Carmel enum value | llvm::AArch64Subtarget | |
classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const | llvm::AArch64Subtarget | |
classifyGlobalFunctionReference(const GlobalValue *GV) const override | llvm::AArch64Subtarget | inline |
ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const | llvm::AArch64Subtarget | |
CortexA35 enum value | llvm::AArch64Subtarget | |
CortexA510 enum value | llvm::AArch64Subtarget | |
CortexA53 enum value | llvm::AArch64Subtarget | |
CortexA55 enum value | llvm::AArch64Subtarget | |
CortexA57 enum value | llvm::AArch64Subtarget | |
CortexA65 enum value | llvm::AArch64Subtarget | |
CortexA710 enum value | llvm::AArch64Subtarget | |
CortexA715 enum value | llvm::AArch64Subtarget | |
CortexA72 enum value | llvm::AArch64Subtarget | |
CortexA73 enum value | llvm::AArch64Subtarget | |
CortexA75 enum value | llvm::AArch64Subtarget | |
CortexA76 enum value | llvm::AArch64Subtarget | |
CortexA77 enum value | llvm::AArch64Subtarget | |
CortexA78 enum value | llvm::AArch64Subtarget | |
CortexA78C enum value | llvm::AArch64Subtarget | |
CortexR82 enum value | llvm::AArch64Subtarget | |
CortexX1 enum value | llvm::AArch64Subtarget | |
CortexX1C enum value | llvm::AArch64Subtarget | |
CortexX2 enum value | llvm::AArch64Subtarget | |
CortexX3 enum value | llvm::AArch64Subtarget | |
CustomCallSavedXRegs | llvm::AArch64Subtarget | protected |
DefaultSVETFOpts | llvm::AArch64Subtarget | protected |
enableEarlyIfConversion() const override | llvm::AArch64Subtarget | |
enableMachineScheduler() const override | llvm::AArch64Subtarget | inline |
enablePostRAScheduler() const override | llvm::AArch64Subtarget | inline |
ExynosM3 enum value | llvm::AArch64Subtarget | |
Falkor enum value | llvm::AArch64Subtarget | |
forceStreamingCompatibleSVE() const | llvm::AArch64Subtarget | |
FrameLowering | llvm::AArch64Subtarget | protected |
getCacheLineSize() const override | llvm::AArch64Subtarget | inline |
getCallLowering() const override | llvm::AArch64Subtarget | |
getChkStkName() const | llvm::AArch64Subtarget | inline |
getCustomPBQPConstraints() const override | llvm::AArch64Subtarget | |
getFrameLowering() const override | llvm::AArch64Subtarget | inline |
getInlineAsmLowering() const override | llvm::AArch64Subtarget | |
getInstrInfo() const override | llvm::AArch64Subtarget | inline |
getInstructionSelector() const override | llvm::AArch64Subtarget | |
getLegalizerInfo() const override | llvm::AArch64Subtarget | |
getMaxBytesForLoopAlignment() const | llvm::AArch64Subtarget | inline |
getMaximumJumpTableSize() const | llvm::AArch64Subtarget | inline |
getMaxInterleaveFactor() const | llvm::AArch64Subtarget | inline |
getMaxPrefetchIterationsAhead() const override | llvm::AArch64Subtarget | inline |
getMaxSVEVectorSizeInBits() const | llvm::AArch64Subtarget | inline |
getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override | llvm::AArch64Subtarget | inline |
getMinSVEVectorSizeInBits() const | llvm::AArch64Subtarget | inline |
getMinVectorRegisterBitWidth() const | llvm::AArch64Subtarget | inline |
getNumXRegisterReserved() const | llvm::AArch64Subtarget | inline |
getPrefetchDistance() const override | llvm::AArch64Subtarget | inline |
getPrefFunctionAlignment() const | llvm::AArch64Subtarget | inline |
getPrefLoopAlignment() const | llvm::AArch64Subtarget | inline |
getProcFamily() const | llvm::AArch64Subtarget | inline |
getRegBankInfo() const override | llvm::AArch64Subtarget | |
getRegisterInfo() const override | llvm::AArch64Subtarget | inline |
getSecurityCheckCookieName() const | llvm::AArch64Subtarget | inline |
getSelectionDAGInfo() const override | llvm::AArch64Subtarget | inline |
getSVETailFoldingDefaultOpts() const | llvm::AArch64Subtarget | inline |
getTargetLowering() const override | llvm::AArch64Subtarget | inline |
getTargetTriple() const | llvm::AArch64Subtarget | inline |
getVectorInsertExtractBaseCost() const | llvm::AArch64Subtarget | |
getVScaleForTuning() const | llvm::AArch64Subtarget | inline |
hasCustomCallingConv() const | llvm::AArch64Subtarget | inline |
hasFusion() const | llvm::AArch64Subtarget | inline |
hasSVEorSME() const | llvm::AArch64Subtarget | inline |
InlineAsmLoweringInfo | llvm::AArch64Subtarget | protected |
InstrInfo | llvm::AArch64Subtarget | protected |
InstSelector | llvm::AArch64Subtarget | protected |
isCallingConvWin64(CallingConv::ID CC) const | llvm::AArch64Subtarget | inline |
IsLittle | llvm::AArch64Subtarget | protected |
isLittleEndian() const | llvm::AArch64Subtarget | inline |
isStreamingSVEModeDisabled() const | llvm::AArch64Subtarget | inline |
isTargetAndroid() const | llvm::AArch64Subtarget | inline |
isTargetCOFF() const | llvm::AArch64Subtarget | inline |
isTargetDarwin() const | llvm::AArch64Subtarget | inline |
isTargetELF() const | llvm::AArch64Subtarget | inline |
isTargetFuchsia() const | llvm::AArch64Subtarget | inline |
isTargetILP32() const | llvm::AArch64Subtarget | inline |
isTargetIOS() const | llvm::AArch64Subtarget | inline |
isTargetLinux() const | llvm::AArch64Subtarget | inline |
isTargetMachO() const | llvm::AArch64Subtarget | inline |
isTargetWindows() const | llvm::AArch64Subtarget | inline |
isWindowsArm64EC() const | llvm::AArch64Subtarget | inline |
isXRaySupported() const override | llvm::AArch64Subtarget | inline |
isXRegCustomCalleeSaved(size_t i) const | llvm::AArch64Subtarget | inline |
isXRegisterReserved(size_t i) const | llvm::AArch64Subtarget | inline |
isXRegisterReservedForRA(size_t i) const | llvm::AArch64Subtarget | inline |
Kryo enum value | llvm::AArch64Subtarget | |
Legalizer | llvm::AArch64Subtarget | protected |
MaxBytesForLoopAlignment | llvm::AArch64Subtarget | protected |
MaxInterleaveFactor | llvm::AArch64Subtarget | protected |
MaxJumpTableSize | llvm::AArch64Subtarget | protected |
MaxPrefetchIterationsAhead | llvm::AArch64Subtarget | protected |
MaxSVEVectorSizeInBits | llvm::AArch64Subtarget | protected |
MinPrefetchStride | llvm::AArch64Subtarget | protected |
MinSVEVectorSizeInBits | llvm::AArch64Subtarget | protected |
MinVectorRegisterBitWidth | llvm::AArch64Subtarget | protected |
mirFileLoaded(MachineFunction &MF) const override | llvm::AArch64Subtarget | |
Neoverse512TVB enum value | llvm::AArch64Subtarget | |
NeoverseE1 enum value | llvm::AArch64Subtarget | |
NeoverseN1 enum value | llvm::AArch64Subtarget | |
NeoverseN2 enum value | llvm::AArch64Subtarget | |
NeoverseV1 enum value | llvm::AArch64Subtarget | |
NeoverseV2 enum value | llvm::AArch64Subtarget | |
Others enum value | llvm::AArch64Subtarget | |
overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override | llvm::AArch64Subtarget | |
ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) | llvm::AArch64Subtarget | |
PrefetchDistance | llvm::AArch64Subtarget | protected |
PrefFunctionAlignment | llvm::AArch64Subtarget | protected |
PrefLoopAlignment | llvm::AArch64Subtarget | protected |
RegBankInfo | llvm::AArch64Subtarget | protected |
ReserveXRegister | llvm::AArch64Subtarget | protected |
ReserveXRegisterForRA | llvm::AArch64Subtarget | protected |
Saphira enum value | llvm::AArch64Subtarget | |
StreamingSVEModeDisabled | llvm::AArch64Subtarget | protected |
supportsAddressTopByteIgnored() const | llvm::AArch64Subtarget | |
swiftAsyncContextIsDynamicallySet() const | llvm::AArch64Subtarget | inline |
TargetTriple | llvm::AArch64Subtarget | protected |
ThunderX enum value | llvm::AArch64Subtarget | |
ThunderX2T99 enum value | llvm::AArch64Subtarget | |
ThunderX3T110 enum value | llvm::AArch64Subtarget | |
ThunderXT81 enum value | llvm::AArch64Subtarget | |
ThunderXT83 enum value | llvm::AArch64Subtarget | |
ThunderXT88 enum value | llvm::AArch64Subtarget | |
TLInfo | llvm::AArch64Subtarget | protected |
TSInfo | llvm::AArch64Subtarget | protected |
TSV110 enum value | llvm::AArch64Subtarget | |
useAA() const override | llvm::AArch64Subtarget | |
useSmallAddressing() const | llvm::AArch64Subtarget | inline |
useSVEForFixedLengthVectors() const | llvm::AArch64Subtarget | inline |
useSVEForFixedLengthVectors(EVT VT) const | llvm::AArch64Subtarget | inline |
VectorInsertExtractBaseCost | llvm::AArch64Subtarget | protected |
VScaleForTuning | llvm::AArch64Subtarget | protected |