| assignPassManager(PMStack &PMS, PassManagerType T) override | llvm::FunctionPass | virtual |
| assignVirt2Phys(Register virtReg, MCPhysReg physReg) | llvm::VirtRegMap | |
| assignVirt2Shape(Register virtReg, ShapeT shape) | llvm::VirtRegMap | inline |
| assignVirt2StackSlot(Register virtReg) | llvm::VirtRegMap | |
| assignVirt2StackSlot(Register virtReg, int SS) | llvm::VirtRegMap | |
| clearAllVirt() | llvm::VirtRegMap | inline |
| clearVirt(Register virtReg) | llvm::VirtRegMap | inline |
| createPass(AnalysisID ID) | llvm::Pass | static |
| doFinalization(Module &) | llvm::Pass | inlinevirtual |
| doInitialization(Module &) override | llvm::MachineFunctionPass | inlinevirtual |
| dump() const | llvm::VirtRegMap | |
| dumpPassStructure(unsigned Offset=0) | llvm::Pass | virtual |
| FunctionPass(char &pid) | llvm::FunctionPass | inlineexplicit |
| getAdjustedAnalysisPointer(AnalysisID ID) | llvm::Pass | virtual |
| getAnalysis() const | llvm::Pass | |
| getAnalysis(Function &F, bool *Changed=nullptr) | llvm::Pass | |
| getAnalysisID(AnalysisID PI) const | llvm::Pass | |
| getAnalysisID(AnalysisID PI, Function &F, bool *Changed=nullptr) | llvm::Pass | |
| getAnalysisIfAvailable() const | llvm::Pass | |
| getAnalysisUsage(AnalysisUsage &AU) const override | llvm::VirtRegMap | inlinevirtual |
| getAsImmutablePass() | llvm::Pass | virtual |
| getAsPMDataManager() | llvm::Pass | virtual |
| getClearedProperties() const | llvm::MachineFunctionPass | inlineprotectedvirtual |
| getMachineFunction() const | llvm::VirtRegMap | inline |
| getOriginal(Register VirtReg) const | llvm::VirtRegMap | inline |
| getPassID() const | llvm::Pass | inline |
| getPassKind() const | llvm::Pass | inline |
| getPassName() const | llvm::Pass | virtual |
| getPhys(Register virtReg) const | llvm::VirtRegMap | inline |
| getPotentialPassManagerType() const override | llvm::FunctionPass | virtual |
| getPreSplitReg(Register virtReg) const | llvm::VirtRegMap | inline |
| getRegInfo() const | llvm::VirtRegMap | inline |
| getRequiredProperties() const | llvm::MachineFunctionPass | inlineprotectedvirtual |
| getResolver() const | llvm::Pass | inline |
| getSetProperties() const | llvm::MachineFunctionPass | inlineprotectedvirtual |
| getShape(Register virtReg) const | llvm::VirtRegMap | inline |
| getStackSlot(Register virtReg) const | llvm::VirtRegMap | inline |
| getTargetRegInfo() const | llvm::VirtRegMap | inline |
| grow() | llvm::VirtRegMap | |
| hasKnownPreference(Register VirtReg) const | llvm::VirtRegMap | |
| hasPhys(Register virtReg) const | llvm::VirtRegMap | inline |
| hasPreferredPhys(Register VirtReg) const | llvm::VirtRegMap | |
| hasShape(Register virtReg) const | llvm::VirtRegMap | inline |
| ID | llvm::VirtRegMap | static |
| isAssignedReg(Register virtReg) const | llvm::VirtRegMap | inline |
| isShapeMapEmpty() const | llvm::VirtRegMap | inline |
| lookupPassInfo(const void *TI) | llvm::Pass | static |
| lookupPassInfo(StringRef Arg) | llvm::Pass | static |
| MachineFunctionPass(char &ID) | llvm::MachineFunctionPass | inlineexplicitprotected |
| MAX_STACK_SLOT enum value | llvm::VirtRegMap | |
| mustPreserveAnalysisID(char &AID) const | llvm::Pass | |
| NO_PHYS_REG enum value | llvm::VirtRegMap | |
| NO_STACK_SLOT enum value | llvm::VirtRegMap | |
| operator=(const VirtRegMap &)=delete | llvm::VirtRegMap | |
| llvm::MachineFunctionPass::operator=(const Pass &)=delete | llvm::Pass | |
| Pass(PassKind K, char &pid) | llvm::Pass | inlineexplicit |
| Pass(const Pass &)=delete | llvm::Pass | |
| preparePassManager(PMStack &) | llvm::Pass | virtual |
| print(raw_ostream &OS, const Module *M=nullptr) const override | llvm::VirtRegMap | virtual |
| releaseMemory() | llvm::Pass | virtual |
| runOnMachineFunction(MachineFunction &MF) override | llvm::VirtRegMap | virtual |
| setIsSplitFromReg(Register virtReg, Register SReg) | llvm::VirtRegMap | inline |
| setResolver(AnalysisResolver *AR) | llvm::Pass | |
| skipFunction(const Function &F) const | llvm::FunctionPass | protected |
| verifyAnalysis() const | llvm::Pass | virtual |
| VirtRegMap() | llvm::VirtRegMap | inline |
| VirtRegMap(const VirtRegMap &)=delete | llvm::VirtRegMap | |
| ~Pass() | llvm::Pass | virtual |
