LLVM
15.0.0git
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Functions | |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj obj **nth_el If the i64 division is lowered to a then a safe point | will (must) appear for the call site. If a collection occurs |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj obj **nth_el If the i64 division is lowered to a then a safe point array and nth_el no longer point into the correct object The fix for this is to copy address calculations so that dependent pointers are never live across safe point boundaries But the loads cannot be copied like this if there was an intervening so may be hard to get right Only a concurrent mutator can trigger a collection at the libcall safe point So single threaded programs do not have this even with a copying collector LLVM optimizations would probably undo a front end s careful work The ocaml frametable structure supports liveness information It would be good to support it The FIXME in ComputeCommonTailLength in BranchFolding cpp needs to be revisited The check is there to work around a misuse of directives in assembly It would be good to detect collector target compatibility instead of silently doing the wrong thing It would be really nice to be able to write patterns in td files for which would eliminate a bunch of predicates on | them (e.g. no side effects). Once this is in place |
Variables | |
Common register allocation spilling | problem |
Common register allocation spilling | r4 |
Common register allocation spilling lr str | lr |
Common register allocation spilling lr str ldr sxth | r3 |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can | be |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and | mov |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 | reg1037 = ADDri %reg1039 |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 | reg1038 = ADDrs %reg1032 |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 | reg1039 |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 | noreg |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to | CFG |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM | BB |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to | mbb< bb76.outer, 0x8b0c5f0 > |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction | However |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first | place |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably | Consider |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr | nth_el = getelementptr { i32, [0 x %obj] }* %array |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr | i32 |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n | old |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * | new |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj obj **nth_el If the i64 division is lowered to a | libcall |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj obj **nth_el If the i64 division is lowered to a then a safe point array and nth_el no longer point into the correct object The fix for this is to copy address calculations so that dependent pointers are never live across safe point boundaries But the loads cannot be copied like this if there was an intervening | store |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj obj **nth_el If the i64 division is lowered to a then a safe point array and nth_el no longer point into the correct object The fix for this is to copy address calculations so that dependent pointers are never live across safe point boundaries But the loads cannot be copied like this if there was an intervening so may be hard to get right Only a concurrent mutator can trigger a collection at the libcall safe point So single threaded programs do not have this | requirement |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj obj **nth_el If the i64 division is lowered to a then a safe point array and nth_el no longer point into the correct object The fix for this is to copy address calculations so that dependent pointers are never live across safe point boundaries But the loads cannot be copied like this if there was an intervening so may be hard to get right Only a concurrent mutator can trigger a collection at the libcall safe point So single threaded programs do not have this even with a copying collector | Still |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj obj **nth_el If the i64 division is lowered to a then a safe point array and nth_el no longer point into the correct object The fix for this is to copy address calculations so that dependent pointers are never live across safe point boundaries But the loads cannot be copied like this if there was an intervening so may be hard to get right Only a concurrent mutator can trigger a collection at the libcall safe point So single threaded programs do not have this even with a copying collector LLVM optimizations would probably undo a front end s careful work The ocaml frametable structure supports liveness information It would be good to support it The FIXME in ComputeCommonTailLength in BranchFolding cpp needs to be revisited The check is there to work around a misuse of directives in assembly It would be good to detect collector target compatibility instead of silently doing the wrong thing It would be really nice to be able to write patterns in td files for | copies |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj obj **nth_el If the i64 division is lowered to a then a safe point array and nth_el no longer point into the correct object The fix for this is to copy address calculations so that dependent pointers are never live across safe point boundaries But the loads cannot be copied like this if there was an intervening so may be hard to get right Only a concurrent mutator can trigger a collection at the libcall safe point So single threaded programs do not have this even with a copying collector LLVM optimizations would probably undo a front end s careful work The ocaml frametable structure supports liveness information It would be good to support it The FIXME in ComputeCommonTailLength in BranchFolding cpp needs to be revisited The check is there to work around a misuse of directives in assembly It would be good to detect collector target compatibility instead of silently doing the wrong thing It would be really nice to be able to write patterns in td files for which would eliminate a bunch of predicates on it would be even better to have tblgen synthesize the various copy insertion inspection methods in TargetInstrInfo Stack coloring | improvements |
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explicit |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb<bb27,0x8b0a7c0> Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info (i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably ** array_addr i32 n y store obj obj** nth_el If the i64 division is lowered to a then a safe point will | ( | must | ) |
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB |
Definition at line 39 of file README.txt.
Referenced by llvm::AliasSetTracker::add(), addArgumentReturnedAttrs(), llvm::SSAUpdaterBulk::AddAvailableValue(), llvm::MachineSSAUpdater::AddAvailableValue(), llvm::SSAUpdater::AddAvailableValue(), llvm::MachineDominanceFrontier::addBasicBlock(), llvm::DominanceFrontierBase< BasicBlock, false >::addBasicBlock(), addBlockAndPredsToSet(), llvm::LoopBase< BasicBlock, Loop >::addBlockEntry(), llvm::MemoryPhi::addIncoming(), llvm::PHINode::addIncoming(), llvm::MachineDominatorTree::addNewBlock(), llvm::LiveVariables::addNewBlock(), llvm::DominatorTreeBase< BasicBlock, false >::addNewBlock(), llvm::addNodeToInterval(), addNoRecurseAttrs(), AddReturnAttributes(), llvm::DominatorTreeBase< BasicBlock, false >::addRoot(), llvm::RegionBase< RegionTraits< Function > >::addSubRegion(), addUnwindMapEntry(), llvm::ARMBasicBlockUtils::adjustBBOffsetsAfter(), llvm::AggressiveAntiDepState::AggressiveAntiDepState(), llvm::LoopSafetyInfo::allLoopPathsLeadToBlock(), llvm::SIMachineFunctionInfo::allocateSGPRSpillToVGPR(), allPredecessorsComeFromSameSource(), allSameBlock(), llvm::CodeMetrics::analyzeBasicBlock(), analyzeLoopUnrollCost(), llvm::ModifiedPO::appendBlock(), llvm::SampleProfileInference< BT >::apply(), llvm::OpenMPIRBuilder::applySimd(), llvm::ApproximateLoopSize(), areCFlagsAliveInSuccessors(), assureFPCallStub(), llvm::InstIterator< BB_t, BB_i_t, BI_t, II_t >::atEnd(), basicBlockCanReturn(), llvm::SSAUpdaterTraits< SSAUpdater >::BlkSucc_begin(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::BlkSucc_begin(), llvm::SSAUpdaterTraits< LDVSSAUpdater >::BlkSucc_begin(), llvm::SSAUpdaterTraits< SSAUpdater >::BlkSucc_end(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::BlkSucc_end(), llvm::SSAUpdaterTraits< LDVSSAUpdater >::BlkSucc_end(), llvm::ARMBlockPlacement::blockIsBefore(), BlockIsSimpleEnoughToThreadThrough(), llvm::SimpleLoopSafetyInfo::blockMayThrow(), llvm::ICFLoopSafetyInfo::blockMayThrow(), llvm::LoopVectorizationLegality::blockNeedsPredication(), llvm::LoopAccessInfo::blockNeedsPredication(), llvm::LoopVectorizationCostModel::blockNeedsPredicationForAnyReason(), bothUsedInPHI(), llvm::SwitchCG::SwitchLowering::buildBitTests(), llvm::SSAUpdaterImpl< UpdaterT >::BuildBlockList(), buildClonedLoopBlocks(), buildClonedLoops(), llvm::buildDbgValueForSpill(), buildExtractionBlockSet(), llvm::BuildMI(), llvm::R600InstrInfo::buildMovImm(), buildPartialInvariantUnswitchConditionalBranch(), buildPartialUnswitchConditionalBranch(), llvm::IDFCalculatorBase< BasicBlock, IsPostDom >::calculate(), llvm::ForwardDominanceFrontierBase< BasicBlock >::calculate(), llvm::BranchProbabilityInfo::calculate(), llvm::BlockFrequencyInfoImpl< BT >::calculate(), llvm::calculateClrEHStateNumbers(), calculateCXXStateNumbers(), llvm::LoopVectorizationCostModel::calculateRegisterUsage(), llvm::calculateSEHStateNumbers(), calculateSEHStateNumbers(), calculateStateNumbersForInvokes(), llvm::calculateWasmEHInfo(), llvm::calculateWinCXXEHStateNumbers(), llvm::AAResults::canBasicBlockModify(), llvm::canIfConvertPHINodes(), canLoopBeDeleted(), CanPropagatePredecessorsForPHIs(), canProveExitOnFirstIteration(), canReturn(), canRotateDeoptimizingLatchExit(), llvm::canSinkOrHoistInst(), canSplitPredecessors(), canTailPredicateLoop(), llvm::PreservedCFGCheckerInstrumentation::CFG::CFG(), llvm::DominatorTreeBase< BasicBlock, false >::changeImmediateDominator(), llvm::MachineLoopInfo::changeLoopFor(), llvm::LoopInfoBase< BasicBlock, Loop >::changeLoopFor(), llvm::changeToCall(), llvm::changeToInvokeAndSplitBasicBlock(), llvm::MemorySSAUpdater::changeToUnreachable(), llvm::changeToUnreachable(), checkAndUpdateCCRKill(), checkAndUpdateCPSRKill(), checkAndUpdateEFLAGSKill(), checkBasicSSA(), llvm::checkDebugInfoMetadata(), checkEFLAGSLive(), checkForMustTailInVarArgFn(), checkInstructions(), checkLoopsStructure(), checkMixedPrecision(), llvm::ModuloScheduleExpander::cleanup(), cleanupSinglePredPHIs(), llvm::MachineBasicBlock::clearBasicBlock(), llvm::VPBuilder::clearInsertionPoint(), llvm::CloneAndPruneIntoFromInst(), llvm::CloneBasicBlock(), llvm::CloneFunctionInto(), CloneInstructionsIntoPredecessorBlockAndUpdateSSAUses(), llvm::cloneLoop(), CloneLoopBlocks(), cloneLoopBlocks(), cloneLoopNest(), llvm::cloneLoopWithPreheader(), llvm::FunctionComparator::cmpConstants(), llvm::CodeExtractorAnalysisCache::CodeExtractorAnalysisCache(), llvm::OpenMPIRBuilder::OutlineInfo::collectBlocks(), llvm::collectChildrenInLoop(), llvm::collectDebugInfoMetadata(), llvm::LoopVectorizationCostModel::collectElementTypesForWidening(), llvm::LoopVectorizationCostModel::collectInstsToScalarize(), collectTransitivePredecessors(), llvm::LoopVectorizationPlanner::collectTriviallyDeadInstructions(), llvm::LoopVectorizationCostModel::collectValuesToIgnore(), llvm::DominatorTreeBase< BasicBlock, false >::compare(), llvm::DominanceFrontierBase< BasicBlock, false >::compareDomSet(), computeAllocaDefaultAlign(), computeBlocksDominatingExits(), llvm::SampleProfileLoaderBaseImpl< MachineBasicBlock >::computeBlockWeights(), computeFunctionSummary(), computeHeuristicUnrollFactor(), llvm::AbstractDependenceGraphBuilder< DataDependenceGraph >::computeInstructionOrdinals(), computeKillSet(), ComputeLiveInBlocks(), llvm::rdf::Liveness::computeLiveIns(), computeLiveInValues(), computeLiveOutSeed(), computeLoadStoreDefaultAlign(), llvm::SimpleLoopSafetyInfo::computeLoopSafetyInfo(), llvm::ICFLoopSafetyInfo::computeLoopSafetyInfo(), llvm::computeMinimumValueSizes(), ComputePostOrders(), computeUnlikelySuccessors(), computeUnrollAndJamCount(), llvm::JumpThreadingPass::computeValueKnownInPredecessors(), llvm::JumpThreadingPass::computeValueKnownInPredecessorsImpl(), llvm::RandomIRBuilder::connectToSink(), llvm::ConstantFoldTerminator(), ConstructSSAForLoadSet(), llvm::Interval::contains(), llvm::LoopBase< BasicBlock, Loop >::contains(), llvm::RegionBase< RegionTraits< Function > >::contains(), containsLongjmpableCalls(), llvm::convertConstantExprsToInstructions(), llvm::ConvertDebugDeclareToDebugValue(), convertToRelLookupTable(), llvm::IRSimilarity::IRInstructionMapper::convertToUnsignedVec(), countToEliminateCompares(), llvm::CatchReturnInst::Create(), createAllocaInstAtEntry(), llvm::VPRecipeBuilder::createBlockInMask(), llvm::OpenMPIRBuilder::createCanonicalLoop(), llvm::IRSimilarity::IRSimilarityCandidate::createCanonicalRelationFrom(), llvm::DominatorTreeBase< BasicBlock, false >::createChild(), llvm::MIRParserImpl::createDummyFunction(), createEmptyFunction(), llvm::SSAUpdaterTraits< SSAUpdater >::CreateEmptyPHI(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::CreateEmptyPHI(), llvm::SSAUpdaterTraits< LDVSSAUpdater >::CreateEmptyPHI(), llvm::BinaryOperator::CreateExact(), llvm::AbstractDependenceGraphBuilder< DataDependenceGraph >::createFineGrainedNodes(), createFPFnStub(), createFree(), llvm::InnerLoopVectorizer::createInductionResumeValues(), createMalloc(), llvm::MemorySSAUpdater::createMemoryAccessInBB(), createNaturalLoopInternal(), llvm::DominatorTreeBase< BasicBlock, false >::createNode(), llvm::BinaryOperator::CreateNSW(), llvm::BinaryOperator::CreateNUW(), llvm::OpenMPIRBuilder::createParallel(), llvm::createPHIsForSplitLoopExit(), createSwitchStatement(), createTileStore(), createUnreachableSwitchDefault(), createWrapper(), cse(), LiveDebugValues::MLocTracker::defReg(), llvm::Attributor::deleteAfterManifest(), DeleteBasicBlock(), llvm::DeleteDeadBlock(), llvm::DeleteDeadBlocks(), deleteDeadBlocksFromLoop(), deleteDeadClonedBlocks(), llvm::deleteDeadLoop(), llvm::DeleteDeadPHIs(), llvm::DemoteRegToStack(), llvm::detachDeadBlocks(), doCallSiteSplitting(), llvm::CodeExtractorAnalysisCache::doesBlockContainClobberOfAddr(), llvm::ICFLoopSafetyInfo::doesNotWriteMemoryBefore(), llvm::DominatorTree::dominates(), llvm::ScalarEvolution::dominates(), dominatesMergePoint(), llvm::Function::dropAllReferences(), llvm::DomTreeUpdater::dump(), llvm::CFGMST< Edge, BBInfo >::dumpEdges(), llvm::JumpThreadingPass::duplicateCondBranchOnPHIIntoPred(), llvm::DuplicateInstructionsInSplitBetween(), llvm::ehAwareSplitEdge(), EliminateBlockCases(), eliminateConstraints(), llvm::EliminateDuplicatePHINodes(), EliminateDuplicatePHINodesNaiveImpl(), EliminateDuplicatePHINodesSetBasedImpl(), llvm::EliminateUnreachableBlocks(), llvm::PPCTargetLowering::EmitAtomicBinary(), llvm::AsmPrinter::emitBasicBlockStart(), llvm::SelectionDAGBuilder::EmitBranchForMergedCondition(), emitBuildPairF64Pseudo(), llvm::OpenMPIRBuilder::emitCancelationCheckImpl(), llvm::VETargetLowering::emitEHSjLjSetJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::AsmPrinter::emitFunctionBody(), llvm::SITargetLowering::emitGWSMemViolTestLoop(), emitInlineAsm(), llvm::PMDataManager::emitInstrCountChangedRemark(), llvm::Mips16TargetLowering::EmitInstrWithCustomInserter(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::MipsSETargetLowering::EmitInstrWithCustomInserter(), llvm::BPFTargetLowering::EmitInstrWithCustomInserter(), llvm::SparcTargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MSP430TargetLowering::EmitInstrWithCustomInserter(), llvm::VETargetLowering::EmitInstrWithCustomInserter(), llvm::M68kTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::RISCVTargetLowering::EmitInstrWithCustomInserter(), llvm::AArch64TargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), llvm::HexagonTargetLowering::emitLoadLinked(), llvm::AArch64TargetLowering::EmitLoweredCatchRet(), llvm::PPCTargetLowering::EmitPartwordAtomicBinary(), emitPostLd(), emitPostSt(), emitQuietFCMP(), emitReadCycleWidePseudo(), emitSelectPseudo(), llvm::MSP430TargetLowering::EmitShiftInstr(), llvm::VETargetLowering::emitSjLjDispatchBlock(), emitSplitF64Pseudo(), llvm::HexagonTargetLowering::emitStoreConditional(), emitXBegin(), llvm::SIInstrInfo::enforceOperandRCAlignment(), ensureValueAvailableInSuccessor(), llvm::GVNExpression::PHIExpression::equals(), llvm::LoopInfo::erase(), llvm::LazyValueInfo::eraseBlock(), llvm::BranchProbabilityInfo::eraseBlock(), eraseDeadBBsAndChildren(), eraseLifetimeMarkersOnInputs(), llvm::MachineDominatorTree::eraseNode(), llvm::DominatorTreeBase< BasicBlock, false >::eraseNode(), llvm::JumpThreadingPass::evaluateOnPredecessorEdge(), llvm::VPBasicBlock::execute(), llvm::VEInstrInfo::expandExtendStackPseudo(), llvm::SparcTargetLowering::expandSelectCC(), llvm::CodeExtractor::extractCodeRegion(), llvm::CodeExtractor::findAllocas(), findArgParts(), llvm::CFGMST< Edge, BBInfo >::findBBInfo(), findBBsToSinkInto(), llvm::rdf::FuncNode::findBlock(), llvm::rdf::DataFlowGraph::findBlock(), llvm::orc::SpeculateQuery::findCalles(), llvm::SwitchInst::findCaseDest(), llvm::OutlinableRegion::findCorrespondingBlockIn(), findCostForOutputBlocks(), findDependencies(), llvm::SampleProfileLoaderBaseImpl< MachineBasicBlock >::findEquivalenceClasses(), llvm::SSAUpdaterImpl< UpdaterT >::FindExistingPHI(), findFalseBlock(), llvm::MustBeExecutedContextExplorer::findForwardJoinPoint(), llvm::FindFunctionBackedges(), findIBRPredecessor(), FindIDom(), llvm::CodeExtractor::findInputsOutputs(), findLiveSetAtInst(), llvm::HexagonInstrInfo::findLoopInstr(), findMostPopularDest(), llvm::MachinePostDominatorTree::findNearestCommonDominator(), llvm::CodeExtractor::findOrCreateBlockForHoisting(), llvm::RandomIRBuilder::findOrCreateSource(), findPartitions(), FindPHIForConditionForwarding(), FindPredecessorAutoreleaseWithSafePath(), llvm::SSAUpdaterTraits< SSAUpdater >::FindPredecessorBlocks(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::FindPredecessorBlocks(), llvm::SSAUpdaterTraits< LDVSSAUpdater >::FindPredecessorBlocks(), FindPredecessorRetainWithSafePath(), llvm::findSplitCandidate(), llvm::findSplitPointForStackProtector(), findStackProtectorIntrinsic(), findUniqueStoreInBlocks(), llvm::SSAUpdater::FindValueForBlock(), FindWidenableTerminatorAboveLoop(), llvm::SanitizerStatReport::finish(), llvm::po_iterator_storage< LoopBlocksTraversal, true >::finishPostorder(), llvm::LoopBlocksTraversal::finishPostorder(), llvm::InnerLoopVectorizer::fixFirstOrderRecurrence(), fixupFPReturnAndCall(), llvm::FlattenCFG(), llvm::AMDGPULibCalls::fold(), llvm::InstCombinerImpl::foldAggregateConstructionIntoAggregateReuse(), llvm::FoldBranchToCommonDest(), FoldCondBranchOnValueKnownInPredecessorImpl(), llvm::InstCombinerImpl::foldIntegerTypedPHI(), llvm::InstCombinerImpl::foldPHIArgLoadIntoPHI(), llvm::InstCombinerImpl::foldPHIArgOpIntoPHI(), llvm::FoldReturnIntoUncondBranch(), llvm::FoldSingleEntryPHINodes(), FoldTwoEntryPHINode(), foldUnusualPatterns(), foreachMemoryAccess(), llvm::BlockFrequencyInfoImpl< BT >::forgetBlock(), llvm::formDedicatedExitBlocks(), llvm::formLCSSA(), llvm::FunctionComparator::functionHash(), functionHasLines(), gatherIncomingValuesToPhi(), llvm::PredIteratorCache::get(), llvm::gvn::AvailableValueInBlock::get(), llvm::BlockAddress::get(), llvm::AsmPrinter::getAddrLabelSymbol(), llvm::AddrLabelMap::getAddrLabelSymbolToEmit(), llvm::AsmPrinter::getAddrLabelSymbolToEmit(), getAllocaPos(), llvm::rdf::Liveness::getAllReachingDefs(), llvm::MachineBasicBlock::getBasicBlock(), llvm::MemoryPhi::getBasicBlockIndex(), llvm::PHINode::getBasicBlockIndex(), llvm::InstIterator< BB_t, BB_i_t, BI_t, II_t >::getBasicBlockIterator(), llvm::IRSimilarity::IRSimilarityCandidate::getBasicBlocks(), llvm::NonLocalDepEntry::getBB(), llvm::CFGMST< Edge, BBInfo >::getBBInfo(), llvm::RegionBase< RegionTraits< Function > >::getBBNode(), getBestDestForJumpOnUndef(), llvm::MemorySSA::getBlockAccesses(), llvm::AsmPrinter::GetBlockAddressSymbol(), llvm::MemorySSA::getBlockDefs(), llvm::ScalarEvolution::getBlockDisposition(), llvm::BlockFrequencyInfo::getBlockFreq(), llvm::BlockFrequencyInfoImpl< BT >::getBlockFreq(), llvm::IntervalPartition::getBlockInterval(), llvm::bfi_detail::getBlockName(), getBlockName(), llvm::BlockFrequencyInfo::getBlockProfileCount(), llvm::BlockFrequencyInfoImpl< BT >::getBlockProfileCount(), llvm::SampleProfileLoaderBaseImpl< MachineBasicBlock >::getBlockWeight(), getBranchHint(), getCallStackHash(), llvm::RegionInfoBase< RegionTraits< Function > >::getCommonRegion(), llvm::LazyValueInfo::getConstant(), llvm::ScalarEvolution::getConstantMaxTripCountFromArray(), llvm::LazyValueInfo::getConstantRange(), llvm::ScheduleDAGInstrs::getDAGName(), getEHPadFromPredecessor(), llvm::GraphTraits< BasicBlock * >::getEntryNode(), llvm::GraphTraits< const BasicBlock * >::getEntryNode(), llvm::GraphTraits< MachineBasicBlock * >::getEntryNode(), llvm::GraphTraits< const MachineBasicBlock * >::getEntryNode(), llvm::objcarc::getEquivalentPHIs(), llvm::LoopBase< BasicBlock, Loop >::getExitBlocks(), llvm::LoopBase< BasicBlock, Loop >::getExitEdges(), llvm::LoopBase< BasicBlock, Loop >::getExitingBlocks(), getFalkorUnrollingPreferences(), llvm::ImplicitControlFlowTracking::getFirstICFI(), llvm::MemoryWriteTracking::getFirstMemoryWrite(), llvm::InstructionPrecedenceTracking::getFirstSpecialInstruction(), llvm::BlockFrequencyInfoImpl< BT >::getFloatingBlockFreq(), llvm::DOTFuncInfo::getFreq(), llvm::FunctionPropertiesInfo::getFunctionPropertiesInfo(), llvm::ValueEnumerator::getGlobalBasicBlockID(), llvm::DomTreeBuilder::SemiNCAInfo< DomTreeT >::getIDom(), llvm::GetIfCondition(), llvm::MemoryPhi::getIncomingValueForBlock(), llvm::PHINode::getIncomingValueForBlock(), llvm::ModifiedPO::getIndexOf(), getInnermostLoopFor(), llvm::VPBuilder::getInsertBlock(), getInsertPt(), getInstrBB(), llvm::Function::getInstructionCount(), llvm::LoopNest::getInterveningInstructions(), llvm::MemoryDependenceResults::getInvariantGroupPointerDependency(), getJumpThreadDuplicationCost(), llvm::SplitAnalysis::getLastSplitPoint(), llvm::SplitAnalysis::getLastSplitPointIter(), getLayoutSuccessorProbThreshold(), getLoadsAndStores(), getLocalFunctionMetadata(), llvm::MachineLoopInfo::getLoopDepth(), llvm::LoopInfoBase< BasicBlock, Loop >::getLoopDepth(), llvm::MachineLoopInfo::getLoopFor(), llvm::LoopInfoBase< BasicBlock, Loop >::getLoopFor(), llvm::Loop::getLoopID(), GetLoopInvariantInsertPosition(), llvm::getMaxFreq(), llvm::RegionInfoBase< RegionTraits< Function > >::getMaxRegionExit(), llvm::MemorySSA::getMemoryAccess(), getModuleFromVal(), llvm::rdf::Liveness::getNearestAliasedRef(), llvm::MachinePostDominatorTree::getNode(), llvm::MachineDominatorTree::getNode(), llvm::DominatorTreeBase< BasicBlock, false >::getNode(), llvm::RegionBase< RegionTraits< Function > >::getNode(), llvm::DomTreeBuilder::SemiNCAInfo< DomTreeT >::getNodeForBlock(), llvm::getNodeHeader(), llvm::DOTGraphTraits< DomTreeNode * >::getNodeLabel(), llvm::RegionTraits< MachineFunction >::getNumSuccessors(), llvm::RegionTraits< Function >::getNumSuccessors(), getOnlyLiveSuccessor(), llvm::SPIRVGlobalRegistry::getOrCreateSPIRVIntegerType(), llvm::SPIRVGlobalRegistry::getOrCreateSPIRVPointerType(), llvm::SPIRVGlobalRegistry::getOrCreateSPIRVVectorType(), getOtherIncomingValue(), getOutermostLoop(), getOutliningBenefit(), getOutliningPenalty(), llvm::MemoryDependenceResults::getPointerDependencyFrom(), llvm::BasicBlock::getPostdominatingDeoptimizeCall(), llvm::LoopBlocksDFS::getPostorder(), llvm::afdo_detail::IRTraits< BasicBlock >::getPredecessors(), llvm::afdo_detail::IRTraits< MachineBasicBlock >::getPredecessors(), llvm::SampleProfileLoaderBaseImpl< MachineBasicBlock >::getPredecessors(), llvm::LazyValueInfo::getPredicateAt(), getPredState(), llvm::RegionInfoBase< RegionTraits< Function > >::getRegionFor(), getRegsUsedByPHIs(), llvm::SCEVExpander::getRelatedExistingExpansion(), llvm::LoopBlocksDFS::getRPO(), llvm::BranchProbabilityInfo::SccInfo::getSccEnterBlocks(), llvm::BranchProbabilityInfo::SccInfo::getSccExitBlocks(), llvm::BranchProbabilityInfo::SccInfo::getSCCNum(), llvm::gvn::AvailableValueInBlock::getSelect(), llvm::MemoryDependenceResults::getSimplePointerDependencyFrom(), getSingleDef(), getSingleLiveInSuccBB(), llvm::getSourceGraphNode(), llvm::RegionBase< RegionTraits< Function > >::getSubRegionNode(), llvm::GetSuccessorNumber(), llvm::afdo_detail::IRTraits< BasicBlock >::getSuccessors(), llvm::afdo_detail::IRTraits< MachineBasicBlock >::getSuccessors(), llvm::SampleProfileLoaderBaseImpl< MachineBasicBlock >::getSuccessors(), getSuccState(), getSymTab(), getTwoPredecessors(), llvm::gvn::AvailableValueInBlock::getUndef(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::GetUndefVal(), llvm::SSAUpdaterTraits< LDVSSAUpdater >::GetUndefVal(), llvm::LoopBase< BasicBlock, Loop >::getUniqueExitBlocks(), llvm::getUniqueExitBlocksHelper(), llvm::LoopBase< BasicBlock, Loop >::getUniqueNonLatchExitBlocks(), llvm::WebAssemblyTTIImpl::getUnrollingPreferences(), llvm::AMDGPUTTIImpl::getUnrollingPreferences(), llvm::SystemZTTIImpl::getUnrollingPreferences(), llvm::RISCVTTIImpl::getUnrollingPreferences(), llvm::AArch64TTIImpl::getUnrollingPreferences(), llvm::ARMTTIImpl::getUnrollingPreferences(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getUnrollingPreferences(), llvm::WasmEHFuncInfo::getUnwindDest(), llvm::WasmEHFuncInfo::getUnwindSrcs(), llvm::SSAUpdaterImpl< UpdaterT >::GetValue(), llvm::MachineSSAUpdater::GetValueAtEndOfBlock(), llvm::SSAUpdater::GetValueAtEndOfBlock(), llvm::SelectionDAGBuilder::getValueImpl(), llvm::MachineSSAUpdater::GetValueInMiddleOfBlock(), llvm::SSAUpdater::GetValueInMiddleOfBlock(), getWorklist(), llvm::MemorySSA::getWritableBlockAccesses(), llvm::MemorySSA::getWritableBlockDefs(), HandleCallsInBlockInlinedThroughInvoke(), HandleInlinedEHPad(), HandleInlinedLandingPad(), handlePhiDef(), llvm::objcarc::BottomUpPtrState::HandlePotentialUse(), hasAddressTakenAndUsed(), hasCallsInBlocksBetween(), hasChangeableCC(), llvm::ImplicitControlFlowTracking::hasICF(), hasOnlyColdCalls(), hasOnlyUniformBranches(), llvm::LoopBlocksDFS::hasPostorder(), llvm::LoopBlocksDFS::hasPreorder(), hasSameSuccessors(), llvm::InstructionPrecedenceTracking::hasSpecialInstructions(), llvm::WasmEHFuncInfo::hasUnwindDest(), llvm::WasmEHFuncInfo::hasUnwindSrcs(), hasUseAfterLoop(), hasUsersIn(), llvm::MachineSSAUpdater::HasValueForBlock(), llvm::SSAUpdater::HasValueForBlock(), llvm::hoistAllInstructionsInto(), hoistLoopToNewParent(), llvm::hoistRegion(), llvm::identifyNoAliasScopesToClone(), InBlock(), IncomingValuesAreCompatible(), llvm::ValueEnumerator::incorporateFunction(), IncorporateFunctionInfoGlobalBBIDs(), llvm::StackProtectorDescriptor::initialize(), INITIALIZE_PASS(), llvm::IRSimilarity::IRInstructionMapper::initializeForBBs(), llvm::IRSimilarity::IRInstructionData::initializeInstruction(), initSlots2BasicBlocks(), initSlots2Values(), llvm::InlineFunction(), llvm::DivergenceAnalysisImpl::inRegion(), llvm::VPBuilder::insert(), llvm::objcarc::BundledRetainClaimRVs::insertAfterInvokes(), llvm::VPRecipeBase::insertBefore(), llvm::insertDebugValuesForPHIs(), llvm::IRBuilderDefaultInserter::InsertHelper(), llvm::IRBuilderCallbackInserter::InsertHelper(), llvm::InstructionPrecedenceTracking::insertInstructionTo(), llvm::ICFLoopSafetyInfo::insertInstructionTo(), llvm::MemorySSA::insertIntoListsBefore(), llvm::MemorySSA::insertIntoListsForBlock(), InsertNewDef(), llvm::InstCombinerImpl::InsertNewInstBefore(), llvm::InstCombiner::InsertNewInstBefore(), llvm::BPFCoreSharedInfo::insertPassThrough(), insertTrivialPHIs(), llvm::InstIterator< BB_t, BB_i_t, BI_t, II_t >::InstIterator(), llvm::Instruction::Instruction(), llvm::SampleProfileProber::instrumentOneFunc(), inSubLoop(), llvm::invalidateParentIListOrdering(), llvm::IRSimilarity::IRSimilarityCandidate::IRSimilarityCandidate(), llvm::StackLifetime::isAliveAfter(), llvm::Loop::isAnnotatedParallel(), llvm::Attributor::isAssumedDead(), IsAvailableOnEntry(), llvm::ScalarEvolution::isBasicBlockEntryGuardedByCond(), llvm::SCCPSolver::isBlockExecutable(), llvm::SparseSolver< LatticeKey, LatticeVal, KeyInfo >::isBlockExecutable(), llvm::SCCPInstVisitor::isBlockExecutable(), llvm::IsBlockFollowedByDeoptOrUnreachable(), isBlockInLCSSAForm(), isBlockValidForExtraction(), isChainSelectCmpBranch(), llvm::ProfileSummaryInfo::isColdBlock(), llvm::ProfileSummaryInfo::isColdBlockNthPercentile(), isDefLiveOut(), isEFLAGSLiveAfter(), llvm::CodeExtractor::isEligible(), isExitBlock(), isFreeInLoop(), isFullDominator(), isFullPostDominator(), llvm::ProfileSummaryInfo::isFunctionColdInCallGraph(), llvm::ProfileSummaryInfo::isFunctionHotInCallGraph(), isFunctionMallocLike(), llvm::isGuaranteedToTransferExecutionToSuccessor(), llvm::HardwareLoopInfo::isHardwareLoopCandidate(), llvm::PPCTTIImpl::isHardwareLoopProfitable(), llvm::ARMTTIImpl::isHardwareLoopProfitable(), llvm::ProfileSummaryInfo::isHotBlock(), llvm::ProfileSummaryInfo::isHotBlockNthPercentile(), isIndirectBrTarget(), llvm::isInlineViable(), llvm::BlockFrequencyInfo::isIrrLoopHeader(), llvm::BlockFrequencyInfoImpl< BT >::isIrrLoopHeader(), llvm::Loop::isLCSSAForm(), llvm::CodeExtractor::isLegalToShrinkwrapLifetimeMarkers(), llvm::ScalarEvolution::isLoopBackedgeGuardedByCond(), isLoopDead(), llvm::LoopBase< BasicBlock, Loop >::isLoopExiting(), llvm::MachineLoopInfo::isLoopHeader(), llvm::LoopInfoBase< BasicBlock, Loop >::isLoopHeader(), llvm::LoopBase< BasicBlock, Loop >::isLoopLatch(), IsNonLocalValue(), isNotUsedOrFreeInLoop(), isOpDefinedInBlock(), llvm::PreservedCFGCheckerInstrumentation::CFG::isPoisoned(), llvm::isPotentiallyReachable(), llvm::isPotentiallyReachableFromMany(), llvm::Loop::isRecursivelyLCSSAForm(), isReturnNonNull(), isSafePHIToSpeculate(), llvm::Loop::isSafeToClone(), llvm::isSafeToMoveBefore(), llvm::BranchProbabilityInfo::SccInfo::isSCCExitingBlock(), llvm::BranchProbabilityInfo::SccInfo::isSCCHeader(), llvm::orc::SpeculateQuery::isStraightLine(), llvm::Interval::isSuccessor(), isSuspendBlock(), isUniformlyReached(), llvm::Value::isUsedInBasicBlock(), llvm::Instruction::isUsedOutsideOfBlock(), isUsedOutsideOfDefiningBlock(), isValInBlock(), IsValueFullyAvailableInBlock(), iterativelySimplifyCFG(), LLVMAppendExistingBasicBlock(), LLVMBasicBlockAsValue(), LLVMBlockAddress(), LLVMBuildCatchRet(), LLVMBuildCleanupRet(), LLVMGetBasicBlockName(), LLVMGetBasicBlockParent(), LLVMGetBasicBlocks(), LLVMGetBasicBlockTerminator(), LLVMGetFirstInstruction(), LLVMGetLastInstruction(), LLVMGetNextBasicBlock(), LLVMGetPreviousBasicBlock(), LLVMInsertBasicBlockInContext(), LLVMInsertExistingBasicBlockAfterInsertBlock(), LLVMMoveBasicBlockAfter(), LLVMMoveBasicBlockBefore(), LLVMPositionBuilder(), LLVMPositionBuilderAtEnd(), LookForIdenticalPHI(), llvm::BlockAddress::lookup(), llvm::LoopBase< BasicBlock, Loop >::LoopBase(), lowerAtomics(), LowerCallResults(), lowerConstantIntrinsics(), llvm::LowerDbgDeclare(), lowerExpectIntrinsic(), LowerFPToInt(), llvm::PatternMatch::m_Deferred(), llvm::PatternMatch::m_SpecificBB(), llvm::MachineInstrSpan::MachineInstrSpan(), makeReducible(), markAliveBlocks(), llvm::SCCPSolver::markBlockExecutable(), llvm::SparseSolver< LatticeKey, LatticeVal, KeyInfo >::MarkBlockExecutable(), llvm::SCCPInstVisitor::markBlockExecutable(), MarkBlocksLiveIn(), llvm::SCCPInstVisitor::markFunctionUnreachable(), markTails(), llvm::PatternMatch::specific_bbval::match(), llvm::gvn::AvailableValueInBlock::MaterializeAdjustedValue(), llvm::JumpThreadingPass::maybeMergeBasicBlockIntoOnlyPred(), llvm::JumpThreadingPass::maybethreadThroughTwoBasicBlocks(), llvm::SIMachineFunctionInfo::mayUseAGPRs(), llvm::MemoryWriteTracking::mayWriteToMemory(), llvm::MergeBlockIntoPredecessor(), llvm::MergeBlockSuccessorsIntoGivenBlocks(), MergeCompatibleInvokes(), mergeConditionalStores(), mergeConditionalStoreToAddress(), llvm::ARMBlockPlacement::moveBasicBlock(), llvm::Instruction::moveBefore(), llvm::VPRecipeBase::moveBefore(), llvm::MemorySSA::moveTo(), llvm::LoopBase< BasicBlock, Loop >::moveToHeader(), llvm::MemorySSAUpdater::moveToPlace(), llvm::IRMutationStrategy::mutate(), llvm::InjectorIRStrategy::mutate(), llvm::InstDeleterIRStrategy::mutate(), needsFP(), llvm::PHITransAddr::NeedsPHITranslationFromBlock(), needToInsertPhisForLCSSA(), NegateValue(), llvm::RandomIRBuilder::newSink(), llvm::RandomIRBuilder::newSource(), llvm::EscapeEnumerator::Next(), llvm::HexagonInstrInfo::nonDbgBBSize(), llvm::NonLocalDepEntry::NonLocalDepEntry(), normalizeForInvokeSafepoint(), nullifySetjmp(), oneUseOutsideLoop(), llvm::orc::SequenceBBQuery::operator()(), llvm::bfi_detail::BlockEdgesAdder< BT >::operator()(), llvm::RNSuccIterator< NodeRef, BlockT, RegionT >::operator*(), llvm::RNSuccIterator< FlatIt< NodeRef >, BlockT, RegionT >::operator*(), llvm::InstIterator< BB_t, BB_i_t, BI_t, II_t >::operator--(), llvm::NonLocalDepEntry::operator<(), llvm::rdf::operator<<(), llvm::InstIterator< BB_t, BB_i_t, BI_t, II_t >::operator==(), llvm::MachinePostDominatorTree::operator[](), llvm::MachineLoopInfo::operator[](), llvm::MachineDominatorTree::operator[](), llvm::DominatorTreeBase< BasicBlock, false >::operator[](), llvm::RegionInfoBase< RegionTraits< Function > >::operator[](), llvm::LoopInfoBase< BasicBlock, Loop >::operator[](), optimizeBlock(), optimizeDivRem(), llvm::BranchFolder::OptimizeFunction(), llvm::slpvectorizer::BoUpSLP::optimizeGatherSequence(), optimizeSQRT(), orderModule(), llvm::RegionBase< RegionTraits< Function > >::outermostLoopInRegion(), partitionLoopBlocks(), llvm::peelLoop(), peelToTurnInvariantLoadsDerefencebale(), performBlockTailMerging(), performBranchToCommonDestFolding(), llvm::ARMTargetLowering::PerformBRCONDCombine(), llvm::GVNExpression::PHIExpression::PHIExpression(), pointerInvalidatedByBlock(), pointerInvalidatedByLoop(), populateDependencyMatrix(), llvm::pred_begin(), llvm::pred_empty(), llvm::pred_end(), llvm::pred_size(), llvm::predecessors(), predictUseListOrder(), prepareICWorklistFromFunction(), llvm::LoopVectorizationLegality::prepareToFoldTailByMasking(), llvm::PrepareToSplitEntryBlock(), llvm::LegacyDivergenceAnalysis::print(), llvm::GenericSSAContext< Function >::print(), llvm::PhiValues::print(), llvm::DominanceFrontierBase< BasicBlock, false >::print(), llvm::WebAssemblyException::print(), llvm::Value::print(), llvm::RegionBase< RegionTraits< Function > >::print(), llvm::LoopBase< BasicBlock, Loop >::print(), llvm::MemoryPhi::print(), llvm::MachineFunction::print(), llvm::BlockFrequencyInfoImpl< BT >::print(), llvm::PredicatedScalarEvolution::print(), printBBName(), llvm::SampleProfileLoaderBaseImpl< MachineBasicBlock >::printBlockEquivalence(), llvm::BlockFrequencyInfo::printBlockFreq(), llvm::BlockFrequencyInfoImpl< BT >::printBlockFreq(), llvm::printBlockSet(), llvm::SampleProfileLoaderBaseImpl< MachineBasicBlock >::printBlockWeight(), llvm::PreservedCFGCheckerInstrumentation::CFG::printDiff(), llvm::GVNExpression::PHIExpression::printInternal(), printIRBlockReference(), llvm::DOTGraphTraits< RegionInfo * >::printRegionCluster(), llvm::JumpThreadingPass::processBlock(), ProcessBlock(), llvm::JumpThreadingPass::processBranchOnPHI(), llvm::JumpThreadingPass::processBranchOnXOR(), processDbgDeclares(), llvm::HexagonFrameLowering::processFunctionBeforeFrameFinalized(), llvm::AArch64FrameLowering::processFunctionBeforeFrameIndicesReplaced(), llvm::JumpThreadingPass::processGuards(), llvm::JumpThreadingPass::processImpliedCondition(), llvm::DebugInfoFinder::processModule(), processPHI(), processSwitch(), llvm::JumpThreadingPass::processThreadableEdges(), programUndefinedIfUndefOrPoison(), promoteArguments(), promoteMemoryToRegister(), PropagateCallSiteMetadata(), llvm::SampleProfileLoaderBaseImpl< MachineBasicBlock >::propagateThroughEdges(), llvm::SampleProfileLoaderBaseImpl< MachineBasicBlock >::propagateWeights(), llvm::ScalarEvolution::properlyDominates(), llvm::ValueEnumerator::purgeFunction(), rebuildLoopAfterUnswitch(), llvm::LiveVariables::recomputeForSingleDefVirtReg(), recomputeLoopBlockSet(), reconnectChildLoops(), llvm::SSAUpdaterImpl< UpdaterT >::RecordMatchingPHIs(), redirectToHub(), redirectValuesFromPredecessorsToPhi(), llvm::Attributor::registerManifestAddedBasicBlock(), llvm::remapInstructionsInBlocks(), llvm::removeAllNonTerminatorAndEHPadInstructions(), llvm::MachineDominanceFrontier::removeBlock(), llvm::DominanceFrontierBase< BasicBlock, false >::removeBlock(), llvm::MachineLoopInfo::removeBlock(), llvm::LoopInfoBase< BasicBlock, Loop >::removeBlock(), llvm::LoopBase< BasicBlock, Loop >::removeBlockFromLoop(), removeBlockFromLoops(), llvm::MemorySSAUpdater::removeBlocks(), removeEmptyCleanup(), llvm::MemorySSA::removeFromLists(), llvm::PHINode::removeIncomingValue(), llvm::InstructionPrecedenceTracking::removeInstruction(), removeNonFeasibleEdges(), removePhis(), llvm::RemoveRedundantDbgInstrs(), removeRedundantDbgInstrsUsingBackwardScan(), removeRedundantDbgInstrsUsingForwardScan(), removeSSACopy(), removeUndefIntroducingPredecessor(), llvm::removeUnreachableBlocks(), removeUnusedBlocksFromParent(), llvm::removeUnwindEdge(), llvm::MemorySSA::renamePass(), replaceAllUsesOfWithIn(), replaceArgumentUses(), replaceDbgUsesOutsideBlock(), llvm::replaceDominatedUsesWith(), llvm::RegionBase< RegionTraits< Function > >::replaceExit(), llvm::replaceNonLocalUsesWith(), replaceUndefValuesInPhi(), llvm::Value::replaceUsesOutsideBlock(), llvm::SCCPInstVisitor::resolvedUndefsIn(), restoreSSA(), rewrite(), rewritePHIs(), llvm::GuardWideningPass::run(), llvm::RedundantDbgInstEliminationPass::run(), llvm::InstrProfiling::run(), llvm::TypeFinder::run(), llvm::AMDGPUSimplifyLibCallsPass::run(), llvm::AMDGPUUseNativeCallsPass::run(), llvm::InstCombinerImpl::run(), llvm::TruncInstCombine::run(), llvm::PhiValuesPrinterPass::run(), llvm::LoadAndStorePromoter::run(), llvm::DivergenceAnalysisPrinterPass::run(), llvm::GVNHoist::run(), llvm::InlineCostAnnotationPrinterPass::run(), runCGProfilePass(), llvm::DomTreeBuilder::SemiNCAInfo< DomTreeT >::runDFS(), llvm::runFunctionSpecialization(), runImpl(), llvm::SLPVectorizerPass::runImpl(), llvm::JumpThreadingPass::runImpl(), llvm::runIPSCCP(), runOnBasicBlock(), llvm::RewriteStatepointsForGC::runOnFunction(), runOnFunction(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::AVRFrameAnalyzer::runOnMachineFunction(), llvm::IRTranslator::runOnMachineFunction(), runPartiallyInlineLibCalls(), runPass(), runSCCP(), llvm::BranchProbabilityInfo::SccInfo::SccInfo(), selectIncomingValueForBlock(), llvm::LoopVectorizationCostModel::selectInterleaveCount(), separateNestedLoop(), llvm::FunctionLoweringInfo::set(), llvm::MemoryAccess::setBlock(), llvm::BlockFrequencyInfo::setBlockFreq(), llvm::BlockFrequencyInfoImpl< BT >::setBlockFreq(), llvm::BlockFrequencyInfo::setBlockFreqAndScale(), llvm::MIRProfileLoader::setBranchProbs(), llvm::LoopVectorizationCostModel::setCostBasedWideningDecision(), llvm::MemoryPhi::setIncomingBlock(), llvm::PHINode::setIncomingBlock(), llvm::PHINode::setIncomingValueForBlock(), llvm::VPBuilder::setInsertPoint(), llvm::Loop::setLoopID(), setMemoryPhiValueForBlock(), llvm::DominatorTreeBase< BasicBlock, false >::setNewRoot(), llvm::RegionInfoBase< RegionTraits< Function > >::setRegionFor(), llvm::WasmEHFuncInfo::setUnwindDest(), llvm::StackProtector::shouldEmitSDCheck(), shouldInstrumentBlock(), llvm::shouldOptimizeForSize(), llvm::simplifyCFG(), SimplifyCondBranchToCondBranch(), SimplifyFunction(), llvm::SimplifyInstructionsInBlock(), simplifyInstsInBlock(), llvm::simplifyLoopAfterUnroll(), simplifyLoopInst(), simplifyOneLoop(), simplifyTerminatorLeadingToRet(), simplifyUsingControlFlow(), sink(), llvm::SinkAndHoistLICMFlags::SinkAndHoistLICMFlags(), SinkCommonCodeFromPredecessors(), SinkInstruction(), sinkLastInstruction(), sinkLoopInvariantInstructions(), llvm::sinkRegion(), llvm::InnerLoopVectorizer::sinkScalarOperands(), llvm::PredIteratorCache::size(), llvm::InstCombinerImpl::SliceUpIllegalIntegerPHI(), llvm::SparseSolver< LatticeKey, LatticeVal, KeyInfo >::Solve(), llvm::SCCPInstVisitor::solve(), llvm::SplitAllCriticalEdges(), splitBlockIfNotFirst(), llvm::SplitBlockPredecessors(), SplitBlockPredecessorsImpl(), splitCoroutine(), SplitCriticalSideEffectEdges(), llvm::SplitEdge(), llvm::SplitIndirectBrCriticalEdges(), llvm::SITargetLowering::splitKillBlock(), llvm::CriticalAntiDepBreaker::StartBlock(), llvm::AggressiveAntiDepBreaker::StartBlock(), llvm::stripDebugInfo(), llvm::succ_begin(), llvm::succ_empty(), llvm::succ_end(), llvm::succ_size(), llvm::successors(), SwitchToLookupTable(), llvm::SyncDependenceAnalysis::SyncDependenceAnalysis(), tailMergeBlocksWithSimilarFunctionTerminators(), llvm::JumpThreadingPass::threadEdge(), llvm::JumpThreadingPass::threadGuard(), llvm::JumpThreadingPass::threadThroughTwoBasicBlocks(), llvm::PopulateLoopsDFS< BlockT, LoopT >::traverse(), llvm::JumpThreadingPass::tryThreadEdge(), TryToMergeLandingPad(), llvm::TryToSimplifyUncondBranchFromEmptyBlock(), llvm::JumpThreadingPass::tryToUnfoldSelect(), llvm::JumpThreadingPass::tryToUnfoldSelectInCurrBB(), tryToVectorizeHorReductionOrInstOperands(), tryWidenCondBranchToCondBranch(), llvm::JumpThreadingPass::unfoldSelectInstr(), unifyLoopExits(), llvm::MemoryPhi::unorderedDeleteIncomingBlock(), llvm::UnrollAndJamLoop(), llvm::UnrollLoop(), llvm::UnrollRuntimeLoopRemainder(), unswitchBestCondition(), unswitchNontrivialInvariants(), unswitchTrivialSwitch(), llvm::MemorySSAUpdater::updateForClonedBlockIntoPred(), llvm::MemorySSAUpdater::updateForClonedLoop(), updatePredecessorProfileMetadata(), llvm::JumpThreadingPass::updateSSA(), updateSuccessor(), validateAndCostRequiredSelects(), ValidateMVEStore(), llvm::ValueEnumerator::ValueEnumerator(), valueEscapes(), llvm::MemorySSA::verifyDominationNumbers(), llvm::DomTreeBuilder::SemiNCAInfo< DomTreeT >::VerifyLevels(), llvm::LoopBase< BasicBlock, Loop >::verifyLoop(), llvm::DomTreeBuilder::SemiNCAInfo< DomTreeT >::verifyParentProperty(), llvm::MemorySSA::verifyPrevDefInPhis(), llvm::DomTreeBuilder::SemiNCAInfo< DomTreeT >::verifyReachability(), llvm::DomTreeBuilder::SemiNCAInfo< DomTreeT >::verifySiblingProperty(), llvm::InstVisitor< ObjectSizeOffsetVisitor, SizeOffsetType >::visit(), llvm::SelectionDAGBuilder::visitBitTestCase(), visitDomSubTree(), llvm::LoopBlocksTraversal::visitPreorder(), llvm::VPlanSlp::VPlanSlp(), willLeaveFunctionImmediatelyAfter(), and llvm::WriteGraph().
Definition at line 14 of file README.txt.
Referenced by llvm::dump(), and fixELFSymbolsInTLSFixupsImpl().
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to CFG |
Definition at line 39 of file README.txt.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb<bb27,0x8b0a7c0> Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info (i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably Consider |
Definition at line 121 of file README.txt.
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inline |
Definition at line 158 of file README.txt.
< i32 > br label bb114 eax ecx movl ebp subl ebp eax movl ebp subl ebp eax movl ebp subl ebp eax subl ecx movl ebp eax movl ebp eax movl ebp ebp This appears to be bad because the RA is not folding the store to the stack slot into the movl The above instructions could ebp ebp This seems like a cross between remat and spill folding This has redundant subtractions of eax from a stack slot However |
Definition at line 43 of file README.txt.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb<bb27,0x8b0a7c0> Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info (i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably ** array_addr i32 |
Definition at line 122 of file README.txt.
Referenced by abort_gzip(), bar(), foo(), matchZExtFromI32(), AMDGPUDAGToDAGISel::Select(), R600DAGToDAGISel::SelectADDRIndirect(), R600DAGToDAGISel::SelectADDRVTX_READ(), AMDGPUDAGToDAGISel::SelectBuildVector(), and SelectSAddrFI().
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb<bb27,0x8b0a7c0> Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info (i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably ** array_addr i32 n y store obj obj** nth_el If the i64 division is lowered to a then a safe point array and nth_el no longer point into the correct object The fix for this is to copy address calculations so that dependent pointers are never live across safe point boundaries But the loads cannot be copied like this if there was an intervening so may be hard to get right Only a concurrent mutator can trigger a collection at the libcall safe point So single threaded programs do not have this even with a copying collector LLVM optimizations would probably undo a front end s careful work The ocaml frametable structure supports liveness information It would be good to support it The FIXME in ComputeCommonTailLength in BranchFolding cpp needs to be revisited The check is there to work around a misuse of directives in assembly It would be good to detect collector target compatibility instead of silently doing the wrong thing It would be really nice to be able to write patterns in td files for which would eliminate a bunch of predicates on it would be even better to have tblgen synthesize the various copy insertion inspection methods in TargetInstrInfo Stack coloring improvements |
Definition at line 170 of file README.txt.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb<bb27,0x8b0a7c0> Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info (i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably ** array_addr i32 n y store obj obj** nth_el If the i64 division is lowered to a libcall |
Definition at line 127 of file README.txt.
Referenced by llvm::AArch64LegalizerInfo::AArch64LegalizerInfo(), llvm::MipsLegalizerInfo::MipsLegalizerInfo(), and llvm::X86LegalizerInfo::X86LegalizerInfo().
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla lr |
Definition at line 6 of file README.txt.
Referenced by call(), and llvm::LiveRangeUpdater::setDest().
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb76.outer, 0x8b0c5f0 > |
Definition at line 41 of file README.txt.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and mov |
Definition at line 23 of file README.txt.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb<bb27,0x8b0a7c0> Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info (i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably ** array_addr i32 n y store obj* new |
Definition at line 125 of file README.txt.
Referenced by llvm::DwarfUnit::addSectionDelta(), llvm::DenseMapBase< DenseMap< llvm::VPInstruction *, llvm::InterleaveGroup< llvm::VPInstruction > *, DenseMapInfo< llvm::VPInstruction * >, llvm::detail::DenseMapPair< llvm::VPInstruction *, llvm::InterleaveGroup< llvm::VPInstruction > * > >, llvm::VPInstruction *, llvm::InterleaveGroup< llvm::VPInstruction > *, DenseMapInfo< llvm::VPInstruction * >, llvm::detail::DenseMapPair< llvm::VPInstruction *, llvm::InterleaveGroup< llvm::VPInstruction > * > >::copyFrom(), llvm::optional_detail::OptionalStorage< uint64_t >::emplace(), llvm::optional_detail::OptionalStorage< T, true >::emplace(), llvm::SmallVectorImpl< uint64_t >::emplace_back(), llvm::SmallDenseMap< LocPair, CacheEntry, 8 >::grow(), llvm::SmallVectorTemplateBase< T, bool >::growAndEmplaceBack(), llvm::DenseMapBase< DenseMap< llvm::VPInstruction *, llvm::InterleaveGroup< llvm::VPInstruction > *, DenseMapInfo< llvm::VPInstruction * >, llvm::detail::DenseMapPair< llvm::VPInstruction *, llvm::InterleaveGroup< llvm::VPInstruction > * > >, llvm::VPInstruction *, llvm::InterleaveGroup< llvm::VPInstruction > *, DenseMapInfo< llvm::VPInstruction * >, llvm::detail::DenseMapPair< llvm::VPInstruction *, llvm::InterleaveGroup< llvm::VPInstruction > * > >::moveFromOldBuckets(), llvm::optional_detail::OptionalStorage< uint64_t >::operator=(), llvm::yaml::SIArgument::operator=(), llvm::optional_detail::OptionalStorage< T, true >::operator=(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::yaml::SIArgument::SIArgument(), and llvm::SmallDenseMap< LocPair, CacheEntry, 8 >::swap().
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 noreg |
Definition at line 36 of file README.txt.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb<bb27,0x8b0a7c0> Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info (i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably ** array_addr nth_el = getelementptr { i32, [0 x %obj] }* %array |
Definition at line 122 of file README.txt.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb<bb27,0x8b0a7c0> Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info (i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably ** array_addr i32 n old |
Definition at line 123 of file README.txt.
Referenced by llvm::install_out_of_memory_new_handler(), llvm::SparseBitVectorElement< ElementSize >::intersectWith(), llvm::SparseBitVectorElement< ElementSize >::intersectWithComplement(), llvm::SparseBitVectorElement< ElementSize >::test_and_set(), llvm::SparseBitVector< ElementSize >::test_and_set(), and llvm::SparseBitVectorElement< ElementSize >::unionWith().
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb<bb27,0x8b0a7c0> Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info (i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first place |
Definition at line 50 of file README.txt.
Common register allocation spilling problem |
Definition at line 5 of file README.txt.
entry mr r3 |
Definition at line 8 of file README.txt.
entry mr r2 blr This could be reduced to the much andc r2 r3 slwi or r2 rlwimi stw r3 blr We could collapse a bunch of those ORs and ANDs and generate the following equivalent r3 rlwinm r4 |
Definition at line 5 of file README.txt.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to reg1037 = ADDri %reg1039 |
Definition at line 35 of file README.txt.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 reg1038 = ADDrs %reg1032 |
Definition at line 36 of file README.txt.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 reg1039 |
Definition at line 36 of file README.txt.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb<bb27,0x8b0a7c0> Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info (i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably ** array_addr i32 n y store obj obj** nth_el If the i64 division is lowered to a then a safe point array and nth_el no longer point into the correct object The fix for this is to copy address calculations so that dependent pointers are never live across safe point boundaries But the loads cannot be copied like this if there was an intervening so may be hard to get right Only a concurrent mutator can trigger a collection at the libcall safe point So single threaded programs do not have this requirement |
Definition at line 136 of file README.txt.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb<bb27,0x8b0a7c0> Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info (i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably ** array_addr i32 n y store obj obj** nth_el If the i64 division is lowered to a then a safe point array and nth_el no longer point into the correct object The fix for this is to copy address calculations so that dependent pointers are never live across safe point boundaries But the loads cannot be copied like this if there was an intervening so may be hard to get right Only a concurrent mutator can trigger a collection at the libcall safe point So single threaded programs do not have this even with a copying collector Still |
Definition at line 137 of file README.txt.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb<bb27,0x8b0a7c0> Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info (i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably ** array_addr i32 n y store obj obj** nth_el If the i64 division is lowered to a then a safe point array and nth_el no longer point into the correct object The fix for this is to copy address calculations so that dependent pointers are never live across safe point boundaries But the loads cannot be copied like this if there was an intervening store |
Definition at line 133 of file README.txt.
Referenced by abort_gzip().