#include <algorithm>

Include dependency graph for README.txt:

Typedefs
using	tmp1 = urem i32 %X, 255 ret i32 %tmp1 } Currently it compiles to:... movl $2155905153, %ecx movl 8(%esp), %esi movl %esi, %eax mull %ecx ... This could be "reassociated" into:movl $2155905153, %eax movl 8(%esp), %ecx mull %ecx to avoid the copy. In fact, the existing two-address stuff would do this except that mul isn 't a commutative 2-addr instruction. I guess this has to be done at isel time based on the #uses to mul? Make sure the instruction which starts a loop does not cross a cacheline boundary. This requires knowning the exact length of each machine instruction. That is somewhat complicated, but doable. Example 256.bzip2:In the new trace, the hot loop has an instruction which crosses a cacheline boundary. In addition to potential cache misses, this can 't help decoding as I imagine there has to be some kind of complicated decoder reset and realignment to grab the bytes from the next cacheline. 532 532 0x3cfc movb(1809(%esp, %esi), %bl<<<--- spans 2 64 byte lines 942 942 0x3d03 movl %dh,(1809(%esp, %esi) 937 937 0x3d0a incl %esi 3 3 0x3d0b cmpb %bl, %dl 27 27 0x3d0d jnz 0x000062db< main+11707 > In c99 mode, the preprocessor doesn 't like assembly comments like #TRUNCATE. This could be a single 16-bit load. int f(char *p) { if((p[0]==1) &(p[1]==2)) return 1

using	a = =0.0 ? 0.0 :(a > 0.0 ? 1.0 :-1.0)

using	edx = sar eax, 31) more aggressively

using	mtune = pentium2/3/4/m/etc.:abs:movl 4(%esp), %eax cltd xorl %edx, %eax subl %edx, %eax ret Take the following code(from http:extern unsigned char first_one[65536]

using	tmp = call i32 @t4( i32 %tmp.5 )

Functions
http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg	support (From http:but without the unnecessary and.) movl %ecx

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit	shifts (in general) expand to really bad code. Instead of using cmovs

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit we should expand to a conditional branch like GCC produces Some isel and Sequencing of Instructions Scheduling for reduced register pressure E g Minimum Register Instruction Sequence load p Because the compare isn t it is not matched with the load on both sides The dag combiner should be made smart enough to canonicalize the load into the RHS of a compare when it can invert the result of the compare for free In many LLVM generates code like eax cmpl esp setl al movzbl eax ret on some	processors (which ones?)

void	clearbit (int *target, int bit)

Instead of the following for memset char edx edx edx It might be better to generate eax movl edx movl edx movw edx when we can spare a register It reduces code size Evaluate what the best way to codegen sdiv C is For we currently get ret i32 Y eax movl ecx ecx ecx addl eax eax ret GCC knows several different ways to codegen one of which is eax eax	leal (%eax)

Instead of the following for memset char edx edx edx It might be better to generate eax movl edx movl edx movw edx when we can spare a register It reduces code size Evaluate what the best way to codegen sdiv C is For we currently get ret i32 Y eax movl ecx ecx ecx addl eax eax ret GCC knows several different ways to codegen one of which is eax eax ecx cmovle eax eax ret which is probably but it s interesting at since libc is hand tuned for medium and large mem	ops (avoiding RFO for large stores, TLB preheating, etc) Optimize this into something reasonable

_test eax	movaps (%eax)

_test eax xmm0	movl (%esp)

_test eax xmm0 eax xmm1 comiss xmm1 setae al movzbl ecx eax edx ecx cmove eax ret Note the cmove can be replaced with a single cmovae There are a number of issues We are introducing a setcc between the result of the intrisic call and select The intrinsic is expected to produce a i32 value so a any	extend (which becomes a zero extend) is added. We probably need some kind of target DAG combine hook to fix this. We generate significantly worse code for this than GCC

We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax	leal (%eax,%eax, 2)

the multiplication has a latency of four as opposed to two cycles for the movl lea variant It appears gcc place string data with linkonce linkage in section coalesced instead of section coalesced Take a look at darwin there are other Darwin assembler directives that we do not make use of define i32	foo (i32 *%a, i32 %t)

esp	movl (%esp, 1)

esp eax movl ecx ecx cvtsi2ss xmm0 eax cvtsi2ss xmm1 xmm0 addss xmm0 movss	flds (%esp, 1) 0000002d addl $0x04

we currently eax	movsbl (%esp)

_test eax	subl (%esp)

For the entry BB esp pxor xmm0	movsd (%esp)

For the entry BB esp pxor xmm0 xmm1 ucomisd xmm1 setnp al sete cl testb al jne LBB1_5 xmm2 cvtss2sd	LCPI1_1 (%rip)

For the entry BB esp pxor xmm0 xmm1 ucomisd xmm1 setnp al sete cl testb al jne LBB1_5 xmm2 cvtss2sd xmm3 ucomisd xmm0 ja LBB1_3 xmm2 xmm0 ret We should sink the load into xmm3 into the LBB1_2 block This should be pretty and will nuke all the copies bool	full_add (unsigned a, unsigned b)

bool	no_overflow (unsigned a, unsigned b)

< i32 > br label bb114 eax ecx movl ebp subl ebp	movswl (%ebp)

to esp esp setne al movzbw ax esp setg cl movzbw cx cmove cx cl jne LBB1_2 esp	ret (also really horrible code on ppc). This is due to the expand code for 64-bit compares. GCC produces multiple branches

int	caller (int32 arg1, int32 arg2)

Here we don t need to write any variables to the top of the stack since they don t overwrite each other int	callee (int32 arg1, int32 arg2)

Here we need to push the arguments because they overwrite each other	main ()

void	test (double *P)

The generated code on x86 for checking for signed overflow on a multiply the obvious way is much longer than it needs to be int	x (int a, int b)

int	FirstOnet (unsigned long long arg1)

The following code is currently eax eax ecx jb LBB1_2 eax movzbl	first_one (%eax)

The following code is currently eax eax ecx jb LBB1_2 eax movzbl eax ret eax ret We could change the eax into	movzwl (%esp)

< i32 > ret i32 tmp10 ecx esp je LBB0_2 eax addl eax ret edx movl eax subl eax ret There s an obviously unnecessary movl in and we could eliminate a couple more movls by putting(%esp) into %eax instead of %ecx. See rdar< i1 * > define fastcc void	abort_gzip () noreturn nounwind

declare void	exit (i32) noreturn nounwind This compiles into

	into (-m64)

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp	leaq (%rsp)

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp eax rsp ret ecx eax	addq (%rsp)

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp eax rsp ret ecx eax rcx movl rsp jmp LBB1_2 gcc rsp rax movq rsp rsp movq rsp rax movq rsp eax eax jb L6	movq (%rsp)

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp eax rsp ret ecx eax rcx movl rsp jmp LBB1_2 gcc rsp rax movq rsp rsp movq rsp rax movq rsp eax eax jb L6 rdx eax rsp ret p2align edx rdx eax movl rsp eax rsp ret and it gets compiled into this on ebp esp eax movl ebp eax movl ebp eax esp popl ebp ret gcc ebp eax popl ebp ret Teach tblgen not to check bitconvert source type in some cases This allows us to consolidate the following patterns in X86InstrMMX	v2i32 (MMX_MOVDQ2Qrr VR128:$src))>

def	v4i16 (MMX_MOVDQ2Qrr VR128:$src))>

def	v8i8 (MMX_MOVDQ2Qrr VR128:$src))>

We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax	addl (%esp)

Current eax eax eax ret Ideal eax eax ret Re implement atomic builtins	__sync_add_and_fetch () and __sync_sub_and_fetch properly. When the return value is not used(i.e. only care about the value in the memory)

int	bar (struct B *a)

define i32	bar (%struct.B *nocapture %a) nounwind readonly optsize

bar al al movzbl eax ret Missed when stored in a memory are stored as single byte objects the value of which is	always (false) or 1(true). We are not using this fact

define i32	bar (i8 *nocapture %a) nounwind readonly optsize

<%struct.bf ** > define void	t1 () nounwind ssp

LLVM currently emits rax rax movq	bfi (%rip)

else	if (x==1) qux()

Variables
Improvements to the multiply shift add	algorithm

Improvements to the multiply shift add e g in	LLVM

http	__pad4__

http eax xorl edx	testb

http eax xorl edx cl sete al setne dl sall	cl

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support	Also

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra	shift

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction	shorter

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax	shrl

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl	eax

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx	xorl

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit we should expand to a conditional branch like GCC produces Some isel	ideas

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit we should expand to a conditional branch like GCC produces Some isel	Duplication

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit we should expand to a conditional branch like GCC produces Some isel and Sequencing of Instructions Scheduling for reduced register pressure E g Minimum Register Instruction Sequence	Problem

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit we should expand to a conditional branch like GCC produces Some isel and Sequencing of Instructions Scheduling for reduced register pressure E g Minimum Register Instruction Sequence load p Because the compare isn t	commutative

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit we should expand to a conditional branch like GCC produces Some isel and Sequencing of Instructions Scheduling for reduced register pressure E g Minimum Register Instruction Sequence load p Because the compare isn t it is not matched with the load on both sides The dag combiner should be made smart enough to canonicalize the load into the RHS of a compare when it can invert the result of the compare for free In many	cases

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit we should expand to a conditional branch like GCC produces Some isel and Sequencing of Instructions Scheduling for reduced register pressure E g Minimum Register Instruction Sequence load p Because the compare isn t it is not matched with the load on both sides The dag combiner should be made smart enough to canonicalize the load into the RHS of a compare when it can invert the result of the compare for free In many LLVM generates code like	this

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit we should expand to a conditional branch like GCC produces Some isel and Sequencing of Instructions Scheduling for reduced register pressure E g Minimum Register Instruction Sequence load p Because the compare isn t it is not matched with the load on both sides The dag combiner should be made smart enough to canonicalize the load into the RHS of a compare when it can invert the result of the compare for free In many LLVM generates code like eax cmpl esp setl al movzbl	al

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit we should expand to a conditional branch like GCC produces Some isel and Sequencing of Instructions Scheduling for reduced register pressure E g Minimum Register Instruction Sequence load p Because the compare isn t it is not matched with the load on both sides The dag combiner should be made smart enough to canonicalize the load into the RHS of a compare when it can invert the result of the compare for free In many LLVM generates code like eax cmpl esp setl al movzbl eax ret on some it is more efficient to do ebx xor eax cmpl	ebx

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit we should expand to a conditional branch like GCC produces Some isel and Sequencing of Instructions Scheduling for reduced register pressure E g Minimum Register Instruction Sequence load p Because the compare isn t it is not matched with the load on both sides The dag combiner should be made smart enough to canonicalize the load into the RHS of a compare when it can invert the result of the compare for free In many LLVM generates code like eax cmpl esp setl al movzbl eax ret on some it is more efficient to do ebx xor eax cmpl esp setl al ret Doing this correctly is tricky	though

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit we should expand to a conditional branch like GCC produces Some isel and Sequencing of Instructions Scheduling for reduced register pressure E g Minimum Register Instruction Sequence load p Because the compare isn t it is not matched with the load on both sides The dag combiner should be made smart enough to canonicalize the load into the RHS of a compare when it can invert the result of the compare for free In many LLVM generates code like eax cmpl esp setl al movzbl eax ret on some it is more efficient to do ebx xor eax cmpl esp setl al ret Doing this correctly is tricky as the xor clobbers the flags We should generate bts btr etc instructions on targets where they are cheap or when codesize is important e	g

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit we should expand to a conditional branch like GCC produces Some isel and Sequencing of Instructions Scheduling for reduced register pressure E g Minimum Register Instruction Sequence load p Because the compare isn t it is not matched with the load on both sides The dag combiner should be made smart enough to canonicalize the load into the RHS of a compare when it can invert the result of the compare for free In many LLVM generates code like eax cmpl esp setl al movzbl eax ret on some it is more efficient to do ebx xor eax cmpl esp setl al ret Doing this correctly is tricky as the xor clobbers the flags We should generate bts btr etc instructions on targets where they are cheap or when codesize is important e	for

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit we should expand to a conditional branch like GCC produces Some isel and Sequencing of Instructions Scheduling for reduced register pressure E g Minimum Register Instruction Sequence load p Because the compare isn t it is not matched with the load on both sides The dag combiner should be made smart enough to canonicalize the load into the RHS of a compare when it can invert the result of the compare for free In many LLVM generates code like eax cmpl esp setl al movzbl eax ret on some it is more efficient to do ebx xor eax cmpl esp setl al ret Doing this correctly is tricky as the xor clobbers the flags We should generate bts btr etc instructions on targets where they are cheap or when codesize is important e int	bit

Instead of the following for memset char edx	movl

Instead of the following for memset char edx edx	movw

Instead of the following for memset char edx edx edx It might be better to generate eax movl edx movl edx movw edx when we can spare a register It reduces code size Evaluate what the best way to codegen sdiv	X

Instead of the following for memset char edx edx edx It might be better to generate eax movl edx movl edx movw edx when we can spare a register It reduces code size Evaluate what the best way to codegen sdiv C is For we currently get ret i32 Y	_test1

Instead of the following for memset char edx edx edx It might be better to generate eax movl edx movl edx movw edx when we can spare a register It reduces code size Evaluate what the best way to codegen sdiv C is For we currently get ret i32 Y eax movl ecx	sarl

Instead of the following for memset char edx edx edx It might be better to generate eax movl edx movl edx movw edx when we can spare a register It reduces code size Evaluate what the best way to codegen sdiv C is For we currently get ret i32 Y eax movl ecx ecx ecx addl	ecx

Instead of the following for memset char edx edx edx It might be better to generate eax movl edx movl edx movw edx when we can spare a register It reduces code size Evaluate what the best way to codegen sdiv C is For we currently get ret i32 Y eax movl ecx ecx ecx addl eax eax ret GCC knows several different ways to codegen	it

Instead of the following for memset char edx edx edx It might be better to generate eax movl edx movl edx movw edx when we can spare a register It reduces code size Evaluate what the best way to codegen sdiv C is For we currently get ret i32 Y eax movl ecx ecx ecx addl eax eax ret GCC knows several different ways to codegen one of which is eax	cmpl

Instead of the following for memset char edx edx edx It might be better to generate eax movl edx movl edx movw edx when we can spare a register It reduces code size Evaluate what the best way to codegen sdiv C is For we currently get ret i32 Y eax movl ecx ecx ecx addl eax eax ret GCC knows several different ways to codegen one of which is eax eax ecx cmovle eax eax ret which is probably	slower

Instead of the following for memset char edx edx edx It might be better to generate eax movl edx movl edx movw edx when we can spare a register It reduces code size Evaluate what the best way to codegen sdiv C is For we currently get ret i32 Y eax movl ecx ecx ecx addl eax eax ret GCC knows several different ways to codegen one of which is eax eax ecx cmovle eax eax ret which is probably but it s interesting at	least

_test	__pad5__

_test eax xmm0 eax xmm1 comiss	xmm0

_test eax xmm0 eax xmm1 comiss xmm1 setae al movzbl ecx eax edx ecx cmove eax ret Note the	setae

_test eax xmm0 eax xmm1 comiss xmm1 setae al movzbl ecx eax edx ecx cmove eax ret Note the	movzbl

We currently emits	imull

We currently emits	esp

We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles	Note

We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable	However

We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code	size

We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium	M

We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium both variants have the same characteristics with regard to	throughput

	however

the multiplication has a latency of four	cycles

the multiplication has a latency of four as opposed to two cycles for the movl lea variant It appears gcc place string data with linkonce linkage in section	__TEXT

the multiplication has a latency of four as opposed to two cycles for the movl lea variant It appears gcc place string data with linkonce linkage in section	__const_coal

the multiplication has a latency of four as opposed to two cycles for the movl lea variant It appears gcc place string data with linkonce linkage in section coalesced instead of section	__DATA

the multiplication has a latency of four as opposed to two cycles for the movl lea variant It appears gcc place string data with linkonce linkage in section coalesced instead of section coalesced Take a look at darwin	h

is pessimized by loop reduce and indvars u32 to float conversion	improvement

float	fh = (int) (u >> 16)

fh *return fh	fl = 0x1.0p16f

	subl

esp eax movl ecx ecx cvtsi2ss xmm0	andl

esp eax movl ecx ecx cvtsi2ss xmm0 eax cvtsi2ss xmm1	mulss

esp eax movl ecx ecx cvtsi2ss xmm0 eax cvtsi2ss xmm1 xmm0 addss	xmm1

	return

We should lrintf and probably other libc functions This	code

is currently compiled	to

is currently compiled esp esp jne LBB1_1	addl

is currently compiled esp esp jne LBB1_1 esp ret	LBB1_1

is currently compiled esp esp jne LBB1_1 esp ret esp esp jne L_abort $stub esp ret This can be applied to any no return function call that takes no arguments etc	Alternatively

is currently compiled esp esp jne LBB1_1 esp ret esp esp jne L_abort $stub esp ret This can be applied to any no return function call that takes no arguments etc the stack save restore logic could be shrink	wrapped

is currently compiled esp esp jne LBB1_1 esp ret esp esp jne L_abort $stub esp ret This can be applied to any no return function call that takes no arguments etc the stack save restore logic could be shrink producing something like esp jne LBB1_1 ret esp call L_abort $stub Both are useful in different situations	Finally

is currently compiled esp esp jne LBB1_1 esp ret esp esp jne L_abort $stub esp ret This can be applied to any no return function call that takes no arguments etc the stack save restore logic could be shrink producing something like esp jne LBB1_1 ret esp call L_abort $stub Both are useful in different situations it could be shrink wrapped and tail	called

we currently	produce

we currently eax ecx subl eax ret We would use one fewer register if codegen d	as

we currently eax ecx subl eax ret We would use one fewer register if codegen d eax neg eax	add

we currently eax ecx subl eax ret We would use one fewer register if codegen d eax neg eax eax ret Note that this isn t beneficial if the load can be folded into the sub In this	case

we currently eax ecx subl eax ret We would use one fewer register if codegen d eax neg eax eax ret Note that this isn t beneficial if the load can be folded into the sub In this we want a	sub

_test	__pad6__

_test eax eax ret Leaf functions that require one byte spill slot have a prolog like esp and an epilog like esp popl esi ret It would be	smaller

_test eax eax ret Leaf functions that require one byte spill slot have a prolog like esp and an epilog like esp popl esi ret It would be and potentially	faster

For	example

For the entry BB	is

For the entry BB esp pxor xmm0 xmm1 ucomisd xmm1 setnp al sete cl testb al jne LBB1_5 xmm2 cvtss2sd xmm3 ucomisd xmm0 ja LBB1_3	LBB1_2

For the entry BB esp pxor xmm0 xmm1 ucomisd xmm1 setnp al sete cl testb al jne LBB1_5 xmm2 cvtss2sd xmm3 ucomisd xmm0 ja LBB1_3 xmm2	LBB1_3

For the entry BB esp pxor xmm0 xmm1 ucomisd xmm1 setnp al sete cl testb al jne LBB1_5 xmm2 cvtss2sd xmm3 ucomisd xmm0 ja LBB1_3 xmm2 xmm0 ret We should sink the load into xmm3 into the LBB1_2 block This should be pretty	easy

For the entry BB esp pxor xmm0 xmm1 ucomisd xmm1 setnp al sete cl testb al jne LBB1_5 xmm2 cvtss2sd xmm3 ucomisd xmm0 ja LBB1_3 xmm2 xmm0 ret We should sink the load into xmm3 into the LBB1_2 block This should be pretty and will nuke all the copies	This

Should compile edi setae al movzbl eax ret on	x86

Should compile edi setae al movzbl eax ret on instead of the rather stupid	looking

Should compile edi setae al movzbl eax ret on instead of the rather stupid edi setb al	xorb

	preds

< i32 >	tmp233 = sub i32 32

< i32 >	tmp231232

< i32 >	tmp245246 = sext i16 %tmp65 to i32

< i32 >	tmp252253 = sext i16 %tmp68 to i32

< i32 >	tmp254 = sub i32 32

< i32 >	tmp553554 = bitcast i16* %tmp37 to i8*

< i8 * >	tmp583584 = sext i16 %tmp98 to i32

< i32 >	tmp585 = sub i32 32

< i32 >	tmp614615 = sext i16 %tmp101 to i32

< i32 >	tmp621622 = sext i16 %tmp104 to i32

< i32 >	tmp623 = sub i32 32

< i32 > br label bb114	produces

< i32 > br label bb114 eax ecx movl ebp subl ebp eax movl ebp subl ebp eax movl ebp subl ebp eax subl ecx movl ebp eax movl ebp eax movl ebp ebp This appears to be bad because the RA is not folding the store to the stack slot into the movl The above instructions could	be

< i32 > br label bb114 eax ecx movl ebp subl ebp eax movl ebp subl ebp eax movl ebp subl ebp eax subl ecx movl ebp eax movl ebp eax movl ebp ebp This appears to be bad because the RA is not folding the store to the stack slot into the movl The above instructions could ebp ebp This seems like a cross between remat and spill folding This has redundant subtractions of eax from a stack slot ecx doesn t	change

< i32 > br label bb114 eax ecx movl ebp subl ebp eax movl ebp subl ebp eax movl ebp subl ebp eax subl ecx movl ebp eax movl ebp eax movl ebp ebp This appears to be bad because the RA is not folding the store to the stack slot into the movl The above instructions could ebp ebp This seems like a cross between remat and spill folding This has redundant subtractions of eax from a stack slot ecx doesn t so we could simply subtract eax from ecx first and then use ecx(or vice-versa). This code< i1 > br i1	tmp659

< i32 > br label bb114 eax ecx movl ebp subl ebp eax movl ebp subl ebp eax movl ebp subl ebp eax subl ecx movl ebp eax movl ebp eax movl ebp ebp This appears to be bad because the RA is not folding the store to the stack slot into the movl The above instructions could ebp ebp This seems like a cross between remat and spill folding This has redundant subtractions of eax from a stack slot ecx doesn t so we could simply subtract eax from ecx first and then use ecx(or vice-versa). This code< i1 > br i1 label	cond_true662

< i32 > br label bb114 eax ecx movl ebp subl ebp eax movl ebp subl ebp eax movl ebp subl ebp eax subl ecx movl ebp eax movl ebp eax movl ebp ebp This appears to be bad because the RA is not folding the store to the stack slot into the movl The above instructions could ebp ebp This seems like a cross between remat and spill folding This has redundant subtractions of eax from a stack slot ecx doesn t so we could simply subtract eax from ecx first and then use ecx(or vice-versa). This code< i1 > br i1 label label cond_next715 produces cx movswl	cx

to	__pad7__

to esp esp setne al movzbw ax esp setg cl movzbw cx cmove	ax

to esp esp setne al movzbw ax esp setg cl movzbw cx cmove cx cl jne LBB1_2 esp which is much	nicer

to esp esp setne al movzbw ax esp setg cl movzbw cx cmove cx cl jne LBB1_2 esp which is much esp edx eax decl edx jle L7	L5

to esp esp setne al movzbw ax esp setg cl movzbw cx cmove cx cl jne LBB1_2 esp which is much esp edx eax decl edx jle L7 esp ret	p2align

to esp esp setne al movzbw ax esp setg cl movzbw cx cmove cx cl jne LBB1_2 esp which is much esp edx eax decl edx jle L7 esp ret	L7

to esp esp setne al movzbw ax esp setg cl movzbw cx cmove cx cl jne LBB1_2 esp which is much esp edx eax decl edx jle L7 esp ret eax ja L5	L4

to esp esp setne al movzbw ax esp setg cl movzbw cx cmove cx cl jne LBB1_2 esp which is much esp edx eax decl edx jle L7 esp ret eax ja L5 call abort Tail call optimization	improvements

to esp esp setne al movzbw ax esp setg cl movzbw cx cmove cx cl jne LBB1_2 esp which is much esp edx eax decl edx jle L7 esp ret eax ja L5 call abort Tail call optimization	int64

Moving arg1 onto the stack slot of callee function would overwrite arg2 of the caller Possible	optimizations

Moving arg1 onto the stack slot of callee function would overwrite arg2 of the caller Possible int32	arg2

gcc compiles this esp xorl eax jmp L2	L3

gcc compiles this esp xorl eax jmp L2 eax je L10	L2

gcc compiles this esp xorl eax jmp L2 eax je L10 eax eax jne L3 call L_abort $stub	L10

gcc compiles this esp xorl eax jmp L2 eax je L10 eax eax jne L3 call L_abort $stub esp call L_exit $stub	llvm

gcc compiles this esp xorl eax jmp L2 eax je L10 eax eax jne L3 call L_abort $stub esp call L_exit $stub esp eax ecx eax jge LBB1_4 ecx ecx jne LBB1_1 eax esp ret	LBB1_4

it should cost the same as a move shift on any modern	processor

it should cost the same as a move shift on any modern but it s a lot shorter Downside is that it puts more pressure on register allocation because it has fixed operands	Example

The following code is currently	generated

this lets us change the cmpl into a	testl

this lets us change the cmpl into a which is and eliminate the shift We compile this	function

this lets us change the cmpl into a which is and eliminate the shift We compile this i32	b { return (unsigned char)a == (unsigned char)b

this lets us change the cmpl into a which is and eliminate the shift We compile this i32 i32	c

this lets us change the cmpl into a which is and eliminate the shift We compile this i32 i32 i8 zeroext d	nounwind

< i1 > br i1	tmp2

< i1 > br i1 label	bb7

< i1 > br i1 label label bb	bb

< i32 > ret i32 tmp10 ecx	cmpb

< i32 > ret i32 tmp10 ecx esp je LBB0_2 eax addl eax ret	LBB0_2

gets compiled into this on rsp movaps	xmm7

gets compiled into this on rsp movaps rsp movaps	xmm6

gets compiled into this on rsp movaps rsp movaps rsp movaps	xmm5

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps	xmm4

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps	xmm3

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps	xmm2

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq	r9

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq	r8

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq	rcx

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq	rdx

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq	rsi

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq	rax

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp eax	addq

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp eax rsp ret ecx eax rcx movl rsp jmp LBB1_2 gcc	generates

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp eax rsp ret ecx eax rcx movl rsp jmp LBB1_2 gcc rsp	LCFI0

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp eax rsp ret ecx eax rcx movl rsp jmp LBB1_2 gcc rsp rax movq rsp rsp movq rsp rax movq rsp eax eax jb L6 rdx eax rsp ret p2align	L6

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp eax rsp ret ecx eax rcx movl rsp jmp LBB1_2 gcc rsp rax movq rsp rsp movq rsp rax movq rsp eax eax jb L6 rdx eax rsp ret p2align edx rdx eax movl rsp eax rsp ret and it gets compiled into this on ebp esp eax movl ebp eax movl ebp eax esp popl ebp ret gcc ebp eax popl ebp ret Teach tblgen not to check bitconvert source type in some cases This allows us to consolidate the following patterns in X86InstrMMX	td

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp eax rsp ret ecx eax rcx movl rsp jmp LBB1_2 gcc rsp rax movq rsp rsp movq rsp rax movq rsp eax eax jb L6 rdx eax rsp ret p2align edx rdx eax movl rsp eax rsp ret and it gets compiled into this on ebp esp eax movl ebp eax movl ebp eax esp popl ebp ret gcc ebp eax popl ebp ret Teach tblgen not to check bitconvert source type in some cases This allows us to consolidate the following patterns in X86InstrMMX	iPTR

def	__pad8__

def	__pad9__

There are other cases in various td files Take something like the following on unsigned	y {return x % y

We currently generate a	libcall

We currently generate a but we really shouldn	t

We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2	and

We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2	or

We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2	xor

We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2	neg

We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2	shl

We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2	sra

We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2	srl

We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2	shld

We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2	shrd

We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2 atomic	ops

We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2 atomic and others It is also currently not done for read modify write instructions It is also current not done if the OF or CF flags are needed The shift operators have the complication that when the shift count is	zero

We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2 atomic and others It is also currently not done for read modify write instructions It is also current not done if the OF or CF flags are needed The shift operators have the complication that when the shift count is EFLAGS is not	set

Current	output

Current eax eax eax ret Ideal eax eax ret Re implement atomic builtins x86 does not have to use add to implement these	Instead

Current eax eax eax ret Ideal eax eax ret Re implement atomic builtins x86 does not have to use add to implement these it can use	inc

bar	__pad10__

bar al	andb

bar al al movzbl eax ret Missed	optimization

bar al al movzbl eax ret Missed when stored in a memory	object

bar	__pad11__

bar al al movzbl eax ret GCC produces	bar

We generate the following IR with	clang

We generate the following IR with i32 b nounwind	readnone

< i32 >	tmp6 = and i32 %tmp

< i32 >< i32 >	cmp = icmp eq i32 %tmp6

< i32 >< i32 >< i1 >	conv5 = zext i1 %cmp to i32

< i32 >	conv1 = ashr i32 %sext

< i32 >< i32 >	sext6 = shl i32 %b

< i32 >< i32 >< i32 >	conv4 = ashr i32 %sext6

< i32 > ret i32 conv5 And the following x86 eax movsbl	dil

< i32 > ret i32 conv5 And the following x86 eax movsbl ecx cmpl ecx sete al movzbl eax ret It should be possible to eliminate the sign extensions LLVM misses a load store narrowing opportunity in this	i16

< i32 > ret i32 conv5 And the following x86 eax movsbl ecx cmpl ecx sete al movzbl eax ret It should be possible to eliminate the sign extensions LLVM misses a load store narrowing opportunity in this i32	bfi = external global %struct.bf*

LLVM currently emits rax rax movq rax rax ret It could narrow the loads and stores to emit rax rax movq rax rax ret The trouble is that there is a TokenFactor between the store and the	load

currently compiles	into

currently compiles eax eax je LBB0_3 testl eax jne LBB0_4 the testl could be	removed

Typedef Documentation

◆ a

Should also combine to x Currently not optimized with clang emit llvm bc opt O3 int a

Definition at line 489 of file README.txt.

◆ edx

We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl edx

Definition at line 923 of file README.txt.

◆ mtune

using mtune = pentium2/3/4/m/etc.: abs: movl 4(%esp), %eax cltd xorl %edx, %eax subl %edx, %eax ret Take the following code (from http: extern unsigned char first_one[65536]

Definition at line 943 of file README.txt.

◆ tmp

< i32 > tmp = call i32 @t4( i32 %tmp.5 )

Definition at line 1347 of file README.txt.

◆ tmp1

using tmp1 = urem i32 %X, 255 ret i32 %tmp1 } Currently it compiles to: ... movl $2155905153, %ecx movl 8(%esp), %esi movl %esi, %eax mull %ecx ... This could be "reassociated" into: movl $2155905153, %eax movl 8(%esp), %ecx mull %ecx to avoid the copy. In fact, the existing two-address stuff would do this except that mul isn't a commutative 2-addr instruction. I guess this has to be done at isel time based on the #uses to mul? Make sure the instruction which starts a loop does not cross a cacheline boundary. This requires knowning the exact length of each machine instruction. That is somewhat complicated, but doable. Example 256.bzip2: In the new trace, the hot loop has an instruction which crosses a cacheline boundary. In addition to potential cache misses, this can't help decoding as I imagine there has to be some kind of complicated decoder reset and realignment to grab the bytes from the next cacheline. 532 532 0x3cfc movb (1809(%esp, %esi), %bl <<<--- spans 2 64 byte lines 942 942 0x3d03 movl %dh, (1809(%esp, %esi) 937 937 0x3d0a incl %esi 3 3 0x3d0b cmpb %bl, %dl 27 27 0x3d0d jnz 0x000062db <main+11707> In c99 mode, the preprocessor doesn't like assembly comments like #TRUNCATE. This could be a single 16-bit load. int f(char *p) { if ((p[0] == 1) & (p[1] == 2)) return 1

Definition at line 375 of file README.txt.

Function Documentation

◆ __sync_add_and_fetch()

Current eax eax eax ret Ideal eax eax ret Re implement atomic builtins __sync_add_and_fetch ( )

◆ abort_gzip()

<i32> ret i32 tmp10 ecx esp je LBB0_2 eax addl eax ret edx movl eax subl eax ret There s an obviously unnecessary movl in and we could eliminate a couple more movls by putting (%esp) into %eax instead of %ecx. See rdar<i1*> define fastcc void abort_gzip ( )

Definition at line 1060 of file README.txt.

References b, bb, call(), entry, exit(), i1, i32, load, nounwind, preds, store, and uses.

◆ addl()

We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax addl ( % esp )

◆ addq()

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp eax rsp ret ecx eax addq ( % rsp )

◆ always()

bar al al movzbl eax ret Missed when stored in a memory are stored as single byte objects the value of which is always ( false )

Definition at line 1412 of file README.txt.

Referenced by llvm::LegalizeRuleSet::alwaysLegal(), llvm::LegalizeRuleSet::fallback(), llvm::LegalizeRuleSet::libcall(), and llvm::LegalizeRuleSet::lower().

◆ bar() [1/3]

define i32 bar ( %struct.B *nocapture % a )

Definition at line 1390 of file README.txt.

◆ bar() [2/3]

define i32 bar ( i8 *nocapture % a )

Definition at line 1418 of file README.txt.

◆ bar() [3/3]

int bar ( struct B * a )

Definition at line 1388 of file README.txt.

◆ bfi()

LLVM currently emits rax rax movq bfi ( % rip )

◆ callee()

Here we don t need to write any variables to the top of the stack since they don t overwrite each other int callee	(	int32	arg1,
		int32	arg2
	)

◆ caller()

int caller	(	int32	arg1,
		int32	arg2
	)

Definition at line 681 of file README.txt.

Referenced by useFuncSeen().

◆ clearbit()

void clearbit	(	int *	target,
		int	bit
	)

Definition at line 111 of file README.txt.

References bit.

◆ exit()

declare void exit ( i32 )

Definition at line 1072 of file README.txt.

References x, and y.

Referenced by abort_gzip(), appendFile(), llvm::RegionBase< RegionTraits< Function > >::contains(), llvm::Hexagon_MC::createHexagonMCSubtargetInfo(), llvm::LLVMContext::diagnose(), llvm::sys::Process::Exit(), llvm::Interpreter::exitCalled(), fatalOpenError(), llvm::RegionBase< RegionTraits< Function > >::getExit(), llvm::RegionBase< RegionTraits< Function > >::getExitingBlock(), llvm::RegionBase< RegionTraits< Function > >::getExitingBlocks(), llvm::RegionBase< RegionTraits< Function > >::getExpandedRegion(), llvm::handleExecNameEncodedBEOpts(), llvm::handleExecNameEncodedOptimizerOpts(), iJIT_NotifyEvent(), llvm::RegionBase< RegionTraits< Function > >::isTopLevelRegion(), parseCHRFilterFiles(), llvm::PrintFatalError(), llvm::PrintFatalNote(), llvm::RegionBase< RegionTraits< Function > >::replaceExit(), llvm::MCContext::reportFatalError(), and reportOpenError().

◆ extend()

_test eax xmm0 eax xmm1 comiss xmm1 setae al movzbl ecx eax edx ecx cmove eax ret Note the cmove can be replaced with a single cmovae There are a number of issues We are introducing a setcc between the result of the intrisic call and select The intrinsic is expected to produce a i32 value so a any extend ( which becomes a zero extend )

Definition at line 213 of file README.txt.

Referenced by DecodeAddSubERegInstruction(), and llvm::slpvectorizer::BoUpSLP::vectorizeTree().

◆ first_one()

The following code is currently eax eax ecx jb LBB1_2 eax movzbl first_one ( % eax )

Referenced by FirstOnet().

◆ FirstOnet()

int FirstOnet ( unsigned long long arg1 )

Definition at line 944 of file README.txt.

References first_one().

◆ flds()

esp eax movl ecx ecx cvtsi2ss xmm0 eax cvtsi2ss xmm1 xmm0 addss xmm0 movss flds	(	%	esp,
		1
	)

◆ foo()

the multiplication has a latency of four as opposed to two cycles for the movl lea variant It appears gcc place string data with linkonce linkage in section coalesced instead of section coalesced Take a look at darwin there are other Darwin assembler directives that we do not make use of define i32 foo	(	i32 *%	a,
		i32 %	t
	)

Definition at line 266 of file README.txt.

References add, entry, i1, i32, load, llvm::numbers::phi, preds, ret(), t, tmp2, tmp5, uses, and x.

◆ full_add()

For the entry BB esp pxor xmm0 xmm1 ucomisd xmm1 setnp al sete cl testb al jne LBB1_5 xmm2 cvtss2sd xmm3 ucomisd xmm0 ja LBB1_3 xmm2 xmm0 ret We should sink the load into xmm3 into the LBB1_2 block This should be pretty and will nuke all the copies bool full_add	(	unsigned	a,
		unsigned	b
	)

Definition at line 531 of file README.txt.

◆ if()

else if ( x = =1 )

◆ into()

into ( - m64 )

Definition at line 1092 of file README.txt.

References x.

◆ LCPI1_1()

For the entry BB esp pxor xmm0 xmm1 ucomisd xmm1 setnp al sete cl testb al jne LBB1_5 xmm2 cvtss2sd LCPI1_1 ( % rip )

◆ leal() [1/2]

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp eax rsp ret ecx eax rcx movl rsp jmp LBB1_2 gcc rsp rax movq rsp rsp movq rsp rax movq rsp eax eax jb L6 rdx eax rsp ret p2align edx rdx eax movl rsp eax rsp ret and it gets compiled into this on ebp esp eax movl ebp leal ( % eax )

◆ leal() [2/2]

We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax leal	(	%	eax,
		%	eax,
		2
	)

◆ leaq()

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp eax rsp ret ecx eax rcx movl rsp jmp LBB1_2 gcc rsp rax movq rsp rsp movq rsp leaq ( % rsp )

◆ main()

Here we need to push the arguments because they overwrite each other main ( )

Definition at line 718 of file README.txt.

◆ movaps()

_test eax movaps ( % eax )

◆ movl() [1/2]

_test eax xmm0 movl ( % esp )

◆ movl() [2/2]

esp movl	(	%	esp,
		1
	)

◆ movq()

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp eax rsp ret ecx eax rcx movl rsp jmp LBB1_2 gcc rsp rax movq rsp rsp movq rsp rax movq rsp eax eax jb L6 movq ( % rsp )

◆ movsbl()

we currently eax movsbl ( % esp )

◆ movsd()

For the entry BB esp pxor xmm0 movsd ( % esp )

◆ movswl()

< i32 > br label bb114 eax ecx movl ebp subl ebp eax movl ebp subl ebp eax movl ebp subl ebp eax subl ecx movl ebp eax movl ebp movswl ( % ebp )

◆ movzwl()

The following code is currently eax eax ecx jb LBB1_2 eax movzbl eax ret eax ret We could change the eax into movzwl ( % esp )

◆ no_overflow()

bool no_overflow	(	unsigned	a,
		unsigned	b
	)

Definition at line 533 of file README.txt.

References b, and full_add().

◆ ops()

Instead of the following for memset char edx edx edx It might be better to generate eax movl edx movl edx movw edx when we can spare a register It reduces code size Evaluate what the best way to codegen sdiv C is For we currently get ret i32 Y eax movl ecx ecx ecx addl eax eax ret GCC knows several different ways to codegen one of which is eax eax ecx cmovle eax eax ret which is probably but it s interesting at since libc is hand tuned for medium and large mem ops	(	avoiding RFO for large	stores,
		TLB	preheating,
		etc
	)

Definition at line 167 of file README.txt.

◆ processors()

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit we should expand to a conditional branch like GCC produces Some isel and Sequencing of Instructions Scheduling for reduced register pressure E g Minimum Register Instruction Sequence load p Because the compare isn t it is not matched with the load on both sides The dag combiner should be made smart enough to canonicalize the load into the RHS of a compare when it can invert the result of the compare for free In many LLVM generates code like eax cmpl esp setl al movzbl eax ret on some processors ( which ones? )

◆ ret()

to esp esp setne al movzbw ax esp setg cl movzbw cx cmove cx cl jne LBB1_2 esp ret ( also really horrible code on ppc )

◆ shifts()

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit shifts ( in general )

◆ subl()

_test eax subl ( % esp )

◆ support()

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg support ( From http:but without the unnecessary and. )

◆ t1()

<%struct.bf**> define void t1 ( )

Definition at line 1497 of file README.txt.

Referenced by expandLog(), expandLog10(), expandLog2(), GetExponent(), getLimitedPrecisionExp2(), and GetSignificand().

◆ test()

void test ( double * P )

Definition at line 898 of file README.txt.

References b, bar, c, P, and X.

◆ v2i32()

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp eax rsp ret ecx eax rcx movl rsp jmp LBB1_2 gcc rsp rax movq rsp rsp movq rsp rax movq rsp eax eax jb L6 rdx eax rsp ret p2align edx rdx eax movl rsp eax rsp ret and it gets compiled into this on ebp esp eax movl ebp eax movl ebp eax esp popl ebp ret gcc ebp eax popl ebp ret Teach tblgen not to check bitconvert source type in some cases This allows us to consolidate the following patterns in X86InstrMMX v2i32 ( MMX_MOVDQ2Qrr VR128:$src )

◆ v4i16()

def v4i16 ( MMX_MOVDQ2Qrr VR128:$src )

◆ v8i8()

def v8i8 ( MMX_MOVDQ2Qrr VR128:$src )

◆ x()

The generated code on x86 for checking for signed overflow on a multiply the obvious way is much longer than it needs to be int x	(	int	a,
		int	b
	)

Definition at line 913 of file README.txt.

References b.

Variable Documentation

◆ __const_coal

the multiplication has a latency of four as opposed to two cycles for the movl lea variant It appears gcc place string data with linkonce linkage in section coalesced instead of section __const_coal

Definition at line 259 of file README.txt.

◆ __DATA

the multiplication has a latency of four as opposed to two cycles for the movl lea variant It appears gcc place string data with linkonce linkage in section coalesced instead of section __DATA

Definition at line 260 of file README.txt.

◆ pad10

bar __pad10__

Definition at line 1400 of file README.txt.

◆ pad11

bar __pad11__

Definition at line 1426 of file README.txt.

◆ pad4

http __pad4__

Definition at line 20 of file README.txt.

◆ pad5

_test __pad5__

Definition at line 197 of file README.txt.

◆ pad6

_test __pad6__

Definition at line 462 of file README.txt.

◆ pad7

to __pad7__

Definition at line 630 of file README.txt.

◆ pad8

def __pad8__

Definition at line 1207 of file README.txt.

◆ pad9

def __pad9__

Definition at line 1210 of file README.txt.

◆ __TEXT

the multiplication has a latency of four as opposed to two cycles for the movl lea variant It appears gcc place string data with linkonce linkage in section __TEXT

Definition at line 259 of file README.txt.

◆ _test1

Instead of the following for memset char edx edx edx It might be better to generate eax movl edx movl edx movw edx when we can spare a register It reduces code size Evaluate what the best way to codegen sdiv C is For we currently get ret i32 Y _test1

Definition at line 143 of file README.txt.

◆ add

Current eax eax eax ret Ideal eax eax ret Re implement atomic builtins x86 does not have to use add to implement these it can use add

Definition at line 454 of file README.txt.

Referenced by foo().

◆ addl

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp eax rsp ret ecx eax rcx movl rsp jmp LBB1_2 gcc rsp rax movq rsp rsp movq rsp rax movq rsp eax eax jb L6 rdx eax rsp ret p2align edx rdx eax movl rsp eax rsp ret and it gets compiled into this on ebp esp eax movl ebp eax movl ebp eax addl

Definition at line 397 of file README.txt.

◆ addq

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp eax rsp ret ecx eax rcx movl rsp jmp LBB1_2 gcc rsp rax movq rsp rsp movq rsp rax movq rsp eax eax jb L6 rdx eax rsp ret p2align edx rdx eax movl rsp eax addq

Definition at line 1143 of file README.txt.

◆ al

< i32 > ret i32 conv5 And the following x86 eax movsbl ecx cmpl ecx sete al movzbl al

Definition at line 89 of file README.txt.

◆ algorithm

Improvements to the multiply shift add algorithm

Definition at line 10 of file README.txt.

◆ Also

We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2 atomic and others It is also currently not done for read modify write instructions It is also current not done if the OF or CF flags are needed The shift operators have the complication that when the shift count is EFLAGS is not so they can only subsume a test instruction if the shift count is known to be non zero Also

Definition at line 30 of file README.txt.

◆ Alternatively

is currently compiled esp esp jne LBB1_1 esp ret esp esp jne L_abort $stub esp ret This can be applied to any no return function call that takes no arguments etc Alternatively

Definition at line 412 of file README.txt.

◆ and

We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2 and

Definition at line 1271 of file README.txt.

Referenced by llvm::gsym::operator<<().

◆ andb

LLVM currently emits rax rax movq rax rax ret It could narrow the loads and stores to emit rax rax movq rax andb

Definition at line 1401 of file README.txt.

◆ andl

LLVM currently emits rax rax movq rax andl

Definition at line 302 of file README.txt.

◆ arg2

Moving arg1 onto the stack slot of callee function would overwrite arg2 of the caller Possible int32 arg2

Definition at line 700 of file README.txt.

◆ as

we currently eax ecx subl eax ret We would use one fewer register if codegen d as

Definition at line 452 of file README.txt.

◆ ax

to esp esp setne al movzbw ax esp setg cl movzbw cx cmove ax

Definition at line 637 of file README.txt.

◆ b

<i32> ret i32 conv5 And the following x86 edi dil sete al movzbl eax ret A cmpb instead of the xorl testb would be one instruction shorter Given the following C int b { return (unsigned char)a == (unsigned char)b

Definition at line 973 of file README.txt.

◆ bar

bar al al movzbl eax ret GCC produces bar

Definition at line 1434 of file README.txt.

Referenced by foo(), and test().

◆ bb

<i1> br i1 label label bb bb

Definition at line 978 of file README.txt.

Referenced by abort_gzip(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::ScheduleDAGInstrs::enterRegion(), llvm::ScheduleDAGMI::enterRegion(), llvm::ScheduleDAGMILive::enterRegion(), llvm::MipsAsmPrinter::isBlockOnlyReachableByFallthrough(), llvm::MachineBasicBlock::printName(), llvm::ScheduleDAGSDNodes::Run(), llvm::ScheduleDAGInstrs::startBlock(), llvm::ScheduleDAGMI::startBlock(), and useFuncSeen().

◆ bb7

< i32 > ret i32 tmp6 bb7

Definition at line 976 of file README.txt.

◆ be

<i32> br label bb114 eax ecx movl ebp subl ebp eax movl ebp subl ebp eax movl ebp subl ebp eax subl ecx movl ebp eax movl ebp eax movl ebp ebp This appears to be bad because the RA is not folding the store to the stack slot into the movl The above instructions could be

Definition at line 592 of file README.txt.

◆ bfi

LLVM currently emits rax rax movq rax rax ret It could narrow the loads and stores to emit rax rax movq bfi = external global %struct.bf*

Definition at line 1495 of file README.txt.

Referenced by llvm::InstructionSelector::setupMF().

◆ bit

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit we should expand to a conditional branch like GCC produces Some isel and Sequencing of Instructions Scheduling for reduced register pressure E g Minimum Register Instruction Sequence load p Because the compare isn t it is not matched with the load on both sides The dag combiner should be made smart enough to canonicalize the load into the RHS of a compare when it can invert the result of the compare for free In many LLVM generates code like eax cmpl esp setl al movzbl eax ret on some it is more efficient to do ebx xor eax cmpl esp setl al ret Doing this correctly is tricky as the xor clobbers the flags We should generate bts btr etc instructions on targets where they are cheap or when codesize is important e int bit

Initial value:

{

*target |= (1 << bit)

Definition at line 108 of file README.txt.

◆ c

c

Definition at line 973 of file README.txt.

◆ called

is currently compiled esp esp jne LBB1_1 esp ret esp esp jne L_abort $stub esp ret This can be applied to any no return function call that takes no arguments etc the stack save restore logic could be shrink producing something like esp jne LBB1_1 ret esp call L_abort $stub Both are useful in different situations it could be shrink wrapped and tail called

Definition at line 424 of file README.txt.

◆ case

we currently eax ecx subl eax ret We would use one fewer register if codegen d eax neg eax eax ret Note that this isn t beneficial if the load can be folded into the sub In this case

Definition at line 458 of file README.txt.

◆ cases

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit we should expand to a conditional branch like GCC produces Some isel and Sequencing of Instructions Scheduling for reduced register pressure E g Minimum Register Instruction Sequence load p Because the compare isn t it is not matched with the load on both sides The dag combiner should be made smart enough to canonicalize the load into the RHS of a compare when it can invert the result of the compare for free In many cases

Definition at line 83 of file README.txt.

◆ change

<i32> br label bb114 eax ecx movl ebp subl ebp eax movl ebp subl ebp eax movl ebp subl ebp eax subl ecx movl ebp eax movl ebp eax movl ebp ebp This appears to be bad because the RA is not folding the store to the stack slot into the movl The above instructions could ebp ebp This seems like a cross between remat and spill folding This has redundant subtractions of eax from a stack slot ecx doesn t change

Definition at line 599 of file README.txt.

◆ cl

to esp esp setne al movzbw ax esp setg cl movzbw cl

Definition at line 25 of file README.txt.

Referenced by compareMBBPriority().

◆ clang

We generate the following IR with clang

Definition at line 1443 of file README.txt.

◆ cmp

< i32 >< i32 >< i32 >< i32 > cmp = icmp eq i32 %tmp6

Definition at line 1447 of file README.txt.

Referenced by llvm::OpenMPIRBuilder::createCopyinClauseBlocks().

◆ cmpb

<i32> ret i32 tmp10 ecx cmpb

Definition at line 992 of file README.txt.

◆ cmpl

currently compiles eax eax je LBB0_3 testl eax jne LBB0_4 the testl could be eax cmpl

Definition at line 155 of file README.txt.

◆ code

LLVM currently emits rax rax movq rax rax ret It could narrow the loads and stores to emit rax rax movq rax rax ret The trouble is that there is a TokenFactor between the store and the making it non trivial to determine if there s anything between the load and the store which would prohibit narrowing This code

inline

Definition at line 388 of file README.txt.

◆ commutative

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit we should expand to a conditional branch like GCC produces Some isel and Sequencing of Instructions Scheduling for reduced register pressure E g Minimum Register Instruction Sequence load p Because the compare isn t commutative

Definition at line 77 of file README.txt.

◆ cond_true662

<i32> br label bb114 eax ecx movl ebp subl ebp eax movl ebp subl ebp eax movl ebp subl ebp eax subl ecx movl ebp eax movl ebp eax movl ebp ebp This appears to be bad because the RA is not folding the store to the stack slot into the movl The above instructions could ebp ebp This seems like a cross between remat and spill folding This has redundant subtractions of eax from a stack slot ecx doesn t so we could simply subtract eax from ecx first and then use ecx (or vice-versa). This code<i1> br i1 label cond_true662

Definition at line 607 of file README.txt.

◆ conv1

<i32> conv1 = ashr i32 %sext

Definition at line 1470 of file README.txt.

◆ conv4

< i32 >< i32 >< i32 >< i32 > conv4 = ashr i32 %sext6

Definition at line 1472 of file README.txt.

◆ conv5

< i1 > conv5 = zext i1 %cmp to i32

Definition at line 1448 of file README.txt.

◆ cx

<i32> br label bb114 eax ecx movl ebp subl ebp eax movl ebp subl ebp eax movl ebp subl ebp eax subl ecx movl ebp eax movl ebp eax movl ebp ebp This appears to be bad because the RA is not folding the store to the stack slot into the movl The above instructions could ebp ebp This seems like a cross between remat and spill folding This has redundant subtractions of eax from a stack slot ecx doesn t so we could simply subtract eax from ecx first and then use ecx (or vice-versa). This code<i1> br i1 label label cond_next715 produces cx movswl cx

Definition at line 612 of file README.txt.

◆ cycles

the multiplication has a latency of four cycles

Definition at line 253 of file README.txt.

◆ dil

<i32> ret i32 conv5 And the following x86 eax movsbl dil

Definition at line 1480 of file README.txt.

◆ Duplication

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit we should expand to a conditional branch like GCC produces Some isel Duplication

Definition at line 51 of file README.txt.

◆ easy

For the entry BB esp pxor xmm0 xmm1 ucomisd xmm1 setnp al sete cl testb al jne LBB1_5 xmm2 cvtss2sd xmm3 ucomisd xmm0 ja LBB1_3 xmm2 xmm0 ret We should sink the load into xmm3 into the LBB1_2 block This should be pretty easy

Definition at line 525 of file README.txt.

◆ eax

currently compiles eax eax je LBB0_3 testl eax

Definition at line 36 of file README.txt.

◆ ebx

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit we should expand to a conditional branch like GCC produces Some isel and Sequencing of Instructions Scheduling for reduced register pressure E g Minimum Register Instruction Sequence load p Because the compare isn t it is not matched with the load on both sides The dag combiner should be made smart enough to canonicalize the load into the RHS of a compare when it can invert the result of the compare for free In many LLVM generates code like eax cmpl esp setl al movzbl eax ret on some it is more efficient to do ebx xor eax cmpl ebx

Definition at line 97 of file README.txt.

◆ ecx

< i32 > ret i32 tmp10 ecx esp je LBB0_2 eax addl eax ret edx movl ecx

Definition at line 147 of file README.txt.

Referenced by getReadTimeStampCounter().

◆ esp

esp eax movl ecx ecx cvtsi2ss xmm0 eax cvtsi2ss xmm1 xmm0 addss xmm0 movss esp

Definition at line 235 of file README.txt.

◆ example

For example

Definition at line 492 of file README.txt.

◆ Example

it should cost the same as a move shift on any modern but it s a lot shorter Downside is that it puts more pressure on register allocation because it has fixed operands Example

Definition at line 928 of file README.txt.

◆ faster

_test eax eax ret Leaf functions that require one byte spill slot have a prolog like esp and an epilog like esp popl esi ret It would be and potentially faster

Definition at line 479 of file README.txt.

◆ fh

float fh = (int) (u >> 16)

Definition at line 292 of file README.txt.

◆ Finally

is currently compiled esp esp jne LBB1_1 esp ret esp esp jne L_abort $stub esp ret This can be applied to any no return function call that takes no arguments etc the stack save restore logic could be shrink producing something like esp jne LBB1_1 ret esp call L_abort $stub Both are useful in different situations Finally

Definition at line 423 of file README.txt.

◆ fl

fh* return fh fl = 0x1.0p16f

Definition at line 293 of file README.txt.

◆ for

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit we should expand to a conditional branch like GCC produces Some isel and Sequencing of Instructions Scheduling for reduced register pressure E g Minimum Register Instruction Sequence load p Because the compare isn t it is not matched with the load on both sides The dag combiner should be made smart enough to canonicalize the load into the RHS of a compare when it can invert the result of the compare for free In many LLVM generates code like eax cmpl esp setl al movzbl eax ret on some it is more efficient to do ebx xor eax cmpl esp setl al ret Doing this correctly is tricky as the xor clobbers the flags We should generate bts btr etc instructions on targets where they are cheap or when codesize is important e for

Definition at line 108 of file README.txt.

◆ function

this lets us change the cmpl into a which is and eliminate the shift We compile this function

Definition at line 973 of file README.txt.

◆ g

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit we should expand to a conditional branch like GCC produces Some isel and Sequencing of Instructions Scheduling for reduced register pressure E g Minimum Register Instruction Sequence load p Because the compare isn t it is not matched with the load on both sides The dag combiner should be made smart enough to canonicalize the load into the RHS of a compare when it can invert the result of the compare for free In many LLVM generates code like eax cmpl esp setl al movzbl eax ret on some it is more efficient to do ebx xor eax cmpl esp setl al ret Doing this correctly is tricky as the xor clobbers the flags We should generate bts btr etc instructions on targets where they are cheap or when codesize is important e g

Definition at line 106 of file README.txt.

◆ generated

The following code is currently generated

Definition at line 954 of file README.txt.

◆ generates

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp eax rsp ret ecx eax rcx movl rsp jmp LBB1_2 gcc rsp rax movq rsp rsp movq rsp rax movq rsp eax eax jb L6 rdx eax rsp ret p2align edx rdx eax movl rsp eax rsp ret and it gets compiled into this on ebp esp eax movl ebp eax movl ebp eax esp popl ebp ret gcc generates

Definition at line 1153 of file README.txt.

◆ h

the multiplication has a latency of four as opposed to two cycles for the movl lea variant It appears gcc place string data with linkonce linkage in section coalesced instead of section coalesced Take a look at darwin h

Definition at line 261 of file README.txt.

Referenced by llvm::CommonHandleTraits::Close(), llvm::CryptContextTraits::Close(), llvm::RegTraits::Close(), llvm::FindHandleTraits::Close(), DecodeMoveHRegInstruction(), llvm::DecodePSWAPMask(), freezeset(), llvm::object::hashSysV(), llvm::CommonHandleTraits::IsValid(), llvm::CryptContextTraits::IsValid(), llvm::RegTraits::IsValid(), llvm::ScopedHandle< HandleTraits >::operator=(), and llvm::ARMFunctionInfo::setHasITBlocks().

◆ However

<i32> br label bb114 eax ecx movl ebp subl ebp eax movl ebp subl ebp eax movl ebp subl ebp eax subl ecx movl ebp eax movl ebp eax movl ebp ebp This appears to be bad because the RA is not folding the store to the stack slot into the movl The above instructions could ebp ebp This seems like a cross between remat and spill folding This has redundant subtractions of eax from a stack slot However

Definition at line 249 of file README.txt.

◆ however

however

Definition at line 253 of file README.txt.

◆ i16

< i32 > ret i32 conv5 And the following x86 eax movsbl ecx cmpl ecx sete al movzbl eax ret It should be possible to eliminate the sign extensions LLVM misses a load store narrowing opportunity in this i16

Definition at line 1493 of file README.txt.

◆ ideas

http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra but it s one instruction and doesn t stress bit subreg eax eax movl edx edx sall eax sall cl edx bit we should expand to a conditional branch like GCC produces Some isel ideas

Definition at line 51 of file README.txt.

◆ improvement

is pessimized by loop reduce and indvars u32 to float conversion improvement

Definition at line 291 of file README.txt.

◆ improvements

to esp esp setne al movzbw ax esp setg cl movzbw cx cmove cx cl jne LBB1_2 esp which is much esp edx eax decl edx jle L7 esp ret eax ja L5 call abort Tail call optimization improvements

Definition at line 665 of file README.txt.

◆ imull

We currently emits imull

Definition at line 235 of file README.txt.

◆ inc

Current eax eax eax ret Ideal eax eax ret Re implement atomic builtins x86 does not have to use add to implement these it can use inc

Definition at line 1367 of file README.txt.

Referenced by DecodeVLD2LN(), DecodeVLD3DupInstruction(), DecodeVLD3LN(), DecodeVLD4DupInstruction(), DecodeVLD4LN(), DecodeVST2LN(), DecodeVST3LN(), and DecodeVST4LN().

◆ Instead

Current eax eax eax ret Ideal eax eax ret Re implement atomic builtins x86 does not have to use add to implement these Instead

Definition at line 1366 of file README.txt.

◆ int64

to esp esp setne al movzbw ax esp setg cl movzbw cx cmove cx cl jne LBB1_2 esp which is much esp edx eax decl edx jle L7 esp ret eax ja L5 call abort Tail call optimization int64

Definition at line 680 of file README.txt.

◆ into

currently compiles into

Definition at line 1544 of file README.txt.

◆ iPTR

def iPTR

Definition at line 1205 of file README.txt.

◆ is

For the entry BB is

Definition at line 495 of file README.txt.

◆ it

Instead of the following for memset char edx edx edx It might be better to generate eax movl edx movl edx movw edx when we can spare a register It reduces code size Evaluate what the best way to codegen sdiv C is For we currently get ret i32 Y eax movl ecx ecx ecx addl eax eax ret GCC knows several different ways to codegen it

Definition at line 151 of file README.txt.

◆ L10

gcc compiles this esp xorl eax jmp L2 eax je L10 eax eax jne L3 call L_abort $stub L10

Definition at line 747 of file README.txt.

◆ L2

gcc compiles this esp xorl eax jmp L2 eax je L10 L2

Definition at line 742 of file README.txt.

◆ L3

gcc compiles this esp xorl eax jmp L2 L3

Definition at line 739 of file README.txt.

◆ L4

to esp esp setne al movzbw ax esp setg cl movzbw cx cmove cx cl jne LBB1_2 esp which is much esp edx eax decl edx jle L7 esp ret eax ja L5 L4

Definition at line 662 of file README.txt.

Referenced by llvm::SparcTargetLowering::getRegisterByName().

◆ L5

to esp esp setne al movzbw ax esp setg cl movzbw cx cmove cx cl jne LBB1_2 esp which is much esp edx eax decl edx jle L7 L5

Definition at line 656 of file README.txt.

Referenced by llvm::SparcTargetLowering::getRegisterByName().

◆ L6

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp eax rsp ret ecx eax rcx movl rsp jmp LBB1_2 gcc rsp rax movq rsp rsp movq rsp rax movq rsp eax eax jb L6 rdx eax rsp ret p2align L6

Definition at line 1168 of file README.txt.

Referenced by llvm::SparcTargetLowering::getRegisterByName().

◆ L7

to esp esp setne al movzbw ax esp setg cl movzbw cx cmove cx cl jne LBB1_2 esp which is much esp edx eax decl edx jle L7 esp ret L7

Definition at line 658 of file README.txt.

Referenced by llvm::SparcTargetLowering::getRegisterByName(), and verifyLeafProcRegUse().

◆ LBB0_2

< i32 > ret i32 tmp10 ecx esp je LBB0_2 eax addl eax ret edx movl eax subl eax ret There s an obviously unnecessary movl in LBB0_2

Definition at line 999 of file README.txt.

◆ LBB1_1

We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2 LBB1_1

Definition at line 405 of file README.txt.

◆ LBB1_2

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp LBB1_2

Definition at line 519 of file README.txt.

◆ LBB1_3

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp eax rsp ret LBB1_3

Definition at line 521 of file README.txt.

◆ LBB1_4

gcc compiles this esp xorl eax jmp L2 eax je L10 eax eax jne L3 call L_abort $stub esp call L_exit $stub esp eax ecx eax jge LBB1_4 ecx ecx jne LBB1_1 eax esp ret LBB1_4

Definition at line 773 of file README.txt.

◆ LCFI0

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp eax rsp ret ecx eax rcx movl rsp jmp LBB1_2 gcc rsp LCFI0

Definition at line 1155 of file README.txt.

◆ least

Instead of the following for memset char edx edx edx It might be better to generate eax movl edx movl edx movw edx when we can spare a register It reduces code size Evaluate what the best way to codegen sdiv C is For we currently get ret i32 Y eax movl ecx ecx ecx addl eax eax ret GCC knows several different ways to codegen one of which is eax eax ecx cmovle eax eax ret which is probably but it s interesting at least

Definition at line 166 of file README.txt.

◆ libcall

We currently generate a libcall

Definition at line 1221 of file README.txt.

◆ LLVM

Improvements to the multiply shift add e g in LLVM

Definition at line 11 of file README.txt.

◆ llvm

gcc compiles this esp xorl eax jmp L2 eax je L10 eax eax jne L3 call L_abort $stub esp call L_exit $stub llvm

Definition at line 753 of file README.txt.

◆ load

LLVM currently emits rax rax movq rax rax ret It could narrow the loads and stores to emit rax rax movq rax rax ret The trouble is that there is a TokenFactor between the store and the load

Definition at line 1531 of file README.txt.

Referenced by abort_gzip(), DecodeT2LdStPre(), DecodeVLDST1Instruction(), DecodeVLDST2Instruction(), DecodeVLDST3Instruction(), DecodeVLDST4Instruction(), foo(), getLoadStoreRegOpcode(), and LowerCallResult().

◆ looking

Should compile edi setae al movzbl eax ret on instead of the rather stupid looking

Definition at line 543 of file README.txt.

◆ M

We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M

Definition at line 252 of file README.txt.

◆ movl

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp eax rsp ret ecx eax rcx movl rsp jmp LBB1_2 gcc rsp rax movq rsp rsp movq rsp rax movq rsp movl

Definition at line 117 of file README.txt.

◆ movw

< i32 > br label bb114 eax ecx movl ebp subl ebp eax movl ebp subl ebp eax movl ebp subl ebp eax subl ecx movl ebp eax movl ebp eax movl ebp movw

Definition at line 121 of file README.txt.

◆ movzbl

into eax xorps xmm0 xmm0 eax xmm0 eax xmm0 ret esp movzbl

Definition at line 210 of file README.txt.

◆ mulss

esp eax movl ecx ecx cvtsi2ss xmm0 eax cvtsi2ss xmm1 mulss

Definition at line 304 of file README.txt.

◆ neg

We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2 neg

Definition at line 1271 of file README.txt.

◆ nicer

to esp esp setne al movzbw ax esp setg cl movzbw cx cmove cx cl jne LBB1_2 esp which is much nicer

Definition at line 650 of file README.txt.

◆ Note

We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles Note

Definition at line 239 of file README.txt.

Referenced by llvm::ELFYAML::NoteSection::NoteSection().

◆ nounwind

We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We

Typedefs

Functions

Variables

Typedef Documentation

◆ a

◆ edx

◆ mtune

◆ tmp

◆ tmp1

Function Documentation

◆ __sync_add_and_fetch()

◆ abort_gzip()

◆ addl()

◆ addq()

◆ always()

◆ bar() [1/3]

◆ bar() [2/3]

◆ bar() [3/3]

◆ bfi()

◆ callee()

◆ caller()

◆ clearbit()

◆ exit()

◆ extend()

◆ first_one()

◆ FirstOnet()

◆ flds()

◆ foo()

◆ full_add()

◆ if()

◆ into()

◆ LCPI1_1()

◆ leal() [1/2]

◆ leal() [2/2]

◆ leaq()

◆ main()

◆ movaps()

◆ movl() [1/2]

◆ movl() [2/2]

◆ movq()

◆ movsbl()

◆ movsd()

◆ movswl()

◆ movzwl()

◆ no_overflow()

◆ ops()

◆ processors()

◆ ret()

◆ shifts()

◆ subl()

◆ support()

◆ t1()

◆ test()

◆ v2i32()

◆ v4i16()

◆ v8i8()

◆ x()

Variable Documentation

◆ __const_coal

◆ __DATA

◆ __pad10__

◆ __pad11__

◆ __pad4__

◆ __pad5__

◆ __pad6__

◆ __pad7__

◆ __pad8__

◆ __pad9__

◆ __TEXT

◆ _test1

◆ add

◆ addl

◆ addq

◆ al

◆ algorithm

◆ Also

◆ Alternatively

◆ and

◆ andb

◆ andl

◆ pad10

◆ pad11

◆ pad4

◆ pad5

◆ pad6

◆ pad7

◆ pad8

◆ pad9